JPH01112403A - Programmable controller - Google Patents
Programmable controllerInfo
- Publication number
- JPH01112403A JPH01112403A JP62270982A JP27098287A JPH01112403A JP H01112403 A JPH01112403 A JP H01112403A JP 62270982 A JP62270982 A JP 62270982A JP 27098287 A JP27098287 A JP 27098287A JP H01112403 A JPH01112403 A JP H01112403A
- Authority
- JP
- Japan
- Prior art keywords
- program
- cpu
- status
- input
- time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000002093 peripheral effect Effects 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 241000201776 Steno Species 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、ブロクうマブルコントローラに関するもの
である。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a blockable controller.
第2図は例えば従来のプログラマブルコントローラの制
御系を示す構成図であり、図において、(1)はブロク
うマブルコントローラを動作させるためのシーケンスプ
ログラム作成、入出力の状態をモニタ、又ブロクラムに
関係なく人出力を強制的にON、OFFできる機能を有
した周辺装置、(2)はシーケンスブロクラムに従って
入出力を制御するCPU、(2a)はCPU(2)の一
部を構成する演算部、(3)はCPU(2)からの入出
力指令によって実際に制御対象をON、OFFするI1
0ユニー、 1−1(4)はI10二二、−、)−(3
)に筬続されろ制御対象である。Figure 2 is a block diagram showing, for example, the control system of a conventional programmable controller. (2) is a CPU that controls input/output according to the sequence block diagram; (2a) is a calculation unit that forms part of CPU (2); , (3) is I1 that actually turns on and off the controlled object according to input/output commands from the CPU (2).
0 unit, 1-1(4) is I1022, -, )-(3
) is the controlled object.
次に動作に−1・いて説明する1通常、最初にシーケン
スブロクうムを作成した場合、ブロクうム中のバグをi
(vるためにデバー・りを行う。このデバー澹グはI1
0ユニ・・ト(3)に制御対象(4)を接続して行う場
合と接続しないで行う場合かあるが、いきなり通常通り
C!PTJ(2)を動作させても、プログラムのどの箇
所が悪いのか判断ができない。そこで、I10二二〜ト
(3)からの入力信号を切っておき、CPU(2)を実
行状態にして周辺装fM (1)からキー人力により入
力信号を与えてやることにより、順次出力の状態を制御
X4象(4)の状態ヌはI10ユニ、・・ト(3)の出
力状態を示すLEDの状態などにより判断シ、プロクラ
ムをデバ、・・グし、でいくという方法をとる。そして
バグが発見され1こ場合、プログラムを修正し、又最初
から順次入力指令を与えていくという上記方法をバグが
なくなるまでくり返す。Next, let's explain the operation.1 Normally, when you create a sequence block program for the first time, you can correct any bugs in the block program.
(Deva-ri is performed in order to
0 unit... There are cases in which the controlled object (4) is connected to (3) and cases in which it is not connected, but suddenly C! Even if PTJ (2) is operated, it is not possible to determine which part of the program is bad. Therefore, by cutting off the input signal from I1022-G (3), putting the CPU (2) in the running state, and manually inputting the input signal from the peripheral fM (1), the outputs can be sequentially output. The state of the X4 element (4) is determined based on the state of the LED indicating the output state of the I10, etc., and the program is debugged. If a bug is found, the program is modified and the above method of sequentially giving input commands from the beginning is repeated until the bug is eliminated.
従来のプログラマブルコントローラは以上の様に構成さ
れているので、プログうムのデバ、、り時に一部プログ
ラムを修正する度に最初からデバ噌グの終了した箇所ま
で、入力指令を順に与えなおしてやらなければならず、
更に、制御対象(4)が大きくなり、シーケンスプログ
ラムの容jkも大きくなってくると、この作業は大変に
時間がかかるという問題点があった。Conventional programmable controllers are configured as described above, so every time you modify a part of the program when debugging a program, you have to re-give the input commands in order from the beginning to the point where the debugging ended. must,
Furthermore, as the object to be controlled (4) becomes larger and the size of the sequence program also becomes larger, there is a problem in that this work takes a lot of time.
この発明は上記の様な問題点を解消するためになされた
もので、プロクラムのデパ・・・グ時に、ブロクうムを
修正した場合にも最初からキー人力を与えなおすという
ロスをなくしデバーjグ時間の短縮を図ることを目的と
する。This invention was made to solve the above-mentioned problems, and it eliminates the loss of having to reassign key personnel from the beginning even when a block is modified when depacking a program. The purpose is to reduce the time required for programming.
また、この発明の別の目的は、上記目的に加えてキー人
力を与えなおしているときの入力指令の与えまちがいを
なくすことを目的とする。In addition to the above-mentioned object, another object of the present invention is to eliminate errors in inputting commands when re-applying human power to keys.
この発明に係るプログラマブルコントローラは、シーケ
ンスプログラムの実行中、入力指令の変化により変化す
る内部の出力接点8内部接点、タイマーなどのステータ
ス情報の全部あるいは一部を記憶する様にしたものであ
る。The programmable controller according to the present invention is configured to store all or part of the status information of internal output contacts 8, internal contacts, timers, etc. that changes due to changes in input commands during execution of a sequence program.
〔作用二1
この発明においては、ステータス記憶メモリが入力指令
の変化によって変化したステータス情報を記憶する。[Operation 21] In the present invention, the status storage memory stores status information that has changed due to changes in input commands.
以下、この発明の一実施例を図について説明する。第1
図において、従来例を示す第2図と同一の符号は同一部
分を示しているので説明は省略する。図において、(2
h)はCPU(21内部の演算部(2a)とデータのや
りとりを行りステータス記憶メモリである、
次に動作について説明する。制御対象(4)はト勺二ニ
ー、ト(3)に接続してもしなくてもよい。又、vつ!
=、ト(3)からの入力信号は切っておく 次にcpu
(2)にプログラムを書き込み、実行させておき、周辺
装置(1)よりCPU(2)に入力指令を順次、キー人
力により与えていく。この時、CPU(2)は内部に設
けられたステータス記憶用のメモリ(21))に入力汰
愈が変わる度にステータスの全部、又は一部・ン記憶し
でいく。入力指令が一つ与えられるごとに−ステーJブ
進むとすると、最後のステー・ブから何ステ、・、ブ前
まで記憶するかはメモリ容態を大きくすればするほど、
多くのステ・リブを記憶できる。途中でシーケンスプロ
グうムにバクを発見した場合は、入力指令を与えること
をやめ、プログラムの修正を行う。修正が終ったら再度
、シーケンスブロクうムの実行を行うが、この時ステー
タスをインシセライズするか、記憶しているステータス
同各の状態から実行するかは、モード切換にぼって行う
。モード切換の方法はここでは関連ではない、又、最終
ステ号ブより前のステ、・・ブから実行を開始しtこい
場合は周辺装B(1)より所定のキー人力を行うことで
、記憶をしている範囲内で任急のステーノブから開始す
ることが可能である。An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, the same reference numerals as in FIG. 2, which shows the conventional example, indicate the same parts, so a description thereof will be omitted. In the figure, (2
h) is a status storage memory that exchanges data with the arithmetic unit (2a) inside the CPU (21). Next, the operation will be explained. The controlled object (4) is connected to You don't have to do it.Also, v!
=, cut off the input signal from g (3) Next, cpu
A program is written in (2) and executed, and input commands are sequentially given to the CPU (2) from the peripheral device (1) manually using keys. At this time, the CPU (2) stores all or part of the status in the internally provided status storage memory (21) every time the input status changes. Assuming that each input command advances the number of steps, the larger the memory capacity is, the more steps the program will store from the last step.
I can memorize many Ste Libs. If a bug is discovered in the sequence program during the process, stop giving input commands and correct the program. When the modification is completed, the sequence block is executed again, but whether to incise the status or to execute from the same stored status is determined by mode switching. The mode switching method is not relevant here, and if you want to start execution from the steps before the final step, press the specified key manually from peripheral B (1). It is possible to start with a quick steno knob within the range you have memorized.
’tkr+ m対象(4)が接続されているときには、
開始するステーIプ(ζ相当するように、あらかじめ゛
機械の動作をそこまで進めておけはよい。'tkr+m When target (4) is connected,
It is a good idea to advance the machine's operation to that stage in advance so that it corresponds to the starting stage I (ζ).
な、1づ、上記実施例ではステータスの記憶場所がCP
UQ23内部になっているが、周辺装ff1(1)など
、他の・牌素に持たせても変わりかないことはいうまで
もない。In the above embodiment, the storage location of the status is CP.
Although it is inside the UQ23, it goes without saying that it will not make any difference if it is included in other tiles such as the peripheral ff1 (1).
り上の様に、この発明によればCP Hのステータス情
報を記憶するステータス記憶メモリを設けたので、プロ
グラムを修正する度に同じ入力指令を何誓も与えなおす
といら手[ム1が省け、テハ、、、 り時間の大幅な短
縮ができるとともに、誤った入力指@を与えることがな
く、又、途中の一部分のステリプのみデバ・リグができ
るなどデバー、グ効罵が向tするという効果がある。As described above, according to the present invention, since a status storage memory is provided for storing status information of the CPH, it is possible to avoid the trouble of re-supplying the same input command several times each time the program is modified. In addition to being able to significantly shorten the processing time, there is no need to give incorrect input fingers, and it is said that the debugging effect is improved, such as being able to debug/rig only a part of the steps in the middle. effective.
第1図はこの発明の一実施例によるプログラマブルコン
トローラを示す制御系の構成図、第2図は従来のプログ
うマブルコントローラを示す制御系の構成図である。
図において、(2b)はステータス記憶メモリである。
なお、図中、同一符号は同一、又は相当部分を示す。FIG. 1 is a block diagram of a control system showing a programmable controller according to an embodiment of the present invention, and FIG. 2 is a block diagram of a control system showing a conventional programmable controller. In the figure, (2b) is a status storage memory. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
から入力指令が与えられる度に変化するCPUのステー
タス情報を記憶すると共に所定入力指令により上記ステ
ータス情報をCPUに出力するステータス記憶メモリを
備えたことを特徴とするプログラマブルコントローラ。It is characterized by comprising a status storage memory that executes a sequence program created in advance, stores CPU status information that changes every time an input command is given from the outside, and outputs the status information to the CPU in accordance with a predetermined input command. A programmable controller.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62270982A JPH0719170B2 (en) | 1987-10-27 | 1987-10-27 | Method of debugging sequence program in programmable controller |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62270982A JPH0719170B2 (en) | 1987-10-27 | 1987-10-27 | Method of debugging sequence program in programmable controller |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH01112403A true JPH01112403A (en) | 1989-05-01 |
JPH0719170B2 JPH0719170B2 (en) | 1995-03-06 |
Family
ID=17493743
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62270982A Expired - Lifetime JPH0719170B2 (en) | 1987-10-27 | 1987-10-27 | Method of debugging sequence program in programmable controller |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0719170B2 (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56147205A (en) * | 1980-04-15 | 1981-11-16 | Mitsubishi Electric Corp | Software automatic testing system of programmable controller |
JPS57147763A (en) * | 1981-03-07 | 1982-09-11 | Fujitsu Ltd | Evacuation restoring system of test program |
JPS59208607A (en) * | 1983-05-12 | 1984-11-27 | Toshiba Corp | Simple simulator for debugging |
JPS6155749A (en) * | 1984-08-28 | 1986-03-20 | Oki Electric Ind Co Ltd | Information processor |
-
1987
- 1987-10-27 JP JP62270982A patent/JPH0719170B2/en not_active Expired - Lifetime
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56147205A (en) * | 1980-04-15 | 1981-11-16 | Mitsubishi Electric Corp | Software automatic testing system of programmable controller |
JPS57147763A (en) * | 1981-03-07 | 1982-09-11 | Fujitsu Ltd | Evacuation restoring system of test program |
JPS59208607A (en) * | 1983-05-12 | 1984-11-27 | Toshiba Corp | Simple simulator for debugging |
JPS6155749A (en) * | 1984-08-28 | 1986-03-20 | Oki Electric Ind Co Ltd | Information processor |
Also Published As
Publication number | Publication date |
---|---|
JPH0719170B2 (en) | 1995-03-06 |
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