JPH01112284A - Data processing - Google Patents

Abstract

PURPOSE: To sharply reduce the number of data to be stored, to reduce memory capacity and to quickly execute also the updating of a screen by specifying the number of continuous dots by length data when the same color is continued. CONSTITUTION: Two data, i.e., color data CC for specifying a dot color and length data LC indicating the number of continuous dots in the color data CC, are prepared, each data including discrimination information ATR for discriminating its sort are stored in a memory. When the same color is continued, the number of continuous dots is specified by the length data LC. Consequently the number of data to be stored is sharply reduced, memory capacity can be reduced while holding high resolution and the contents of a screen can be quickly rewritten by rewriting the length data LC.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a data processing method suitable for use when compressing and storing data in a display memory or when decompressing data that has been compressed and stored.

``Prior Art'' In video game devices or other devices that require display, it is necessary to move the image displayed on the display vertically or horizontally. Conventionally, by changing the start address of the display area in memory, scrolling 1 downward was performed, and
When moving the screen from side to side (horizontally), all data in the display area is rewritten.

Furthermore, horizontal scrolling is possible in units of words or bytes (16 or 8 hits).

``Problems to be Solved by the Present Invention'' The point is that when the resolution is high, the amount of display data increases, so it takes time to rewrite it, but if it is not rewritten within a specified time, the state in the middle of rewriting will be is displayed, and the screen does not display normally.

For example, there is a reality that game programs must be rewritten within 1/60 second. On the other hand, in addition to higher resolution, storage of display data for many screens due to the influence of application programs causes the problem of extremely large memory capacity.

This invention was made in view of the circumstances mentioned above, and provides a data processing method that does not limit memory capacity even at high resolution and can update the screen at high speed. The purpose is to

[Means for solving the problem] In order to solve the problem mentioned above, the first invention uses color data that indicates the color of a dot, and a length that indicates how many consecutive dots this color data has. The present invention is characterized in that two types of data are created, and identification information for identifying the type is provided in each of the data and stored in the memory.

Further, in the second invention, when reading data from the memory in addition to the process described in 1, the color data is repeatedly output according to the length indicated by the length data. I have to.

In the third invention, in addition to the processing in the first invention, when reading data from the memory, one part of the display surface is
A series of data corresponding to the line is read out sequentially, and further,
The line from which data reading is to be started is specified.

In a fourth invention, in addition to the processing in the first invention, when reading data from the memory, one part of the display surface is
While sequentially reading out a series of data corresponding to the line,
A list of start addresses for each line is created, and reading is performed in accordance with the order specified by this list.

"Operation" When the same color is continuous, the number of consecutive dots can be specified using length data, so the amount of data to be stored can be significantly reduced.

Furthermore, in the second aspect of the invention, compressed and stored data is expanded, thereby obtaining display data similar to a normal bitmap. In the third invention, since the reading start line is specified, the screen is scrolled in the vertical direction. In the fourth invention, since the start address in the list is specified, images can be synthesized line by line and images can be converted at high speed without rewriting display data.

"Embodiments" Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention. In the figure, l is a CPU that operates based on a predetermined program (I-gram), and 2 is a knock oscillator that outputs a vertical synchronizing signal VSYN, a horizontal synchronizing signal r, Hr+syN and a display period based on a dot clock CK output from a knock oscillator. Display timing signal D' indicating
This is the timing generation circuit for creating I”MG.3
is a row address counter indicating the row address in VRAM (video It AM), and horizontal synchronization signal 1-
ISYN is counted up and the vertical synchronization signal VS
It is designed to be reset by YN. 4 is a column address register into which a predetermined value is written by CPU 1.

This is a V IRAM interface that exchanges data between the CPU 5 and the VRAM 10, and also supplies address data output from the CP tJ I to the VRAM. Note that the display processor 6 is configured with the above configuration.

Next, we will explain the display data written to VT and ΔMIO. FIG. 2(A) is a diagram showing the format of data written to 8M10 by VT. As shown in this figure, the data consists of 8 bits, the 7th bit of which is an attribute bit ATR indicating the attribute (type) of the data. Attribute pit AT
When R is "0", a color code CC is written in the 0th to 6th bits as shown in FIG. 2(b). The color code CC is data that specifies the color of the dots on the display surface. The display color specification using the color code CC is actually indirect, and the color code CC is used by the conversion unit 1 described later.
2 (see FIG. 1) into color data, and this color data determines the actual display color. In addition, when the attribute bit ATT' (is "l", the length code LC is written in the 0th to 6th bits. The length code LC indicates how many dots of the same color are consecutive in the line direction. Here, FIG. 3 is a diagram showing an example of the storage state of VRAMl0.The example shown in the figure is an example of display data corresponding to a part of one line, and The symbol CC with ``7'' indicates the color code, the symbol LC indicates the length coat, and the attribute hit l-ATR is not shown.In the figure, the color code CCo is written in the byte Bl,
Byte B2 following this data also contains color coat CC1. In other words, for color code CCo, the length coat is not banded. this is,
This is a case where the color coat CCo is not continuous on the display surface and adjacent dots are of different colors. Part-time job B
2) - In B3, a length code LC is written, and the color indicated by the color code cc is continuous even if it is in the length indicated by the length code 1' LC. It shows that In addition, color coat Cc2 is written in byte B4, and the following high) B5
．． Both are long in B6: '-to'T-C2o, L C
21 is written on it. This is color code 1'C
C7 is a case where the color is extremely long and continuous, and the length is 1' b c . This is a case where the color code Oc2 is continuous over the total length of , , LC7,. As described above, in this embodiment, when the length codes are consecutive for the Aro color code, that is, when the value of the attribute bit ATR is "1" consecutively, the length codes of these length codes are This means that the color code is continuous over the total length.

- By adopting the data writing method described above, the amount of data writing when the same color is continuous can be significantly reduced.

Next, FIG. 4 is a diagram showing the storage contents of VRAM10. As shown in the figure, VRAMl0 is 2560 × 512
It has eight sets of column memory cell arrays and 512-bit serial renosters SR. The data in units of 8 bits (see FIG. 2) stored in the VRAM10 is bit D from the memory cell array of the drawing element 11[j toward the back. , Dr...B7 are stored respectively. in this case,
The shape of the display data in each line (the display period part in a scanning line is defined as one line) differs from line to line as shown in the figure. This is because the amount of data is significantly reduced for lines with more continuous display colors. ”2-record register SR is a register that performs parallel/serial conversion, and is a register that performs parallel/serial conversion.
The column address specified by is set as the first address of NOFF) and OUT.

The norial register SR performs a noft-out operation according to the serial clock SC supplied from the data decompression circuit 11, and converts the output data into serial data 5Do-3.
I) 7 and is supplied to the data decompression circuit 11.

Here, the timing of each control signal is shown in Figure 5 for the VRAMho (-) ζ cycle (J) cycle. In the figure, the signals or terminals marked with - (bar) are row acknowledges, but the following In the explanatory text, when a symbol indicates a signal or terminal, a - symbol is used to indicate that the signal is active.If there is no - symbol, it is high active.

-RAS and -CAS shown in FIGS.
lobe signal, -DT/-OE,
W E iJ, data and output enable row address RΔ (see figure (E)) are −CΔs, −
wi> is "1°" and -DT/-01ε is "o".The row address strobe signal - is loaded into the memory at 1 at the rising edge of RAS.

At this point, one line of data corresponding to the row address is transferred to each serial register SR. S
It is transferred to R (see diagonal lines in Figure 4). Next, column address CA is applied to column address strobe signal -C.
At the time when AS falls, it is taken into the memory and stored in the serial registers SR and SF (setting this column address 0Δ as the starting address of not-out).

Next, FIG. 6 is a circuit diagram showing the configuration of the data expansion circuit 11. In the figure, 20 is a town counter, and when a "1" signal is supplied to the terminal LI), the input terminal Di
~Die is taken in, and this taken-in value is counted down based on the dot clock CK supplied to the tarlock terminal -CLI (input terminal 1 of the down counter 20)io-Di. ．． are supplied with norial data Sl) and -Sl) 6, respectively. Input terminal ■]1o-D16 (
” Color code CC or length coat L shown in Figure 2
C is supplied, 1, it is like that. The down counter 20 ('') outputs the count contents from the terminal Q.-Q6, and when the count contents become 0-1, the terminal -Z I
) to '0'' (C). Also, clear terminal -C
The display timing signal DTMG is supplied to the L and R. Reference numerals 1 and 21 are D type flip-flops, and when a '1' signal is supplied to the terminals r-L and D, a dot is generated. When CK falls, the signal SD'r supplied to terminal I is taken in.

4゛naitsuji, Atribiko I Hira+- A T R
Incorporate. Also, 1) type flip-flop 21 [J clock input terminal -CLK is supplied with dot clock cK, clear terminal -C 1. , R are supplied with a display timing signal I) TMG. 23
is a circuit board, one input end of which is connected to the output end Q of the D type flip-flop 21, and the other input end connected to the terminals -7 and D of the down counter 20. The output signal SE of the gate 23 is supplied to the down counter 20 and the load terminal LD of the D-type flip-flop 2I. 25 is a register, and when the dot clock CK supplied to the clock terminal -CLK falls while the I'' signal is supplied to the rotor terminal LD, the signal is supplied to the input terminal Dio=Die. Load the current signal.In this case, load terminal L
A signal outputted from the output terminal Q of the D type flip-flop 21 is inverted by an inverter 24 and supplied to the input terminal D, and a dot clock CK is supplied to the clock input terminal CLK. In this register 25,
Only the color code 1' CC is written by the operation described later. The color code CC output from the register 25 is supplied to the conversion section I2 shown in FIG. 26 is an AND gate which performs a logical product of the dot clock CK, the display timing signal DTMG and the signal SE, and its output signal is supplied to the norial registers SR and SR as the serial clock SC.

Next, a conversion unit 12 (not shown in FIG. 1) includes a look-up table for converting the color code CC supplied from the data decompression circuit into color data, and a video signal for creating an analog video signal based on this color data. It consists of a signal generation section, etc.

Here, color data is a digital signal that specifies each part of RGB (red, clean, blue) signals,
Specify the display color directly. Further, the look-up table provides a one-to-one correspondence between the color code CC and color data, and by rewriting its contents, the correspondence relationship between the two can be arbitrarily changed. The video signal output from the converter 12 is sent to the crt'I' display device 13.
be supplied to.

Next, the operation of this embodiment having the configuration described in -4- will be explained.

First, the display processor 6 writes display data into the VRAM10 according to the data format shown in FIG. Then, when drawing, the timing generation circuit 2
, vertical synchronization signal VSYN, horizontal synchronization signal HSYN
and generates a display timing signal DTMG. When the synchronization signals VSYN and H8YN are generated, the contents of the row address counter 3 are incremented in accordance with the synchronization on the display surface, and the data of the line corresponding to the count contents is stored in the serial register 5R1SR shown in FIG.
Transferred to...

On the other hand, when the display timing signal DTMG rises, the reset of the down counter 20 and the D type flip-flop 21 in the data expansion circuit It is released. At this time, since the signal SE is a "1" signal, the tiger clock signal CK is outputted from the game 1.26 as the shift clock SC. This results in
From the serial registers SR, SR, etc. shown in Fig. 4,
The data of the line stored at this point is output.

Now, suppose that data is stored in the serial registers SR, SR, etc. in the order shown in FIG. 3, and at time t5 shown in FIG.
) Assuming that TMG rises, in this case, the shift clock SC rises after time L5.
At time 16, the serial registers SR, SL'(
From Color Coat CCo and Atrivi Coat Hill-A
TR (value "0°') is output. Among these, the color code CCo is supplied to the input terminal of the down counter 20, and the attribi code bit 1-A T Tl is supplied to the input terminal of the D type flip-flop 21. is supplied to the
When the I.t clock CK falls at time L7, the color coat CCo or the down counter 20 and the attribi coat hit ΔTR (value "0") are fetched into the D type flip-flop 21, respectively. As a result, the output signal SE of the Nantes gate 23 maintains the "1°" signal, and the shift clock SC continues to be output from the Nantes gate 26. Then, at time t8, the shift clock SC
When "2" rises, the next data in the serial register 5R9SR, the color code CC, and the attribi code 1-ATR (value "0") are output. Then, these data (", 01J description Similarly to the above case, at time t9 when the clock CK falls, the down counter 20 and the D type flip-flop 2I each take in the signal. Furthermore, at time t8 when the dot clock CK falls, the register 25 takes in data, so the color code CCo is supplied to the converter 12 at this time (see FIG. 7(g)). Then, at the rise of the next shift clock SC, the length codes LC, (
value n+) and atripicote pisotoΔRT (value “l”
) are read out, and these data are stored at time 1. In to, down counter 20
and D type flip-flop 21, respectively. Also, at time tlo, color coat CC3
is taken into the register 25 and further supplied to the conversion section I2.

At time too, when the content of the ■) type flip-flop 21 becomes "1", the output signal of the input/output 24 becomes a "0" signal, and loading of the register 25 is prohibited.

That is, loading of the register 25 is possible only when the content of the D-type flip-flop 2I is 0". Also, when the content of the D-type flip-flop 21 becomes 1" at time ↑, . Signal S
F becomes "0", and as a result, the shift clock SC output from the anime game 1/26 is stopped (7th
(See figures (c) and (e)). This allows you to read data from serial registers SR and SR・! ? 1-1
1 +l: , done. Furthermore, as the signal S E becomes 0, the load terminal l71) of the down counter 20 and the D-type flip-flop 21 becomes 0, and subsequent data loading is prohibited.
When the dot clock CK falls at I+, the value nl is decremented by 1 and becomes r n , -1-, I (see FIG. 7(d)).

Thereafter, the contents of the down counter 20 are counted down in the same manner every time CK falls, and at time t12 shown in FIG. When becomes 10'', the signal SB becomes a 1'' signal, which enables the D-type flip-flop 21 and the down counter 20 to be loaded, and the AND gate 26 outputs the shift clock SC. In this way, While the down counter 20 is counting down (at a certain time).

~t12), transmission of the shift clock SC is stopped, and reading of data from the norial registers SR, SR, . . . is stopped. And shift clock SC
At time j+3 when dot clock CK rises, color code CC2 and attribute bit ATR (value "0") are output from serial registers SR, SR, .
, it is taken into the down counter 20 and the D type flip-flop 21. Attribute bit A
When TR (value "0") is taken into the D-type flip-flop 21, the output signal of the D-type flip-flop 21 becomes a "0" signal again as shown in FIG.

When the output signal of the D-type flip-flop 2=19-1 becomes "0", the output signal of the inverter 24 becomes the "1" signal, so that the register 25 becomes ready for loading. Then, at time tls, when the knock CK falls, the color coat CC is taken into the register 25 and output to the converter I2 (see FIG. 7(G)). In this way, time! : 10-t
14, the color code CC is input from the register 25.
1 is output, and then the next color code CC7 is output at time t'5 of IJ1. Part 1. Color coat CC
Even while 1 continues to be output, the dot clock C
Since K is being output continuously, the CRT display device 13
The dots displayed in the ``-'' period have the color corresponding to the color code 1' CG. In addition, the number (nl+I) of dots obtained by adding 1 to the value of the length data LC, are added as the color specified by the color code C01, and in the end, the dots displayed by the color code CC1 are (n, +2) Continuous.

On the other hand, at the rising edge of the shift clock SC after time 114, the attribute bit ARTC value is set to "1" from the serial register SR,5=20-R...
) and the length code LC2o (value n, ) are output, and at time L15 when the dot clock CK falls, the ``--signed data is taken into the D type flip-flop 21 and the down counter 20. Therefore, time 1,5
, the content of D type flip-flop 2I is “I”
, and loading of register 25 is prohibited at this point. As a result, the length code LC7° taken in by the down counter 20 is not loaded into the register 25. Further, at time t15, when the length code LC7o is loaded into the down counter 20, the "l" signal is output from the terminal -ZD, and as a result, both input terminals of the AND gate 23 become "1" level, and the signal SE falls. Signal S
When E falls (see FIG. 7(C)), loading of the down counter 20 and the D-type flip-flop 21 is prohibited, and the shift clock SC is stopped again (see FIG. 7(P)). Thereafter, until time [16, time t, . ~t+.

The operation is similar to that of the down counter 20, and the value "n,
' is counted down. Then, when the dot clock CK falls at the time the, the count value of the down counter 20 becomes IQ -1, and the terminal -Z
0°" signal should be output from D.

At this time, the content of the D type flip-flop 21 is “I
”, one input terminal of the AND gate 23 becomes a “0” signal and the signal SE rises. Therefore, the down counter 20 and the D type flip-flop 21 become ready for loading, and the ant gate 26 outputs the down clock SC. When the soft clock SC is output, the serial registers SR and S
Attribute bit ART (value “l”) and length code LC3l (value n3) are output from R (see FIG. 3), and these are transferred to the D type flip-flop at time LI7.
It is taken into the J tube 21 and the down counter 20.

When the attribute bit A R'I' with the value "1" is taken into the D type flip-flop 2I, the signal SE
falls again, and loading of the D type flip-flop 21 and down counter 20 is prohibited, and
Sending of the soft clock SC is prohibited. in this way,
The soft clock SC is stopped again just by calling the length data LC2I, and the down counter 20 enters the load inhibited state immediately after loading the length data LC2+. Then, from time tI7 to time 1.18, the value "n3" in the down counter 20 is counted down. At time t19, the dot clock CK falls and the count value of the down counter 20 becomes "0".
'', the signal SE rises, thereby enabling the D-type flip-flop 21 and the down counter 20 to be loaded, and the shift clock SC is sent out. Then, in the same manner as in the previous case, the color code CC3 and attribute bit ART (value "0") in the serial registers SR and SR are read out, and these data are supplied to the down counter 20 and the D type flip-flop 21. Further, at time t,.

At this point, the signal is supplied from the register 25 to the converter 12 .

Then, as shown in FIG. 7(G), time elapses from time L15. However, the color code CC3 continues to be output.

During this period, the dot clock CK continues to be output, so the dots displayed on the CRT display device 13 have the color corresponding to the color code CC3 during the period 1. In other words, the sum of the six values of length data LC2゜ and LC7 plus 1 plus 1, that is, ((rz+I) -+-(n3'
The number of dots corresponding to +-1) +1) is the color code C.
The color is specified by C7.

As described above, according to the above embodiment, the data stored in the VRAM 1O is compressed as shown in FIGS. 3 and 4, so that the amount of data to be stored is significantly reduced. Furthermore, at the time of reading, the color code CC is expanded by the data expansion circuit 11 in correspondence with the length data LC, so that the same display as when display data is stored using a bitmap is performed.

In addition, in the above embodiment, the value of length data LC is 1.
However, depending on the circuit configuration, it is also possible to add the same number of color codes as the length data LC. Furthermore, if an up counter is used instead of the down counter 20, the length data L
It is also possible to add color code data of a number corresponding to the complement of C or complement +1.

In addition, in the embodiment 1, the Norial clock SC
However, if you use a VRAM that does not have a serial register SR, you can achieve the same function by stopping the display address count-up. realizable.

Next, a second embodiment of the invention will be described. 8th
The figure is a block diagram showing the configuration of a second embodiment of the invention. Note that this embodiment is an embodiment in which multiple images are displayed.

In FIG. 8, 20 to 22 are VRAMs, each having the same configuration as the VRAM10 shown in FIG. 4. In this case, background data indicating the background is stored in the VRAM 20, scene data indicating the foreground (t(F7) is stored in the VRAM2+, and data on objects such as cars (j) is stored in the VRAM 22.

Reference numerals 23 to 25 each designate a data expansion circuit, which has the same structure as data expansion circuit II shown in FIG. 27~
28 are look-up tables, each of which converts the color code CC output from the data decompression circuits 23 to 25 into color data.

Two are priority control circuits, and lookup table 2
The color data output from 6 to 28 are combined and output in accordance with a predetermined priority order. In this case, the order of priority is object, 1171 view, and background. therefore,
The foreground should be displayed in front of the background, and the object (J) should be displayed in front of the foreground (and background).

30 is an I)/A converter, and a priority control circuit 2
9 converts the output color data to analog cube color data.

Here, FIG. 1O shows an example of a multiplexed image, in which a background such as the sky, clouds, mountains, hills, etc., a foreground such as a road, and objects such as a car, q, tree, etc. are superimposed. FIG. 9 shows v rtΔM
22, the illustrated areas DE,
Do is the display area. Areas DE and Do are display areas corresponding to one screen, and are used alternately to properly display moving images. Zunai Tsuchi,
Assuming that a display is performed based on the memory contents of area DE in a certain frame, during this display period,
A screen with a slightly shifted position of the image to be moved and displayed is prepared in area I)O. Then, after the display in area DE is finished, a display based on the contents of area Do is performed,
While this display is being performed, the next screen is prepared in area DB. Then, a display based on the contents of area DE is performed. After that, when the above operation is repeated, screens in which the position of the image to be moved is shifted little by little are displayed one after another, and as a result, the image is displayed as if it were moving.In this case, the area of the VRAM 20 The background data is in the areas corresponding to DE and DO, and the areas DE and DO of VRAM21 are
Foreground data is written in the corresponding portions, and these images are eventually combined to create a display in which trees and cars move within the image as shown in FIG. 10.

I-As mentioned above, regarding the moving display of object data,
This is done each time the various object data stored in other areas of the VRAM 22 are written in the display areas DII>, I) and O by changing their positions as appropriate.

Also, if the object is moving away or close to you,
Characters are selected so that they become smaller (or larger) and written alternately in predetermined positions in areas DE and Do. Note that such a display method is a method commonly used in the past.

Next, the background and foreground in this embodiment are rewritten as follows.

For example, change the μY of the foreground (31 If there is one color from both ends of the screen to the road edge, rewrite the length data for these color coats as appropriate for areas DE and Do. As a result, the distance between the road edge and the screen The distance between both ends changes, and the way the road curves changes.Similarly, the width of the road can be changed to any color by changing the length data of the color code of the road part. reactor. You can also rewrite the background in exactly the same way, such as clouds,
The position and shape of mountains etc. can be rewritten at high speed. In this rewriting, only the length data is rewritten, so the effect is equivalent to extremely high-speed rewriting.

Note that scrolling of the background and foreground in the vertical direction is performed by rewriting the row address at which reading starts.

By the way, rewriting the background and foreground using the conventional method is
All the bitmap data that makes up the background and foreground had to be rewritten, which required a lot of time, but according to this embodiment, only the length data is rewritten, so rewriting is extremely fast. can be carried out. As described above, in this embodiment, multiple images can be displayed and the background and foreground can be updated at high speed.

Next, a third embodiment of the present invention will be described with reference to FIG. 11.

In the figure, 30 is a VRAM and has a pointer PO inside. The pointer PO is a pointer in which a large number of line start address data consisting of a ['7 address RΔ and a column address CA are stored to form a list. A plurality of screen data SAO and SAI are contained in VRAM2O.

SA2. SA3, etc. are stored, and the line start address data ('', which is stored in the pointer PO), is data indicating the start address of a series of data corresponding to each line in these screen data SAO, SAI, SA2, SA3. (A dot is added to the diagram to indicate the starting address.)

In the illustrated example, the screen data SAO includes only color code data without length data (data similar to the human map), screen data SΔ1°SA2 . SA3 is data based on the method shown in FIG. 3, and the row address is updated for each series of data corresponding to the ■ line.

Furthermore, the screen data SΔ3 is data based on the method shown in FIG. 3, in which a series of data corresponding to the ■ line is continuously stored in a predetermined area. A data storage method such as this screen data SA3 is the most efficient data storage method when using the method according to the present invention.

Note that the VRAM 30 in this embodiment has a serial register like the VRAMIO (see FIG. 1) described above.

Next, 50 and 51 shown in FIG. 11 are a row address register and a first column address register, respectively, and C
A row address and a column address are each written from the PUI. In this case, the CPU outputs the pointer address to the VRAM 30, reads out the row address and column address written in the part of the pointer address, and writes the row address register 50.
and is written to the first column address register 51. Further, the row address register 50 is configured to be loaded with address data when a strobe signal RA-Wl'' (T) is supplied.

53 and 5/I are a row address counter and a second column address register into which the row address in the row address register 50 and the column address in the first column address register 5I are respectively loaded. The second output and address data 54 are respectively supplied to the address bus of the VRAM 30. D FP ] is a flip-flop, the "0°' signal is supplied to the D input terminal, the horizontal synchronization signal T-ISYN is supplied to the clock input terminal, and the horizontal synchronization signal 1.(S Y At the falling edge of N, the "0 signal" of the D input terminal is taken in. Also, the flip-flop I) F F I should be supplied to the S input terminal. When RΔW RT rises, it will be set. It has become. ANI is the Q output signal of the flip-flop D F F I and the horizontal synchronization signal T5Y.
It is an AND gate that takes the logical product of N, and this ant game
When the output signal of 1-A N + becomes “1°’ signal, the second
Column address register 54 performs the loading. Also, the output of Antogame 1/ANI is 4゛ro "1".

The signal is also supplied to the load terminal of the waitress counter 53 via the OR gate ORI. ORGATE ORI
The vertical synchronizing signal VSYN is supplied to the other input terminal of the jυj signal VSYN.
"Please supply the signal. Also, the row address counter 53
is the horizontal synchronizing signal T-TSY at the clock input terminal C.
N is supplied, and the horizontal synchronizing signal 1-[S Y N rises-
The count is increased every time the number goes up by 1. However, the row address counter 53 is connected to the load terminal ■ from the clock input terminal C.

has priority, and when a load operation and a count operation conflict, the count! ^ It is stopped and the rotor is performed.

Next, the operation of this embodiment according to the configuration described in -1- will be explained. First, the CPU I appropriately writes necessary column addresses and row addresses to the pointer PO.

When drawing is performed based on any of the screen data SAO to SA2, the row address and column address of the first line of any of the screen data SΔ0 to SΔ2 are read from the pointer PO, and the column address is first read out from the pointer PO. Write to the first column address register 5I, and then write the row address to the row address register 5o. In this case, when writing is performed to the row address register 5o, the signal II A -W RT is output, so the solve flop DFFI is set. Then, when the horizontal synchronizing signal 1-ISYN rises, the two-signed address is loaded into the row address counter 53 and the second column address register 54.

Furthermore, when the horizontal synchronization signal HSYN falls, the flip-flop DPI'I is reset. Then, when the row address and column address are loaded into the row address stack 53 and the second column register 54, respectively, the data on the line corresponding to these addresses is read out and written into a serial register (not shown). Then, the data in the serial register is read out in accordance with the dot clock, and display control similar to that of the first embodiment described above is performed. In this way, the first line is displayed.

Then, in displaying subsequent lines, the CPU 1 does not read from the pointer PO and does not write to the row address register 50 and the first column register 51. As a result, the flip-flop DFP I remains reset, and the horizontal synchronization signal HSY
Even if N is output, address data is not loaded into the row address counter 53 and the second column register 54.

However, the row address counter 53 uses the horizontal synchronization signal H
It is incremented each time SYN is output. As a result, lines whose row addresses are incremented are sequentially read out from the VRAM 30, and display is performed according to the data on these lines. This control is performed because the screen data SAO to SA2 have the same column address at the top address of each line, as shown in FIG. 11, and the row addresses increase successively. Then, when the display of one screen is finished, the vertical synchronization signal VS
When YN is output, the row address power counter 53 loads the row address in the row address register 50 (first written row address: row address of the first line). As a result, the line to be displayed returns to the first line, and the same operation as described above is repeated, and as a result,
Display is performed using any one of the screen data SAO to SA2.

In the second control, the address data read from the pointer is written to the row address register 50 and the first column register 51 only at the beginning, and then the required line is read by incrementing the row address counter 53. There is.

Next, a case will be described in which display control is performed using screen data SA3. When reading out each line in the screen data SAa corresponding to the screen, it is necessary to sequentially designate the start address of the next line, as can be seen from FIG. Therefore, the CPUI sequentially writes the start address of each line to the pointer PO in advance, and
A is incremented, and the next [l address and color 1 address are sequentially read from the pointer PO and written to the row address register 50 and the first column address register 5I. As a result, the horizontal synchronization signal HS Y N
Each time the address data is output, the row address counter 53 and the second column address register 54 are loaded with address data, and the line of the address is read out. Display processing based on the screen data SA3 is performed as described below.

Furthermore, according to the configuration described in item 1, the screen data SAO to SA
It is possible to combine each data in 3 line by line.

For example, the second 1/3 of the screen is based on the screen data SAO, the middle 1/3 of the screen is based on the screen data SAI, and
The lower 1/3 of the screen can be drawn using the screen data SA3. In this case, screen data 5AO1SAI
, SA3 (the line corresponding to 1/3 of the screen can be extracted from any part of the screen data), and for the screen data SAO and SAI, pointer I points to the start address of the first line of the extracted part. )0
In screen data SA3, the start address of each line of the extracted portion is written to pointer 1)0. Then, the CPU] reads the appropriate row address and column address from the pointer I]0 and writes them to the row address register 50 and the first column address register 51, thereby writing each screen data SAO, S
It should be possible to display a mixture of AD and SA3 content on the screen.

In addition, the above-mentioned mixed display of screen data can be performed using the pointer PO.
By appropriately selecting the address to be written to from each screen data SAO to SA3, it is possible to write to each line frj arbitrarily, so combinations of extremely different types of lines are possible. However, even when using one screen data, it is extremely easy to perform unconventional display control such as changing the order of lines, since there is no restriction on the number of lines written in the order of the line start address written to the pointer PO. You can do it.

Furthermore, since the contents of the pointer address PO can be rewritten at high speed, the combination and arrangement of lines can be changed instantaneously. Therefore, images can be updated extremely quickly.

Furthermore, as can be seen from the above embodiment, bitmap data (SAO) and compressed data (SA1
．． Even if SA2.9A3) are mixed, images can be displayed in exactly the same way without distinguishing the processing.

``Effects of the Invention'' As explained hereinafter, according to the first to fourth aspects of the invention, the color data indicating the color of the dot and the length data indicating the number of consecutive dots of this color data are used. create a seed, and
Identification information for identifying the type is provided in each data and stored in the memory, so if the same color is consecutive, you can specify the number of consecutive colors using the length data. Therefore, the amount of data to be stored can be significantly reduced, and the memory capacity can be reduced even at high resolution. Also, by rewriting the length data, the screen can be rewritten at high speed.

Further, in the second invention, when reading data from the memory in addition to the process described in -, 1) the color data is repeatedly outputted according to the length indicated by the length data in 71. As a result, the compressed and stored data is decompressed, and display data similar to a normal human map is obtained.

In a third aspect of the invention, in addition to the first aspect of the invention, when reading data from the memory, one part of the display surface is
A series of data corresponding to the line is read out sequentially, and further,
Since the line from which data reading is to be started is specified, scrolling in the vertical direction of the screen can be easily performed.

In the fourth invention, in addition to the processing in the first invention, when reading data from the memory, a series of data corresponding to one line on the display surface is sequentially read out, and each line By creating a list of start addresses and specifying the start address in this list, you can combine images for each line (=40-) and update images at high speed without rewriting the display data. It can be carried out.

[Brief explanation of the drawing]

FIG. 1 shows the configuration of an embodiment of the present invention, and FIG. 2 shows the format of data stored in VRAM10 in the same embodiment. Figure 3 is VR
FIG. 4 is a diagram showing an example of data to be stored in AM10, FIG. 4 is a diagram showing data read processing of VRAM10 according to the same embodiment, FIG. 7 is a timing diagram showing the operation of the data expansion circuit 11, and FIG. 8 is an off-line diagram showing the configuration of the second embodiment. FIG. 9 is a diagram showing the drawing process of object data in the same embodiment, and FIG. 10 is an example of a multiplexed image.
4-Front view, and FIG. 11 is a block diagram showing the configuration of the third embodiment. I... CPU, 2... Timing generation circuit,
3...RA counter, 4...CA Renstar, 5...
・・V RAM interface, IO-=-VR
A.M. I1...data expansion circuit, I2...conversion section, A
TR...atrich coat (identification information), cc...
Color coat (color data), LC...Length code (
length data), PO... pointer (list).

Claims (7)

[Claims] (1) Create two types of color data: color data that indicates the color of the dot, and length data that indicates how many consecutive dots of this color data, and identify information that identifies the type in each of the data. 1. A data processing method, comprising: providing a data processing method and storing the data in a memory. (2) The data processing method according to claim 1, wherein the color data and the length data are written into the memory in any order and in any combination. (3) The data processing method according to claim 1, wherein the memory is prepared for a plurality of surfaces for multiple images, and data is written for each surface. (4) Create two types of data: color data that indicates the color of the dot, and length data that indicates how many consecutive dots of this color data, and identify information that identifies the type in each of the data. 1. A data processing method, wherein the color data is stored in a memory, and when reading data from the memory, the color data is repeatedly output in accordance with the length indicated by the length data. (5) Prepare the memory for multiple images, write data for each side, and when reading data, write data for each side that is repeatedly output according to the length data. 5. The data processing method according to claim 4, wherein the data processing method is performed in accordance with the priority order of the data processing method. (6) Create two types of data: color data that indicates the color of the dots, and length data that indicates how many consecutive dots of this color data, and identify information that identifies the type in each of the data. When data is read from the memory, a series of data corresponding to one line on the display surface is sequentially read out, and furthermore, it is specified from which line data reading is to be started. data processing method. (7) Create two types of data: color data that indicates the color of the dots, and length data that indicates how many consecutive dots of this color data, and identify information that identifies the type in each of the data. When reading data from the memory, a series of data corresponding to one line on the display surface is sequentially read out, a list of start addresses for each line is created, and a list of start addresses for each line is created, and when data is read from the memory, a list of start addresses for each line is created and A data processing method characterized by reading data in order.