JPH01111324A - Method for forming fine pattern - Google Patents

Method for forming fine pattern

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Publication number
JPH01111324A
JPH01111324A JP62269678A JP26967887A JPH01111324A JP H01111324 A JPH01111324 A JP H01111324A JP 62269678 A JP62269678 A JP 62269678A JP 26967887 A JP26967887 A JP 26967887A JP H01111324 A JPH01111324 A JP H01111324A
Authority
JP
Japan
Prior art keywords
film
resist
pattern
organic
electron beam
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62269678A
Other languages
Japanese (ja)
Other versions
JP2610898B2 (en
Inventor
Kazuhiko Hashimoto
和彦 橋本
Taichi Koizumi
太一 小泉
Kenji Kawakita
川北 憲司
Noboru Nomura
登 野村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP62269678A priority Critical patent/JP2610898B2/en
Priority to KR1019880013966A priority patent/KR930000293B1/en
Priority to US07/262,871 priority patent/US4936951A/en
Publication of JPH01111324A publication Critical patent/JPH01111324A/en
Priority to US07/520,654 priority patent/US4976818A/en
Application granted granted Critical
Publication of JP2610898B2 publication Critical patent/JP2610898B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Drying Of Semiconductors (AREA)
  • Electron Beam Exposure (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To prevent electrons from charging up to be generated at the time of exposure with an electron beam and to accurately form a fine pattern by reducing an intermediate layer of multilayer resist, an organic polysiloxane film with reducing gas ions. CONSTITUTION:Before an electron beam direct lithography is conducted by a multilayer resist method, conduction rate is raised by ion irradiating gas 4 having reducing power, such as H2, Co, SO2, etc., to an organic polysiloxane film SOG 3 being an intermediate layer. Then, when the SOG 3 is coated with an electron beam resist 5 and exposed, excess electrons are transmitted to the SOG 3 having high conduction rate. Thus, it can prevent the electrons from charging up, and an accurate fine pattern lithography can be performed by an electron beam 6 on the multilayer resist.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、多層レジスト法を用いて、半導体基板上に電
子ビーム直接描画により、高精度微細加工用の任意のレ
ジストパターンを形成する微細パターン形成方法に関す
るものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a micropattern forming method for forming an arbitrary resist pattern for high-precision microfabrication on a semiconductor substrate by electron beam direct writing using a multilayer resist method. It is related to.

従来の技術 従来、IC及びLSI等の製造においては、紫外線を用
いたホトリソグラフィーによってパターン形成を行なっ
ている。近年LSI素子のパターン寸法の微細化、また
、ムSZCの製造に伴ない。
2. Description of the Related Art Conventionally, in the manufacture of ICs, LSIs, etc., patterns have been formed by photolithography using ultraviolet rays. In recent years, the pattern dimensions of LSI devices have become finer, and mu SZCs have been manufactured.

電子ビーム直接描画技術を用いるようになってきている
。パターン形成に使用される電子ビームレジストは一般
に、耐ドライエツチ性が悪いため、また、電子ビームの
基板からの反射による近接効果によりパターンの解像性
が悪くなるため、電子ビームリソグラフィーにおいては
多層レジスト法が使用されている。多層レジスト法のう
ち、二層レジストは高分子有機膜上に、それとミキシン
グをおこさないシリコン含有レジストを塗布した構造を
しておシ、また、三層レジストは二層レジストの高分子
有機膜とレジストとの間に無機膜、主にSi、02、ま
たは有機ポリシロキサン膜(soG)を形成した構造を
しており、どちらも基板からの電子の反射による近接効
果を押える働きをしている。しかし、これらの多層レジ
ストでは有機膜が非常に厚いため、新たな問題点が生じ
てくる。それは絶縁膜による電子のチャージ・アップ効
果である。電子が絶縁膜であるレジスト、有機膜。
Electron beam direct writing techniques are increasingly being used. Electron beam resists used for pattern formation generally have poor dry etch resistance, and pattern resolution deteriorates due to the proximity effect caused by reflection of the electron beam from the substrate. Therefore, multilayer resist methods are used in electron beam lithography. is used. Among the multilayer resist methods, the two-layer resist has a structure in which a silicon-containing resist that does not mix with the organic polymer film is coated on top of the organic polymer film, and the three-layer resist has a structure in which the organic polymer film of the two-layer resist is coated with a silicon-containing resist that does not mix with the organic film. It has a structure in which an inorganic film, mainly Si, 02, or organic polysiloxane film (soG) is formed between the resist and the resist, and both serve to suppress the proximity effect due to reflection of electrons from the substrate. However, because the organic films in these multilayer resists are very thick, new problems arise. This is the effect of charging up electrons due to the insulating film. Resist, organic film where electrons are an insulating film.

SiO□中に蓄積してくると、パターンのずれ、パッテ
ィングエラー、フィールドのずれ等、パターンを正確に
描画することが出来なくなってしまう。
When it accumulates in SiO□, it becomes impossible to accurately draw a pattern due to pattern deviation, putting error, field deviation, etc.

発明が解決しようとする問題点 上記の様に、電子線リソグラフィーにおいては、電子線
レジストの耐ドライエツチ性の低さ、電子による近接効
果等の問題点があシ、多層レジストにより解決を図ろう
としている。しかし、多層レジスト法を用いると、レジ
スト等の絶縁膜が厚いため、電子のチャージ・アップ効
果が顕著にあられれてきてパターンの正確な描画が困難
になってくる。この多層レジストにおける問題点を解決
するために、中間層に金属、特に導伝率の高い金属薄膜
を用いている。例えば、SOG、SiO□にかわりSi
、W、ム1等の金属薄膜を中間層として用いることによ
り、チャージアップを防ぎ正確なパターン描画を行うこ
とができる。しかし、レジストプロセスに金属を用いる
ため、コンタミネーションの問題がある。また、金属を
スパッタ蒸着しなければならないのでプロセスが複雑、
困難となり、パターン形成後の金属のエツチング、金部
の剥離等のプロセス上の問題点、描画においては、金属
薄膜があるため基板からの反射二次電子の減少により位
置合わせが困難になる等の問題点が発生する。
Problems to be Solved by the Invention As mentioned above, in electron beam lithography, there are problems such as the low dry etch resistance of the electron beam resist and the proximity effect due to electrons. There is. However, when a multilayer resist method is used, since the insulating film such as the resist is thick, the charge-up effect of electrons becomes noticeable, making it difficult to accurately draw a pattern. In order to solve this problem with multilayer resists, metals, particularly metal thin films with high conductivity, are used for the intermediate layer. For example, Si instead of SOG, SiO□
By using a metal thin film such as , W, Mu1, etc. as an intermediate layer, charge-up can be prevented and accurate pattern drawing can be performed. However, since metal is used in the resist process, there is a problem of contamination. In addition, the process is complicated because the metal must be sputter-deposited.
There are process problems such as etching of the metal after pattern formation and peeling off of the metal parts, and during writing, there are problems such as alignment difficulties due to a decrease in secondary electrons reflected from the substrate due to the presence of a thin metal film. A problem occurs.

問題点を解決するための手段 本発明は、多層レジスト法を用いて電子ビーム直接描画
を行う前に、中間層であるsoeまたはシリコン含有レ
ジストを還元することによって、導伝率を上げて電子ビ
ーム露光を行い、電子によるチャージ、アップをなくし
、正確な微細パターンを形成することができる方法であ
る。
Means for Solving the Problems The present invention provides a method for increasing conductivity by reducing the interlayer SOE or silicon-containing resist before performing electron beam direct writing using a multilayer resist method. This is a method that performs exposure, eliminates charge and build-up caused by electrons, and can form accurate fine patterns.

SOGまたはシリコン含有レジストを還元する方法とし
て、まず還元力のあるガス例えば”2+co、so2等
のガスをイオン照射することにより。
As a method for reducing SOG or silicon-containing resist, first, ion irradiation is performed with a gas having reducing power, such as 2+CO, SO2, etc.

導伝率を上げることができる。その後、SOG上に通常
の電子線レジストを塗布し、露光すると、余分の電子は
導伝率の高いSOGを伝わっていく。
Conductivity can be increased. After that, when a normal electron beam resist is applied onto the SOG and exposed, the excess electrons travel through the highly conductive SOG.

また、二層レジストの場合、シリコン含有レジスト自身
の導伝率が高いので、レジストを伝わっていくので、電
子のチャージ、アップはなくなり、正確な微細なバター
/を多層レジスト上に電子線を用いて描画することがで
きる。
In addition, in the case of a two-layer resist, since the conductivity of the silicon-containing resist itself is high, the electrons will not be charged or increased as they will pass through the resist, and an accurate fine butter/butter will be applied to the multilayer resist using an electron beam. You can draw with

また、別の還元方法として、還元性のある溶液。Another method of reduction is using a reducing solution.

例えばRCHO(R=Hor、CH3)、(COOH)
2H2S O3等の溶液をSOGまたはシリコン含有レ
ジスト上に滴下し1表面を還元して導伝率を上げる。そ
うすることによって、チャージ、アップのない正確なパ
ターン描画を行うことができる。
For example, RCHO (R=Hor, CH3), (COOH)
A solution such as 2H2S03 is dropped onto the SOG or silicon-containing resist to reduce the surface and increase the conductivity. By doing so, accurate pattern drawing can be performed without charge or up.

作用 本発明は前記したプロセスにより、三層レジストの中間
層としての有機ポリシロキサン膜(30G)または二層
レジストの上層レジストとしてのシリコン含有レジスト
にイオン照射、または還元性溶液処理することにより、
導伝率を上げ、電子ビーム露光時のチャージアップを防
ぎ、正確な微細パターンを形成することができる。従っ
て、前記プロセスは、多層レジストを用いて電子線直接
描画を行う時、正確なパターン描画に有効に作用する。
Operation The present invention uses the process described above to ion irradiate or treat with a reducing solution an organic polysiloxane film (30G) as an intermediate layer of a three-layer resist or a silicon-containing resist as an upper layer resist of a two-layer resist.
It increases conductivity, prevents charge-up during electron beam exposure, and allows formation of accurate fine patterns. Therefore, the above process is effective for accurate pattern writing when direct electron beam writing is performed using a multilayer resist.

実施例 本発明の一実施例を第1図に示す。半導体基板1上に下
層膜2として高分子有機膜を塗布し、この上に5OG3
をスピンコードした。この上から加速電圧4oxv、ド
ーズ量I X 10 ” io n!!/crIでH+
イオンを全面−括照射した(a)。次に、上層レジスト
としてPMM人レジスト5をスピンコードシ、加速電圧
2oKV、ドーズ量1’OOμC/cIIで電子線露光
を行った(b)。H+イオン照射されたSoGは導伝率
が高くなっている。メチルイソブチルケトン(MIBK
)とイソプロピルアルコール(IPA)の混合液で60
秒間現像を行った所、正確な微細パターンがあられれた
(C)。このレジストパターン5Pをマスクとして、中
間層SOGをドライエツチングし、下層膜をエツチング
して。
Embodiment An embodiment of the present invention is shown in FIG. A polymeric organic film is applied as a lower layer film 2 on a semiconductor substrate 1, and 5OG3 is applied on top of this.
was spin coded. From above, H+ with acceleration voltage 4oxv and dose amount I x 10” ion!!/crI
The entire surface was irradiated with ions (a). Next, electron beam exposure was performed using the PMM resist 5 as an upper layer resist at a spin code, an acceleration voltage of 2 kV, and a dose of 1'OOμC/cII (b). SoG irradiated with H+ ions has high conductivity. Methyl isobutyl ketone (MIBK
) and isopropyl alcohol (IPA).
When the film was developed for a second, an accurate fine pattern was formed (C). Using this resist pattern 5P as a mask, the intermediate layer SOG is dry etched, and the lower layer film is etched.

垂直形状の微細パターンを形成することができた((1
)。
It was possible to form vertical fine patterns ((1
).

以上のように、本実施例によれば、中間層SOG+ にHイオン照射した三層レジストを用いて電子線直接描
画を行うと、チャージアップを防ぐことができ、正確な
微細パターンを形成することができる。また、H+イオ
ン以外に、還元性のあるガス、例えばco、so□等で
あればいずれでもよい。
As described above, according to this example, when electron beam direct writing is performed using a three-layer resist in which the intermediate layer SOG+ is irradiated with H ions, charge-up can be prevented and accurate fine patterns can be formed. Can be done. In addition to H+ ions, any reducing gas such as co, so□, etc. may be used.

次に本発明の第2の実施例を第2図に示す。半導体基板
1上に下層膜2を塗布し、この上に5OG3をスピンコ
ードした。この上にアルデヒド液14を滴下し、1分間
放置し、スピン乾燥した(a)。次に、上層レジストと
してPMM人レジスト16をスピンコードし、加速電圧
20KV、ドーズ量1oOμC/crilで電子線露光
を行った(b)。アルデヒド液で表面処理したSOGは
導伝率が高くなっているので、MlBKとIPAの混合
液で、60秒間現像を行った所、正確な微細パターンが
あられれた(0)。このレジストパターン16Pをマス
クとして中間層SOG、下層膜をドライエツチングして
垂直形状の微細パターンを形成することができた(d)
Next, a second embodiment of the present invention is shown in FIG. A lower layer film 2 was applied onto a semiconductor substrate 1, and 5OG3 was spin-coded thereon. Aldehyde solution 14 was dropped onto this, left to stand for 1 minute, and spin-dried (a). Next, a PMM human resist 16 was spin-coded as an upper layer resist, and electron beam exposure was performed at an acceleration voltage of 20 KV and a dose of 10OμC/cril (b). SOG surface-treated with an aldehyde solution has a high conductivity, so when it was developed for 60 seconds with a mixed solution of MIBK and IPA, an accurate fine pattern was formed (0). Using this resist pattern 16P as a mask, the intermediate layer SOG and the lower layer film were dry-etched to form a vertical fine pattern (d)
.

以上のように1本実施例によれば、中間層SOGにアル
デヒド液で表面処理した三層レジストを用いて電子線直
接描画を行うと、チャージアップを防ぐことができ、正
確な微細パターンを形成することができる。また、アル
デヒド液以外に還元剤として作用する(COoH)2.
H2SO3等であればいずれでもよい。
As described above, according to this embodiment, if electron beam direct writing is performed using a three-layer resist surface-treated with an aldehyde solution on the intermediate layer SOG, charge-up can be prevented and accurate fine patterns can be formed. can do. In addition to the aldehyde solution, it also acts as a reducing agent (COoH)2.
Any H2SO3 etc. may be used.

次に本発明の第3の実施例を第3図に示す。半導体基板
1上に下層膜2を塗布し、この上に上層レジストとして
シリコン含有レジストであるSIRをスピンコードした
。この上から加速電圧40KV。
Next, a third embodiment of the present invention is shown in FIG. A lower layer film 2 was applied onto a semiconductor substrate 1, and SIR, which is a silicon-containing resist, was spin-coded thereon as an upper layer resist. Accelerating voltage is 40KV from above.

ドーズ量1x 1o14ions/d(でH+イオンを
全面−括照射した(IL)。次に、加速電圧20KV、
ドーズ量10μC/crlで電子線露光を行った(b)
。H+イオン照射されたシリコン含有レジストは導伝率
が高くなっているので、専用現像液で30秒間現像を行
った所、正確な微細パターンがあられれた(C)。この
レジストパターン25Pをマスクとして下層膜をドライ
エツチングして垂直形状の微細パターンを形成すること
ができた(d)。
The entire surface was irradiated with H+ ions (IL) at a dose of 1x 1o14 ions/d. Next, an accelerating voltage of 20 KV,
Electron beam exposure was performed at a dose of 10 μC/crl (b)
. Since the silicon-containing resist irradiated with H+ ions has a high conductivity, when it was developed for 30 seconds with a special developer, an accurate fine pattern was formed (C). Using this resist pattern 25P as a mask, the underlying film was dry-etched to form a vertical fine pattern (d).

以上のように、本実施例によれば、二層レジストの上層
レジストにH+イオンまたは他の還元性ガスイオンを照
射することによって、チャージ、アップを防ぐことがで
き、正確な微細パターンを形成することができる。また
、アルデヒド液等の還元剤として作用するもので表面処
理をしても同様の効果を得ることができる。
As described above, according to this embodiment, by irradiating the upper resist of the two-layer resist with H+ ions or other reducing gas ions, charging and build-up can be prevented and accurate fine patterns can be formed. be able to. The same effect can also be obtained by surface treatment with something that acts as a reducing agent, such as an aldehyde solution.

発明の詳細 な説明したように、本発明によれば、三層レジストの中
間層、有機ポリシロキサン膜を還元ガスイオンまたは還
元溶剤によって還元することによシ、電子線露光時にお
こるチャージ、アップを防ぐことができ、正確な微細パ
ターンを形成することができる。また、二層レジストの
上層シリコン含有レジストを同様に還元することによっ
て、露光時のチャージ、アップを防ぎ、正確な微細パタ
ーンを形成することができ、超高密度集積回路の製造に
大きく寄与するととができる。
As described in detail, according to the present invention, the intermediate layer of the three-layer resist, the organic polysiloxane film, is reduced by reducing gas ions or reducing solvent, thereby reducing the charge and build-up that occurs during electron beam exposure. can be prevented and accurate fine patterns can be formed. In addition, by similarly reducing the upper silicon-containing resist of the two-layer resist, it is possible to prevent charging and build-up during exposure and form accurate fine patterns, which will greatly contribute to the production of ultra-high-density integrated circuits. Can be done.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の第1の実施例方法の工程断面図、第2
図は同第2の実施例方法の工程断面図、第3図は同第3
の実施例方法の工程断面図である。 1・・・・・・半導体基板、2・・・・・・下層膜、3
・・・・・・SOG。 4.24・・・・・・Hイオン、6.16・・・・・・
PMMAレジスト、6・・・・・・電子線、14・・・
・・・アルデヒド液。 23・・・・・・SNRレジスト。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名7−
−−卒導イ苓基ネ更   、Sl’−PrM門ハレジス
ト第 1121−
FIG. 1 is a process sectional view of the first embodiment method of the present invention, and the second
The figure is a cross-sectional view of the process of the second embodiment method, and FIG.
FIG. 3 is a process cross-sectional view of an example method. 1... Semiconductor substrate, 2... Lower layer film, 3
...SOG. 4.24...H ion, 6.16...
PMMA resist, 6...Electron beam, 14...
...Aldehyde liquid. 23...SNR resist. Name of agent: Patent attorney Toshio Nakao and 1 other person7-
--Graduation I Reiki Nesara, Sl'-PrM Gate No. 1121-

Claims (3)

【特許請求の範囲】[Claims] (1)半導体基板上に高分子有機膜を塗布し熱処理する
工程と、上記高分子有機膜上に有機ポリシロキサン膜を
塗布し熱処理した後、水素、一酸化炭素、シラン亜硫酸
等の還元力のあるガスを上記有機ポリシロキサン膜上に
イオン照射する工程と、上記有機ポリシロキサン膜上に
電子線レジスト膜を塗布し熱処理する工程と、上記レジ
スト膜にパターンを描画し現像する工程と、上記レジス
トパターンをマスクとして上記有機ポリシロキサン膜を
エッチングする工程と、上記有機ポリシロキサンパター
ンをマスクとして上記高分子有機膜をエッチングする工
程とから成る微細パターン形成方法。
(1) The process of applying a polymeric organic film on a semiconductor substrate and heat-treating it, and after applying an organic polysiloxane film on the above-mentioned polymeric organic film and heat-treating it, remove the reducing power of hydrogen, carbon monoxide, silane sulfite, etc. A step of ion-irradiating a certain gas onto the organic polysiloxane film, a step of applying an electron beam resist film onto the organic polysiloxane film and heat-treating it, a step of drawing a pattern on the resist film and developing it, and a step of drawing a pattern on the resist film and developing the resist film. A method for forming a fine pattern comprising the steps of: etching the organic polysiloxane film using the pattern as a mask; and etching the organic polymer film using the organic polysiloxane pattern as a mask.
(2)半導体基板上に高分子有機膜を塗布し熱処理する
工程と、上記高分子有機膜上に有機ポリシロキサン膜を
塗布し熱処理した後、アルデヒド、シュウ酸、亜硫酸等
の還元性のある溶液を上記有機ポリシロキサン膜上に滴
下し上記溶液を除去する工程と、上記有機ポリシロキサ
ン膜上に電子線レジスト膜を塗布し熱処理する工程と、
上記レジスト膜にパターンを描画し現像する工程と、上
記レジストパターンをマスクとして上記有機ポリシロキ
サン膜をエッチングする工程と、上記有機ポリシロキサ
ンパターンをマスクとして上記高分子有機膜をエッチン
グする工程とから成る微細パターン形成方法。
(2) A process of applying a polymeric organic film on a semiconductor substrate and heat-treating it, and after applying an organic polysiloxane film on the polymeric organic film and heat-treating it, a reducing solution such as aldehyde, oxalic acid, sulfite, etc. a step of dropping the solution onto the organic polysiloxane film and removing the solution; a step of applying an electron beam resist film on the organic polysiloxane film and heat-treating the film;
The steps include drawing a pattern on the resist film and developing it, etching the organic polysiloxane film using the resist pattern as a mask, and etching the polymeric organic film using the organic polysiloxane pattern as a mask. Fine pattern formation method.
(3)半導体基板上に高分子有機膜を塗布し、熱処理す
る工程と、上記高分子有機膜上に電子線レジストとして
のシリコン含有レジストを塗布し熱処理した後、上記レ
ジスト上に還元力のあるガスをイオン照射するか、また
は、還元性のある溶液を滴下する工程と、上記レジスト
膜にパターンを描画し現像する工程と、上記レジストパ
ターンをマスクとして上記高分子有機膜をエッチングす
る工程とから成る微細パターン形成方法。
(3) A step of applying a polymeric organic film on a semiconductor substrate and heat-treating it, and applying a silicon-containing resist as an electron beam resist on the above-mentioned polymeric organic film and heat-treating it, and then applying a reducing power on the resist. A step of irradiating gas with ions or dropping a reducing solution; a step of drawing and developing a pattern on the resist film; and a step of etching the polymeric organic film using the resist pattern as a mask. A method for forming fine patterns.
JP62269678A 1987-10-26 1987-10-26 Fine pattern forming method Expired - Lifetime JP2610898B2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP62269678A JP2610898B2 (en) 1987-10-26 1987-10-26 Fine pattern forming method
KR1019880013966A KR930000293B1 (en) 1987-10-26 1988-10-26 Fine pattern forming method
US07/262,871 US4936951A (en) 1987-10-26 1988-10-26 Method of reducing proximity effect in electron beam resists
US07/520,654 US4976818A (en) 1987-10-26 1990-04-24 Fine pattern forming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62269678A JP2610898B2 (en) 1987-10-26 1987-10-26 Fine pattern forming method

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JPH01111324A true JPH01111324A (en) 1989-04-28
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980031110A (en) * 1996-10-31 1998-07-25 김영환 Method of forming photoresist pattern of semiconductor device
WO2005093800A1 (en) * 2004-03-25 2005-10-06 Matsushita Electric Industrial Co., Ltd. Method of impurity introduction, impurity introduction apparatus and semiconductor device produced with use of the method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59105637A (en) * 1982-12-09 1984-06-19 Fujitsu Ltd Forming method of resist pattern
JPS6053023A (en) * 1983-09-02 1985-03-26 Hitachi Ltd Formation of pattern
JPS60262151A (en) * 1984-06-11 1985-12-25 Nippon Telegr & Teleph Corp <Ntt> Intermediate layer for 3-layer resist material and method for using it

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59105637A (en) * 1982-12-09 1984-06-19 Fujitsu Ltd Forming method of resist pattern
JPS6053023A (en) * 1983-09-02 1985-03-26 Hitachi Ltd Formation of pattern
JPS60262151A (en) * 1984-06-11 1985-12-25 Nippon Telegr & Teleph Corp <Ntt> Intermediate layer for 3-layer resist material and method for using it

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980031110A (en) * 1996-10-31 1998-07-25 김영환 Method of forming photoresist pattern of semiconductor device
WO2005093800A1 (en) * 2004-03-25 2005-10-06 Matsushita Electric Industrial Co., Ltd. Method of impurity introduction, impurity introduction apparatus and semiconductor device produced with use of the method
US7682954B2 (en) 2004-03-25 2010-03-23 Panasonic Corporation Method of impurity introduction, impurity introduction apparatus and semiconductor device produced with use of the method

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