JPH01110743A - Device for testing integrated circuit - Google Patents
Device for testing integrated circuitInfo
- Publication number
- JPH01110743A JPH01110743A JP62267329A JP26732987A JPH01110743A JP H01110743 A JPH01110743 A JP H01110743A JP 62267329 A JP62267329 A JP 62267329A JP 26732987 A JP26732987 A JP 26732987A JP H01110743 A JPH01110743 A JP H01110743A
- Authority
- JP
- Japan
- Prior art keywords
- light
- circuit
- integrated circuit
- under test
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 55
- 238000006243 chemical reaction Methods 0.000 claims abstract description 22
- 239000000523 sample Substances 0.000 claims abstract description 20
- 239000013078 crystal Substances 0.000 claims abstract description 16
- 238000005070 sampling Methods 0.000 claims abstract description 11
- 230000005684 electric field Effects 0.000 claims abstract description 4
- 230000001678 irradiating effect Effects 0.000 claims abstract 5
- 230000003287 optical effect Effects 0.000 claims description 7
- 230000008878 coupling Effects 0.000 claims 1
- 238000010168 coupling process Methods 0.000 claims 1
- 238000005859 coupling reaction Methods 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 10
- 238000012545 processing Methods 0.000 abstract description 4
- 238000005259 measurement Methods 0.000 abstract description 3
- 238000004806 packaging method and process Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 8
- 239000010408 film Substances 0.000 description 7
- 239000002184 metal Substances 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000011156 evaluation Methods 0.000 description 2
- 230000010287 polarization Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Measuring Instrument Details And Bridges, And Automatic Balancing Devices (AREA)
- Measurement Of Current Or Voltage (AREA)
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
〔従来の技術〕
集積回路あるいはデバイスの試験において、超高速の集
積回路の内部ノードを非接触で試験する手段としては、
パルス中の狭い光パルスをサンプリングパルスとして用
いる方法が知られている。[Detailed Description of the Invention] [Prior Art] In testing integrated circuits or devices, the following methods are used to non-contact test internal nodes of ultra-high-speed integrated circuits:
A method is known in which a narrow optical pulse in a pulse is used as a sampling pulse.
すなわち、電気光学結晶を被テスト回路の近傍に配置し
、極短光パルスを該結晶に照射すると、被テスト回路内
の電気信号の大きさに応じて、照射した光の偏光状態が
変化するという原理を利用して試験する方法は、現代最
も時間分解能が高いものとして位置付られている。これ
らの詳しい情報については、例えば、IEEE J、
Quant。In other words, when an electro-optic crystal is placed near a circuit under test and an extremely short pulse of light is irradiated onto the crystal, the polarization state of the irradiated light changes depending on the magnitude of the electrical signal within the circuit under test. Testing methods that utilize this principle are positioned as having the highest temporal resolution in modern times. For detailed information on these, see, for example, IEEE J,
Quant.
Elec、1986年1月、P69〜78のJ。Elec, January 1986, P69-78 J.
A、Valdmanis等による論文からも知ることが
できる。This can also be learned from the paper by A. Valdmanis et al.
一方これまでの集積回路あるいはデバイスのテストにお
いては、外部の信号発生器からの電気信号を同軸ケーブ
ルによつセ被試験回路(以下被テスト回路と略称す)を
実装したストリップ線路からなる平面回路(以下実装基
板と略称す)に導き、該ストリップ線路からボンディン
グワイヤ等を介して、被テスト回路に印加して駆動し、
その測定結果を同様の経路で見る方法が一般的である。On the other hand, in conventional tests of integrated circuits or devices, electrical signals from an external signal generator are transmitted via a coaxial cable to a planar circuit consisting of a strip line on which the circuit under test (hereinafter referred to as the circuit under test) is mounted. (hereinafter abbreviated as a mounting board), and drives the circuit under test by applying it from the strip line via a bonding wire or the like,
A common method is to view the measurement results using a similar route.
しかし実装基板上のA1等の金属導体からなるストリッ
プ線路を伝搬するパルス信号は、線路上を伝搬するに伴
ない、たとえばパルス中が10ピコ秒程度の電気パルス
は3〜5mmの距離を伝搬すると、パルス中が分散によ
り、その約2〜3倍に広がるという問題がある。これは
、たとえば超伝導材料によるストリップ線路を回路とし
て用いた場合でも、1〜2ピコ秒の巾のパルスでは、1
0mm程度の伝搬距離でその巾が2〜3倍に広がること
がわかっている。これらの詳しい情報は、たとえばJ、
Appl、Phys、1978年1月、P2O3〜31
4のRoL、Kautzによる論文からも得ることがで
きる。However, as the pulse signal propagates on a strip line made of a metal conductor such as A1 on a mounting board, as it propagates on the line, for example, an electric pulse with a duration of about 10 picoseconds propagates over a distance of 3 to 5 mm. , there is a problem in that the pulse is spread by about 2 to 3 times due to dispersion. For example, even if a strip line made of superconducting material is used as a circuit, a pulse with a width of 1 to 2 picoseconds will cause 1
It is known that the width increases two to three times with a propagation distance of about 0 mm. Detailed information on these can be found, for example, in J.
Appl, Phys, January 1978, P2O3~31
It can also be obtained from the paper by Kautz, RoL 4.
また、同軸ケーブルと実装基板上のストリップ線路との
接続部でのインピーダンス不整合や伝搬モードの変換に
伴う電気信号の反射の問題がある。Additionally, there are problems with impedance mismatching at the connection between the coaxial cable and the strip line on the mounting board and reflection of electrical signals due to propagation mode conversion.
この接続部のコネクタの性能も従来の試験装置の帯域を
決定する上のひとつの大きな問題となっている。The performance of this connector is also a major issue in determining the bandwidth of conventional test equipment.
以上のように、これまでの方法では試験信号の被テスト
回路への入力方法に問題があり、実装基板上の回路と接
続部との特性により測定帯域が支配され、超高速、高周
波で動作する集積回路やデバイスの被テスト回路固有の
性能を直接的に評価することができなかった。As described above, the conventional methods have problems with the method of inputting the test signal to the circuit under test, and the measurement band is dominated by the characteristics of the circuit on the mounting board and the connection part, and it operates at ultra-high speed and high frequency. It has not been possible to directly evaluate the inherent performance of the circuit under test in integrated circuits and devices.
従って試験信号の入力から出力までの、ピコ秒からサブ
ピコ秒に及ぶ時間分解能で集積回路の試験を行うために
は、集積回路のチップの被テスト回路の極く近傍に電気
信号の発生源を設けるか、もしくはオンチップで電気信
号を発生するかして被テスト回路に試験信号を供給する
ことが必要であった。Therefore, in order to test integrated circuits with a time resolution ranging from picoseconds to sub-picoseconds from test signal input to output, an electrical signal generation source must be placed very close to the circuit under test on the integrated circuit chip. It was necessary to supply the test signal to the circuit under test by either generating an electrical signal on-chip.
上述の如く集積回路あるいはデバイスの任意の内部ノー
ドをサブピコ秒に迫る時間分解能でモニタできる手段が
あっても、集積回路あるいはデバイスを駆動する高速の
電気信号を伴わないかぎり、前述したように集積回路本
来の性能を知ることは不可能である。。即ち、高速で動
作する回路の試験技術においては、高速の入力信号を生
成して被テスト回路に供給する装置と、回路内部の波形
をモニタする装置を、統合した装置が要求される。Even if there is a means to monitor any internal node of an integrated circuit or device with a time resolution approaching sub-picoseconds, as described above, unless a high-speed electrical signal is used to drive the integrated circuit or device, the integrated circuit cannot be monitored. It is impossible to know the true performance. . That is, in testing techniques for circuits operating at high speed, a device is required that integrates a device that generates a high-speed input signal and supplies it to the circuit under test, and a device that monitors the waveform inside the circuit.
本発明の目的は、集積回路あるいはデバイス固有の特性
をl T Hz程度の帯域まで、人力の実装等の帯域制
限に形容されずに評価するための試験装置を提供するこ
とである。このためチップ上の被テスト回路の電気パル
ス信号の導入と、チップ内への高速な電気パルス信号の
測定を光パルスを用いて同時に行う装置で、電気光学結
晶よりなるプローブの構成法、被テスト回路の実装法、
およびマルチ光パルスの照射法等の技術を統合化した。An object of the present invention is to provide a test apparatus for evaluating characteristics specific to an integrated circuit or a device up to a band of approximately 1 T Hz without being limited by band limitations such as manual implementation. For this purpose, it is a device that simultaneously introduces electrical pulse signals from the circuit under test on the chip and measures high-speed electrical pulse signals into the chip using optical pulses. circuit implementation method,
and integrated technologies such as multi-light pulse irradiation method.
本発明を実施例に従い添付図面を参照しながら詳細に説
明する。The present invention will be described in detail according to embodiments and with reference to the accompanying drawings.
第1図は本発明の実施例の概略を示すブロック図である
。図において1は光源、2は分波・遅延回路部、3は照
射位置制御部、4は対物レンズ、5はプローブ部、6は
位置制御部、7は光電気変換部、8はステージ、9は電
源、10はモニタ装置、11は信号処理部、12はデイ
スプレィ装置である。第2図は第1図のプローブ部5、
光電気変換部7の詳細図である。図において13はチッ
プ、14は被テスト回路、15は基板、16は光電気変
換回路、17はポンディングワイヤ、18は電気光学結
晶、19は反射膜、20は支持体、21は電歪素子であ
る。FIG. 1 is a block diagram schematically showing an embodiment of the present invention. In the figure, 1 is a light source, 2 is a branching/delay circuit section, 3 is an irradiation position control section, 4 is an objective lens, 5 is a probe section, 6 is a position control section, 7 is a photoelectric conversion section, 8 is a stage, 9 1 is a power supply, 10 is a monitor device, 11 is a signal processing section, and 12 is a display device. Figure 2 shows the probe section 5 of Figure 1,
FIG. 7 is a detailed diagram of the photoelectric conversion section 7. FIG. In the figure, 13 is a chip, 14 is a circuit under test, 15 is a substrate, 16 is a photoelectric conversion circuit, 17 is a bonding wire, 18 is an electro-optic crystal, 19 is a reflective film, 20 is a support, and 21 is an electrostrictive element. It is.
光源1より発生した短い光パルスは、分波・遅延回路部
2により、マルチ光パルスとして所望の相対的の遅延が
与えられたトリガ光T1.T2・・・およびサンプリン
グ光Sl、S2・・・に分波され、照射位置制御部3を
経て、対物レンズ4、プローブ部5を通過して光電気変
換部7に投影される。A short optical pulse generated from the light source 1 is converted into a trigger light T1. T2... and sampling light Sl, S2..., which pass through the irradiation position control section 3, the objective lens 4, and the probe section 5, and are projected onto the photoelectric conversion section 7.
このうちトリガ光Tは光電気変換部7の光電気変換回路
16に投影され、定電気パルスに変換しパルス信号とし
て被テスト回路14に入力される。Of these, the trigger light T is projected onto the photoelectric conversion circuit 16 of the photoelectric conversion section 7, converted into a constant electric pulse, and inputted to the circuit under test 14 as a pulse signal.
一方サンプリング光Sは被テスト回路14に対向して配
置された電気光学結晶18よりなるプローブ部5の平面
上の任意の点を照射するように制御される。同時にモニ
タ装置IOによって照射行位置およびビームスポット径
の確認がなされる。電気光学結晶18よりなるプローブ
5の被テスト回路側の面の一部或いは全面には誘電体多
層膜からなる反射膜19が形成され、サンプリング光S
t。On the other hand, the sampling light S is controlled so as to irradiate any point on the plane of the probe section 5 made of an electro-optic crystal 18 disposed facing the circuit under test 14. At the same time, the irradiation row position and beam spot diameter are confirmed by the monitor device IO. A reflective film 19 made of a dielectric multilayer film is formed on a part or the entire surface of the test circuit side of the probe 5 made of an electro-optic crystal 18, and reflects the sampling light S.
t.
S2は被テスト回路14の電界の状況に対応して反射し
た反射光R1,R2となり、対物レンズ4を再び通過し
た後、信号処理部11において、光信号としであるいは
その後の光電気変換装置によって電気信号して処理され
る。そこで処理された結果はデイスプレィ装置12に出
力される。光電気変換回路およびテスト回路7を駆動す
るための電源9がある。また、プローブ部5と被テスト
回路14との距離との感度を決める重要なファクタとな
っており位置制御部6の電歪素子21によって精密かつ
再現性よく制御される。S2 becomes reflected lights R1 and R2 that are reflected according to the electric field condition of the circuit under test 14, and after passing through the objective lens 4 again, they are converted into optical signals in the signal processing section 11 or by a subsequent photoelectric conversion device. It is processed as an electrical signal. The processed results are output to the display device 12. There is a power supply 9 for driving the opto-electric conversion circuit and test circuit 7 . Further, the distance between the probe section 5 and the circuit under test 14 is an important factor that determines the sensitivity, and is controlled precisely and reproducibly by the electrostrictive element 21 of the position control section 6.
第2図において基板15の中央部には被テスト回路14
を持ったチップ13が置かれ、A1等の金属からなるポ
ンディングワイヤ17を介して、前記光電気変換回路1
6と結合される。チップ13上の被テスト回路14に対
向し支持体20の先端に接着された電気光学結晶18が
配置され、底面全面に亘つ°ζ前記の反射膜19が施さ
れる。プローブ部5は電歪素子21により支えられて、
対物レンズ4あるいは照射位置制御部3に固定される。In FIG. 2, the circuit under test 14 is located in the center of the board 15.
The photoelectric conversion circuit 1 is placed on a chip 13 having
Combined with 6. An electro-optic crystal 18 is placed facing the circuit under test 14 on the chip 13 and bonded to the tip of the support 20, and the above-mentioned reflective film 19 is applied over the entire bottom surface. The probe section 5 is supported by an electrostrictive element 21,
It is fixed to the objective lens 4 or the irradiation position control section 3.
プローブ部5と被テスト回路14との微小距離の制御は
この電歪素子21に電圧を印加することによってサブミ
クロンの分解能でなされる。The minute distance between the probe section 5 and the circuit under test 14 is controlled with submicron resolution by applying a voltage to the electrostrictive element 21.
尚、サンプリングの原理は、電気光学結晶18に入り込
んだ被テスト回路14により発生する信号電界の一部に
より同結晶の屈折率を変化させ、その変化撤を光パルス
の偏波状態の変化として読み取るという、前述のVal
dmanis等の方法に従っており、第1図のパルス光
の径路中には、偏光子、検光子、波長板等を必要とする
が、簡単のため省略している。現代高速光検出器におい
ては100GIIz以上の帯域で動作し、高速光導電素
子はサブピコ秒の電気パルスの発生が可能である。マル
チ光パルスビームを用いることにより、任意の巾をもっ
たパルス列の発生も可能となろう。The principle of sampling is that the refractive index of the crystal is changed by a portion of the signal electric field generated by the circuit under test 14 that has entered the electro-optic crystal 18, and the change is read as a change in the polarization state of the optical pulse. The above-mentioned Val
dmanis et al., and requires a polarizer, analyzer, wave plate, etc. in the path of the pulsed light in FIG. 1, but these are omitted for simplicity. Modern high-speed photodetectors operate in bands of 100 GIIz or higher, and high-speed photoconductive elements are capable of generating sub-picosecond electrical pulses. By using a multi-optical pulse beam, it would also be possible to generate pulse trains with arbitrary widths.
ボンディングワイヤ上の伝搬はP、G、May等(Ul
trafast Phenomena V。The propagation on the bonding wire is based on P, G, May, etc. (Ul
trafast Phenomena V.
Springer−Verlag社P120−122)
によれば、250μm程度であれば、3ピコ秒の11】
の電気パルスを歪なく伝えることが可能であることが実
験的に示されており、帯域中質GHzまでの評価には十
分使用可能である。Springer-Verlag P120-122)
According to 11] of 3 picoseconds if it is about 250 μm
It has been experimentally shown that it is possible to transmit electrical pulses without distortion, and it can be used satisfactorily for evaluations up to mid-range GHz.
第3図は本発明の他の実施例の詳細図である。FIG. 3 is a detailed view of another embodiment of the invention.
図において22は金属配線である。第2図と異なるのは
、被テスト回路14と光電気変換回路16とを同一チッ
プ13上にモノリシック化する点と、被テスト回路14
のあるチップ13の直上面のみを覆う反射膜19を施し
、トリガ光Tはその周辺の反射膜のない部分を通過して
チップ13周辺の光電気変換回路16を励起する点であ
る。被テスト回路14と光電気変換回路16とは、同一
平面上で薄膜の金属配線22により短い距離結ばれてい
るので第2図の例に比べ、インダクタンスも小さく、よ
り一層の広帯域化が可能となる。In the figure, 22 is a metal wiring. The difference from FIG. 2 is that the circuit under test 14 and the photoelectric conversion circuit 16 are monolithically formed on the same chip 13, and the circuit under test 14
A reflective film 19 is applied to cover only the surface immediately above a certain chip 13, and the trigger light T passes through the area without the reflective film in the periphery and excites the photoelectric conversion circuit 16 around the chip 13. Since the circuit under test 14 and the photoelectric conversion circuit 16 are connected over a short distance on the same plane by a thin film metal wiring 22, the inductance is smaller than in the example shown in FIG. 2, making it possible to achieve an even wider band. Become.
第4図は本発明の他の実施例の詳細図である。FIG. 4 is a detailed view of another embodiment of the invention.
図において23はハンダバンプである。StあるいはG
aAs等の基Fi15には周辺部に光電気変換回路16
が形成されている。チップ13を裏返しにした被テスト
回路14は基板15の中央部で被テスト回路14を基板
15に対向して、ハンダバンプ23により光電気変換回
路16に接続されている。サンプリング光Sはチップ1
3の裏面よりチップ材料を透して被テスト回路14の配
線の裏面に照射され、被テスト回路14の金属で反射さ
れた反射光Rとしてその後の系で処理検出される。この
方法は数十μm程度のハンダバンプ23を用いるので、
接続部のインダクタンスが20〜50 pH程度に減少
し、より広帯域な信号の伝達が可能になる。またプロー
ブ部5が不要であるという長所があるが、チップ13の
裏面からの透過か作用を利用するので、チ・ンプ材料と
してGaAS、InP等のものしか適用できない。In the figure, 23 is a solder bump. St or G
A photoelectric conversion circuit 16 is installed in the periphery of the base Fi 15 such as aAs.
is formed. The circuit to be tested 14 with the chip 13 turned upside down is connected to the opto-electrical conversion circuit 16 by solder bumps 23 with the circuit to be tested 14 facing the board 15 at the center of the board 15 . Sampling light S is chip 1
The light is irradiated from the back surface of the chip 3 to the back surface of the wiring of the circuit under test 14 through the chip material, and is processed and detected in the subsequent system as reflected light R reflected by the metal of the circuit under test 14. This method uses solder bumps 23 of about several tens of μm, so
The inductance of the connection part is reduced to about 20 to 50 pH, making it possible to transmit signals over a wider range. Another advantage is that the probe section 5 is not required, but since the transmission effect from the back surface of the chip 13 is utilized, only GaAS, InP, etc. can be used as the chip material.
本発明により、チップ上の被テスト回路の任意のノード
を、サブピコ秒の分解能でモニタできることは勿論、I
THzに及ぶ帯域まで、被テスト回路を駆動するための
高速入力信号を、反射や波形歪の無い状態で供給するこ
とが可能となり、実装法に左右されない集積回路あるい
はデバイスの固有の特性を評価する集積回路の試験装置
を提供することができた。According to the present invention, it is possible to monitor any node of a circuit under test on a chip with sub-picosecond resolution;
It is now possible to supply high-speed input signals to drive the circuit under test up to THz without reflections or waveform distortion, allowing evaluation of the unique characteristics of integrated circuits or devices regardless of the mounting method. We were able to provide integrated circuit testing equipment.
第1図は本発明の実施例の概略を示すブロック図、第2
図は第1図のプローブ部5、光電気変換部7の詳細図、
第3図は本発明の他の実施例の詳細図、第4図は本発明
の他の実施例の詳細図である。
1・・・光源゛
2・・・分波・遅延回路部
3・・・照射位置制御部
4・・・対物レンズ
5・・・プローブ部
6・・・位置制御部
7・・・光電気変換部
8・・・ステージ
9・・・電源
10・・・モニタ装置
11・・・信号処理部
12・・・デイスプレィ装置
13・・・チップ
14・・・被テスト回路
15・・・基板
16・・・光電気変換回路
17・・・ボンディングワイヤ
18・・・電気光学結晶
19・・・反射膜
20・・・支持体
21・・・電歪素子
22・・・金属配線
23・・・ハンダバンプ
特許出願人 日本電信電話株式会社
代理人 弁理士 玉 蟲 久 五 部
(外2名)
本発明のテスト装置のブロック図
本発明の弛の実施例のブロー1部、光電気友撰邪の詳細
図第3図
本発明の他の突施例のプローブ部
光電気°変興部の斜視図差に詳細図
案 4 図FIG. 1 is a block diagram showing an outline of an embodiment of the present invention, and FIG.
The figure is a detailed view of the probe section 5 and photoelectric conversion section 7 in FIG.
FIG. 3 is a detailed diagram of another embodiment of the invention, and FIG. 4 is a detailed diagram of another embodiment of the invention. 1... Light source 2... Demultiplexing/delay circuit section 3... Irradiation position control section 4... Objective lens 5... Probe section 6... Position control section 7... Photoelectric conversion Section 8... Stage 9... Power supply 10... Monitor device 11... Signal processing section 12... Display device 13... Chip 14... Circuit under test 15... Board 16...・Photoelectric conversion circuit 17...Bonding wire 18...Electro-optic crystal 19...Reflection film 20...Support 21...Electrostrictive element 22...Metal wiring 23...Solder bump patent application Person Nippon Telegraph and Telephone Co., Ltd. agent Patent attorney Hisashi Tama Mushi 5 (2 others) Block diagram of the test device of the present invention Part 1 of the blow of the loose embodiment of the present invention, detailed diagram of the optoelectronic friend selection 3 Figure 4 Detailed diagram of the perspective view of the photoelectric transformation part of the probe part of another embodiment of the present invention.
Claims (4)
の光源から複数のマルチ光パルスに分波し、各光パルス
を相対的に時間遅延を与える手段と、前記マルチ光パル
スの1本あるいは複数本の光パルスをトリガ光として集
積回路周辺の光電気変換回路の任意の点を照射する手段
と、 前記マルチ光パルスの1本あるいは複数本の光パルスを
サンプリング光として集積回路に対向して配置されたプ
ローブ部の先端に位置する電気光学結晶の任意の点を照
射する手段と、前記集積回路上の被テスト回路が生ずる
電界に応じて変化する前記サンプリング光の反射光を受
ける手段と、 前記プローブ部を、電歪素子を介して前記電気光学結晶
を照射する手段に結合し、前記プローブ部の該電気光学
結晶と前記集積回路の間隔を近接調整させる手段と、 を備えたことを特徴とする集積回路の試験装置。(1) In an apparatus for non-contact testing of integrated circuits, a means for splitting a single light source into a plurality of multi-light pulses and giving a relative time delay to each light pulse; means for irradiating an arbitrary point of a photoelectric conversion circuit around the integrated circuit using one or more optical pulses as trigger light; and means for irradiating one or more optical pulses of the multi-light pulses as sampling light toward the integrated circuit. means for irradiating an arbitrary point on an electro-optic crystal located at the tip of a probe portion arranged as a probe, and means for receiving reflected light of the sampling light that changes in accordance with an electric field generated by a circuit under test on the integrated circuit. and means for coupling the probe section to a means for irradiating the electro-optic crystal via an electrostrictive element, and adjusting the distance between the electro-optic crystal of the probe section and the integrated circuit in close proximity. An integrated circuit testing device featuring:
、前記電気光学結晶の片面に反射膜が施されていること
を特徴とする特許請求の範囲第1項記載の集積回路の試
験装置。(2) Testing of an integrated circuit according to claim 1, wherein the probe section has a size that covers the circuit under test, and a reflective film is provided on one side of the electro-optic crystal. Device.
積回路の全面を覆う大きさを有し、前記反射膜は被試験
集積回路に対向する範囲に施されていることを特徴とす
る特許請求の範囲第1項記載の集積回路の試験装置。(3) The probe portion has a size that covers the entire surface of the photoelectric conversion circuit and the integrated circuit, and the reflective film is provided in an area facing the integrated circuit under test. A testing device for integrated circuits according to item 1.
のない側から照射して、被テスト回路より反射された光
パルスを得る手段を備えたことを特徴とする特許請求の
範囲第1項記載の集積回路の試験装置。(4) The device comprises means for emitting sampling light from the back side of the integrated circuit where the circuit under test is not located, and obtaining a light pulse reflected from the circuit under test. integrated circuit testing equipment.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62267329A JPH0787211B2 (en) | 1987-10-23 | 1987-10-23 | Integrated circuit test equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62267329A JPH0787211B2 (en) | 1987-10-23 | 1987-10-23 | Integrated circuit test equipment |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH01110743A true JPH01110743A (en) | 1989-04-27 |
JPH0787211B2 JPH0787211B2 (en) | 1995-09-20 |
Family
ID=17443306
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62267329A Expired - Fee Related JPH0787211B2 (en) | 1987-10-23 | 1987-10-23 | Integrated circuit test equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0787211B2 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04357472A (en) * | 1991-03-01 | 1992-12-10 | Nippon Telegr & Teleph Corp <Ntt> | Probe for measuring electric field |
US5465043A (en) * | 1992-07-28 | 1995-11-07 | Hewlett-Packard Company | Non-contact type probe and non-contact type voltage measuring apparatus, wherein the probe's irradiation surface is coated with a conductive film having a pinhole |
US5552716A (en) * | 1993-03-15 | 1996-09-03 | Hamamatsu Photonics K.K. | Method of positioning an electrooptic probe of an apparatus for the measurement of voltage |
JP2001255354A (en) * | 2000-01-13 | 2001-09-21 | Schlumberger Technol Inc | Inspection apparatus for semiconductor integrated circuit by pulse-shaped laser beam |
-
1987
- 1987-10-23 JP JP62267329A patent/JPH0787211B2/en not_active Expired - Fee Related
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04357472A (en) * | 1991-03-01 | 1992-12-10 | Nippon Telegr & Teleph Corp <Ntt> | Probe for measuring electric field |
US5465043A (en) * | 1992-07-28 | 1995-11-07 | Hewlett-Packard Company | Non-contact type probe and non-contact type voltage measuring apparatus, wherein the probe's irradiation surface is coated with a conductive film having a pinhole |
US5552716A (en) * | 1993-03-15 | 1996-09-03 | Hamamatsu Photonics K.K. | Method of positioning an electrooptic probe of an apparatus for the measurement of voltage |
JP2001255354A (en) * | 2000-01-13 | 2001-09-21 | Schlumberger Technol Inc | Inspection apparatus for semiconductor integrated circuit by pulse-shaped laser beam |
Also Published As
Publication number | Publication date |
---|---|
JPH0787211B2 (en) | 1995-09-20 |
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