JPH01110442U - - Google Patents
Info
- Publication number
- JPH01110442U JPH01110442U JP1988005336U JP533688U JPH01110442U JP H01110442 U JPH01110442 U JP H01110442U JP 1988005336 U JP1988005336 U JP 1988005336U JP 533688 U JP533688 U JP 533688U JP H01110442 U JPH01110442 U JP H01110442U
- Authority
- JP
- Japan
- Prior art keywords
- frame
- ground conductor
- conductor plate
- semiconductor package
- recess
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
Landscapes
- Microwave Amplifiers (AREA)
Description
第１図は本考案に係る半導体パツケージの１つ
の実施例を示す斜視図、第２図は第１図の断面図
、第３図は他の実施例を示す断面図である。
１……半導体パツケージ、２……ＦＥＴ素子、
３……接地電極板、４……枠体、７……ペルチエ
素子、８……凹部。
FIG. 1 is a perspective view showing one embodiment of a semiconductor package according to the present invention, FIG. 2 is a sectional view of FIG. 1, and FIG. 3 is a sectional view showing another embodiment. 1... Semiconductor package, 2... FET element,
3... Ground electrode plate, 4... Frame, 7... Peltier element, 8... Recessed portion.
Claims (1)
導体素子が収納される半導体パツケージにおいて
、前記半導体素子の直下の前記接地導体板に設け
られた凹部と、この凹部に組込まれたペルチエ素
子とを具備することを特徴とする半導体パツケー
ジ。 In a semiconductor package in which a frame is placed on a ground conductor plate and a semiconductor element is housed in the frame, a recess provided in the ground conductor plate directly below the semiconductor element and a Peltier element incorporated in the recess are provided. A semiconductor package characterized by comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988005336U JPH01110442U (en) | 1988-01-21 | 1988-01-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988005336U JPH01110442U (en) | 1988-01-21 | 1988-01-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01110442U true JPH01110442U (en) | 1989-07-26 |
Family
ID=31208622
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988005336U Pending JPH01110442U (en) | 1988-01-21 | 1988-01-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01110442U (en) |
-
1988
- 1988-01-21 JP JP1988005336U patent/JPH01110442U/ja active Pending