JPH01109815A - Timing adjusting circuit - Google Patents

Abstract

PURPOSE:To adjust the timing of an input pulse signal by changing a delay of a clock pulse signal supplied to a 2nd flip-flop circuit. CONSTITUTION:When a clock pulse CK rises at a time t1, a pulse signal C being an output of a D flip-flop circuit 3 rises at the time t1. When a clock pulse DCK descends at a time t3, a pulse signal E being an output of a D flip- flop circuit 12 rises at a time t4. When an external device receiving the pulse signal E and the clock pulse CK fetches the pulse signal E at the trailing of the clock pulse CK at a time t5, the time T3 to fetch the pulse signal E is adjusted by having only to select any output of buffer amplifiers 9-11 at a terminal CP of the D flip-flop circuit 12.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Field of Industrial Application The present invention relates to a timing adjustment circuit that adjusts the timing of pulse signals when transmitting and receiving pulse signals.

(2) Prior Art When transmitting and receiving pulse signals, it becomes necessary to adjust the timing of the pulse signals according to the setup time and hold time of the pulse signals and the input/output conditions of the pulse circuit. A circuit shown in FIG. 6 is conventionally known as a circuit for adjusting the timing of such pulse signals.

In FIG. 6, an input terminal 1 is supplied with a pulse signal A (FIG. 7(a)) from the outside. This pulse signal A is supplied to the D terminal of the D-type flip-flop circuit 3.

A clock pulse CK (FIG. 7(c)) applied to the input terminal 2 is supplied to the CP terminal of the D-type flip-flop circuit 3.

A pulse signal C (FIG. 7(C)) equal to the level of the pulse signal at the rising edge of the clock pulse CK is output from the output terminal Q of the D-type flip-flip circuit N3. After being delayed by the circuit 4, it is outputted from the output terminal 5 as a pulse signal D (FIG. 7(d)).

The circuit shown in FIG. 6 operates as shown in the waveform diagram in FIG.

In FIG. 7, when the clock pulse CK rises at time 11, the level of the pulse signal A at that time is high level, so the pulse signal C, which is the output of the D-type flip-flop circuit 3 (see FIG. )) starts up at time t2. The time T1 from time t1 to time t2 is a delay time due to the operation of the D-type flip-flop circuit 3.

Therefore, time Tl is fixed.

The pulse signal C is delayed by the delay circuit 4 and becomes the pulse signal D.
(Fig. 7(d)) is obtained. The time difference T2 between the rise of the pulse signal C at time t2 and the rise of the pulse signal C at time 13 is the delay amount of the delay circuit 4.

The pulse signals and clock pulses CK obtained in this way are output from the output terminals 5 and 6, and an external device (not shown) that receives these pulse signals and clock pulses CK determines the time. Assuming that the pulse signal RI is taken in at the rising edge of the clock pulse CK at time t4, by adjusting the delay amount T2 of the delay circuit 4, the time T3 until the pulse signal RI is taken in can be adjusted.

Therefore, by adjusting the delay ff1T2 of the delay circuit 4 according to the set-up time and hold time of the pulse signal, the timing of the input pulse signal A is adjusted and output.

3) Problems to be Solved by the Invention However, in the circuit shown in FIG. 6, since the timing adjustment to the input pulse signal is performed by adjusting the delay amount T2 of the delay circuit 4, it is necessary to change the delay amount T2. If this is attempted, there is a problem in that the delay circuit 4 must be replaced each time.

(4) Means for Solving the Problems The present invention has been made in view of the above points, and aims to facilitate timing adjustment of input pulse signals, and to achieve this purpose. a first flip-flop circuit to which an input pulse signal and a clock pulse signal are supplied, and a delay means for delaying the clock signal;
and a second flip-flop circuit to which the output of the first flip-flop circuit is supplied as an input signal and the output of the delay means is supplied as a clock pulse signal.

(5) Effect In this configuration, the timing of the input pulse signal is adjusted by changing the amount of delay of the clock pulse signal supplied to the second flip-flop circuit, instead of delaying the output pulse signal itself. act.

(6) Examples Hereinafter, the present invention will be explained based on the drawings.

FIG. 1 is a block diagram showing one embodiment of a timing adjustment circuit according to the present invention.

In FIG. 1, an input terminal 1 is supplied with an external pulse signal A (FIG. 2(a)). This pulse signal A is supplied to the D terminal of the D-type flip-flop circuit 3.

The CP terminal of the D-type flip-flop circuit 3 receives a clock pulse CK (see FIG. 2) generated by the clock generation circuit 7.
C)) is supplied via the buffer amplifier 8.

The output terminal Q of the D-type flip-flop circuit 3 outputs a pulse signal C (FIG. 2(C)) that is equal to the level of the pulse signal A at the rising edge of the clock pulse CK. D of flip-flop circuit 12
Supplied to the terminal.

The clock pulse CK (FIG. 2(C)) generated by the clock generation circuit 7 is applied to the CP terminal of the D-type flip-flop circuit 12 through the buffer amplifier 8 and the buffer amplifiers 9 to 9.
A delayed clock pulse DCK is supplied through 11.

Note that the inverted clock pulse DCK is supplied to the CP terminal of the D-type flip-flop circuit 12. The buffer amplifier 9 and the buffer amplifiers 10 to 11 are used as a delay circuit for the clock pulse CK, and the output of one of the buffer amplifiers 9 to 11 is selected and supplied to the CP terminal of the D-type flip-flop circuit 12. Ru.

The amount of delay of this clock pulse DCK with respect to the clock pulse CK (FIG. 2(C)) is time T5 (second
(See figure (d)).

A pulse signal E (FIG. 2(e)) obtained from the output terminal Q of the D-type flip-flop circuit 12 is outputted from the output terminal 5 as a signal obtained by adjusting the timing of the input pulse signal A.

The circuit shown in FIG. 1 operates as shown in the waveform diagram in FIG. 2.

In FIG. 2, when the clock pulse CK rises at time t1, the level of the pulse signal at that time is high level, so the pulse signal C which is the output of the D-type flip-flop circuit 3 (FIG. 2 (C) ) rises at time t1. The time rriT1 from time t1 to time t2 is
This is the delay time due to the operation of the D-type flip-flop circuit 3. Therefore, time T1 is fixed.

The pulse signal C is supplied to the D terminal of the D-type flip-flop circuit 12, and the clock pulse D is supplied from the buffer amplifier IO to the CP terminal of the D-type flip-flop circuit 12.
CK is being supplied. Clock pulse DC at time t3
When K falls, the level of pulse signal C at that time is high level, so D-type flip-flop circuit 1
The pulse signal E (Fig. 2(e)) which is the output of
Get up at 4 o'clock. Time T from time t3 to time t4
2 is a delay time due to the operation of the D-type flip-flop circuit 12. Therefore, time T2 is also fixed.

The pulse signal E and clock pulse CK obtained in this way are output from the output terminal 5 and the output terminal 6. Assuming that the pulse signal E is captured at the falling edge of the clock pulse CK at 15:00, the pulse signal E can be captured by simply selecting the output of one of the buffer amplifiers 9 to 11 to the CI' terminal of the D-type flip-flop circuit 12. The time T3 until capture can be adjusted. That is, D type flip flop times 11
Since the clock pulse DCK having a different delay amount T5 is supplied to the CP terminal of No. 2 depending on whether the output of any of the buffer amplifiers 9 to 11 is selected, the output of any one of the buffer amplifiers 9 to 11 is selected. By doing so, the delay amount T5 can be easily adjusted.

Therefore, depending on the set-up time and hold time of the pulse signal E, which is the output signal, the output is adjusted by adjusting the timing of the input pulse signal depending on which output of the buffer amplifiers 9 to 11 is selected as the clock pulse DCK. I try to do it.

Next, another embodiment of the timing adjustment circuit according to the present invention will be described with reference to FIGS. 3 and 4.

FIG. 3 is a block diagram showing another embodiment of the timing adjustment circuit according to the present invention, and FIG. 4 is a waveform diagram illustrating the operation of the circuit shown in FIG. 3.

In the figure, the same components as in FIGS. 1 and 2 are denoted by the same reference numerals and their explanations will be omitted.

In this embodiment, the output pulse signal E of the D-type flip-flop circuit 12 is supplied to the D terminal of the D-type flip-flop circuit 13. A clock pulse DCK obtained by delaying the clock pulse CK is supplied to the CP terminal of the D-type flip-flop circuit 13 without being inverted. A pulse signal F (FIG. 4(f)) obtained from the output terminal Q of the D-type flip-flop circuit 13 is outputted from the output terminal 5 as a signal whose timing to the input pulse signal is adjusted.

From the output terminal Q of the D-type flip-flop circuit 13, a pulse signal F (FIG. 4(e)) which is obtained by delaying the pulse signal E (FIG. 4(e)) by a half cycle of the clock pulse DCK (that is, a half cycle of the clock pulse CK) is output. (f)) is obtained, and this pulse signal F and clock pulse CK are output from output terminal 5 and output terminal 6. By using these pulse signals F, external equipment (
(not shown) can take in the pulse signal F at the rising edge of the clock pulse CK at time 17:00 (FIG. 4).

By providing the D-type flip-flop circuit 13, the only difference is whether the external device can use the falling edge of the clock pulse CK or the rising edge of the clock pulse CK. So,
This is similar to the first embodiment shown in FIGS. 1 and 2.

Note that FIG. 5 shows the general form of the waveform diagrams shown in FIGS. 2 and 4 described above. That is, in FIGS. 2 and 4, only D(2) and D(4) in FIG. 6 are high-level pulse signals, and the other D(-1) to D(5) are low-level pulse signals. It shows the case where it is a signal. This fifth
Even if D(-1) to D(5) shown in the figure are high-level pulse signals or low-level pulse signals,
The circuits shown in FIGS. 1 and 3 operate normally.

Although the present invention has been described above using examples, various modifications are possible according to the technical idea of the present invention. For example, in the above-described embodiment, the clock generation circuit 7 is provided within the circuit, but it is also possible to provide the clock generation circuit 7 from outside as in the conventional circuit shown in FIG. Further, although the buffer amplifiers 9 to 11 have been described as being provided in Arata, it is also possible to use clock pulse signals obtained by other circuits without newly providing buffer amplifiers 9 to 11.

(7) Effects of the Invention As explained above, the present invention provides a first flip-flop circuit to which an input pulse signal and a clock pulse signal are supplied, a delay means for delaying the clock signal, and a first flip-flop circuit to which an input pulse signal and a clock pulse signal are supplied. and a second flip-flop circuit to which the output of the flip-flop circuit is supplied as an input signal and the output of the delay means is supplied as a clock pulse signal.

In this configuration, the timing of the input pulse signal can be adjusted by changing the delay amount of the clock pulse signal supplied to the second flip-flop circuit, rather than delaying the output pulse signal itself. It becomes possible to easily adjust the timing of the input pulse signal without requiring replacement or the like.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the timing adjustment circuit according to the present invention, FIG. 2 is a waveform diagram explaining the operation of the circuit shown in FIG. 1, and FIG. 3 is a timing adjustment circuit according to the present invention. FIG. 4 is a waveform diagram explaining the operation of the circuit shown in FIG. 3; FIG. 5 is a waveform diagram explaining the operation of the circuit shown in FIGS. 1 and 3. 6 is a block diagram showing a conventional timing adjustment circuit, and FIG. 7 is a waveform diagram illustrating the operation of the circuit shown in FIG. 6. 3...D type flip-flop circuit 7? ... Clock generation circuit 9 ... Buffer amplifier 10 ... Buffer amplifier 11 ... Buffer amplifier 12 ... D-type flip-flop circuit 13 ... D
Type flip-flop circuit patent applicant NEC Home Electronics Co., Ltd. Agent Patent attorney Yama 1) Itsuki Take

Claims (1)

[Claims] a first flip-flop circuit to which an input pulse signal and a clock pulse signal are supplied; a delay means for delaying the clock signal; and an output of the first flip-flop circuit to which an output of the first flip-flop circuit is supplied as an input signal and an output of the delay means. a second flip-flop circuit to which is supplied as a clock pulse signal.