JPH01108893A - Video signal processing circuit - Google Patents

Abstract

PURPOSE:To eliminate a dot interference by obtaining a correction value 1/2 only when a picture whose color is different on the boundary of a present (n) line and a preceding (n-1) line on the screen is projected. CONSTITUTION:When the picture whose color is different on the boundary of the (n) line and the preceding (n-1) line on the screen is projected, concerning a carrier chrominance (C) signal, a signal (a) of the (n) line is 1, a signal (b) of the (n-1) line is 1 and the inverse of a signal c'' that a signal c'' of an (n-2) line is inverted is 1. Only in such a case, the correction value is obtained by a circuit 39 and in cases except this, a correction value 0 is obtained. Thus, at the time of the correction value 0, the halftone of the C signal and the dot interference of a luminance (Y) signal is prevented and at the time of the correction value 1/2, C=1 and Y=0 and the dot interference on the present (n) line is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a video signal processing circuit, which separates a Y (luminance r!1) signal and a C (carrier color) signal from a composite video signal in, for example, a VTR. This relates to circuits that can be extracted.

Prior Art The present applicant previously filed Japanese Patent Application No. 62-140921 (title of the invention ``Video Signal Processing Circuit'') in which a composite video signal is separated to include a part of the luminance signal component, as shown in FIG. a first circuit for obtaining a first color signal a; (a bandpass filter 12); a second color signal C' containing a color separation error signal by removing the luminance signal component from the first color signal a; a second circuit 10 which obtains two of the first color signal a, the second color signal C' and the reference potential;
A video signal processing circuit has been proposed which includes a third circuit 11 which takes out the signal with the highest potential and takes out the color signal C without a separation error signal.

Here, 2 is a 1H logic circuit, and 23 is a delay circuit for Δ.

17.22 is an adder, and 8 is a subtracter. Also, MAX1
3.15, 18, 2H, with high potential detection circuit, Fig. 4 (
It has the configuration shown in A), and outputs the higher potential of either the signal a or the signal -su.

MIN14, 16, 19, and 20 are low potential detection circuits having the configuration shown in FIG. 4(B), and output the lower potential of either signal a or signal -su.

The truth table for this is shown in Table 1. In particular, in the part marked *1 in the table, C=1.0, and in the conventional comb-shaped fill, c=1/2. -1/2, it is possible to remove the halftone and color shift of the C signal that occurred in the vertical transient part of the color bar signal, etc., and the dot interference caused by the C signal that occurred in the Y signal, and also remove small characters etc. vertical resolution deterioration can be improved.

Problems to be Solved by the Invention As shown in FIG. 5(A), when the image is magenta from the top of the screen to the (n-1) line and green from the n line to the bottom of the screen, the C signal on each line is As shown in FIG. 5(B), parts with vertical correlation ((n-2) lines, (n-1) lines) have opposite polarities, and parts with no vertical correlation ((n-1) lines, n line) have the same polarity. In particular, the relationship between the (n-1) line at the boundary between magenta and green and the n line (the part with no vertical correlation) is the first
As shown in the middle mark in the table, a=1. b-1゜c=o, Y
= 1, and in the case of a high-frequency Y signal as shown in Figure 6 (Y
(there is a vertical correlation in the signals), and the signals are apparently equal.

That is, on line n, which is the current line, all of the C signal energy enters the Y signal side, as shown in the marked part of Table 1, and as a result, dot interference occurs on line n, as shown in Figure 7. , there was a problem that the image quality deteriorated.

SUMMARY OF THE INVENTION An object of the present invention is to provide a video signal processing circuit that can improve image quality in a portion where there is no vertical correlation with respect to a C signal.

Means for Solving the Problems In FIG. 1, the bandpass filter includes a first circuit for separating a composite video signal to obtain a first color signal partially containing a luminance signal component; A second color signal including a color separation error signal is obtained by removing the luminance signal component from the first color signal using a color signal and a color signal obtained by delaying the first color signal by a predetermined line. The second circuit, the circuit 38, takes out the signal of the second highest potential among the first color signal, the second color signal, and the reference potential, and the third circuit takes out the color signal without a minute error signal. , when the first color signal, the color signal delayed by the predetermined line, and the color signal obtained by inverting the color signal delayed by the predetermined line are all 1, the circuit 39 sets 1/2 of the signal to the reference potential. , and otherwise outputs only the above reference potential (signal component zero).
Each of the circuits shown in FIG.

When displaying an image with a different color at the border with the (n-1) line before n lines on the working screen, for the C signal, the signal a of the n line is -1, and the signal b of the (n-1) line is 1, (n-2
) line signal C″ becomes inverted signal −c”=1,
Only in such a case, the circuit 39 obtains a correction value of 1/2, and in other cases, a correction value of 0 is obtained. When the correction value is O, halftone of the C signal and dot interference of the Y signal can be prevented by the same operation as the circuit shown in FIG. 3 proposed earlier by the applicant, and when the correction value is 1/2, C= 1. Y=O, and no dot interference occurs on the current n line.

Embodiment FIG. 1 shows a block diagram of a first embodiment of the circuit of the present invention,
In the figure, the same components as those in FIG. 3 are given the same numbers and will be explained. A circuit 39 surrounded by a dashed line in the figure is a newly added circuit to the circuit shown in FIG.

In FIG. 1, 30 is a one-day delay circuit, which delays the output of the one-day delay circuit 2 by one more day. A signal c'' is obtained. An inverting circuit 31 inverts the output of the one-day delay circuit 30 to obtain a signal -c''. 32.33 is MAX, 34
．． 35 is MIN.

36 is an adder, 37 is a 1/2 amplifier, and the signal @a.

A correction value is obtained from "b" and "-c" and is used as a reference potential of MIN20.MAX21.

To explain the operation of the circuit surrounded by the dashed line, M
At AX32, the maximum of the signals a, b, -c'' is detected, while at MIN34, the signals a, b, -c'' are detected.
The smallest one of c" is detected, and each detection output is M
IN35. Supplied to MAX33. At MIN35, the smaller potential between the detection output of MAX32 and the zero potential is taken out, while at MAX33, the larger potential between the detection output of MIN34 and the zero potential is taken out,
Each detection output is added by a calculator 36. The output of the adder 36 is halved in level by a 1/2 amplifier 37 to become a correction value signal, and the output signal is MIN20. It is supplied to MAX21 as a reference potential.

Let us now consider again the images described in FIGS. 5(A) and 5(B). As mentioned above, if the signal a of the current n line is 1, then the (n-1) line one line before is the signal b=i, and the two lines before (n-2> line is the signal c''=- 1. On the other hand, in the case of the high-frequency Y signal shown in FIG. 6, all lines have the same polarity, so a=1.b=1.
c'' = 1, and the two can be distinguished.

That is, as shown in FIGS. 5(A) and 5(B), a=1. b
-1, correction value 1/2 only when C″=-1<-C″=1)
, the C signal is set to 1, and the Y signal is set to O. In other cases, the correction value is O. Therefore, for all cases other than the correction value O, the results are the same as those obtained by the circuit shown in FIG. The portion marked with * in Table 2 of the truth table of the circuit of this embodiment is the case where the image shown in FIG. 5 is obtained.

Table 2 Therefore, when obtaining an image as shown in Fig. 5, the current n
Since the line C signal is 1 and the Y signal is O, the dot interference for one line as shown in FIG. 7 does not occur, and the image quality can be improved.

In this case, the circuit 38 including MAX18.21, MIN19.20, and the adder 22 outputs the 2rjth higher potential among the signals a, C=, and the reference potential (correction value).

That is, as shown in Table 3, when the correction value is O, the same calculation as in the circuit shown in Fig. 3 is performed, but the correction value is 1/2.
In this case, c=1. When the correction value is 1/2, a=l,
C-=Q, the second highest potential among the correction values 1/2 in Table 3 is 1/2, but if you take it as the C signal output as 1/2, it will become a half-tone. , I actually want to output it as 1. For this purpose, the correction value must be reduced to 1/2, and in practice, C
It is the same as outputting a signal (a=1.C”=O
The second highest potential among 1 correction value 1 is 1).

FIG. 2 shows a block diagram of a second embodiment of the circuit of the present invention,
In the figure, the same components as those in FIG. 1 are given the same numbers and their explanations will be omitted. This circuit performs substantially the same operation as the circuit 10 shown in FIG. 1 by subtracting the signal @b from the signal a with the reducer 24, and has a simpler configuration than the circuit shown in FIG. It is possible.

In addition, in both the circuits shown in FIGS. 1 and 2, a two-day delay circuit may be used in place of the IH1 delay circuit 2.30 in order to apply the circuit to the PAL system. In this case, in the PA/L method, when obtaining an image as shown in Fig. 5, a calculation error occurs over two lines, so dot interference is more noticeable than in the NTSC method, and the effect of the present invention is more noticeable than in the NTSC method. It's bigger than that.

Effects of the Invention According to the present invention, Vertic-a of color par signals etc.
It does not cause dot interference in the Y signal or halftone or color shift in the C signal in the transition area, and improves the vertical resolution deterioration that occurs with conventional comb filters when reproducing small characters. Moreover, since the correction value 1/2 is obtained only when displaying an image with different colors at the border between the current n line and the (n-1) line one line before on the screen, the C signal is 1, the Y signal becomes 0, and the dot interference that occurred in the circuit previously proposed by the applicant can be eliminated.

[Brief explanation of the drawing]

1 and 2 are block diagrams of the first and second embodiments of the circuit of the present invention, FIG. 3 is a block diagram previously proposed by the applicant, and FIG. 4 is a specific circuit for MAX and MIN. Figure, 5th
The figure is a diagram for explaining the signal of each line when the colors are different at the top and bottom of the screen, FIG. 6 is an image of a high-frequency Y signal, and FIG. 7 is a diagram for explaining dot interference. 1...Composite video signal input terminal, 2,3C...
・1 day delay circuit, 6...C signal output terminal, 8, 24・
...Subtractor, 9...Y signal output terminal, 12...Band filter, 13.15.18, 21, 32.33...
MAX (high potential detection circuit), 14.16.19°20.
34.35...MIN (low potential detection circuit), 17.2
2.36... tightener, 23... Δ delay circuit, 31
...Inversion circuit. Patent applicant: Victor Japan Co., Ltd., 44. :;'' Figure 3 Figure 4 Figure 5 (A) (s) Figure 6 Figure 7

Claims (1)

[Scope of Claims] A first circuit that separates a composite video signal to obtain a first color signal that partially includes a luminance signal component, and delays the first color signal and the first color signal by a predetermined line. a second circuit for obtaining a second color signal including a color separation error signal by removing the luminance signal from the first color signal using the first color signal and the first color signal; a third circuit that extracts a signal with the second highest potential between the second color signal and the reference potential and extracts a color signal without a separation error signal; When both the signal and the color signal obtained by inverting the color signal delayed by the predetermined line and the color signal delayed by a predetermined line are both 1, output 1/2 of the signal to the reference potential, and otherwise. A video signal processing circuit comprising: a fourth circuit that sets the reference potential to zero.