JPH01107400A - Setting method for switch system by eeprom - Google Patents

Setting method for switch system by eeprom

Info

Publication number
JPH01107400A
JPH01107400A JP62263702A JP26370287A JPH01107400A JP H01107400 A JPH01107400 A JP H01107400A JP 62263702 A JP62263702 A JP 62263702A JP 26370287 A JP26370287 A JP 26370287A JP H01107400 A JPH01107400 A JP H01107400A
Authority
JP
Japan
Prior art keywords
data
cell
cells
address
array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62263702A
Other languages
Japanese (ja)
Inventor
Shigehiro Yoshimura
吉村 成弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Home Electronics Ltd
NEC Corp
Original Assignee
NEC Home Electronics Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Home Electronics Ltd, Nippon Electric Co Ltd filed Critical NEC Home Electronics Ltd
Priority to JP62263702A priority Critical patent/JPH01107400A/en
Publication of JPH01107400A publication Critical patent/JPH01107400A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To substantially decrease the number of time of write of a cell and to raise its reliability by constructing a switch system for installing a data in an information apparatus by using a cell array. CONSTITUTION:The number of cells of an array is made larger than the number of data storage cells, the number of addresses is shifted at every rewriting, and a data overflowed from the array executes such cyclic write as writing from a head address of the array. Accordingly, comparing with the case when write is executed by making the number of cells of the array the same as the number of data storage cells, the number of times of write decreases substantially, as for each cell. Also, as for the cell in which an error is generated, it is disposed of so that its address can be known by a managing means, by which thereafter, the cell concerned can be removed at the time of rewriting. Also, in which cell a data is stored can be known easily by detecting an address of a tag. In such a way, a switch having reliability which is settled a problem of reliability by limiting the number of rewriting of an EEPROM can be constructed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、EEPROMに記憶されたデータを一連のス
イッチデータとして使用するスイッチシステムに関する
。特にスイッチデータを、EEPROM (電気的に消
去可能なプログラマブルROM)の特性を利用して、書
換えを行ない、再設定することのできるシステムに関す
る。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a switch system that uses data stored in an EEPROM as a series of switch data. In particular, the present invention relates to a system in which switch data can be rewritten and reset using the characteristics of EEPROM (electrically erasable programmable ROM).

〔従来の技術〕[Conventional technology]

情報機器においては、所定のデータを設定するために、
機械的なデイツプスイッチを利用することが多い。しか
し最近は電気的に消去可能で書込みを多数回行ないうる
EEPROMを使用することにより、従来のデイツプス
イッチの代わりに用いることが多い。デイツプスインチ
は1”。
In information equipment, in order to set certain data,
A mechanical dip switch is often used. However, recently, EEPROMs, which are electrically erasable and can be written many times, are often used in place of conventional dip switches. Dates inch is 1”.

O”の2値しか記憶できないが、EEPROMでは複数
個のビットを1アドレスに設定することも容易で、より
複雑なデータを記憶できるので、システムとして応用範
囲は広くなる。
Although it can only store two values, ``0'', in EEPROM it is easy to set multiple bits to one address, and more complex data can be stored, so the range of application as a system is widened.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来、この種のEEPROMを利用したスイッチシステ
ムは、EEPROMのアドレスを固定的に使用していた
。たとえば、第4図に示すように、EEPROMは8ケ
のアドレスO〜7番地のセルをもっている場合でも、(
a)のようにA、B、Cのデータを書込んだセルを書換
えの際に、(b)のように同一番地のセルにA’、B’
、C’とデータ書換えを行なう。そのためEEPROM
の特定のバイトやビットに書換え回数の限界が来ると、
全システムが無効とされる欠点があった。また、書込み
チェックは、書込みデータと読出しデータを比較しエラ
ーチェックするだけで、エラーを回避する手段は特に取
っていなかった。
Conventionally, switch systems using this type of EEPROM have used fixed EEPROM addresses. For example, as shown in FIG. 4, even if an EEPROM has eight cells with addresses O to 7, (
When rewriting cells in which data A, B, and C have been written as shown in a), data A' and B' are written to cells at the same location as shown in (b).
, C' and rewrite the data. Therefore, EEPROM
When a certain byte or bit reaches the limit of the number of times it can be rewritten,
There was a drawback that the entire system was invalidated. Further, the write check merely compares write data and read data to check for errors, and no particular measures have been taken to avoid errors.

本発明の目的は、EEPROMの書換え回数の制限によ
る信頼性の問題を解決した、信頼性のあるスイッチシス
テムを構築する設定方法を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a setting method for constructing a reliable switch system that solves the reliability problem caused by the limit on the number of times EEPROM can be rewritten.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のEEPROMによるスイッチシステムの書換え
方法は、アレイのセル数をデータを記憶すべきセル数よ
りあらかじめ大きく定めておき、該セルアレイ内におい
て特定のタグを先頭に記憶し、該タグのアドレスに引続
くアドレスのセルに後記の管理手段により不良とされて
いるアドレスのセルを除き、一連のデータを記憶する手
段と。
The method for rewriting a switch system using an EEPROM of the present invention is to predetermine the number of cells in the array to be larger than the number of cells in which data is to be stored, store a specific tag at the beginning in the cell array, and write the tag to the address of the tag. means for storing a series of data in cells at subsequent addresses, excluding cells at addresses determined to be defective by a management means described later;

データ書換えごとに、一連のデータをタグごとアドレス
をずらし、かつアレイからオーバフローしたデータはア
レイ頭初のアドレスから書込む、サイクリックな書換え
手段と、書換え後のチェックに不良とされたセルは、該
セルを飛びこして次のセルに書込みを行なうとともに、
以後の書換えに使用しないように管理する手段とを含む
ものである。
Each time data is rewritten, the address of a series of data is shifted for each tag, and data that overflows from the array is written from the first address at the beginning of the array.A cyclic rewrite means is used, and cells that are found to be defective in the post-rewrite check are Skip the cell and write to the next cell, and
This includes means for managing the data so that it is not used for subsequent rewriting.

〔作用〕[Effect]

アレイのセル数はデータ記憶セル数より大きくし、書換
えごとにアドレス数をずらし、アレイからオーバフロー
したデータは、アレイ頭初のアドレスから書込むような
サイクリックな書込みを行なう。したがって、アレイの
セル数とデータ記憶セル数とを同一とし、書換えを行な
う場合に対し、各セルとしては書込み回数が実質的に減
少する。
The number of cells in the array is made larger than the number of data storage cells, the number of addresses is shifted every time data is rewritten, and data overflowing from the array is written in a cyclic manner such that it is written from the first address at the beginning of the array. Therefore, compared to the case where the number of cells in the array and the number of data storage cells are the same and rewriting is performed, the number of times each cell is written is substantially reduced.

さらにエラーが生じたセルは、管理手段によってそのア
ドレスがわかるようにしておくことで、以後当該セルを
書換えの際除去できる。データがどのセルから記憶され
ているかはタグのアドレスを検出して、容暑に知ること
ができる。
Furthermore, if the address of a cell in which an error has occurred is made known by the management means, the cell can be removed at the time of subsequent rewriting. You can easily find out from which cell the data is stored by detecting the address of the tag.

〔実施例〕〔Example〕

以下、図面を参照して、本発明の一実施例につき説明す
る。第1図は、本発明の書換え方法の一例を示すもので
、(a)がある時期におけるEEPROMの記憶状況で
、アドレスO番地にタグがあり、引続くアドレス1,2
.3の各番地にA、B、Cのデータが記憶されている。
Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows an example of the rewriting method of the present invention. (a) shows the storage status of an EEPROM at a certain time, with a tag at address O and subsequent addresses 1 and 2.
.. Data A, B, and C are stored at each address of 3.

なお7番地はそれまでにエラーチェックで不良と判定さ
れたセルで、管理のため不良アドレスであることを示す
タグを固定的に付する(登録)ようにしている。
Note that address 7 is a cell that has been previously determined to be defective by error checking, and for management purposes, a tag indicating that it is a defective address is fixedly attached (registered) to the cell.

書換えは第1図(b)のように、アドレスをずらしてA
’、B’、C’なる書換えデータを書込む。
Rewriting is done by shifting the address as shown in Figure 1(b).
Write rewrite data ', B', and C'.

このとき6番地に仮りにデータがあるとすれば、7番地
に不良アドレスタグがあるので、書換えの際は0番地に
新しいデータがサイクリックに書込まれる。このように
、データを格納するセルは移動するが、その先頭にタグ
があるので、容易にデータの所在アドレスを知ることが
でき、また不良アドレスタグにより、そのセルを飛びこ
して書込みができる。
At this time, if there is data at address 6, there is a defective address tag at address 7, so new data is cyclically written to address 0 during rewriting. In this way, the cell storing data moves, but since there is a tag at the beginning of the cell, the address where the data is located can be easily known, and the defective address tag allows writing to be performed by skipping that cell.

次に、エラーのチェック動作を、第2図のフローチャー
トにより説明する。このフローチャートは1つのデータ
の書込みに関するものである。先ず所定のアドレスにデ
ータの書込み(Pl)を行なう。そして読出して(P2
)、書込んだデータと比較する(P3)。データが一敗
すれば書込みは終了するが、書込みデータと読出しデー
タが異なる場合は、再書込みを行なう。このリライト回
数に制限を設けておいて、リライト回数が制限以内(P
4)ならば、さらに再書込みとエラーチェックを行なう
 (Pi〜P3)。リライト回数が制限より多くなった
場合は、当該アドレスのセルは、不良セルとしてそのア
ドレスを登録しくP5)、Piにもどりこのアドレスの
次のアドレスにデータの書込みを行なう。ただしこの飛
びこしはデータ数が全アドレスセル数から不良アドレス
セル数を引いた書込み可能な領域より少ない(P6)場
合にのみ行なうことができ、そうでない場合は、もはや
データの書込みはできないから、エラーと判定される(
P7)。
Next, the error checking operation will be explained with reference to the flowchart shown in FIG. This flowchart relates to writing one piece of data. First, data is written (Pl) to a predetermined address. Then read it out (P2
) and compare it with the written data (P3). If the data is lost once, the writing ends, but if the written data and the read data are different, rewriting is performed. Set a limit on the number of rewrites so that the number of rewrites is within the limit (P
4), further rewriting and error checking are performed (Pi to P3). If the number of rewrites exceeds the limit, the cell at that address registers that address as a defective cell (P5), returns to Pi, and writes data to the next address after this address. However, this jump can only be performed when the number of data is less than the writable area (P6), which is the total number of address cells minus the number of defective address cells. Otherwise, data can no longer be written. It is judged as an error (
P7).

不良アドレスの管理は、上述のようにセルアレイの特定
アドレスに不良アドレスタグを付しておくことで行なう
が、別方法として、たとえば第3図に示した管理ファイ
ル2をEEPROMの別の領域内に設け、スイッチシス
テムのEEPROMのセルアレイ1のアドレスに相応し
て、良セルを“1”、不良セルを“0”として登録して
、このファイルを参照することもできる。
Defective addresses can be managed by attaching a defective address tag to a specific address in the cell array as described above, but as an alternative method, for example, the management file 2 shown in FIG. 3 can be stored in another area of the EEPROM. It is also possible to refer to this file by registering a good cell as "1" and a defective cell as "0" in accordance with the address of the cell array 1 of the EEPROM of the switch system.

〔発明の効果〕〔Effect of the invention〕

以上、説明したように、本発明はEEPROMにおいて
セルアレイを使用して情報機器内にデータを設置するス
イッチシステムを構築する方法に関するものであるが、
アレイのセル数をデータ数より大きくするとともに、書
換えごとにアドレスをずらしてサイクリックに書込むこ
とによって、セルの書込み回数を実質的に減少し、その
信頼性を高めることができる。゛なお不良セルがある場
合、このセルを飛ばして次のアドレスにデータ書込みを
行なうので、アレイのセル数からデータ数を引いた数だ
けの余裕数だけ、不良セルが生じても充分スイッチシス
テムとして使用できるので、このシステムの使用寿命を
延長できる利点がある。
As explained above, the present invention relates to a method of constructing a switch system for installing data in information equipment using a cell array in an EEPROM.
By making the number of cells in the array larger than the number of data and cyclically writing by shifting the address for each rewrite, it is possible to substantially reduce the number of times cells are written and improve their reliability.゛If there is a defective cell, this cell is skipped and the data is written to the next address, so even if a defective cell occurs, the switch system can still function as long as there is a margin equal to the number of cells in the array minus the number of data. This has the advantage of extending the service life of the system.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図乃至第3図は本発明の一実施例に係り、第1図は
この方法の概念を示す図、第2図はこのシステムにおけ
るデータ設定の不良チェックのフローチャート、第3図
は不良セルの管理方法の1例を示す説明図、第4図は従
来例の概念を示す図である。 1−セルアレイ、  2−管理ファイル。
Figures 1 to 3 relate to an embodiment of the present invention, with Figure 1 being a diagram showing the concept of this method, Figure 2 being a flowchart for checking for defective data settings in this system, and Figure 3 being a diagram showing defective cells. FIG. 4 is an explanatory diagram showing an example of a management method, and FIG. 4 is a diagram showing the concept of a conventional example. 1-Cell array, 2-Management file.

Claims (1)

【特許請求の範囲】  EEPROMに複数個の一連のデータを記憶しておく
、セルアレイによって構成されるスイッチシステムにお
いて、 アレイのセル数をデータを記憶すべきセル数よりあらか
じめ大きく定めておき、該セルアレイ内において特定の
タグを先頭に記憶し、該タグのアドレスに引続くアドレ
スのセルに、後記の管理手段により不良とされているア
ドレスのセルを除き、一連のデータを記憶する手段と、
データ書換えごとに、一連のデータをタグごとアドレス
をずらし、かつアレイからオーバフローしたデータはア
レイ頭初のアドレスから書込む、サイクリックな書換え
手段と、書換え後のチェックに不良とされたセルは、該
セルを飛びこして次のセルに書込みを行なうとともに、
以後の書換えに使用しないように管理する手段とを含む
ことを特徴とするEEPROMによるスイッチシステム
の設定方法。
[Claims] In a switch system constituted by a cell array in which a plurality of series of data are stored in an EEPROM, the number of cells in the array is determined in advance to be larger than the number of cells in which data is to be stored, and the number of cells in the cell array is means for storing a specific tag at the beginning, and storing a series of data in cells at addresses following the address of the tag, excluding cells at addresses that are determined to be defective by the management means described later;
Each time data is rewritten, the address of a series of data is shifted for each tag, and data that overflows from the array is written from the first address at the beginning of the array.A cyclic rewrite means is used, and cells that are found to be defective in the post-rewrite check are Skip the cell and write to the next cell, and
1. A method for setting a switch system using an EEPROM, comprising means for managing the EEPROM so that it is not used for subsequent rewriting.
JP62263702A 1987-10-21 1987-10-21 Setting method for switch system by eeprom Pending JPH01107400A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62263702A JPH01107400A (en) 1987-10-21 1987-10-21 Setting method for switch system by eeprom

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62263702A JPH01107400A (en) 1987-10-21 1987-10-21 Setting method for switch system by eeprom

Publications (1)

Publication Number Publication Date
JPH01107400A true JPH01107400A (en) 1989-04-25

Family

ID=17393140

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62263702A Pending JPH01107400A (en) 1987-10-21 1987-10-21 Setting method for switch system by eeprom

Country Status (1)

Country Link
JP (1) JPH01107400A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04307647A (en) * 1991-04-04 1992-10-29 Fuji Photo Film Co Ltd Memory card storage control system
US5297103A (en) * 1992-01-20 1994-03-22 Fujitsu Limited Electrically erasable and programmable semiconductor memory device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04307647A (en) * 1991-04-04 1992-10-29 Fuji Photo Film Co Ltd Memory card storage control system
US5297103A (en) * 1992-01-20 1994-03-22 Fujitsu Limited Electrically erasable and programmable semiconductor memory device

Similar Documents

Publication Publication Date Title
US8694855B1 (en) Error correction code technique for improving read stress endurance
US11127471B2 (en) Read retry threshold voltage selection
EP0862762B1 (en) Semiconductor memory device having error detection and correction
US20050036390A1 (en) Non-volatile memory and non-volatile memory data rewriting method
JPH05282889A (en) Nonvolatile semiconductor memory
JP2019169217A (en) Memory system, control method thereof and program
CN104347118B (en) For emulating the system and method for Electrically Erasable Read Only Memory
RU2269814C2 (en) Method for reliable recording of pointer for circular memory
KR101468432B1 (en) Flash memory refresh techniques triggered by controlled scrub data reads
CN103578565A (en) Calibration method and device of NAND Flash memory chip
US10176876B2 (en) Memory control method and apparatus for programming and erasing areas
JP5180957B2 (en) Memory controller, semiconductor recording device, and rewrite count notification method
US20090019244A1 (en) Information Record/Read Apparatus
JPH01107400A (en) Setting method for switch system by eeprom
KR100692982B1 (en) NAND type flash memory for recording bad block information
CN113434086B (en) Data storage method, device, nonvolatile memory device and memory
JPH08203292A (en) Nonvolatile memory
JP2003036209A (en) Nonvolatile memory and data rewriting method thereof
US9558110B2 (en) Method for managing a flash memory
CN114038493A (en) Method, device, memory and storage medium for preventing EEPROM damage caused by frequent erasing of check bits
JP3670151B2 (en) Flash memory access method, system including driver for accessing flash memory, and flash memory
JP4171518B2 (en) Nonvolatile semiconductor memory device
US20060117134A1 (en) System and method for prolonging usage lifetime of a non-volatile memory
US11119854B2 (en) Method of controlling verification operations for error correction of non-volatile memory device, and non-volatile memory device
CN114371816A (en) Data storage method and electronic equipment