JPH01107056U - - Google Patents
Info
- Publication number
- JPH01107056U JPH01107056U JP189288U JP189288U JPH01107056U JP H01107056 U JPH01107056 U JP H01107056U JP 189288 U JP189288 U JP 189288U JP 189288 U JP189288 U JP 189288U JP H01107056 U JPH01107056 U JP H01107056U
- Authority
- JP
- Japan
- Prior art keywords
- control circuit
- save
- tape recorder
- jack
- circuit side
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
Description
第１図は本考案の実施例を示す構成図、第２図
は従来装置を示す構成図である。
１…信号処理部、２…カセツト・テープレコー
ダー、３…信号ケーブル、１０１…ＣＰＵモジユ
ール、１０２…キー操作部、１０３…ロード制御
回路、１０４…セーブ制御回路、１０７…ジヤツ
ク、１０８…スイツチ、２０１…イアフオン・ジ
ヤツク、２０２…マイクロフオン・ジヤツク。
FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional device. DESCRIPTION OF SYMBOLS 1...Signal processing section, 2...Cassette tape recorder, 3...Signal cable, 101...CPU module, 102...Key operation section, 103...Load control circuit, 104...Save control circuit, 107...Jack, 108...Switch, 201 …Iafon Jatsk, 202…Microphon Jatsk.
Claims (1)
して使用した信号処理装置で、ロード・キー操作
、或はセーブ・キー操作に基づきＣＰＵから与え
られる信号によつてロード制御回路、或はセーブ
制御回路を選択し、このＣＰＵ中のＲＡＭへの前
記カセツト・テープレコーダーの記憶内容のロー
デイング、或は前記テープレコーダーへの前記Ｒ
ＡＭ内容のセービングを行うようにした信号処理
装置において、信号ケーブルの一端が接続される
ジヤツクと、このジヤツクを前記ロード制御回路
側、或は前記セーブ制御回路側に切換接続するス
イツチとを設け、前記信号ケーブルの他端を前記
カセツト・テープレコーダーのイアフオン・ジヤ
ツク、或はマイクロフオン・ジヤツクに接続した
状態で、前記ロード・キー操作、或はセーブ・キ
ー操作を行うと共に、前記ＣＰＵから切換信号を
発生させ前記スイツチを前記ロード制御回路側、
或は前記セーブ制御回路側に切換えるようにした
ことを特徴とする入・出力切換装置。 A signal processing device using a cassette tape recorder as an external storage device, which selects a load control circuit or a save control circuit by a signal given from a CPU based on a load key operation or a save key operation, Loading the storage contents of the cassette tape recorder into the RAM in this CPU, or loading the R into the tape recorder.
A signal processing device configured to save AM content, comprising a jack to which one end of the signal cable is connected, and a switch for switching and connecting the jack to the load control circuit side or the save control circuit side, With the other end of the signal cable connected to the earphone jack or microphone jack of the cassette tape recorder, the load key or save key is operated and a switching signal is sent from the CPU. generating the switch on the load control circuit side,
Alternatively, an input/output switching device characterized in that the input/output switching device is configured to switch to the save control circuit side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP189288U JPH01107056U (en) | 1988-01-11 | 1988-01-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP189288U JPH01107056U (en) | 1988-01-11 | 1988-01-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01107056U true JPH01107056U (en) | 1989-07-19 |
Family
ID=31202177
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP189288U Pending JPH01107056U (en) | 1988-01-11 | 1988-01-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01107056U (en) |
-
1988
- 1988-01-11 JP JP189288U patent/JPH01107056U/ja active Pending
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