JPH01105683A - Supervisory equipment - Google Patents

Abstract

PURPOSE:To execute rational supervisory control corresponding to the presence and absence of the movement of an object by detecting the difference of two video signals which are outputted from an image pickup device at a different time and deciding the pressure and absence of the moving object based on this detecting output. CONSTITUTION:A solid-state image pickup device MID has vertical shift registers VSR and VSRE, interlace circuits ITG and ITGE and a pair of vertical scanning circuits to be respectively composed of driving circuits VD and VDE to a picture element array PD. Different rows are simultaneously selected from the picture element array by respective vertical scanning operation. Then, a video signal is outputted from terminals S and RV simultaneously with synchronizing to the scanning operation by a horizontal shift register HSR. Namely, in order to detect the presence and absence of the movement of the object, the video signal for sensitivity control, etc., from the terminal RV is utilized. Thus, without using an image memory, etc., the presence and absence of the movement of the object can be decided by a direct signal processing with a simplified signal processing circuit.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a monitoring device, and for example, to a technique that is effective when used in a monitoring device that has a function of detecting the movement of a subject. .

[Conventional technology]

2. Description of the Related Art Solid-state imaging devices consisting of a combination of a photodiode and a switch MO3FET are conventionally known. Regarding such a solid-state imaging device, for example, Japanese Patent Application Laid-Open No. 56-1
There is a publication No. 52382.

[Problem that the invention seeks to solve]

2. Description of the Related Art Surveillance cameras and the like record captured video signals on a recording device with an endless tape, or operate the recording device intermittently to increase recording time.

Generally, the probability of abnormal conditions occurring is low, so most of the recording portion is spent on pointless photography. For this reason, even when endless tapes are used in the above-mentioned monitoring devices, they require a large amount of recording tapes because they must be stored in order to deal with incidents or accidents that are discovered later. In addition, in order to check for the presence or absence of the abnormality, it is necessary to play back the entire recorded magnetic tape, and since the detection is extremely inhuman, there is a problem that it is easy to miss the detection of the abnormality. .

An object of the present invention is to provide a monitoring device having a function of detecting the movement of a subject.

Another object of the present invention is to provide a monitoring device that is capable of recording only the state to be monitored.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a signal detection circuit detects the difference between two video signals output from the imaging device at different times, and based on this detection output, it is determined whether there is a moving subject.

[For production]

According to the above-described means, rational monitoring control can be performed depending on whether or not the subject is moving.

(Example 1) FIG. 2 shows a TS L used in the monitoring device according to the present invention and having a variable sensitivity function and a two-wire output function.
(Transversal Stgnal Line
2 shows a circuit diagram of a main part of an embodiment of an MO3 type solid-state imager of the ) type. Each circuit element in the figure is formed on a single semiconductor substrate such as, but not limited to, single-crystal silicon using known semiconductor integrated circuit manufacturing techniques. The main circuit blocks in the figure are drawn in accordance with the actual geometric arrangement on the semiconductor chip.

The pixel array PD is exemplarily shown with four rows and two columns. However, in order to prevent the drawing from becoming complicated, circuit symbols are added to only two of the four rows of pixel cells. One pixel cell is
A switch MO3FET QI whose gate is coupled to the photodiode D1 and the vertical scanning line VLI, and a switch MO3FET whose gate is coupled to the horizontal scanning line HLI.
It consists of a series circuit of Q2. The above photo die, t-
)' The output nodes of other similar pixel cells (D2.Q3.Q4) arranged in the same row (horizontal direction) as the pixel cell consisting of DI and switch MO3FETQI, Q2 are extended horizontally in the figure. The horizontal signal line H3I is coupled to the horizontal signal line H3I. Pixel cells similar to those described above are similarly combined for other rows.

The exemplified horizontal scanning line HLI extends vertically in the figure, and includes switches MO3FETQ2 . It is commonly coupled to gates such as Q6. Pixel cells arranged in other columns are also coupled to corresponding horizontal scanning lines HL2 and the like in the same manner as described above.

In order to add a substantial electronic automatic diaphragm function to the solid-state imaging device, in other words, to make the substantial storage time for the photodiode variable, the horizontal signal lines that constitute the pixel array) ( Switches MO3FETQB, Q9 and Q26, Q28 are provided at both ends of the horizontal signal lines H31 to H34, respectively.The switches MO3FETQ8 and Q9 disposed on the right end side serve as outputs extending vertically from the horizontal signal lines H31 and H32, respectively. line V
Combine with S. This output gys is coupled to a terminal S, and a read signal is transmitted via this terminal S to the input of a preamplifier provided externally.

In addition, the above switch MO3FETQ placed on the left end side
26 and Q28 are dummy (reset) output lines DV extending vertically from the horizontal signal lines H51 and H32, respectively.
Combine with S. This output line DVS is coupled to the terminal RV, although not particularly limited thereto. This allows the signal of the dummy output line DVS to be sent out from the external terminal RV if necessary. In this embodiment, as will be described later, the motion of the subject is detected by using the video signal output from the external terminal RV.

Although not particularly limited, the horizontal signal lines H81 to H34 in each row are provided with switches MO3FETQ27, Q29, etc. that are turned on by a reset signal supplied from the terminal RP during the horizontal retrace period. By turning on these MO3FETs Q27, Q29, etc., a constant bias voltage (not shown) is applied to each of the horizontal signals mH31 to H84 from the external terminal RV via the dummy output line DVS. MO3F for reset as above
The reason why ETQ27, Q29, etc. are provided is as follows. Semiconductor regions such as the drains of switch MO3FETs coupled to the horizontal signal lines H3I to H84 may also be photosensitive, and false signals (smear, blooming) formed by such parasitic photodiodes can cause
It is accumulated in the horizontal signal line which is left in a floating state when it is not selected. Therefore, as described above, all the horizontal signals IH&1 to H34 are reset to the predetermined bias voltage using the horizontal retrace period.

As a result, for the selected horizontal signal line, the pixel signals are always extracted from the state in which the false signals have been reset, so that the false signals included in the output image signal can be significantly reduced. Regarding the above-mentioned false signals (smear, blooming), for example, Japanese Patent Application Laid-Open No. 57-17276
It is described in detail in the publication.

A horizontal scanning signal formed by a horizontal shift register H3R is supplied to the horizontal scanning lines HLI to HL2, etc.

The scanning circuit that performs the vertical selection operation (horizontal scanning operation) in the pixel array PD is composed of the following circuits.

In this embodiment, the horizontal signal line H3 of the pixel array PD
A pair of switch 7 + M O at both ends of I to H34 etc.
S F E T Q 8, Q9 etc. and switch MO3F
A pair of scanning circuits are provided corresponding to the provision of ETQ26, Q28, etc.

In this embodiment, in order to be applicable to industrial applications, in addition to the increment mode, selective two-line simultaneous scanning and non-interlaced mode scanning are enabled. The following scanning circuit is provided on the right side of the pixel array PD.

The vertical shift register VSR forms output signals SV1, SV2, etc. used for reading. These output signals SV1, SV2, etc. are output to the increment gate circuit ITG.
and the vertical scanning lines VLI to VL4 and the switches MO3FETQ8 . It is supplied to gates such as Q9.

Since the interlace gate circuit ITG performs a vertical selection operation (horizontal scanning operation) in the interlace mode, in the first (odd number) field, the adjacent vertical scanning lines VLI, VL2 are connected to the vertical scanning lines VLI to VL4. and VL
3 combinations are selected simultaneously. That is, the switch MO3FE controlled by the odd field signal FA
By TQI 8, the output signal Sv1 of the vertical shift register VSR is applied to the vertical scanning line V that selects the horizontal signal line H3I.
Output to LI. Similarly, the switches MO3FET02G and Q22 controlled by the signal FA cause the output signal SV2 of the vertical shift register VSR to be applied to the vertical scanning line VL2 so as to simultaneously select the horizontal signal lines H32 and H83.
is output to VL3.

Thereafter, selection signals for a pair of horizontal signal lines consisting of combinations in the same order are formed.

In addition, in the second (even numbered) field, the vertical scanning line VLI
to VL4, adjacent vertical scanning lines VLI and VL2
and simultaneously selected in combination of VL3 and VL4 (7). That is, the output signal SVI of the vertical shift register vSR is transferred to the horizontal signal line H by the switches MO3FETQ19 and Q21 controlled by the even field signal FB.
Vertical scan 1 which selects 3I and H32 is output to VL1 and VL2. Similarly, the output signal SV2 of the vertical shift register VSR is controlled by the switches MO3FETQ23 and Q25 controlled by the signal FB so that the vertical scanning lines VL3 and VL4 simultaneously select the horizontal signal lines H33 and IS4.
is output to. Thereafter, selection signals for a pair of horizontal signal lines consisting of combinations in the same order are formed.

A plurality of types of horizontal scanning operations as described below are realized by the interlace gate circuit ITG as described above and the following drive circuit DV.

The output signal from the interlaced gate circuit ITG corresponding to the one vertical scanning line VLI is transmitted to the switch MO3F.
Supplied to the gates of ETQI 4 and Q15. The common drain electrodes of these switches MO3FETs QI4 and Q15 are coupled to terminal V3. The switch MO3FETQI4 supplies the signal supplied from the terminal v3 to the vertical scanning line VLI. Also, switch MO
The 3FET Q15 supplies the signal supplied from the terminal v3 to the gate of a switch MO3FETQ8 that couples the horizontal signal line 1 (Sl) to the output line vS.

Also, the high level of the output signal is the switch MO3FETQ
14. In order to prevent the threshold voltage from decreasing by the threshold voltage due to Q15, although not particularly limited, MO3FET
A capacitor C1 is provided between the gate of QI4 and the output side (source side) of MO3FETQ15. As a result, when the output signal from the increase gate circuit ITG is set to a high level, the potential of the terminal v3 is set to a low level and the capacitor C1 is precharged.

After this, when the potential of the terminal v3 is set to high level, the above-mentioned MO
The gate voltage of 3FET QI4 and Q15 can be boosted.

The output signal from the incremental gate circuit ITG corresponding to the vertical scanning line VL2 adjacent to the vertical scanning mVL1 is supplied to the gates of the switches MO3FETQI6 and Q17. The common drain electrodes of these switches MO5FETQI6 and Q17 (7) are coupled to the terminal 4. The switch MO8FETQ16 supplies the signal supplied from the terminal v4 to the vertical scanning line VL2. Switch MO3FETQI 7 connects the above terminal v4
is supplied to the gate of a switch MO5FETQ9 that couples the horizontal signal line H32 to the output line VS. The high level of the output signal is the switch MO3FETQ
In order to prevent the threshold voltage from decreasing by the threshold voltage due to I6 and Q17, MO3FE is used, although it is not particularly limited.
A capacitor C2 is provided between the gate of TQ16 and the output side (source side) of MO3FETQI7. As a result, by changing the potential of the terminal v4 at the same timing as described above, the gate voltages of the MOSFETs QI6 and Q16 can be boosted by the bootstrap action of the capacitor C2.

The above terminal v3 is an odd-numbered vertical scanning line (horizontal signal m)
The terminal v4 is provided in common for the drive switch MO3FET corresponding to the above, and the terminal v4 is provided in common for even-numbered vertical scanning lines (horizontal signal lines).

As can be understood from the above, the read operation in the interlace mode is achieved by the combination of selectively supplying timing signals to the terminals v3 and v4 and the simultaneous selection of two rows by the interlace gate circuit ITG. For example, in an odd field in which the terminal FA is set to a high level, by keeping the terminal v4 at a low level and supplying a timing signal synchronized with the operation of the vertical shift register VSR to the terminal ■3,
Vertical scanning line (horizontal signal line) VLI (H31), VL
3 (H33). In addition, in an even field in which the terminal FB is set to high level, the vertical scanning line ( It is possible to select the horizontal signal line (horizontal signal line) in the order of VL2 (H32), VL4 (H54) (7).

On the other hand, if the terminals V3 and 4 are simultaneously set to high level in the same manner as described above, two rows can be simultaneously scanned in accordance with the output signal from the interlace gate circuit ITG.

In this case, as mentioned above, two field signals FA and F
By shifting the combination of two lines outputted every two screens by B up and down by one line, the spatial center of gravity is shifted up and down, in other words, an isometric interlace mode is realized.

Furthermore, for example, by setting only the terminal FB to a high level, the horizontal shift register H3R is set to 2 at one vertical scanning timing.
By operating the terminals V3 and V4 at high level in synchronization with the operation, VLl, VL2 . VL3.
It is possible to realize a selection operation in a non-increment mode such as VL4 (7) order.

In this case, in order to achieve higher image quality, it is desirable that the clocks supplied to the horizontal shift register H3R and vertical shift register VSR be doubled in frequency. By doubling the frequency of the clock signal supplied to the shift register H3R and the vertical shift register VSR, it is possible to read out 60 images per second in a non-interlaced manner. Note that the terminals HIN and ViN are terminals that supply input signals to be shifted by the shift registers H3R and VSR, respectively, and a shift operation is started from the time the input signals are supplied. Therefore, the increase gate circuit ITG and the input terminal V3. Depending on the combination of input signals supplied to V4, simultaneous reading of the two rows, incremental scanning,
When non-incremental scanning or the like is performed, consideration must be given to the timing when supplying the input signal to the shift register VSR so that the vertical relationship of the output signal is not reversed.

Furthermore, reset MOS FETs QIO and Qll are provided between the gates of each of the vertical scanning lines VLI and the corresponding switches MO5FETQ8 and the ground potential point of the circuit. These reset MO3FETQI O
and Qll are the other vertical scanning lines and switch MOS F
In response to the clock signal supplied from terminal 2 in common with the reset MO3FET provided corresponding to the ET, the vertical scanning line and switch MOS FET in the selected state are
The gate potential of the circuit is pulled down to a low level at high speed.

In this embodiment, in order to add the variable function as described above, a vertical shift register VSRE for sensitivity control, an interlace gate circuit ITGE, and a drive circuit DVE are provided. Each of these sensitivity control circuits is arranged on the left side with respect to the pixel array PD, although it is not particularly limited. These vertical shift register VSRE, increment gate circuit ITG, and drive circuit DVE are constituted by circuits similar to the above-mentioned vertical shift register VSR for reading, interlace gate circuit ITG, and drive circuit DV. Timing signals similar to those described above are supplied from terminals VIE to V4E, VINE, FAE, and ABE, respectively. In this case, since the vertical shift register VSR for readout and the vertical shift register VSRE for variable sensitivity are shifted at synchronized timing, the terminals VIE and vl and V2E and v2 are not particularly limited. , are supplied with the same clock signal. Therefore, the above-mentioned terminals VIE and vl and v2E and v2 may be shared by an internal circuit.The reason why the unique terminals VIE and V2B are provided as described above is as follows.
This solid-state imaging device is intended to be applicable to television cameras with manual aperture or conventional mechanical aperture functions. When the sensitivity variable operation is not performed in this way, the vertical shift register VS
Consideration has been taken to avoid wasteful power consumption of the RE.

Next, the sensitivity control operation in the solid-state imaging device of this embodiment will be explained.

To simplify the explanation, the vertical scanning operation in the non-interlaced mode will be described below as an example. For example, by the vertical shift register VSRE for sensitivity control, the interlace gate circuit ITGB, and the drive circuit DVE,
In parallel with the reading of the first row (vertical scanning line VLI, horizontal signal line H81) by the vertical shift register VSR, interlace gate circuit TG and drive circuit DV for reading, the fourth row (vertical scanning line VL4) is read out. , horizontal signal line H34
) selection operation. As a result, the horizontal scanning lines HLI・,H formed by the horizontal shift register H3H
In synchronization with the selection operation of L2, etc., the output signal line vS has the first
The optical signals accumulated in the photodiodes D1, D2, etc. in the row are read out in time series. This read operation is performed by supplying a current corresponding to the optical signal from the terminal S through the load resistor, and a precharge (reset) operation is performed simultaneously with the read operation. A similar operation is
This is also done in the photodiode in the fourth row. In this case, the scanning circuit for devil variable (VS
RE, ITGE, DVE), the read operation on the fourth row is performed on the dummy output line DVS. When only the sensitivity control operation is performed, the same bias voltage as the terminal S is applied to the terminal RV. As a result, the optical signals already accumulated in each pixel cell in the fourth row are swept out, or in other words, a reset operation is performed.

Therefore, by the above vertical scanning operation, the vertical shift register VSR for reading and the interlace gate circuit T
41st Te (vertical scanning line V) by TG and drive circuit DV
L4, horizontal signal line H34) readout operation is performed by the above-mentioned first
Since this is performed after the readout operation of the first to third rows, the storage time of the photodiode of the pixel cell arranged in the fourth row is the readout time of the pixel cells of three rows.

In place of the above, vertical shift register VSR for sensitivity control
E, increase gate circuit ITGE and drive circuit DV
By E, vertical shift register VSR for reading,
Interlace gate circuit ■Selection of the second row (vertical scanning line VL2, horizontal signal line H32) in parallel with reading of the first row (vertical scanning line VL1, horizontal signal line H3l) by TG and drive circuit DV make the action take place. by this,
Horizontal scanning line HL1. formed by horizontal shift register H3H. In synchronization with the selection operation of HL2 etc., the output signal vA
vS includes photodiodes D1 and D2 in the first row.
The optical signals accumulated in the above are read out in time series. This read operation is performed by supplying a current corresponding to the optical signal from the terminal S through the load resistor, and a precharge (reset) operation is performed simultaneously with the read operation. A similar operation occurs in the photodiode D3 in the second row,
This is also done in D4 etc. As a result, in parallel with the readout operation of the first row, the operation of sweeping out the optical signals already accumulated in each pixel cell of the second row is performed. Therefore, by the vertical scanning operation, the reading operation of the second row (vertical scanning @VL2, horizontal signal line IS2) by the reading vertical shift register VSR, interlace gate circuit ITG, and drive circuit DV is performed by the reading vertical shift register VSR, interlace gate circuit ITG, and drive circuit DV. Since this is performed after the row readout operation, the storage time of the photodiodes of the pixel cells arranged in the second row is the readout time of the pixel cells for one row. This reduces the effective storage time of the photodiode by 1 compared to the above case.
/3, in other words, the sensitivity is reduced to 1/3.
It can be lowered to 3.

As mentioned above, since the pixel cells in that row are reset by the preceding vertical scanning operation performed by the scanning circuit for sensitivity control, the period from the reset operation to the actual reading by the scanning circuit for reading out is The time is taken as the storage time for the photodiode. Therefore, in a pixel array consisting of 525 rows, the readout time for one row is a maximum of 262 rows per unit (minimum) due to the different addressing by both vertical scanning circuits and the pixel cell selection operation by the common horizontal scanning circuit. In other words, the sensitivity can be set over 262 stages. However, it is assumed that the change in the light-receiving surface illuminance can be ignored with respect to the scanning time constituting one screen, and that substantially constant light is incident on the photodiode. In addition, the maximum sensitivity (262) is
The scanning circuit for sensitivity control is obtained in a non-operating state.

FIG. 1 shows a block diagram of an embodiment of a monitoring device using the solid-state imaging device.

The solid-state imaging device MID shown in the figure has a variable sensitivity function and a two-wire output function as shown in FIG. 2 above. That is, the solid-state imaging device MID has its pixel array P
Vertical shift register VSR,V as described above for D
SRE, interlace gate circuit IG, ITGE and drive circuit VD.

It has a pair of vertical scanning circuits each composed of VDB, and simultaneously selects different rows from the pixel array by each vertical scanning operation, and simultaneously receives video signals from terminals S and RV in synchronization with the scanning operation by the horizontal shift register H5R. Output. In this embodiment, in order to realize the function of detecting the presence or absence of movement of a subject, the video signal from the terminal RV for controlling the sensitivity is used. Thereby, the presence or absence of movement of the subject can be determined by direct signal processing using a simplified signal processing circuit as described later, without using an image memory (frame memory) or the like.

One of the video signals output from the terminal S of the solid-state imaging device MID is amplified by the preamplifier PA1. The output signal Sv of this preamplifier FAI is supplied to one input terminal of an adder circuit ADD, although not particularly limited, and the other is supplied to a non-inverting input terminal (+) of a subtraction circuit OP consisting of an operational amplifier circuit or the like. Ru. The other video signal output from the terminal RV is amplified by the preamplifier PA2. This preamplifier P
The output signal RVE of A2 is output from the vertical scanning circuit VSEL consisting of a vertical shift register etc. and the preamplifier PA as described above.
The signal is supplied to a delay circuit DLY for obtaining temporal consistency with the output signal of L.

The output signal RVE' of the delay circuit DLY is supplied on one side to the other input terminal of the addition circuit ADD, although not particularly limited, and on the other hand to the inverting input terminal (-) of the subtraction circuit OP. The above adding circuit ADD
As described above, the two image signals Sv and RVE' for which temporal consistency has been obtained are added together, and the signal level is increased to improve the signal-to-noise ratio (S/N), etc. It is something. The addition output signal of this addition circuit ADD is input to the video processing circuit vP. The video process circuit VP is
The input signal Vin of the recording device VTR is generated using the above addition output signal and the timing signal supplied from the synchronization signal generation circuit 5YNC. The adder circuit ADD is not particularly required, and may be configured to supply the output signal SV of the preamplifier PAL as it is to the input of the video processing circuit VP.

The subtraction circuit OP sends out a signal Vo representing the difference between the two signals from its output. That is, when the two signals are equal, in other words, when there is no movement of the subject, the subtraction circuit OP cancels out the two signals to form a zero signal Vo. Furthermore, if there is movement in the subject, the corresponding video signals will have different results, so an output signal vO is generated accordingly. In addition to using an operational amplification circuit as the subtraction circuit oP, for example, the preamplifier PA2 may be caused to perform an inversion amplification operation, or its output signal or delayed signal may be inverted to make both signals relatively opposite in phase. This also allows the use of a simple resistance adder circuit.

The output signal Vo of the subtraction circuit oP is input to the timer circuit TM via the coupling capacitor CC.

The coupling capacitor CC is connected to the output signal V
Only the alternating current component of o is transmitted to the timer circuit TM. In this way, when only the alternating current component is taken out by the coupling capacitor CC, even if there is a slight level difference between the two outputs of the subtraction circuit oP, it can be regarded as a direct current component, so level matching can be simplified. be. The timer circuit TM performs a timekeeping operation for a certain period of time using the AC component as a trigger.The timer circuit TM includes:
Since the trigger has a logic threshold voltage, activation occurs when an AC signal of a certain level exceeding the logic threshold voltage is supplied. When the alternating current signal as the trigger signal is repeatedly supplied within a set time, the timer circuit TM is activated each time, and as a result, the timer circuit TM stops after the time measurement operation corresponding to the last trigger force is applied.

While the timer circuit TM is activated as described above, it forms a control signal that instructs the recording device VTR to record REC, and when the timer circuit TM wants to stop its timekeeping operation, it instructs it to stop recording STP. form a control signal.

Note that instead of the above configuration, the output signal of the subtraction circuit OP is rectified, and a voltage comparison circuit compares the rectified subtraction output with a predetermined reference level, thereby directly forming a control signal for the recording device. In this case, it is desirable that the voltage comparator circuit has a hysteresis characteristic to prevent an oscillation state caused by the rectified subtracted output being maintained constant near the reference voltage. When setting the minimum recording time for the recording device VTR using the timer circuit TM as described above, it is possible to prevent frames from appearing continuously when playing back the recording state. .

In addition, in order to set the levels of the video signals output from the two output terminals S and RV of the solid-state imaging device MID to be equal, two vertical scanning circuits corresponding to each A time shift is set by half, ie, 131 lines. Therefore, in this case, the delay circuit DLY is set to a delay time corresponding to the time difference.

In order to simplify the delay circuit DLY, the vertical scanning operation of the terminal S may be performed with a time difference of one or two lines with respect to the vertical scanning operation corresponding to the terminal RV. In this case, a highly accurate delay time can be obtained using a relatively simple COD (charge-coupled device). However, in this case, a level difference will occur between the video signal output from the terminal RV and the video signal output from the terminal S. If a level difference occurs between the two signals, the above-mentioned subtraction An attenuation circuit or an amplification circuit for level matching may be inserted into the input of the circuit OP to match the levels of both signals.

In this embodiment, the presence or absence of movement of the subject is detected from the subtraction result of two video signals whose levels are matched according to time and necessity, so it is possible to determine the presence or absence of movement of the subject with high accuracy. Can be done.

Therefore, since the recording device VTR records only when there is movement in the subject, the recording tape can be used efficiently and its playback can be easily checked.

(Embodiment 2) FIG. 3 shows a block diagram of another embodiment of the present invention.

In this embodiment, two output terminals S and RV are used as described above.
Instead of comparing two video signals outputted from a solid-state imaging device MID with temporal correspondence, this method simply calculates the difference in smoothing level between the two signals. In other words, when a condition to be monitored occurs on the monitoring screen,
In other words, it detects when a different subject enters the screen or when the brightness of the entire screen changes depending on the movement of the subject. Therefore, the output signals of the two preamplifiers FAI and PA2 similar to that shown in FIG.
It is converted into a direct current by T2. Smoothing circuit DETI, DET2
The voltage outputs Vl and V2 respectively formed by the above correspond to the average brightness of the video signal at different times. In order to match the levels of the two video signals output from the terminals S and RV of the solid-state imaging device MID, the difference in scanning time between the pair of vertical scanning circuits in the solid-state imaging device MID is , is set for 131 lines as above.

Output signals of the above two smoothing circuits DETI and DET2■1
and v2 are subtracted by a subtraction circuit OP similar to the above.

The output signal V of this subtraction circuit OP.

is supplied to the voltage comparator circuit VC. This voltage comparison circuit V
C compares the output signal Vo and the reference voltage Vref to form a starting signal for a timer circuit TM similar to the above.

The output signal Vo of the subtraction circuit oP is a voltage signal of positive/negative polarity depending on the relative level difference between the two smoothed voltages v1 and v2. Therefore, the voltage comparator circuit VC is
It should be understood that the voltage comparator circuit is composed of two voltage comparison circuits each receiving a positive reference voltage and a negative reference voltage, and an OR circuit receiving their output signals. Therefore, the reference voltage Vref indicates its absolute value. I want to be understood as something.

For example, if a moving subject enters a still screen, the brightness of the entire screen will change. Furthermore, when the subject moves within the screen, the background screen changes, so the brightness of the entire screen changes. Such changes in screen brightness are caused by the vertical scanning being performed with the time difference mentioned above.
This results in a change in the brightness of the two video signals. Smoothing circuits DETI and DET2 smooth the respective video signals to generate a voltage signal V according to their brightness.
1 and v2, an output signal corresponding to the presence or absence of a moving subject is obtained from the output of the subtraction diagram 90P, and this can be determined by the voltage comparison circuit VC. In response to this determination result, the timer circuit TM is activated, and as described above, a video signal in which a moving subject is present can be recorded by the recording device VTR, or in other words, can be monitored.

In this embodiment, the delay circuit DLY for obtaining temporal consistency between two video signals output with a time difference as shown in FIG. , Simplification and low cost of monitoring equipment! − It becomes possible to In this embodiment, since the time adjustment function (delay circuit DLY) of the two video signals is omitted, the adder circuit ADD is also omitted. That is, the output signal of the preamplifier PA1 (or it may be the output signal of the preamplifier PA2) is supplied as the input signal Vin to the recording device VTR via the video processing circuit VP.

(Embodiment 3) FIG. 4 shows a block diagram of still another embodiment of the present invention.

In this embodiment, instead of simply determining the difference in the smoothing level of two signals as described above, the presence or absence of a moving object is detected by determining the difference in high frequency components that indicate the outline of the object. It is. In other words, when a condition to be monitored occurs on the monitoring screen, in other words,
This is detected by focusing on the fact that a different subject enters the screen, or that the high frequency components corresponding to the line drawings across the screen differ depending on the movement of the subject.

Therefore, two preamplifiers PA similar to those shown in FIG.
The low frequency components of the output signals of L and PA2 are removed by the bypass filter HPF, and only predetermined high frequency components are converted into DC by the smoothing circuits DETl and DET2, respectively. In the figure, the bypass filter) (PF) and the smoothing circuits DETI and DET2 are each shown as one circuit block, and as mentioned above, each smoothing circuit DETI,
The bypass filter HPF is arranged on the input side of DET2. Smoothing circuit DET1゜DET
The voltage outputs Vl and v2 respectively formed by 2 correspond to the contours of the video signal at different times. The above two smoothing circuits DET1. The output signals v1 and v2 of DET2 are subtracted by a subtraction circuit OP similar to the above. The output signal vO of this subtraction circuit OP is supplied to the voltage comparison circuit VC. This voltage comparison circuit VC compares the output signal Vo and the reference voltage Vref to form a starting signal for a timer circuit TM similar to the above.

The output signal Vo of the subtraction circuit oP is a voltage signal of positive/negative polarity depending on the relative level difference between the two smoothed voltages v1 and v2. Therefore, similarly to the above, it should be understood that the voltage comparison circuit VC is composed of two voltage comparison circuits each receiving a positive reference voltage and a negative reference voltage, and an OR circuit receiving their output signals. , the reference voltage Vref should be understood to indicate its absolute value.

For example, when a moving subject enters a still screen, the outline of the moving subject and the outline of the background that corresponds to the movement of the moving subject will change, so the high frequency component that shows the outline of the entire screen will change. It is. Such a change in the high frequency components results in a difference in the high frequency components of the two video signals that are vertically scanned with the above-mentioned time difference.

The smoothing circuits DETI and DET2 form voltage signals v1 and v2 corresponding to the unification of the contours by smoothing the high frequency components of the respective video signals. The presence or absence of a moving subject can be determined by VC. In response to this determination result, the timer circuit TM is activated, and as described above, a video signal in which a moving subject is present can be recorded by the recording device 1VTR, or in other words, can be monitored.

In this embodiment, the delay circuit DLY for obtaining temporal consistency between two video signals outputted with a time difference as shown in FIG. 1 is not required, so adjustment of the delay time is not required. Furthermore, since high frequency components are compared, constraints on vertical scanning timing and level matching to obtain brightness consistency as shown in FIG. 3 are unnecessary. This makes it possible to simplify the monitoring device and its adjustment while reducing costs. In this embodiment, since the time adjustment function (delay circuit DLY) of the two video signals is omitted, the adder circuit ADD is also omitted.

That is, the output signal of the preamplifier FAI (or it may be the output signal of the preamplifier PA2) is supplied as the input signal Vin to the recording device VTR via the video processing circuit vP.

(Embodiment 4) FIG. 5 shows a block diagram of still another embodiment of the present invention.

In this embodiment, two output terminals S and RV are used as described above.
Instead of the solid-state imaging device MID having a single output terminal, a solid-state imaging device MID having one output terminal is used. In this case, a changeover switch SW is provided on the output terminal side of the preamplifier PA in order to form two video signals having the above-mentioned time difference. Although this changeover switch SW is not particularly limited, switching control is performed by the odd field signal FA and even field signal FB formed by the drive control circuit C0NT. When the field is even field FB, it is switched to the contact side. On the contact a side, there is a smoothing circuit DETI similar to the above, and its output signal v1.
A sample-and-hold circuit S/H is provided to hold the signal for an even field FB period. Further, on the contact side, a smoothing circuit DET2 similar to the above-mentioned smoothing circuit DET2 and a sample hold circuit S/H for holding the output signal v2 for the period of the odd field FA are provided. As a result, voltage signals v1 and v2 corresponding to the average brightness of the video signal with an isometric time difference are obtained.
can be formed. In this embodiment as well, the two smoothing circuits DETI are similar to the embodiment shown in FIG.

By subtracting the output signal Vl of DET2 and (2) by the subtraction circuit oP and supplying it to the voltage comparison circuit VC, it becomes possible to determine the presence or absence of a moving subject.

For example, when a moving subject enters a still screen, the brightness of the entire screen will differ between odd and even fields. Furthermore, when the subject moves within the screen, the background screen changes, so the brightness of the entire screen changes. Smoothing circuit DETI and DE
T2 forms voltage signals v1 and v2 corresponding to the brightness by smoothing each video signal, so an output signal corresponding to the presence or absence of a moving object (object) can be obtained from the output of the subtraction circuit OP. , it can be determined by the voltage comparison circuit VC.The timer circuit TM is activated in accordance with this determination result, and the video signal in which the moving subject is present is recorded by the recording device VTR in the same manner as described above.
In other words, it can be monitored.

In this embodiment, since a solid-state imaging device having only one output terminal function can be used, the drive control circuit C
The configuration of 0NT can be easily made. If bypass filters are provided at the inputs of the smoothing circuits DETI and DET2 as in the embodiment of FIG. 4, it is possible to determine a moving subject based on substantially the same principle as in FIG. 4.

As in the embodiment described above, the recording device VTR records only moving video signals, so magnetic tape can be used efficiently and only the recording that should be monitored is played back. can. This prevents the user's attention from becoming distracted when viewing the playback screen (and allows the user to quickly find suspicious persons and detect abnormal conditions on the monitoring screen).

The output signal of the solid-state imaging device may be one that is supplied to the recording device or one that is displayed on the screen of a monitor television. As a result, when video signals captured by a large number of imaging devices are monitored using a small number of monitors, video signals from solid-state imaging devices that have some movement on the screen are automatically selected. Since the images can be displayed on the monitor screen, monitoring can be done easily and efficiently using a small number of monitor televisions.

Furthermore, when performing signal processing using a pattern recognition device, the moving direction and speed of the subject can be determined.

That is, in the embodiment shown in FIG. 1, the direction and speed of the moving image can be calculated by detecting the difference in scanning time between the two vertical scanning circuits and the seated image of the moving image. Such a function effectively acts on, for example, a monitoring device such as the conveyance status of parts in a factory automation machine or the eyes of a robot.

The effects obtained from the above examples are as follows.

(1) A signal detection circuit detects the difference between two video signals output from the imaging device at different times, and the presence or absence of a moving subject is determined based on this detection output. This has the effect of enabling rational monitoring and control.

(2) Since the presence or absence of a moving subject is identified based on the video signal formed by the imaging device, it is possible to achieve the effect that reliable monitoring control is possible.

That is, when an ultrasonic sensor or the like is used, it also detects movement of objects other than the photographing screen, making it difficult to correspond to the photographing operation.

(3) a first scanning circuit that outputs signals of a plurality of pixel cells arranged two-dimensionally from a first terminal in time series; and a selection address in the vertical scanning direction by the first scanning circuit; a second scanning circuit that performs a selection operation in a vertical scanning direction using an independent address and outputs a time-series output from a second terminal in accordance with a horizontal scanning operation by the first scanning circuit; Among the output signals obtained from the terminal and the second terminal, the output signal output at an earlier timing is delayed to align the output signal with an output signal at a later timing, and the signal levels are made to match so that both output signals are output at the same time. By outputting the difference, two images with a time difference according to the scanning timing by the first and second scanning circuits are generated.
Since the video signals constituting the two screens can be obtained, there is no need to install an image memory, etc., and by simply adding a simple signal processing circuit that calculates the difference by matching the time difference between the two video signals and the level as necessary, The effect is that movement can be detected.

(4) According to (3) above, by adding a simple circuit that detects the difference between the above two signals, the video signal from the surveillance camera is sent to the recording device or monitor TV camera only when it is in a condition to be monitored. can do. This has the effect that an efficient monitoring device can be obtained with an extremely simple configuration.

(5) By controlling the recording/stopping of the recording device according to the detection result of the presence or absence of a moving subject, only moving video signals are recorded, so magnetic tape can be used efficiently. Since only the recorded state, which is the state that should be monitored, can be played back, there is no need to be distracted when looking at the playback screen. Effects can be obtained.

(6) To achieve temporal consistency between the two video signals by determining the presence or absence of movement of the subject by determining the average level difference between the two video signals output from the imaging device at different times. This eliminates the need for a delay circuit, resulting in the simplification of the device and the ease of adjustment.

(ηThe temporal alignment of the two video signals is determined by determining the presence or absence of movement of the subject by determining the difference in high-frequency components indicating the outline of the object in the two video signals output at different times from the imaging device.) This eliminates the need for a delay circuit or a level matching circuit for achieving consistency and level consistency, resulting in the effects that the device can be simplified and its adjustment can be made easier.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, the rain detection methods of the embodiments shown in FIGS. 3 and 4 may be provided, and the presence or absence of a moving subject may be determined based on the OR output. , changes in high frequency components representing the contour may be detected, and if any one change is detected, it may be determined that there is a moving subject.

Such a detection method may be applied to an imaging device having one output terminal as shown in FIG.
The stop control of the video device VTR may utilize a pause function (pause) in the recording state.

In addition, in the embodiment shown in Fig. 1, which performs pixel-by-pixel comparison, in order to prevent excessive response to minute object movements, video signals corresponding to discrete scanning lines are compared. Further, the reference level for determining the presence or absence of a moving subject may be adjustable based on the subtraction output of each pixel, the average brightness, or the subtraction output of high frequency components. In addition to this, settings can be made according to the shooting environment and usage.

Since the present invention can detect the movement of a subject, it can be widely used in various monitoring devices used as surveillance cameras, FA (factory automation) cameras, and robot eyes.

〔Effect of the invention〕

A brief explanation of the disadvantages obtained by typical inventions disclosed in this application is as follows. That is, a signal detection circuit detects the difference in signal components based on two video signals output from an imaging device at different times, and the presence or absence of a moving subject is determined based on this detection output, thereby determining the movement of the subject. It becomes possible to perform rational monitoring and control depending on the presence or absence.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a monitoring device according to the present invention, FIG. 2 is a schematic circuit diagram showing an embodiment of a solid-state imaging circuit used in the monitoring device, and FIG. FIG. 4 is a block diagram showing still another embodiment of the monitoring device according to the present invention; FIG. 5 is a block diagram showing still another embodiment of the monitoring device according to the present invention; FIG. FIG. 7 is a block diagram showing still another embodiment of the device. PD: Pixel array, VSR: Vertical shift register for readout, ITG: Increment gate circuit for readout, DV: Drive circuit for readout, VSRE: Vertical shift register for sensitivity setting, ITGE: Ink for sensitivity setting Race gate circuit, DVE...sensitivity setting drive circuit,
H3R...Horizontal shift register, MID...Solid-state imaging circuit, PA.

Claims (1)

[Claims] 1. A subject that includes an imaging device and a signal comparison circuit that detects a difference between two video signals output from the imaging device at different times, and that moves based on the output signal of the signal comparison circuit. A monitoring device characterized by having a function of detecting the presence or absence of. 2. The function of detecting the presence or absence of a moving subject is performed by the recording/recording device that receives the video signal output from the imaging device.
2. The monitoring device according to claim 1, wherein the monitoring device performs stop control. 3. The imaging device includes a first scanning circuit that outputs signals of a plurality of pixel cells arranged two-dimensionally from a first terminal in time series, and a vertical scanning direction by the first scanning circuit. A second scanning circuit that performs a selection operation in the vertical scanning direction using an address independent of the selection address of the first scanning circuit, and outputs data from the second terminal in time series according to the horizontal scanning operation of the first scanning circuit.
3. The monitoring device according to claim 1, wherein the monitoring device is a solid-state imaging device including a scanning circuit. 4. The signal comparison circuit delays the output signal output at an earlier timing among the output signals from the first and second terminals of the solid-state imaging device, and compares the output signal with the output signal output at a later timing. 4. The monitoring device according to claim 3, further comprising a signal processing circuit that performs time adjustment, matches the signal levels, and outputs the difference between the two signals. 5. Claims 1 and 2, characterized in that the signal comparison circuit has a function of converting the high frequency components of the two video signals into direct current and detecting the level difference between them.
, the monitoring device according to item 3. 6. The solid-state imaging device has two-dimensionally arranged pixel cells consisting of a photoelectric conversion element, a switch element whose control terminal is coupled to a vertical scanning line, and a switch element whose control terminal is coupled to a horizontal scanning line. The output nodes of the pixel cells arranged in the same row are coupled to a horizontal signal line, and this horizontal signal line is connected to the first pixel cell through a pair of switch elements whose control terminals are coupled to the corresponding vertical scanning line. and a pair of output signal lines respectively coupled to the second terminal;
A patent claim characterized in that the vertical shift register included in the first scanning circuit and the vertical shift register included in the second scanning circuit are respectively arranged corresponding to the pair of switch elements. The monitoring device according to the third, fourth or fifth item.