JPH01102880U - - Google Patents
Info
- Publication number
- JPH01102880U JPH01102880U JP20109887U JP20109887U JPH01102880U JP H01102880 U JPH01102880 U JP H01102880U JP 20109887 U JP20109887 U JP 20109887U JP 20109887 U JP20109887 U JP 20109887U JP H01102880 U JPH01102880 U JP H01102880U
- Authority
- JP
- Japan
- Prior art keywords
- surface mount
- mount package
- connector
- pin
- utility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Tests Of Electronic Circuits (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20109887U JPH01102880U (de) | 1987-12-28 | 1987-12-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20109887U JPH01102880U (de) | 1987-12-28 | 1987-12-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01102880U true JPH01102880U (de) | 1989-07-11 |
Family
ID=31491475
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20109887U Pending JPH01102880U (de) | 1987-12-28 | 1987-12-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01102880U (de) |
-
1987
- 1987-12-28 JP JP20109887U patent/JPH01102880U/ja active Pending