JPH0110018Y2 - - Google Patents

Description

[Detailed description of the invention] This invention relates to a receiving device that receives television signals through tuning control of tuning signals.
The purpose is to improve the performance of tuning control.

An example of a conventional receiving device of this kind is constructed as shown in FIG. Convert and output. 2 is an intermediate frequency amplification circuit connected to tuner 1, which amplifies and outputs the intermediate frequency signal of tuner 1, and also amplifies and outputs the intermediate frequency signal of tuner 1.
Outputs signal Sb. 3 is a synchronization circuit to which the intermediate frequency signal of the intermediate frequency amplification circuit 2 is input; by separating and extracting the intermediate frequency signal, it outputs a horizontal synchronization signal Sc of the television signal, and also outputs a horizontal oscillation signal Sd, which will be described later. .

4 is a discrimination circuit to which the AFT signal Sb, horizontal synchronization signal Sc, and horizontal oscillation signal Sd are input, and outputs first and second discrimination signals Se and Sf, which will be described later.

Reference numeral 5 denotes a voltage control unit to which both discrimination signals Se and Sf are input, and it outputs a band switching command signal for a reception band switching command, and also outputs both discrimination signals Se, Sf.
A read command signal of the tuning data signal Sg is output to the memory 6 by processing Sf, and a digital tuning data signal read out from the memory 6.
Sg is output to the analog converter 7.

A band switching section 8 outputs a band switching signal to the tuner 1 upon input of a band switching command signal, and controls the reception band of the tuner 1.

Reference numeral 9 denotes a low-pass filter to which the output signal of the analog conversion section 7 is input, and outputs to the tuner 1 a tuning signal Sa formed by analog conversion of the output signal of the conversion section 7, that is, the tuning data signal Sg.

10 is a tuning control circuit consisting of a voltage control section 5, a memory 6, an analog conversion section 7, a band switching section 8, and a filter 9.

Furthermore, the discrimination circuit 4 is configured as shown in FIG. 2, in which Ia is a synchronization input terminal to which a horizontal synchronization signal Sc is input, Ib is an oscillation input terminal to which a horizontal oscillation signal Sd is input, First capacitor Ca, diode Da, resistor Ra for decoupling
is connected to a 12 volt first power supply Va.

Aa is the first comparator whose inverting input terminal - is connected to the input terminal Ia via a diode Db, and its non-inverting input terminal + is connected to the power supply Va via a resistor Rb and grounded via a resistor Rc. has been done.
Vb is the 12 volt second power supply connected to the output terminal of comparator Aa through resistor Rd, Re, Cb are the comparator
Integrating resistor and capacitor installed in series between Aa output terminal and ground; Rf and Cc are resistors
This is an integrating resistor and capacitor that are connected in series between the connection point of Re and capacitor Cb and the ground, and forms a two-stage integrating circuit together with resistor Re and capacitor Cb.

Ab is the inverting input terminal - is the resistor Rf and the capacitor Cc
This is the second comparator connected to the connection point of
Connected to Va.

Ic is an AFT input terminal to which the AFT signal Sb is input, and a voltage obtained by dividing the voltage of the power supply Va by the resistors Ri and Rj is applied. Ac is a third comparator whose non-inverting input terminal + is connected to the input terminal Ic via a resistor Rk, and the voltage of the power supply Va is divided into the inverting input terminal - by a series circuit of resistors R and Rm and a resistor Rn. voltage is applied. Cd is a filter capacitor provided between the non-inverting input terminal + of the comparator Ac and the ground.

Ad is a fourth comparator whose inverting input terminal - is connected to the non-inverting input terminal + of the comparator Ac, and the voltage of the power supply Va is connected to the non-inverting input terminal + by a resistor R and a resistor Rm.
A voltage divided by a series circuit of Rn is applied.

Oa is a first discrimination output terminal connected to the output terminal of the comparator Ad, and outputs a first discrimination signal Se.
Vc is 5 connected to output terminal Oa via resistor Ro.
Volt third power supply, DC is output terminal Oa and comparator Ab
This is a backflow prevention diode installed between the output terminal and the output terminal.

Ob is a second discrimination output terminal connected to the output terminal of the comparator Ac, and outputs a second discrimination signal Sf.
Rp is the load resistance of output terminal Ob, Dd is output terminal Ob
This is a backflow prevention diode provided between the output terminal of the comparator Ab and the output terminal of the comparator Ab.

At the time of tuning, the tuning signal Sa based on the tuning data signal Sg read from the memory 6 and the band switching signal from the band switching section 8 are input to the tuner 1, and the reception band of the tuner 1 is controlled by the band switching signal. At the same time, tuner 1 is tuned by the tuning signal Sa.
controlled by the voltage.

Furthermore, the intermediate frequency amplification circuit 2 outputs an AFT whose level becomes 0 at the true tuning point fo, as shown in Figure 3a.
Signal Sb is output.

Note that a in the figure is the first lower limit point where the tuner 1 shifts from the true tuning point fo to the lower frequency side and the AFT signal Sb first becomes a high level lower limit reference level vx;
In b, tuner 1 shifts further to the lower frequency side than the first lower limit point a, and the AFT signal Sb returns to the lower limit reference level.
The second lower limit point that becomes vx, c is the second lower limit point of tuner 1
This is the lower limit detuning point at which the AFT signal Sb is no longer generated by shifting further to the lower frequency side than the lower limit point b, and forms the lower limit base point.

ha is the first upper limit point where tuner 1 shifts from the true tuning point fo to the high frequency side and the AFT signal Sb first becomes the low level upper limit reference level vy; hb is tuner 1
is further shifted to the high frequency side from the first upper limit point ha.
Second, the AFT signal Sb reaches the upper reference level vy again.
The upper limit point, hc, is the upper limit detuning point at which the tuner 1 shifts further to the higher frequency side than the second upper limit point hb, and no longer generates the AFT signal Sb.

On the other hand, the horizontal oscillation signal output from the synchronous circuit 3
Sd is formed by free-running oscillation of the oscillation circuit of the synchronization circuit 3 at the frequency of the horizontal synchronization signal Sc when the power is turned on.

When the tuner 1 starts to tune to the television signal, the synchronization circuit 3 outputs the horizontal synchronization signal Sc as shown in FIG. The phase of the horizontal oscillation signal Sd deviates from the phase of the horizontal synchronization signal Sc.

While the phases of both signals Sc and Sd are shifted, as shown in Fig. 4c, the inverting input terminal of comparator Aa -
The level of the output terminal of the comparator Aa is held at a low level, and the level of the output terminal of the comparator Aa is held at a high level as shown in d of the figure.

Furthermore, when the level of the output terminal of comparator Aa is held at high level, the level of the inverting input terminal of comparator Ab is held at high level, and at this time, the level of the inverting input terminal of comparator Ab is The level va shown in the dashed line in Fig. 4d, that is, the comparator
Reference level set to Ab non-inverting input terminal +
Since the level is higher than va, the level of the output terminal of the comparator Ab is maintained at the low level of 0 volts, as shown in e of the figure.

Next, when the tuner 1 is tuned to the television signal from the case shown in Fig. 4, the phase of the horizontal synchronization signal Sc in Fig. 5a and the phase of the horizontal oscillation signal Sd in Fig. 5b match, and at this time, the comparison The inverting input terminal - of the device Aa changes from high level to low level in synchronization with both signals Sc and Sd, as shown in FIG.

And the output terminal of comparator Aa is the inverting input terminal −
Since the level is the inverse of the level of the comparator
The level at the inverting input terminal of Ab is the level obtained by integrating the level change at the output terminal of the comparator Aa by an integrating circuit consisting of a resistor Re and a capacitor Cb, and an integrating circuit consisting of a resistor Rf and a capacitor Cc, that is, the level of the fifth As shown in Figure d, it is held at a lower level than the reference level va, and the level at the output terminal of comparator Ab becomes high level, as shown in Figure e.

Therefore, as shown in FIG. 3b, the level of the output terminal of comparator Ab remains at the lower limit base point c while the phases of both signals Sc and Sd match and a normal television image can be obtained. to the upper limit base point hd between the first and second upper limit points ha and hb.

Furthermore, since the non-inverting input terminal + of the comparator Ad is set and held at the lower limit reference level vx, if the output terminal is in an open state, the transition from the second lower limit point b to the first lower limit point is shown in FIG. 3c. The output terminal of the comparator Ad becomes low level only during the first lower tuning section Fb up to a.

In addition, since the inverting input terminal - of the comparator Ac is set and held at the upper limit reference level vy, if the output terminal is open, the second
The level of the output terminal of the comparator Ac becomes low level only between the upper limit point hb and the first upper limit point ha.

Then, the logical product of the level of the output terminal of the comparator Ab and the level of the output terminal of the comparator Ad is calculated by the diode Dc, and the output terminal Oa is
As shown in FIG.
Only the level of the lower tuning section Fb is the level of the lower detuning section Fc, which has a lower frequency than the lower limit base point c, and the upper detuning section Fd, which has a higher frequency than the upper limit base point hd.
The first discrimination signal becomes the same low level as the level of
Se is output.

Further, the logical product of the level of the output terminal of the comparator Ab and the level of the output terminal of the comparator Ac is calculated by the diode Dd, and the output terminal Ob is
As shown in , while either one of the output terminals of both comparators Ab and Ac is at low level, that is, the first
A second discrimination signal Sf is output in which the level of the upper tuning section Fe from the upper limit point ha to the upper limit base point hd becomes the same low level as the levels of both detuning sections Fc and Fd.

In addition, Ff in Fig. 3 e and f indicates the true tuning interval from the first lower limit point a to the first upper limit point ha, and Fg indicates the second true tuning interval from the lower limit base point c to the second lower limit point b.
Indicates the lower tuning section.

By the way, the frequency of the true tuning section Ff is the so-called true tuning frequency, and the memory 6 digitally stores the voltage data of the tuning signal Sa corresponding to the frequency of the true tuning section Ff.
A tuning data signal Sg corresponding to a frequency lower than the frequency of Ff is first read out from the memory 6 to the voltage control section 5.

In other words, when temperature drift occurs,
True tuning interval due to rising deviation of tuning frequency
Since the shift from Ff to the high frequency side occurs more easily than the shift from the true tuning section Ff to the low frequency side due to a drop in the tuning frequency, the voltage of the first tuning signal Sa at the time of tuning is lower than the true tuning section Ff. It is set to a voltage of the same frequency and performs a so-called offset operation.

Note that the deviation of the receiving frequency from the true tuning interval Ff due to the first tuning signal Sa varies depending on the receiving band. For example, in the case of VHF low band, the receiving frequency is 60KHz or more from the true tuning interval Ff.
When set to a low frequency of 130KHz, and in the VHF high band, the receiving frequency is 120KHz from the true tuning interval Ff.
It is set to a low frequency of 380KHz, and when in the UHF band, the receiving frequency is from 240KHz to the true tuning interval Ff.
Set to 680KHz lower frequency.

When the tuner 1 starts receiving the first tuning signal Sa, the voltage control section 5 increases or decreases the level of the tuning signal Sa by a predetermined amount at predetermined intervals based on the levels of the first and second discrimination signals Se and Sf. The reception frequency of the tuner 1 is pulled into the frequency of the true tuning section Ff, and the tuning of the tuner 1 is controlled.

That is, in the first lower tuning section Fb in which the first discrimination signal Se is at a low level and the second discrimination signal Sf is at a high level, the period of 60 m ^sec until both discrimination signals Se and Sf become high level. At each time, the receiving frequency of the tuner 1 is controlled to increase by a predetermined frequency between 80 KHz and 250 KHz.

In addition, in the upper tuning section Fe where the first discrimination signal Se is high level and the second discrimination signal Sf is low level, the tuner is tuned every 60 m ^sec until both discrimination signals Se and Sf become high level. The receiving frequency of 1 is controlled to decrease by a predetermined frequency between 80 KHz and 250 KHz.

Furthermore, when both discrimination signals Se and Sf are at high level, the voltage control unit 5 detects that it is in the true tuning interval Ff, and the level change of the tuning signal Sa is stopped, and the receiving frequency of the tuner 1 is kept fixed. be done.

Furthermore, when both discrimination signals Se and Sf are at low level, the voltage control section 5 detects that the lower detuning section Fc or the upper detuning section Fd is present, and at this time, the receiving frequency of the tuner 1 is also It is held fixed.

By the way, when the reception frequency of tuner 1 becomes the frequency of the second lower tuning interval Fg due to temperature drift, etc., both discrimination signals Se and Sf become high level at this time, so the reception frequency is held fixed and becomes the frequency of the true tuning interval Ff. I can't get drawn into it.

Also, if the receiving frequency of tuner 1 is in the upper tuning section
Even when the frequency is Fd, the receiving frequency is held fixed and is not drawn into the true tuning interval Ff.

In other words, even though the AFT signal Sa is output, the receiving frequency is in the second lower tuning section Fg.
When the received frequency deviates from the tuning base range Fa to the upper detuning interval Fd, it is impossible to perform tuning control by pulling into the true tuning interval Ff. It is impossible to draw in and control the synchronization, which is very inconvenient.

This invention was made with the above-mentioned points in mind, and includes a tuner that receives a television signal by controlling the tuning of a tuning signal, and a tuner that is connected to the tuner and whose level becomes 0 at the true tuning point. A first lower limit point of a frequency lower than the true tuning point, and a second lower limit point of a frequency lower than the first lower limit point become the lower limit reference level, and a first upper limit point of a frequency higher than the true tuning point and the first lower limit point. AFT reaches the upper reference level at the second upper limit point of a higher frequency than the upper limit point.
an intermediate frequency amplification circuit that outputs a signal; a horizontal synchronization signal connected to the amplification circuit and extracted from the television signal; and a lower limit base having a frequency of the horizontal synchronization signal and lower than the second lower limit point. a synchronization circuit that outputs a horizontal oscillation signal that has the same phase as the horizontal synchronization signal only during a tuning base range from a point to an upper limit base point between the first and second upper limit points; The tuning base range is detected by the synchronization signal and the horizontal oscillation signal, and the AFT between the tuning base range is detected.
Based on the signal, only the level of the first lower tuning section from the second lower limit point to the first lower limit point is lower than the lower limit base point and higher frequency than the upper limit base point. a first discrimination signal having the same level as the level of the key interval;
a discrimination circuit that outputs a second discrimination signal such that only the level of the upper tuning section from the upper limit point to the upper limit base point is the same level as the level of both the detuning sections; and a tuning control circuit that controls the level of the tuning signal to a level in a true tuning interval from the first lower limit point to the first upper limit point, wherein the tuning control circuit is configured to control the level of both discrimination signals. When the first lower tuning section and the upper tuning section are different from each other, the first lower tuning section and the upper tuning section are determined from a combination of the levels of both discrimination signals, and the level of the tuning signal is determined. a second lower tuning from the lower limit base point to the second lower limit point such that the levels of both discrimination signals are the same level different from the levels of both detuning sections; The level of the tuning signal is varied during the tuning interval to increase the receiving frequency, and the tuning signal is increased in the direction of increasing the receiving frequency by determining the transition to the first lower tuning interval based on the level change of both discrimination signals. means for controlling the level of the tuning signal to the level of the true tuning section by controlling the level of the tuning signal, and the level of the tuning signal when the level of both the discrimination signals becomes the same level as the level of the both detuning sections. is varied to lower the receiving frequency, and the level of the tuning signal is controlled in the direction of decreasing the receiving frequency by determining transition to the upper tuning section based on level changes of both of the discrimination signals. The present invention provides a receiving device equipped with a microcomputer having means for controlling the signal to a level in the true tuning section.

Therefore, according to the receiving device of this invention, even when the reception frequency of the tuner shifts to the second lower tuning interval or to the upper detuning interval, the reception frequency of the tuner is pulled into the true tuning interval and tuned. The performance of tuning control can be significantly improved and convenient.

Next, this invention will be explained in detail with reference to FIG. 6 showing one embodiment thereof.

In the same figure, the same symbols as those in FIG. includes an input section 12 to which both discrimination signals Se and Sf are input, a program control section 13 to which the output signal of the input section 12 is input, and a data storage section 14.

The input unit 12 determines that the receive frequency of the tuner 1 is the first lower tuning section Fb, the upper tuning section Fe, the detuning section Fc or Fd, the true tuning section Ff or the second tuning section from the combination of the levels of both discrimination signals Se and Sf. It is detected which section of the lower tuning section Fg it is in, and the control unit 13 is notified.

Further, the control section 13 instructs reading of the memory 6, and the tuning data signal Sg read from the memory 6 is outputted to the analog conversion section 7 via the data storage section 14.

Furthermore, a band switching command signal to the band switching section 8 is also output from the data storage section 14 .

By the way, the computer 11 does not perform the offset operation as shown in FIG.
Tuning data signal corresponding to the frequency of Ff
Sg is output.

Then, the level of the first discrimination signal Se is low level,
The first one in which the level of the second discrimination signal Sf becomes high level.
In the lower tuning section Fb, as in the case of Fig. 1, the reception frequency is changed from 80KHz to 80KHz every 60m ^sec until both discrimination signals Se and Sf reach high level.
The frequency is increased by a predetermined frequency between 250KHz and pulled into the true tuning interval Ff.

Further, the level of the first discrimination signal Se is high level,
In the upper tuning section Fe where the level of the second discrimination signal Sf becomes low level, as in the case of FIG. 1,
The reception frequency is changed from 80KHz to 250KHz every 60m ^sec until both discrimination signals Se and Sf reach high level.
The true tuning interval is controlled by decreasing the predetermined frequency between
Pull into FF.

Furthermore, when both discrimination signals Se and Sf are at high level, either the true tuning section Ff or the second lower tuning section Fg
In order to determine whether this is the case, the receiving frequency is controlled to increase by a predetermined frequency between 80 KHz and 250 KHz every 60 m ^sec until either one of the discrimination signals Se and Sf becomes low level.

When the transition to the first lower tuning section Fb in which the first discrimination signal Se becomes low level is determined, until both discrimination signals Se and Sf become high level,
The receiving frequency is controlled to increase by a predetermined frequency between 80 KHz and 250 KHz every 60 m ^sec to bring it into the true tuning interval Ff.

On the other hand, when determining the transition to the upper tuning section Fe where the second discrimination signal Sf becomes low level, both discrimination signals
Until both Se and Sf reach high levels,
The received frequency is controlled to decrease by a predetermined frequency between 80 KHz and 250 KHz every 60 m ^sec to bring it into the true tuning interval Ff.

Furthermore, when both discrimination signals Se and Sf are at low level, a tuning signal Sa that lowers the reception frequency by approximately 3 MHz is supplied to tuner 1 in order to discriminate between the lower detuning section Fg and the upper detuning section Fd. do.

If it is the upper detuning interval Fd, the second discrimination signal Sf becomes low level due to the transition to the upper tuning interval Fe, so the transition to the upper tuning interval Fe occurs due to the transition of the second discrimination signal Sf to the low level. At this time, the reception frequency is changed every 60m ^sec until both discrimination signals Se and Sf reach high level.
The frequency is controlled to decrease by a predetermined frequency between 80KHz and 250KHz, and the frequency is pulled into the true tuning section Ff.

By the way, even if the reception frequency is lowered by about 3MHz, if both discrimination signals Se and Sf are at low level, it is determined that the tuner has completely detuned, and the tuning signal Sa corresponding to the reception frequency before lowering is supplied to tuner 1. Either stop the tuning control and wait for the next tuning, or lower the reception frequency until one of the discrimination signals Se and Sf reaches a high level, and then set the reception frequency to one level lower. Tuning base range
Pull into the true tuning interval Fb of Fa.

In addition, the reception frequency is changed from 80KHz to 250K every 60m ^sec .
When controlling the frequency to increase or decrease by a predetermined frequency between Hz, in order to keep the amount of change in frequency almost constant,
During the VHF low band, the voltage of the tuning signal Sa is from 0 volts to 1/2 of the maximum voltage.
The voltage of the tuning signal Sa is varied by 8 millivolts, and from 1/2 of the maximum voltage to the maximum voltage by 12 millivolts.

In addition, when using the VHF high band, the voltage of the tuning signal Sa is varied in 4 millivolt increments from 0 volts to 3/4 of the maximum voltage, and the voltage of the tuning signal Sa is varied from 3/4 of the maximum voltage to 3/4 of the maximum voltage. The voltage is varied in 8 millivolt increments up to the maximum voltage.

Furthermore, when using the UHF band, the voltage of the tuning signal Sa is varied in 4 millivolt increments.

Therefore, according to the embodiment, when the first lower tuning section Fb and the upper tuning section Fe have different levels of the discrimination signals Se and Sf, the computer 11 determines whether the discrimination signals Se, Means for controlling the level of the tuning signal Sa to the level of the true tuning section Ff by determining a first lower tuning section Fb and an upper tuning section Fe from a combination of levels of Sf, and a means for controlling the level of the tuning signal Sa to the level of the true tuning section Ff; During the second lower tuning section Fg, where both of the detuning signals are at a high level different from the levels of the detuning sections Fc and Fd, the level of the tuning signal Sa is varied to increase the receiving frequency, and the levels of the discriminating signals Se and Sf are changed. means for controlling the level of the tuning signal Sa in the upward direction of the reception frequency by determining the transition to the first lower tuning section Fb based on the above-mentioned signal, and controlling the level of the tuning signal Sa to the level of the true tuning section Ff; Both Se and Sf levels are in the detuning interval Fc,
When the level of the tuning signal Sa reaches the same low level as the level of Fd, the receiving frequency is lowered by varying the level of the tuning signal Sa, and the receiving frequency is lowered by determining the transition to the upper tuning section Fe based on the level changes of both discrimination signals Se and Sf. By controlling the level of the tuning signal Sa in the downward direction to the level of the true tuning section Ff, the reception frequency of the tuner 1 is shifted to the second lower tuning section Fg. and upper detuning section
Even when it deviates from Fd, the reception frequency of the tuner 1 can be pulled into the true tuning interval Ff for tuning control, and the performance of tuning control can be significantly improved and convenient.

In addition, when both discrimination signals Se and Sf are both low level, if both discrimination signals Se and Sf remain low level even if the receiving frequency is controlled to decrease by approximately 3MHz, tuning control is stopped and the frequency is decreased. The performance of tuning control can be further improved by holding the reception frequency before the tuning, or by further decreasing the reception frequency and pulling it into the true tuning interval Fb of the tuning base range Fa, which is one level lower.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional receiving device, Fig. 2 is a detailed wiring diagram of the discrimination circuit shown in Fig. 1, and Figs.
f is a waveform diagram of each part in Fig. 2, and Figs. 4 a to e are for explaining the level of the output terminal of the second comparator in Fig. 2 when the phase of the horizontal synchronization signal and the phase of the horizontal oscillation signal do not match. Figures 5a to 5e are waveform diagrams for explaining the level of the output terminal of the second comparator in Figure 2 when the phase of the horizontal synchronization signal and the phase of the horizontal oscillation signal match, Figure 6 1 is a block diagram of one embodiment of the receiving device of this invention. 1...Tuner, 2...Intermediate frequency amplification circuit, 3
... Synchronization circuit, 4 ... Discrimination circuit, 10 ... Tuning control circuit, 11 ... Microcomputer, Sa ...
...Tuning signal, Sb...AFT signal, Sc...
Horizontal synchronization signal, Sd...Horizontal oscillation signal, Se, Sf...
...First and second discrimination signals.

Claims (1)

[Scope of utility model registration request] a tuner that receives a television signal through tuning control of a tuning signal;
The lower limit reference level is reached when the second lower limit point is lower in frequency than the lower limit point, and the upper reference level is reached when the first upper limit point is higher in frequency than the true tuning point and the second upper limit point is higher in frequency than the first upper limit point. an intermediate frequency amplification circuit that outputs an AFT signal that is connected to the amplification circuit and is extracted from the television signal; and a horizontal synchronization signal having a frequency of the horizontal synchronization signal and lower than the second lower limit point a synchronization circuit that outputs a horizontal oscillation signal that has the same phase as the horizontal synchronization signal only during a tuning base range from the lower limit base point to the upper limit base point between the first and second upper limit points; , detecting the tuning base range by the horizontal synchronization signal and the horizontal oscillation signal, and detecting the first lower limit point from the second lower limit point to the first lower limit point based on the AFT signal between the tuning base range. a first discrimination signal in which only the level of the side tuning section is the same as the level of the lower detuned section of frequency lower than the lower limit base point and the upper detuned section of higher frequency than the upper limit base point; and the first discrimination signal; a discrimination circuit that outputs a second discrimination signal in which only the level of the upper tuning section from to the upper limit base point is the same level as the level of both the detuning sections; and the tuning signal based on the levels of both discrimination signals. and a tuning control circuit that controls the level of the discrimination signal to a level in a true tuning interval from the first lower limit point to the first upper limit point, the tuning control circuit is configured to control the level of both discrimination signals to be equal to each other. When the first lower tuning section and the upper tuning section are different, the first lower tuning section and the upper tuning section are respectively determined from a combination of the levels of both the discrimination signals, and the level of the tuning signal is determined from the level of the tuning signal. means for controlling the level of the true tuning section, and a second lower tuning section from the lower limit base point to the second lower limit point in which the levels of both discrimination signals are the same level different from the levels of both the detuning sections. When the receiving frequency is increased by varying the level of the tuning signal, the level of the tuning signal is increased in the upward direction of the receiving frequency by determining transition to the first lower tuning section based on the level change of both the discrimination signals. means for controlling the level of the tuning signal to the level of the true tuning section, and varying the level of the tuning signal when the level of both the discrimination signals becomes the same level as the level of the both detuning sections. and lowers the receiving frequency, and controls the level of the tuning signal in the downward direction of the receiving frequency by determining transition to the upper tuning section based on the level change of both of the discrimination signals. A receiving device equipped with a microcomputer and means for controlling the level in the true tuning section.