JP7848522B2 - Fast Fourier Transform apparatus, digital filter apparatus, fast Fourier transform method, and program - Google Patents

Description

This disclosure relates to a digital filter device for performing digital signal processing, and more particularly to a fast Fourier transform device, a fast Fourier transform method, and a program.

One of the important processes in digital signal processing is the Fast Fourier Transform (FFT). For example, frequency domain equalization (FDE) is a well-known technique for compensating for waveform distortion during signal transmission in wireless and wired communications. In frequency domain equalization, the time-domain signal data is first converted to frequency-domain data using the Fast Fourier Transform, and then a filter is applied for equalization. The filtered data is then converted back to time-domain signal data using the Inverse Fast Fourier Transform (IFFT), thereby compensating for the waveform distortion of the original time-domain signal. Hereafter, when FFT and IFFT are not distinguished, they will be written as "FFT/IFFT".

Generally, "butterfly arithmetic" is used in FFT/IFFT processing. An FFT device using butterfly arithmetic is described, for example, in Patent Document 1. Patent Document 1 also describes "torsion multiplication," that is, multiplication using a torsion coefficient, which will be discussed later.

As an efficient FFT/IFFT processing method, the Cooley-Tukey butterfly operation described in Non-Patent Document 1 is well-known. However, Cooley-Tukey FFT/IFFT with a large number of points results in a complex circuit. Therefore, the FFT/IFFT processing is performed by decomposing the FFT/IFFT into two smaller FFTs using the Prime Factor method, as described in Non-Patent Document 2.

Figure 14 shows the data flow 500 of a 64-point FFT, decomposed into two base-8 butterfly operations using, for example, the Prime Factor method. The data flow 500 includes a data sorting process 501, eight base-8 butterfly operations in each of the butterfly operation processes 502 and 503, and a twist multiplication process 504.

In the data flow shown in Figure 14, the input time-domain data x(n) (n = 0, 1, ..., 63) is Fourier transformed into a frequency-domain signal X(k) (k = 0, 1, ..., 63) through FFT processing. Some parts of the data flow are omitted in Figure 14. Note that the basic configuration of the data flow in Figure 14 is the same even when IFFT processing is performed.

To implement the entire data flow shown in Figure 14 using circuitry would require an enormous amount of circuitry. Therefore, it is common practice to implement the entire FFT process by repeatedly using circuits that perform only a portion of the data flow, depending on the required processing performance.

For example, in the data flow shown in Figure 14, if an FFT device is created as a physical circuit to perform FFT processing on eight data points in parallel (hereinafter simply referred to as "in parallel processing on eight data points"), 64-point FFT processing can be achieved through a total of eight iterations.

The eight iterative processes sequentially execute the partial data flows 505a to 505h, which are applied to eight data points. Specifically, they are performed as follows: The first iteration executes the process corresponding to partial data flow 505a; the second executes the process corresponding to partial data flow 505b; and the third executes the process corresponding to partial data flow 505c (not shown). This process continues sequentially until the eighth iteration, which corresponds to partial data flow 505h. Through these processes, a 64-point FFT is achieved.

In butterfly operations, data arranged in a sequential order is read and processed in an order according to a predetermined rule. Therefore, butterfly operations require data reordering, and a RAM (Random Access Memory) circuit is primarily used to implement this. For example, Patent Document 2 describes an FFT device that uses a RAM circuit for data reordering in butterfly operations. Furthermore, Patent Document 3 describes a technique for accelerating butterfly operations through parallel processing, which reduces memory usage. Patent Document 4 describes a technique for optimizing the output timing and order of FFT processing results, aimed at accelerating and reducing power consumption in the subsequent processing of the FFT device.

Japanese Patent Application Publication No. 8-137832 Japanese Patent Publication No. 2001-56806 Japanese Patent Publication No. 2012-22500 Patent No. 6358096

J.W.Cooley, J.W.Tukey, “An Algorithm for the Machine Calculation of Complex Fourier Series”, Mathematics of Computation, US, American Mathematical Society, Apr. 1965, Vol.19, No.90, pp.297-301 D.P. Kolba, “A Prime Factor FFT Algorithm Using High-Speed Convolution”, IEEE Trans. on Acoustics, US, IEEE Signal Processing Society, Aug. 1977, Vol. 29, No. 4, pp. 281-294

In the FFT processing data flow shown in Figure 14, the order in which the eight iterative processes of partial data flows 505a to 505h, performed on eight data points, are executed is arbitrary. This order determines the output order of the frequency domain signal X(k) (k = 0, 1, ..., N-1) transformed by the FFT, and the order of the internal calculations that realize the FFT. On the other hand, a portion of the power consumption related to calculations such as filtering performed on the signal X(k) and the internal calculations that realize the FFT is determined by the output order of the signal X(k) and the order of the internal calculations that realize the FFT. In other words, in FFT processing, there exists a specific execution order of the iterative processes of partial data flows that can reduce the power consumption related to the FFT processing, and optimizing the execution order is effective in reducing power consumption.

However, the FFT circuits described in Non-Patent Documents 1, 2, and 3 have the problem of high power consumption because they do not consider optimization for reducing power consumption regarding the order of iterative processing of partial data flows.

Patent Document 4 describes an FFT apparatus capable of inputting data to be processed and outputting processing results in any order. To speed up the subsequent processing of the FFT, it can output output X(k) and X(N-k) with a time difference of at most one cycle. However, Patent Document 4 does not clarify the optimal configuration for reducing power consumption, resulting in the problem of high power consumption.

The purpose of this disclosure is to provide a fast Fourier transform device, a digital filter device, a fast Fourier transform method, and a program that enable digital signal processing using the fast Fourier transform with low power consumption.

The Fast Fourier Transform apparatus according to this disclosure is a Fast Fourier Transform apparatus that performs a Fast Fourier Transform or an Inverse Fast Fourier Transform in M cycles (M is a positive integer of 2 or more) for each N consecutive input data (N is a positive integer of 2 or more) in the input time domain,
The fast Fourier transform device processes F fast Fourier transforms or inverse fast Fourier transforms (where F is a positive integer of 2 or more) in succession.
A first data sorting processing means that sorts F × N first input data entered in a first order and outputs first output data in a second order,
Butterfly arithmetic processing means that performs butterfly arithmetic processing on the first output data and outputs the second output data in the first order,
A second data sorting processing means sorts the second output data and outputs the third output data in a third order,
The system includes a torsion multiplication processing means that multiplies the third output data by a torsion coefficient to perform a torsion multiplication process and outputs a fourth output data in the third order,
The third order is the order in which the processing of the C-th cycle (where C is an integer between 0 and M-1) in each of the F fast Fourier transforms or inverse fast Fourier transforms that are processed consecutively is processed in consecutive cycles.

The Fast Fourier Transform method according to this disclosure is a Fast Fourier Transform device that performs a Fast Fourier Transform or inverse Fast Fourier Transform in M cycles (M is a positive integer of 2 or more) for each N consecutive input data (N is a positive integer of 2 or more) in the input time domain.
In a series of F fast Fourier transforms or inverse fast Fourier transforms (where F is a positive integer greater than or equal to 2),
The F × N first input data points, which are input in a first order, are rearranged, and the first output data is output in a second order.
Butterfly arithmetic processing is performed on the first output data, and the second output data is output in the first order.
The second output data is rearranged, and the third output data is output in a third order.
This method involves multiplying the third output data by a torsion coefficient to perform a torsion multiplication process, and then outputting the fourth output data in the third order.
The third order is the order in which the processing of the C-th cycle (where C is an integer between 0 and M-1) in each of the F fast Fourier transforms or inverse fast Fourier transforms that are processed consecutively is processed in consecutive cycles.

The program relating to this disclosure is a Fast Fourier Transform (FFT) device that performs a Fast Fourier Transform or inverse Fast Fourier Transform on input time-domain input data in M cycles (M is a positive integer of 2 or more) for each of N consecutive input data (N is a positive integer of 2 or more).
In a series of F fast Fourier transforms or inverse fast Fourier transforms (where F is a positive integer greater than or equal to 2),
A process that rearranges F × N first input data points, which are input in a first order, and outputs the first output data in a second order,
The process involves performing a butterfly operation on the first output data and outputting the second output data in the first order,
The second output data is rearranged, and the third output data is output in a third order.
The process involves multiplying the third output data by a torsion coefficient to perform a torsion multiplication process, and outputting the fourth output data in the third order,
Make it run,
The third order described above is the order in which the processing of the C-th cycle (where C is an integer between 0 and M-1) in each of the F fast Fourier transforms or inverse fast Fourier transforms that are processed consecutively is processed in consecutive cycles.

This invention provides a high-speed Fourier transform (FPS) device, a digital filter device, a FPS method, and a program that enable digital signal processing using the FPS with low power consumption.

This is a block diagram showing the configuration of the fast Fourier transform device 10 according to the first embodiment. This is a block diagram showing the configuration of a digital filter device 400 according to the second embodiment. This figure shows an array of data sets following a sequential order according to the second embodiment. This figure shows an array of data sets following a bit reverse order according to the second embodiment. This figure shows the operation order of the radix-8 butterfly arithmetic processing according to the second embodiment. This figure shows an array of data sets according to the FFT frame mutual arrangement bit reverse order according to the second embodiment. This figure shows the array of torsion coefficients according to the FFT frame mutual arrangement bit reverse order according to the second embodiment. This figure shows the operation order of the radix-8 butterfly arithmetic processing according to the second embodiment. This is a block diagram showing an example configuration 100 of the first data sorting processing unit 11 according to the second embodiment. This is a block diagram showing an example configuration 200 of the second data sorting processing unit 12 according to the second embodiment. This figure shows the array of filter coefficients according to the FFT frame mutual arrangement bit reverse order according to the second embodiment. This figure shows an array of data sets following the FFT frame interconnection power optimization bit reverse order according to the third embodiment. This figure shows the array of torsion coefficients according to the FFT frame mutual arrangement bit reverse order according to the third embodiment. This figure shows the data flow 500 for a 64-point FFT process using a two-stage butterfly operation.

Embodiments of this disclosure will be described below with reference to the drawings.
(First embodiment)
Figure 1 is a block diagram showing an example of a Fast Fourier Transform (FFT) device according to the first embodiment. The FFT device 10 according to this embodiment is used for Fast Fourier Transform processing or inverse Fast Fourier Transform processing in a digital filter device. Specifically, the FFT device 10 performs Fast Fourier Transform or inverse Fast Fourier Transform on input time-domain input data in M cycles (M is a positive integer of 2 or more) for each N consecutive input data (N is a positive integer of 2 or more). As shown in Figure 1, the FFT device 10 includes a first data sorting processing unit 11 as a first data sorting processing means, a first butterfly arithmetic processing unit 21 as a butterfly arithmetic processing means, a second data sorting processing unit 12 as a second data sorting processing means, and a twist multiplication processing unit 31 as a twist multiplication processing means. The FFT device 10 then performs F (F is a positive integer of 2 or more) Fast Fourier Transform or inverse Fast Fourier Transform processing processes consecutively.

The first data sorting processing unit 11 sorts F × N first input data points in a first order and outputs the first output data in a second order.

The first butterfly arithmetic processing unit 21 performs butterfly arithmetic processing on the first output data and outputs the second output data in the first order.

The second data sorting processing unit 12 sorts the second output data and outputs the third output data in the third order.

The twist multiplication processing unit 31 performs a twist multiplication process by multiplying the third output data by a twist coefficient, and outputs the fourth output data in the third order.

In the first embodiment, the third order is the order in which the processing of the C-th cycle (where C is an integer between 0 and M-1) in each of the F consecutively processed Fast Fourier Transforms or Inverse Fast Fourier Transforms is performed within the consecutive cycles.

According to the FFT apparatus 10 of the first embodiment described above, the processing order (third order) of the data input to the twist multiplication processing unit 31 can be set so that the processing of the Cth cycle is performed in consecutive cycles. In other words, by alternating (interleaving) the processing order of multiple FFT processes that are performed consecutively, the power consumption related to the twist calculation and filter calculation can be reduced. As a result, the power consumption of the entire digital filter process can be reduced.

Furthermore, although this embodiment uses FFT processing as an example, the same principles apply to IFFT processing. That is, by applying the control method of this embodiment to an IFFT processing device and optimizing the processing order within and after the IFFT processing, power consumption within and after the IFFT processing can be reduced.

(Second embodiment)
Figure 2 is a block diagram showing the configuration of a digital filter device (also referred to as a "digital filter circuit") 400 according to a second embodiment of the present invention. The digital filter circuit 400 comprises an FFT device (also referred to as an "FFT circuit") 10 and a filter processing unit 420 as a filtering means.

The digital filter circuit 400 processes a complex number signal in the time domain x(n) = r(n) + js(n) ... (1)
Enter the following:

The FFT circuit 10 converts the input complex number signal x(n) into a frequency-domain complex number signal 431 by performing an FFT.
X(k)=A(k)+jB(k)...(2)
Convert to.

Here, n is an integer between 0 and N-1 representing the signal sample number in the time domain, N is an integer between 0 and N representing the number of FFT transformation samples, and k is an integer between 0 and N-1 representing the frequency number in the frequency domain.

Next, the filter processing unit 420 performs complex number filtering on the complex number signal X(k) (Equation (2)) output by the FFT circuit 10 to the complex number signal 431 using the filter coefficient C(k). Specifically, for each frequency number k between 0 and N-1, the filter processing unit 420 calculates the complex number signal X'(k) = X(k) × C(k) ... (3)
It calculates this and outputs it as a complex number signal 434.
The digital filter circuit 400 performs the above processing repeatedly for every N complex number signals that are continuously input in the time domain.

Next, the details of the FFT circuit 10 according to the second embodiment of the present invention will be described.
The FFT device 10 processes a 64-point FFT, which has been decomposed into two-stage radix 8 butterfly processing, using a pipeline circuit configuration, according to the data flow 500 shown in Figure 14. The FFT device 10 receives time-domain data x(n) (n = 0, 1, ..., N-1), performs a Fourier transform on x(n) using FFT processing to generate and output a frequency-domain signal X(k) (k = 0, 1, ..., N-1). Here, N is a positive integer representing the FFT block size.

The FFT device 10 comprises a first data sorting processing unit 11 as a first data sorting processing means, a first butterfly arithmetic processing unit 21 as a butterfly arithmetic processing means, a second data sorting processing unit 12 as a second data sorting processing means and storage means, a twist multiplication processing unit 31 as a twist multiplication processing means, a second butterfly arithmetic processing unit 22, and a read address generation unit 41 as a read address generation means. The FFT device 10 pipelines the first data sorting process, the first butterfly arithmetic process, the second data sorting process, the twist multiplication process, and the second butterfly arithmetic process.

The first data sorting processing unit 11 and the second data sorting processing unit 12 are buffer circuits for data sorting. The first data sorting processing unit 11 sorts the data sequence based on the data dependencies in the FFT processing algorithm before the first butterfly arithmetic processing unit 21. Similarly, the second data sorting processing unit 12 sorts the data sequence based on the data dependencies in the FFT processing algorithm after the first butterfly arithmetic processing unit 21, by inputting the read address 51. Furthermore, in addition to the above sorting, the second data sorting processing unit 12 performs sorting processing to alternately execute multiple FFT processes that are processed sequentially.

The FFT device 10 is designed to perform 64-point FFT processing in parallel with 8 data points. In this case, the FFT circuit 10 takes time-domain data x(n) as input, generates a frequency-domain signal X(k) by performing a Fourier transform through FFT processing, and outputs it. At this time, as input data x(n), 8 data points are input for each FFT process, over a period of 8 cycles, in the order shown in Figure 3, for a total of 64 data points per FFT process. Figure 3 shows the order of input data x(n) for the first to fourth FFT processes (F1 to F4) that are processed consecutively, and the numbers from 0 to 63 shown in the table in Figure 3 represent the subscript n for x(n). Specifically, for the first FFT process (F1), in the 0th cycle, 8 data points x(0), x(1), ..., x(7) that constitute the data set P0 are input. Then, in the first cycle, the eight data points x(8), x(9), ..., x(15) that constitute data set P1 are input. Similarly, in cycles 2 through 7, the data constituting data sets P2 through P7 are input. Likewise, in cycles 8 through 15, data related to the second FFT process (F2) is input; in cycles 16 through 23, data related to the third FFT process (F3) is input; and in cycles 24 through 31, data related to the fourth FFT process (F4) is input.

Next, the first data sorting processing unit 11 sorts the input data x(n) in the "sequential order" shown in Figure 3, which is the input order, into the "bit reverse order" shown in Figure 4, which is the input order to the first butterfly arithmetic processing unit 21.

Figure 4 shows the bit reverse order for the four FFT processes (F1 to F4) that are performed sequentially, and corresponds to the input data set to the first radix 8 butterfly process 502 in the data flow diagram shown in Figure 14. Specifically, the first data sorting processing unit 11 outputs eight data points, x(0), x(8), ..., x(56), which constitute data set Q0, in the 0th cycle for the first FFT process (F1). Then, in the 1st cycle, it outputs eight data points, x(1), x(9), ..., x(57), which constitute data set Q1. Thereafter, in the 2nd to 7th cycles, it outputs data that constitutes data sets Q2 to Q7 in the same manner. Similarly, data related to the second FFT process (F2) is output from the 8th to the 15th cycle, data related to the third FFT process (F3) is output from the 16th to the 23rd cycle, and data related to the fourth FFT process (F4) is output from the 24th to the 31st cycle.

Here, we will explain "sequential order" and "bit reverse order" in detail. "Sequential order" refers to the order of the eight data sets P0 to P7 shown in Figure 3. Each data set Ps(s=0,1,...,7) consists of eight data points arranged sequentially from ps(0) to ps(7), where ps(i) is...
ps(i)=8s+i
Therefore, sequential ordering is the process of arranging i and s data items in order, starting with the first data item, to create s data sets, and then arranging them in that order.

"Bit reverse order" refers to the order of the eight data sets Q0 to Q7 shown in Figure 4. Each data set Qs (s = 0, 1, ..., 7) consists of eight data points, qs(0) to qs(7), where qs(i) is...

qs(i)=s+8i
In other words, bit reverse order is created by taking i and s data points and arranging them in sets of i data points, with every eight data points starting from the first data point, to create s data sets, and then arranging them.

As described above, the i-th data element of each data set Qs (s = 0, 1, ..., 7) in bit reverse order is the s-th data element of the data set Pi in sequential order. That is,
Qs(i)=Pi(s)
Thus, Qs(i) and Pi(s) are related in such a way that the order of the data sets and the order of the data positions within each data set are swapped. Therefore, when data input in bit-reverse order is rearranged according to bit-reverse order, it becomes sequential order.

In Figure 3, each row ps(i), and in Figure 4, each row qs(i), represent the data to be input to the i-th data point of the next stage. The eight numbers included in each data set are identification information that identifies one of the FFT points, specifically the value of the subscript n in x(n).

Note that the sequential and bit-reverse sequences are not limited to those illustrated in Figures 3 and 4. That is, each data set in a sequential sequence can be created by arranging the data sequentially according to the number of FFT points, the number of cycles, and the number of data points processed in parallel, as described above. Similarly, each data set in a bit-reverse sequence can be created by swapping the order of the sequentially input data relative to the cycle progression and the order relative to the data position, as described above.

The first butterfly arithmetic processing unit 21 is a butterfly circuit that processes the first butterfly arithmetic operation 502 (the first butterfly arithmetic operation) of the radix 8 butterfly arithmetic operation performed in two stages in the data flow 500 of Figure 14. The first butterfly arithmetic processing unit 21 is composed of a radix 8 butterfly arithmetic processing unit 21a and performs radix 8 butterfly arithmetic operations. Figure 5 shows the processing order of the first butterfly arithmetic processing unit 21 for the four consecutive FFT operations (F1 to F4). Specifically, from cycle 0 to cycle 7, the first butterfly arithmetic processing unit 21 processes the eight radix 8 butterfly arithmetic operations #0 to #7, which constitute the butterfly arithmetic operation 502, in the order shown in Figure 5, with respect to the first FFT operation (F1).

In other words, in cycle 0, the radix 8 butterfly arithmetic processing unit 21a receives a data set Q0 in bit reverse order corresponding to radix 8 butterfly arithmetic processing #0, which is output by the first data sorting processing unit 11, and performs radix 8 butterfly arithmetic processing #0. In cycle 1, the radix 8 butterfly arithmetic processing unit 21a receives a data set Q1 in bit reverse order corresponding to radix 8 butterfly arithmetic processing #1, which is output by the first data sorting processing unit 11, and performs radix 8 butterfly arithmetic processing #1. In cycle 2, the radix 8 butterfly arithmetic processing unit 21a receives a data set Q2 in bit reverse order corresponding to radix 8 butterfly arithmetic processing #2, which is output by the first data sorting processing unit 11, and performs radix 8 butterfly arithmetic processing #2. In cycle 3, the radix 8 butterfly arithmetic processing unit 21a receives a data set Q3 in bit reverse order corresponding to the radix 8 butterfly arithmetic processing #3 output by the first data sorting processing unit 11, and performs the radix 8 butterfly arithmetic processing #3. In the following cycles, the same procedure is followed, and in cycles 4 to 7, the radix 8 butterfly arithmetic processing unit 21a receives data sets Q4 to Q7 in bit reverse order corresponding to the radix 8 butterfly arithmetic processing #4 to #7, respectively, output by the first data sorting processing unit 11, and performs the radix 8 butterfly arithmetic processing #4 to #7.
Similarly, the first butterfly arithmetic processing unit 21 performs processing related to the second FFT process (F2) from the 8th to the 15th cycle, processing related to the third FFT process (F3) from the 16th to the 23rd cycle, and processing related to the fourth FFT process (F4) from the 24th to the 31st cycle.

The first butterfly arithmetic processing unit 21 outputs the results of the butterfly arithmetic processing as data y(n) (n = 0, 1, ..., 63) in the sequential order shown in Figure 3.

The second data sorting processing unit 12 sorts the data y(n) output sequentially by the first butterfly arithmetic processing unit 21 in the order shown in Figure 6 (hereinafter referred to as the "FFT frame mutual arrangement bit reverse order"). The "FFT frame mutual arrangement bit reverse order" relates to the order in which s data sets Qs per FFT process, created in bit reverse order, are output in accordance with the progress of the cycle for multiple FFT processes that are processed consecutively, and can be specified by the output order specification 52. In this embodiment, the FFT frame mutual arrangement bit reverse order is specified as a sequence in which Q0 of the first to fourth FFT processes are consecutive, then Q1 of the first to fourth FFT processes are consecutive, then Q2 of the first to fourth FFT processes are consecutive, then Q3 of the first to fourth FFT processes are consecutive, then Q4 of the first to fourth FFT processes are consecutive, then Q5 of the first to fourth FFT processes are consecutive, then Q6 of the first to fourth FFT processes are consecutive, and then Q7 of the first to fourth FFT processes are consecutive.
The second data sorting processing unit 12 receives the read addresses 51 output by the read address generation unit 41 and determines the output order. The read address generation unit 41 generates the read addresses 51 to be output to the second data sorting processing unit 12 by referring to the output order setting 52 provided by a higher-level circuit (not shown), such as a CPU (Central Processing Unit).

Specifically, the second data sorting processing unit 12 outputs Q0 of the first FFT process in the 0th cycle, Q0 of the second FFT process in the 1st cycle, Q0 of the third FFT process in the 2nd cycle, and Q0 of the fourth FFT process in the 3rd cycle. Similarly, it outputs Q1 of the first FFT process in the 4th cycle, Q1 of the second FFT process in the 5th cycle, Q1 of the third FFT process in the 6th cycle, and Q1 of the fourth FFT process in the 7th cycle. And so on.
From cycles 8 to 11, Q2 of the first to fourth FFT processes,
From cycles 12 to 15, Q3 of the first to fourth FFT processes,
From cycle 16 to 19, Q4 of the first to fourth FFT processes,
From cycles 20 to 23, Q5 of the first to fourth FFT processes,
From cycles 24 to 27, Q6 of the first to fourth FFT processes,
From cycles 28 to 31, output Q7 of the first to fourth FFT processes.

In other words, the "FFT frame inter-arrangement bit reverse order" can be described as an order in which the processing order of multiple FFT processes is interleaved, such that the processing of the Cth cycle (C being an integer between 0 and 7) of each of the F consecutively processed F FFT processes (where F is a positive integer greater than or equal to 2) is processed in consecutive cycles.

The twist multiplication processing unit 31 is a circuit that processes the complex rotation on the complex plane in the FFT operation after the first butterfly operation, and corresponds to the twist multiplication process 504 in the data flow 500 of Figure 14. Note that no data reordering is performed in the twist multiplication process.
The twist multiplication processing unit 31 consists of a twist coefficient table 31a and a twist multiplication unit 31b. The twist coefficient table 31a outputs twist coefficients W(n) (n=0,1,...,63) corresponding to the data y(n) (n=0,1,...,63) in each FFT process output by the second data sorting processing unit 12 in the "FFT frame mutual arrangement bit reverse order". W(n) is the twist coefficient corresponding to the data y(n). Therefore, the order in which the twist multiplication processing unit 31 outputs the twist coefficients W(n) is uniquely determined by the "FFT frame mutual arrangement bit reverse order", which is the order in which the second data sorting processing unit 12 outputs the sorted data. Specifically, when the second data sorting processing unit 12 outputs in the "FFT frame mutual arrangement bit reverse order" shown in Figure 6, the twist coefficient table 31a outputs the twist coefficients in the order shown in Figure 7. As is clear from Figures 6 and 7, the torsion coefficient W(n) (n=0,1,...,63) output by the torsion multiplication processing unit 31 corresponds to y(n) output by the second data sorting processing unit 12.
The twist multiplication unit 31b performs a twist multiplication process by multiplying y(n) output by the second data sorting unit 12 by the twist coefficient W(n) output by the twist multiplication unit 31, and outputs the result to the second butterfly arithmetic unit 22.

The second butterfly arithmetic processing unit 22 is a butterfly circuit that processes the second butterfly arithmetic operation 503 (the second butterfly arithmetic operation) of the radix 8 butterfly arithmetic operation performed in two stages in the data flow 500 of Figure 14. The second butterfly arithmetic processing unit 22 consists of a radix 8 butterfly arithmetic processing unit 22a and performs radix 8 butterfly arithmetic operations.

Figure 8 shows the processing order of the second butterfly arithmetic processing unit 22 for the four FFT processes (F1 to F4) that are processed sequentially. Specifically, the second butterfly arithmetic processing unit 22 performs the #0 radix 8 butterfly arithmetic processing that constitutes the butterfly arithmetic processing 503 in the 0th to 3rd cycles for the first to fourth FFT processes (F1 to F4 ). Similarly, the second butterfly arithmetic processing unit 22 performs the following for the first to fourth FFT processes (F1 to F4 ):
In cycles 4 through 7, the butterfly arithmetic process 503 consists of #1,
From the 8th to the 11th cycle, #2, which constitutes the butterfly arithmetic process 503,
From the 12th to the 15th cycle, #3, which constitutes the butterfly arithmetic process 503,
From the 16th to the 19th cycle, #4, which constitutes the butterfly arithmetic process 503,
From the 20th to the 23rd cycle, #5, which constitutes the butterfly arithmetic process 503,
From the 24th to the 27th cycle, #6, which constitutes the butterfly arithmetic process 503,
From the 28th to the 31st cycle, #7, which constitutes the butterfly arithmetic process 503,
Performs radix 8 butterfly arithmetic.

In other words, in cycle 0, the radix 8 butterfly arithmetic processing unit 22a receives a data set Q0 in bit reverse order corresponding to the radix 8 butterfly arithmetic processing #0 output by the second data sorting processing unit 12 for the first FFT processing (F1), and performs the radix 8 butterfly arithmetic processing #0. In cycle 1, the radix 8 butterfly arithmetic processing unit 22a receives a data set Q0 in bit reverse order corresponding to the radix 8 butterfly arithmetic processing #0 output by the second data sorting processing unit 12 for the second FFT processing (F2), and performs the radix 8 butterfly arithmetic processing #0. In cycle 2, the radix 8 butterfly arithmetic processing unit 22a receives a data set Q0 in bit reverse order corresponding to the radix 8 butterfly arithmetic processing #0 output by the second data sorting processing unit 12 for the third FFT processing (F3), and performs the radix 8 butterfly arithmetic processing #0. In cycle 3, the radix-8 butterfly arithmetic processing unit 22a receives the bit-reverse-ordered data set Q0, which corresponds to the radix-8 butterfly arithmetic processing #0 output by the second data sorting processing unit 12, for the fourth FFT process (F4), and performs the radix-8 butterfly arithmetic processing #0.

In subsequent cycles,
In cycles 4 through 7, the radix 8 butterfly arithmetic processing unit 22a receives the bit reverse order data set Q1 corresponding to the radix 8 butterfly arithmetic processing #1 output by the second data sorting processing unit 12 for the four FFT processes (F1 through F4) from the first to the fourth, and performs the radix 8 butterfly arithmetic processing #1.
In cycles 8 through 11, the radix-8 butterfly arithmetic processing unit 22a receives the bit-reverse-ordered data set Q2, which corresponds to the radix-8 butterfly arithmetic processing #2 output by the second data sorting processing unit 12, for the first to fourth FFT processes (F1 to F4), and performs the radix-8 butterfly arithmetic processing #2.
In cycles 12 to 15, the radix 8 butterfly arithmetic processing unit 22a receives the bit reverse order data set Q3 corresponding to the radix 8 butterfly arithmetic processing #3 output by the second data sorting processing unit 12 for the four FFT processes (F1 to F4) from the first to the fourth, and performs the radix 8 butterfly arithmetic processing #3.
In cycles 16 to 19, the radix-8 butterfly arithmetic processing unit 22a receives the bit-reverse-ordered data set Q4 corresponding to the radix-8 butterfly arithmetic processing #4 output by the second data sorting processing unit 12 for the four FFT processes (F1 to F4) from the first to the fourth, and performs the radix-8 butterfly arithmetic processing #4.
In cycles 20 to 23, the radix 8 butterfly arithmetic processing unit 22a receives the bit reverse order data set Q5 corresponding to the radix 8 butterfly arithmetic processing #5 output by the second data sorting processing unit 12 for the four FFT processes from the first to the fourth (F1 to F4), and performs the radix 8 butterfly arithmetic processing #5.
In cycles 24 to 27, the radix-8 butterfly arithmetic processing unit 22a receives the bit-reverse-ordered data set Q6 corresponding to the radix-8 butterfly arithmetic processing #6 output by the second data sorting processing unit 12 for the four FFT processes (F1 to F4) from the first to the fourth, and performs the radix-8 butterfly arithmetic processing #6.
In cycles 28 to 31, the radix 8 butterfly arithmetic processing unit 22a receives a data set Q7 in bit reverse order corresponding to the radix 8 butterfly arithmetic processing #7 output by the second data sorting processing unit 12 for the four FFT processes (F1 to F4) from the first to the fourth, and performs the radix 8 butterfly arithmetic processing #7.

The second butterfly arithmetic processing unit 22 outputs the results of the butterfly arithmetic processing X(k) (n=0,1,...,63) for the four FFT processes (F1-F4) from the first to the fourth, in the same FFT frame mutual arrangement bit reverse order.

The first data sorting processing unit 11 and the second data sorting processing unit 12 temporarily store the input data and control the selection and output of the stored data, thereby realizing data sorting according to the bit reverse order shown in Figure 4 and the FFT frame mutual arrangement bit reverse order shown in Figure 6, respectively. A specific example of the data sorting processing unit is shown below.

The first data sorting processing unit 11 can be implemented, for example, by the data sorting processing unit 100 shown in Figure 9.

The data sorting processing unit 100 takes data sets A to H, consisting of eight data points input as input information 103, and inputs them in a first-in, first-out (FIFO) buffer, writing them to data storage locations 101a to 101h for storage. Specifically, data sets A to H are stored in each of the data storage locations 101a to 101h.

Next, the data sorting processing unit 100 outputs the stored data in the first-to-use order in the FIFO buffer, two data sets at a time. Specifically, the data sorting processing unit 100 reads eight data points from each of the data reading positions 102a to 102h, combines them into one data set, and outputs these eight data sets a to h as output information 104. Thus, data sets a to h are formed by rearranging the data contained in data sets A to H, which are arranged in cyclic order, according to their data positions.

On the other hand, Figure 10 is a configuration diagram of the data sorting processing unit 200, showing an example of the implementation of the second data sorting processing unit 12. The data sorting processing unit 200 consists of four partial data sorting processing units 206a, 206b, 206c, and 206d, each corresponding to the first to fourth FFT processes (F1 to F4).

First, regarding the first FFT process (F1), the partial data sorting processing unit 206a inputs data sets A to H, consisting of eight data points, as input data 203, in first-in-place order in the FIFO buffer, and writes them to data storage positions 201a to 201h for storage. That is, data sets A to H are stored sequentially in each of the data storage positions 201a to 201h corresponding to the cycle order. At this time, when viewing the stored data in the order of the data positions, i.e., in the order of data storage positions 201a to 201h, data sets a to h are stored in each of the data storage positions 201a to 201h.

Similarly, regarding the second FFT process (F2), the partial data sorting processing unit 206b inputs data sets A to H, consisting of eight data points, as input data 203, in first-in-order (FIFO) order in the FIFO buffer, and writes and stores them in data storage locations 201a to 201h. Regarding the third FFT process (F3), the partial data sorting processing unit 206c inputs data sets A to H, consisting of eight data points, as input data 203, in first-in-order (FIFO) order in the FIFO buffer, and writes and stores them in data storage locations 201a to 201h. Regarding the fourth FFT process (F4), the partial data sorting processing unit 206d inputs data sets A to H, consisting of eight data points, as input data 203, in first-in-order (FIFO) order in the FIFO buffer, and writes and stores them in data storage locations 201a to 201h.

Next, the data sorting processing unit 200 reads the stored data one data set at a time using the read circuit 205 and outputs it as output data 204. At this time, the read circuit 205 refers to the read address 51 and selects one of the partial data sorting processing units 206a to 206d, and then selects one of the data storage locations 201a to 201h of the selected partial data sorting processing unit, and reads one of the eight data stored in the data storage locations 201a to 201h in a single read operation. In this way, by assigning read addresses to the read address 51 in any desired combination and order, it is possible to read data in any combination and order. For example, the read address 51 could be set to address 0 of partial data sorting processing unit 206a, address 0 of partial data sorting processing unit 206b, address 0 of partial data sorting processing unit 206c, address 0 of partial data sorting processing unit 206d,
Address 1 of partial data sorting processing unit 206a, Address 1 of partial data sorting processing unit 206b, Address 1 of partial data sorting processing unit 206c, Address 1 of partial data sorting processing unit 206d,
Address 2 of partial data sorting processing unit 206a, address 2 of partial data sorting processing unit 206b, address 2 of partial data sorting processing unit 206c, address 2 of partial data sorting processing unit 206d,
Address 3 of partial data sorting processing unit 206a, address 3 of partial data sorting processing unit 206b, address 3 of partial data sorting processing unit 206c, address 3 of partial data sorting processing unit 206d,
Address 4 of partial data sorting processing unit 206a, address 4 of partial data sorting processing unit 206b, address 4 of partial data sorting processing unit 206c, address 4 of partial data sorting processing unit 206d,
Address 5 of partial data sorting processing unit 206a, address 5 of partial data sorting processing unit 206b, address 5 of partial data sorting processing unit 206c, address 5 of partial data sorting processing unit 206d,
Address 6 of partial data sorting processing unit 206a, address 6 of partial data sorting processing unit 206b, address 6 of partial data sorting processing unit 206c, address 6 of partial data sorting processing unit 206d,
Address 7 of partial data sorting processing unit 206a, address 7 of partial data sorting processing unit 206b, address 7 of partial data sorting processing unit 206c, address 7 of partial data sorting processing unit 206d,
When the read addresses are provided in that order, the data sorting processing unit 200 outputs the stored data in the following order: data set a of the first FFT process (F1), data set a of the second FFT process (F2), data set a of the third FFT process (F3), data set a of the fourth FFT process (F4), and so on thereafter.
Four data sets b, corresponding to the first to fourth FFT processes (F1 to F4),
Four data sets c, corresponding to the first to fourth FFT processes (F1 to F4),
Four data sets d, corresponding to the first to fourth FFT processes (F1 to F4),
Four data sets e, corresponding to the first to fourth FFT processes (F1 to F4),
Four data sets f, corresponding to the first to fourth FFT processes (F1 to F4),
Four data sets g, corresponding to the first to fourth FFT processes (F1 to F4),
Four data sets h corresponding to the first to fourth FFT processes (F1 to F4),
The stored data is output in the order shown above. That is, the data is output in the FFT frame mutual arrangement bit reverse order shown in Figure 6. Here, data sets a to h are formed by rearranging the data contained in data sets A to H, which are arranged in cycle order, in order of data position.

As explained above, in the FFT device 10, the first data sorting processing unit 11 and the second data sorting processing unit 12 perform two sorting processes according to the sequential order in Figure 3, the bit reverse order in Figure 4, and the FFT frame mutual arrangement bit reverse order in Figure 6, respectively.

Next, the details of the filter processing unit 420 according to the second embodiment of the present invention will be described.

The filter processing unit 420 is a circuit that performs complex number filtering by complex number multiplication after processing by the FFT circuit 10. The filter processing unit 420 consists of a filter coefficient table 421 and a filter multiplication unit 422. The filter coefficient table 421 outputs filter coefficients C(k) (k=0,1,...,63) corresponding to the data X(k) (k=0,1,...,63) output by the FFT circuit 10 to the complex number signal 431 in the "FFT frame mutual arrangement bit reverse order". C(k) is the filter coefficient corresponding to the data X(k). Therefore, the order in which the filter coefficient table 421 outputs the filter coefficients C(k) is uniquely determined by the "FFT frame mutual arrangement bit reverse order," which is the order in which the FFT circuit 10 outputs X(k).

Specifically, when the FFT circuit 10 outputs in the "FFT frame mutual arrangement bit reverse order" shown in Figure 6, the filter coefficient table 421 outputs the filter coefficients in the order shown in Figure 11. As is clear from Figures 6 and 11, the filter coefficients C(k) (k = 0, 1, ..., 63) correspond to the data X(k) output by the FFT circuit 10.

The filter multiplication unit 422 performs a filter multiplication process by multiplying the data X(k) output by the FFT circuit 10 with the filter coefficient C(k) output by the filter coefficient table 421, and outputs the result as a complex number signal 434.
Here, we will explain the difference between the "FFT frame mutual arrangement bit reverse order," which is the data order adopted by this embodiment after the output of the second data sorting processing unit 12, and the "bit reverse order," which is adopted before the input of the second data sorting processing unit 12.

In this embodiment, the order in which the twist multiplication processing unit 31 outputs the twist coefficient W(n) is determined by the FFT frame mutual arrangement bit reverse order, which is the output order of the second data sorting processing unit 12. Specifically, it outputs in the order shown in Figure 7.

As is clear from Figure 7, the values of ws(0) to ws(7) in the torsion coefficient W(n) are the same from cycle 0 to cycle 3, the same from cycle 4 to cycle 7, and the same every four cycles corresponding to the first to fourth FFT processes (F1 to F4 ) in subsequent cycles.

Focusing on the power consumption of the twist multiplication processing unit 31, the magnitude of the change in the values of the eight data points from ws(0) to ws(7) greatly affects the power consumption. Specifically, in the binary values obtained by representing the twist coefficient W(n) in binary, the bit-level operation rate (toggle rate) of the eight data points from ws(0) to ws(7) greatly affects the power consumption. This is because the dynamic power consumption P of a digital signal processing circuit realized by a CMOS (Complementary Metal Oxide Semiconductor) circuit can be expressed by the following equation (4):

P=(1/2)*a*C*V2*f...(4)

Here,
a: circuit operation rate,
C: load capacity,
V: Voltage,
f: This is because the bit-level operating rate of the eight data points from operating frequencies ws(0) to ws(7) greatly affects the circuit operating rate a. In other words, selecting an output order that reduces the bit-level operating rate of the eight data points from ws(0) to ws(7) is effective in reducing the power consumption of the twist multiplication processing unit 31.

In this embodiment, the "FFT frame mutual arrangement bit reverse order" does not change the value of the torsion coefficient W(n) within the four cycles corresponding to the first to fourth FFT processing (F1 to F4 ). Therefore, compared to, for example, the "bit reverse order," the operating rate related to the torsion coefficient W(n) can be reduced. As a result, this order can be said to reduce the power consumption related to the torsion multiplication processing unit 31.

Similarly, the order in which the filter processing unit 420 of this embodiment outputs the filter coefficients C(k) is determined by the FFT frame mutual arrangement bit reverse order, which is the output order of the second data sorting processing unit 12, and specifically, it outputs in the order shown in Figure 11.

As is clear from Figure 11, the values of cs(0) to cs(7) in the filter coefficient C(k) are the same from cycle 0 to cycle 3, the same from cycle 4 to cycle 7, and the same every four cycles corresponding to the first to fourth FFT processes (F1 to F4 ) in subsequent cycles.

In this embodiment, the "FFT frame mutual arrangement bit reverse order" does not change the value of the filter coefficient C(k) within the four cycles corresponding to the first to fourth FFT processing (F1 to F4 ). Therefore, compared to, for example, the "bit reverse order," the operating rate related to the filter coefficient C(k) can be reduced. As a result, this order can be said to reduce the power consumption of the filter processing unit 420.

As described above, in this embodiment, the FFT device 10 can output data in any order by specifying the order using the output order setting 52. For example, by alternating the processing order (interleaving) of multiple FFT processes that are processed consecutively, the power consumption related to the twist calculation and filter calculation can be reduced. As a result, the overall power consumption of the digital filter process can be reduced.

In this embodiment, we described a case where a 64-point FFT process (N=64) is processed using 8 data parallelisms (P=8) over 8 cycles (M=N/P=8). However, the number of points in the FFT process is not limited to 64. This embodiment may be applied similarly to any integer N of 2 or more. Furthermore, the number of data parallelisms is not limited to 8; any integer P less than or equal to N may be processed using P data parallelisms. In this case, one N-point FFT process is completed in C=N/P cycles.

Furthermore, while this embodiment describes an example where the processing order of four consecutively processed FFT operations is interleaved, the number of interleaved FFT operations is not limited to four. For any two or more integers F, the processing order of F consecutively processed FFT operations may be interleaved. In this case, the operating rate related to the torsion coefficient W(n) and filter coefficient C(k) can be reduced to 1/F, and accordingly, the power consumption related to the torsion calculation and filter calculation can be reduced.

Furthermore, although this embodiment uses FFT processing as an example, the same principles apply to IFFT processing. That is, by applying the control method of this embodiment to an IFFT processing device and optimizing the processing order within and after the IFFT processing, power consumption within and after the IFFT processing can be reduced.

(Third embodiment)
The digital filter circuit according to the third embodiment of the present invention is an embodiment in which the output order specification 52 is specified in a different order from that of the second embodiment, while having the same circuit configuration as the digital filter circuit 400 according to the second embodiment.

The second data sorting processing unit 12 in the third embodiment sorts the data y(n) output sequentially by the first butterfly arithmetic processing unit 21 in the order shown in Figure 12 (hereinafter referred to as the "FFT frame interconnected arrangement power optimization bit reverse order"). The "FFT frame interconnected arrangement power optimization bit reverse order" relates to the order in which s data sets Qs per FFT process, created in bit reverse order, are output in accordance with the progress of the cycle for a plurality of FFT processes that are processed consecutively, and can be specified by the output order specification 52. In this embodiment, the FFT frame mutual arrangement power optimization bit reverse order is specified as follows: Q3 of the first to fourth FFT processes are performed consecutively, followed by Q5 of the first to fourth FFT processes, followed by Q1 of the first to fourth FFT processes, followed by Q7 of the first to fourth FFT processes, followed by Q0 of the first to fourth FFT processes, followed by Q2 of the first to fourth FFT processes, followed by Q6 of the first to fourth FFT processes, and then Q4 of the first to fourth FFT processes.

The second data sorting processing unit 12 receives the read addresses 51 output by the read address generation unit 41 and determines the output order. The read address generation unit 41 generates the read addresses 51 to be output to the data sorting processing unit 12 by referring to the output order setting 52 provided by a higher-level circuit (not shown), such as the CPU (Central Processing Unit).

Specifically, the second data sorting processing unit 12 outputs Q3 of the first FFT process in the 0th cycle, Q3 of the second FFT process in the 1st cycle, Q3 of the third FFT process in the 2nd cycle, and Q3 of the fourth FFT process in the 3rd cycle. Similarly, it outputs Q5 of the first FFT process in the 4th cycle, Q5 of the second FFT process in the 5th cycle, Q5 of the third FFT process in the 6th cycle, and Q5 of the fourth FFT process in the 7th cycle. And so on.
From cycles 8 to 11, the Q1 of the first to fourth FFT processes are performed in order.
From cycles 12 to 15, Q7 of the first to fourth FFT processes is performed in order.
From cycle 16 to 19, the Q0 of the first to fourth FFT processes are performed in order.
From cycle 20 to 23, the Q2 of the first to fourth FFT processes are performed in order.
From cycle 24 to 27, Q6 of the first to fourth FFT processes is performed in order.
From cycles 28 to 31, Q4 of the first to fourth FFT processes is output in sequence.
In other words, the "FFT frame inter-arrangement power optimization bit reverse order" is similar to the "FFT frame inter-arrangement bit reverse order" in the second embodiment, and can be described as an order in which the processing order of multiple FFT processes is interleaved so that the processing of the Cth cycle (C is an integer between 0 and 7) of each of the F F FFT processes (F is a positive integer of 2 or more) that are processed consecutively is processed in consecutive cycles.

The twist multiplication processing unit 31 in the third embodiment is a circuit that processes the complex rotation on the complex plane in the FFT calculation after the first butterfly operation, and corresponds to the twist multiplication process 504 in the data flow 500 of Figure 14. Note that data reordering is not performed in the twist multiplication process.

The twist multiplication processing unit 31 consists of a twist coefficient table 31a and a twist multiplication unit 31b. The twist coefficient table 31a outputs a twist coefficient W(n) (n=0,1,...,63) corresponding to the data y(n) (n=0,1,...,63) in each FFT process output by the second data sorting processing unit 12 in the "FFT frame mutual arrangement power optimization bit reverse order". W(n) is the twist coefficient corresponding to the data y(n). Therefore, the order in which the twist multiplication processing unit 31 outputs the twist coefficient W(n) is uniquely determined by the "FFT frame mutual arrangement power optimization bit reverse order", which is the order in which the data sorted by the second data sorting processing unit 12 is output. Specifically, when the second data sorting processing unit 12 outputs in the "FFT frame mutual arrangement power optimization bit reverse order" shown in Figure 12, the torsion coefficient table 31a outputs the torsion coefficients in the order shown in Figure 13. As is clear from Figures 12 and 13, the torsion coefficient W(n) (n = 0, 1, ..., 63) output by the torsion multiplication processing unit 31 corresponds to y(n) output by the second data sorting processing unit 12.

Here, we will explain the difference between the "FFT frame mutual arrangement bit reverse order," which is the data order adopted by the second embodiment after the output of the second data sorting processing unit 12, and the "FFT frame mutual arrangement power-optimized bit reverse order," which is the data order adopted by this embodiment after the output of the second data sorting processing unit 12.

Similar to the second embodiment, in this embodiment as well, the output order of the FFT device 10 is determined by the output order of the second data sorting processing unit 12. Accordingly, the order in which the torsion multiplication processing unit 31 outputs the torsion coefficient W(n) in this embodiment is determined by the output order of the second data sorting processing unit 12.

In the "FFT frame mutual arrangement bit reverse order" shown in Figure 6 and the "FFT frame mutual arrangement power optimization bit reverse order" shown in Figure 12, the data set Qs is the same from cycle 0 to cycle 3, the same from cycle 4 to cycle 7, and the same every four cycles corresponding to the first to fourth FFT processing (F1 to F4 ) thereafter. On the other hand, the data set Qs changes from cycle 3 to cycle 4, from cycle 7 to cycle 8, from cycle 11 to cycle 12, from cycle 15 to cycle 16, from cycle 19 to cycle 20, from cycle 23 to cycle 24, and from cycle 27 to cycle 28, but the order in which it changes is different between the "FFT frame mutual arrangement bit reverse order" and the "FFT frame mutual arrangement power optimization bit reverse order".

Specifically, in the "FFT frame mutual arrangement bit reverse order," the bits change in the order Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, whereas in the "FFT frame mutual arrangement power optimization bit reverse order," they change in the order Q3, Q5, Q1, Q7, Q0, Q2, Q6, Q4. Therefore, the torsion coefficient W(n) also changes according to the "FFT frame mutual arrangement power optimization bit reverse order," as shown in Figure 13.

The value of the torsion coefficient W(n) is specific to the FFT process and does not depend on the values of the data input to the FFT device 10. In Figure 13, data sets W0 to W7 each consist of eight data points from ws(0) to ws(7), and the values of ws(0) to ws(7) change from cycle 0 to cycle 7 according to the FFT frame mutual arrangement bit reverse order: W3, W5, W1, W7, W0, W2, W6, W4.

Focusing on the power consumption of the twist multiplication processing unit 31, the magnitude of the change in the values of the eight data points from ws(0) to ws(7) greatly affects the power consumption. Specifically, in the binary values obtained by representing the twist coefficient W(n) in binary, the bit-level operation rate (toggle rate) of the eight data points from ws(0) to ws(7) greatly affects the power consumption. This is because the dynamic power consumption P of a digital signal processing circuit realized by a CMOS (Complementary Metal Oxide Semiconductor) circuit can be expressed by the following equation (4):

P=(1/2)*a*C*V2*f...(4)

Here,
a: circuit operation rate,
C: load capacity,
V: Voltage,
f: This is because the bit-level operating rate of the eight data points from operating frequencies ws(0) to ws(7) greatly affects the circuit operating rate a. In other words, selecting an output order that reduces the bit-level operating rate of the eight data points from ws(0) to ws(7) is effective in reducing the power consumption of the twist multiplication processing unit 31.

One specific method for selecting the output order that minimizes the bit-level operation rate of the eight data points from ws(0) to ws(7) is to use the Hamming distance as an indicator. The Hamming distance is the distance between two data points, and in the case of binary data, it is equal to the number of bits that differ between the two binary data points. That is, when a torsion coefficient data point changes, the operation rate is equal to the Hamming distance between the coefficient data value before the change and the coefficient data value after the change. Therefore, the operation rate related to the torsion coefficient W(n) can be calculated by summing the Hamming distances related to the torsion coefficient W(n) during the FFT process.

For example, the operating rate for the torsion coefficient W(n) due to the bit reverse order of the FFT frame mutual arrangement shown in Figure 13 is expressed as follows, where Hamming(i,j) is the Hamming distance between the torsion coefficients W(i) and W(j), and H(i) is the Hamming distance with respect to the data ws(i):
The data ws(0) is W(3) in cycle 0, W(5) in cycle 1, W(1) in cycle 2, W(7) in cycle 3, W(0) in cycle 4, W(2) in cycle 5, W(6) in cycle 6, and W(4) in cycle 7.
H(0)=Hamming(3,5)+Hamming(5,1)+Hamming(1,7)+Hamming(7,0)+Hamming(0,2)+Hamming(2,6)+Hamming(6,4)
It can be calculated by [method].
Similarly, for H(1) to H(7),
H(1)=Hamming(11,13)+Hamming(13,9)+Hamming(9,15)+Hamming(15,8)+Hamming(8,10)+Hamming(10,14)+Hamming(14,12)
H(2)=Hamming(19,21)+Hamming(21,17)+Hamming(17,23)+Hamming(23,16)+Hamming(16,18)+Hamming(18,22)+Hamming(22,20)
H(3)=Hamming(27,29)+Hamming(29,25)+Hamming(25,31)+Hamming(31,24)+Hamming(24,26)+Hamming(26,30)+Hamming(30,28)
H(4)=Hamming(35,37)+Hamming(37,33)+Hamming(33,39)+Hamming(39,32)+Hamming(32,34)+Hamming(34,38)+Hamming(38,36)
H(5)=Hamming(43,45)+Hamming(45,41)+Hamming(41,47)+Hamming(47,40)+Hamming(40,42)+Hamming(42,46)+Hamming(46,44)
H(6)=Hamming(51,53)+Hamming(53,49)+Hamming(49,55)+Hamming(55,48)+Hamming(48,50)+Hamming(50,54)+Hamming(54,52)
H(7)=Hamming(59,61)+Hamming(61,57)+Hamming(57,63)+Hamming(63,56)+Hamming(56,58)+Hamming(58,62)+Hamming(62,60)
It can be calculated by [method].
Therefore, the rate of motion A with respect to the torsion coefficient W(n) is given by the sum of the Hamming distances P with respect to the torsion coefficient W(n): A = P = H(0) + H(1) + H(2) + H(3) + H(4) + H(5) + H(6) + H(7)
It can be calculated using this method.

The "FFT frame mutual arrangement power optimization bit reverse sequence" of this embodiment is selected from among multiple candidates for the "FFT frame mutual arrangement bit reverse sequence" to obtain the sequence with the smallest operating rate A for the torsion coefficient W(n). In other words, the "FFT frame mutual arrangement power optimization bit reverse sequence" of this embodiment is the sequence with the smallest power consumption related to the torsion coefficient table 31a that outputs the torsion coefficient W(n), among multiple candidates for the "FFT frame mutual arrangement bit reverse sequence".

On the other hand, the twist multiplication unit 31b, which constitutes the twist multiplication processing unit 31, is affected not only by the operating rate of the twist coefficient W(n) but also by the operating rate of y(n) output by the second data sorting processing unit 12. However, since the FFT device 10 accepts arbitrary data as input, the operating rate of y(n) is considered to be constant in the long term, regardless of the order in which y(n) is output. Similarly, for the data sorting processing unit and butterfly arithmetic processing unit that constitute the FFT device 10, since the FFT device 10 accepts arbitrary data as input, the operating rates of these processing units are considered to be constant in the long term, regardless of the order of processing. Therefore, the "FFT frame mutual arrangement power optimization bit reverse order" of this embodiment can be said to be the order in which the power consumption of the FFT device 10 is smallest among multiple candidates for the "FFT frame mutual arrangement bit reverse order".

As described above, in this embodiment as well, the FFT device 10 can output data in any order by specifying the order using the output order setting 52. For example, by alternating the processing order (interleaving) of multiple FFT processes that are processed consecutively, the power consumption related to the twist calculation and filter calculation processes can be reduced. As a result, the overall power consumption of the digital filter process can be reduced.

In this embodiment, we described a case where a 64-point FFT process (N=64) is processed using 8 data parallelisms (P=8) over 8 cycles (M=N/P=8). However, the number of points in the FFT process is not limited to 64. This embodiment may be applied similarly to any integer N of 2 or more. Furthermore, the number of data parallelisms is not limited to 8; any integer P less than or equal to N may be processed using P data parallelisms. In this case, one N-point FFT process is completed in C=N/P cycles.

Furthermore, while this embodiment describes an example where the processing order of four consecutively processed FFT operations is interleaved, the number of interleaved FFT operations is not limited to four. For any two or more integers F, the processing order of F consecutively processed FFT operations may be interleaved. In this case, the operating rate related to the torsion coefficient W(n) and filter coefficient C(k) can be reduced to 1/F, and accordingly, the power consumption related to the torsion calculation and filter calculation can be reduced.

Furthermore, this embodiment processes the operations in an order that minimizes the power consumption associated with the twist multiplication process. As a result, the overall power consumption of the FFT process can be reduced.

Furthermore, although this embodiment uses FFT processing as an example, the same principles apply to IFFT processing. That is, by applying the control method of this embodiment to an IFFT processing device and optimizing the processing order within and after the IFFT processing, power consumption within and after the IFFT processing can be reduced.

In the embodiments described above, this disclosure was explained as a hardware configuration, but this disclosure is not limited thereto. This disclosure can also be implemented by having a CPU (Central Processing Unit) execute a computer program to perform the processing procedures described in the flowchart and other embodiments.

In the above example, the program can be stored and supplied to the computer using various types of non-transitory computer-readable medium. Non-transitory computer-readable mediums include various types of tangible storage mediums. Examples of non-transitory computer-readable mediums include magnetic recording media, magneto-optical recording media, CD-ROMs (Read Only Memory), CD-Rs, CD-R/Ws, and semiconductor memory. Examples of semiconductor memory include mask ROMs, PROMs (Programmable ROMs), EPROMs (Erasable PROMs), flash ROMs, and RAMs (Random Access Memory). Alternatively, the program may be supplied to the computer using various types of transient computer-readable mediums. Examples of transient computer-readable mediums include electrical signals, optical signals, and electromagnetic waves. Transitory computer-readable mediums can be supplied to the computer via wired communication channels such as electric wires and optical fibers, or via wireless communication channels.

Furthermore, this disclosure is not limited to the embodiments described above, and may be modified as appropriate without departing from its intent.

10. FFT device (Fast Fourier Transform device)
11. First data sorting processing unit (first data sorting processing means)
12. Second data sorting processing unit (second data sorting processing means, storage means)
21. First butterfly arithmetic processing unit (butterfly arithmetic processing means)
22 Second butterfly arithmetic processing unit 21a, 22a Base 8 butterfly arithmetic processing unit 31 Twist multiplication processing unit (twist multiplication processing means)
41. Read address generation unit (read address generation means)
51 Read address 52 Output order setting 100, 200 Data sorting processing unit 101a to 101h Data storage position 102a to 102h Data read position 201a to 201h Data storage position 202a to 202h Data read position 400 Digital filter device 420 Filter processing unit (filtering means)
421 Filter coefficient table 422 Filter multiplication section 431, 434 Complex number signal 500 Data flow 501 Data sorting process 502, 503 Butterfly operation process 504 Twist multiplication process 505a to 505h Partial data flow

Claims (7)

A Fast Fourier Transform (FFT) device that performs a Fast Fourier Transform or Inverse Fast Fourier Transform in M cycles (M is a positive integer of 2 or more) for each N consecutive input data (N is a positive integer of 2 or more) in the input time domain,
The fast Fourier transform device processes F fast Fourier transforms or inverse fast Fourier transforms (where F is a positive integer of 2 or more) in succession.
A first data sorting processing means that sorts F × N first input data entered in a first order and outputs first output data in a second order,
Butterfly arithmetic processing means that performs butterfly arithmetic processing on the first output data and outputs the second output data in the first order,
A second data sorting processing means sorts the second output data and outputs the third output data in a third order,
The system includes a torsion multiplication processing means that multiplies the third output data by a torsion coefficient to perform a torsion multiplication process and outputs a fourth output data in the third order,
The third order is the order in which the processing of the C-th cycle (where C is an integer between 0 and M-1) in each of the F fast Fourier transforms or inverse fast Fourier transforms that are processed consecutively is processed in consecutive cycles.
The twist multiplication processing means performs a twist multiplication process on the third output data by outputting twist coefficients in the third order, wherein the third order is an order in which the bit transition rate between consecutive cycles of the twist coefficients is small . This is a fast Fourier transform device. The second data sorting processing means described above is:
A storage means for storing M × N of the second output data,
The system includes a read address generation means that generates F × N read addresses of the third output data from the storage means based on the output order setting,
The fast Fourier transform apparatus according to claim 1 , characterized in that it stores a plurality of the second output data in the second order and reads them out in the third order. A fast Fourier transform apparatus according to claim 1 or 2 ,
With respect to the output data output by the Fast Fourier Transform device in the third order,
A filtering means that outputs filter coefficients in the third order described above and performs a filter multiplication process,
A digital filter device equipped with the following features. A Fast Fourier Transform (FFT) device performs a Fast Fourier Transform or Inverse Fast Fourier Transform for every N consecutive input data points (where N is a positive integer greater than or equal to 2) in M cycles (where M is a positive integer greater than or equal to 2) on input data in the time domain.
In a series of F fast Fourier transforms or inverse fast Fourier transforms (where F is a positive integer greater than or equal to 2),
The F × N first input data points, which are input in a first order, are rearranged, and the first output data is output in a second order.
Butterfly arithmetic processing is performed on the first output data, and the second output data is output in the first order.
The second output data is rearranged, and the third output data is output in a third order.
The third output data is multiplied by a torsion coefficient to perform a torsion multiplication process, and the fourth output data is output in the third order.
The third order is the order in which the processing of the C-th cycle (where C is an integer between 0 and M-1) in each of the F fast Fourier transforms or inverse fast Fourier transforms that are processed consecutively is processed in consecutive cycles.
A fast Fourier transform method characterized in that, in the twist multiplication process, the fast Fourier transform device outputs twist coefficients in the third order to the third output data and performs the twist multiplication process, wherein the third order is an order in which the bit transition rate between consecutive cycles of the twist coefficients is small . In the second data sorting process described above, the Fast Fourier Transform device is
Store M × N of the second output data,
Based on the output order setting, read addresses for F × N third output data are generated from M × N second output data.
The Fast Fourier Transform method according to claim 4 , characterized in that a plurality of the second output data are stored in a second order and read out in a third order. A Fast Fourier Transform (FFT) device performs a Fast Fourier Transform or Inverse Fast Fourier Transform in M cycles (M is a positive integer greater than or equal to 2) for every N consecutive input data points (where N is a positive integer greater than or equal to 2) in the input time domain.
In a series of F fast Fourier transforms or inverse fast Fourier transforms (where F is a positive integer greater than or equal to 2),
A process that rearranges F × N first input data points, which are input in a first order, and outputs the first output data in a second order,
The process involves performing a butterfly operation on the first output data and outputting the second output data in the first order,
The second output data is rearranged, and the third output data is output in a third order.
The process involves multiplying the third output data by a torsion coefficient to perform a torsion multiplication process, and outputting the fourth output data in the third order,
Make it run,
The third order is the order in which the processing of the C-th cycle (where C is an integer between 0 and M-1) in each of the F fast Fourier transforms or inverse fast Fourier transforms that are processed consecutively is processed in consecutive cycles.
A program characterized in that, in the twist multiplication process, the Fast Fourier Transform device is instructed to output twist coefficients to the third output data in the third order and perform the twist multiplication process, wherein the third order is an order in which the bit transition rate between consecutive cycles of the twist coefficients is small . In the second data sorting process described above, the Fast Fourier Transform device is used.
A process for storing M × N of the second output data,
A process to generate read addresses for F × N third output data from M × N second output data based on the output order setting,
The program according to claim 6 , characterized in that it performs a process of storing a plurality of the second output data in a second order and reading them in a third order.