JP7828777B2 - Ultrasound diagnostic equipment - Google Patents

Description

The embodiments disclosed herein and in the drawings relate to ultrasound diagnostic equipment.

In ultrasound diagnostic equipment, when the CPU (Central Processing Unit) sequentially sets control data (such as power-on sequences) for various hardware devices, it may insert a predetermined time interval (waiting time) between the control data. In this case, the CPU uses a software timer to insert the waiting time between the control data.

Recent CPUs have enhanced power management, allowing them to enter a dormant state (hibernation) after a period of inactivity. When the CPU attempts to set control data for hardware devices while in hibernation, it may take time to transition from hibernation to operational mode, potentially preventing sufficient waiting time.

Japanese Patent Publication No. 2005-301812

One of the problems that the embodiments disclosed in this specification and drawings aim to solve is ensuring a predetermined waiting time between control data when setting control data sequentially. However, the problems that the embodiments disclosed in this specification and drawings aim to solve are not limited to the above problem. Problems corresponding to the effects of each configuration shown in the embodiments described later can also be positioned as other problems.

The ultrasound diagnostic apparatus according to this embodiment comprises an equipment unit and a control unit. The equipment unit includes hardware equipment used for ultrasound imaging and a hardware timer. The control unit is connected to the equipment unit and transmits control data to the hardware equipment. When the control unit transmits second control data after a predetermined time interval has elapsed since the transmission of first control data, it counts the predetermined time interval in cooperation with the hardware timer, triggered by the transmission of the first control data, and transmits the second control data upon completion of the counting of the predetermined time interval.

Figure 1 shows an example of the configuration of an ultrasound diagnostic apparatus according to this embodiment. Figure 2 shows the flow of control data within an ultrasound diagnostic device. Figure 3 shows an example of the control data setting process according to Example 1. Figure 4 shows an example of the control data setting process according to Example 2. Figure 5 shows an example of the setting process for multiple control data according to Embodiment 3. Figure 6 shows an example of the control data setting process related to the comparative example.

The following describes in detail an embodiment of the ultrasound diagnostic apparatus with reference to the drawings.

Figure 1 shows an example configuration of the ultrasound diagnostic apparatus 100 according to this embodiment. As shown in Figure 1, the ultrasound diagnostic apparatus 100 has a main unit 10 and a host unit 20. The main unit 10 and the host unit 20 are mounted in the housing of the ultrasound diagnostic apparatus 100. The main unit 10 houses multiple hardware devices used for ultrasound image diagnosis. The main unit 10 includes, as hardware devices, a transmitting circuit 12, a receiving circuit 13, a transmitting/receiving control circuit 14, a signal processing circuit 15, a memory 16, and a power supply circuit 17. The host unit 20 is a computer that controls the main unit 10 for ultrasound image diagnosis. The host unit 20 is connected to the main unit 10 via a cable or backplane. An ultrasound probe 11 is detachably attached to the main unit 10. A biometric information collector 200 is also detachably attached to the host unit 20. The ultrasound probe 11 and the biometric information collector 200 are also examples of hardware devices used for ultrasound image diagnosis.

Figure 2 shows the flow of control data within the ultrasound diagnostic device 100. The arrows in Figure 2 represent the flow of control data. The dotted lines in Figure 2 represent electrical connection relationships. The control data in this embodiment is data transmitted from the host control circuit 21 to various hardware devices, and refers to data related to the setting of control parameters for those hardware devices.

As shown in Figures 1 and 2, the ultrasound probe 11 transmits and receives ultrasound. The ultrasound probe 11 includes, for example, a plurality of transducers, a matching layer, an acoustic lens, and a backing material. The plurality of transducers generate ultrasound based on a drive signal supplied from the transmitting circuit 12. The matching layer is used for impedance matching between the plurality of transducers and the living body. The acoustic lens is made of a flexible material, such as silicone rubber, and focuses the ultrasound into a beam. The backing material prevents the propagation of ultrasound backward in the direction of radiation from the plurality of transducers. When ultrasound is transmitted from the ultrasound probe 11 to the subject, the transmitted ultrasound is reflected one after another at discontinuities in the acoustic impedance of the subject's body tissue, received by the plurality of transducers, and converted into an electrical signal (echo signal). The amplitude of the echo signal depends on the difference in acoustic impedance at the discontinuities where the ultrasound is reflected. In addition, when the transmitted ultrasound pulse is reflected by a moving blood flow or a surface such as the heart wall, the echo signal undergoes a frequency shift due to the Doppler effect, depending on the velocity component of the ultrasound transmission direction of the moving object. The ultrasonic probe 11 operates according to control data related to probe control parameters supplied from the transmit/receive control circuit 14. For example, if the number of transducers in the ultrasonic probe 11 is greater than the number of channels in the transmit circuit 12 and the receive circuit 13, the probe control parameters correspond to hardware switch control data for switching the transducers of the ultrasonic probe 11. If the ultrasonic probe 11 is a mechanical probe that is oscillated by a motor, the probe control parameters correspond to motor control data.

The transmitting circuit 12 is an electrical circuit that supplies a drive signal to the ultrasonic probe 11. The transmitting circuit 12 generates a drive signal to transmit a desired ultrasonic pulse from the ultrasonic probe 11 according to control data related to transmission control parameters such as pulse repetition frequency (PRF), transmission position information, transmission aperture, and transmission delay, supplied from the transmitting/receiving control circuit 14. Specifically, the transmitting circuit 12 is implemented by a trigger generation circuit, a delay circuit, and a pulser circuit. The trigger generation circuit repeatedly generates rate pulses at a predetermined rate frequency to form the transmitted ultrasonic waves. The delay circuit provides a delay time for each of the multiple transducers necessary to focus the ultrasonic waves generated from the ultrasonic probe 11 into a beam and determine the transmission directivity, to each rate pulse generated by the trigger generation circuit. The pulser circuit applies a drive signal (drive pulse) to the multiple transducers provided on the ultrasonic probe 11 at a timing based on the rate pulse. By changing the delay time provided to each rate pulse by the delay circuit, the transmission direction from the surface of the multiple transducers can be arbitrarily adjusted. Note that the transmission control parameters are a type of control parameter.

The receiving circuit 13 is an electrical circuit that generates a received signal by performing various signal processing on the echo signal supplied from the ultrasonic probe 11. The receiving circuit 13 generates a digital signal (beam data) corresponding to the scan line, based on the echo signal obtained from the ultrasonic probe 11, according to control data related to reception control parameters such as reception aperture information and reception delay supplied from the transmitting/receiving control circuit 14. Specifically, the receiving circuit 13 is implemented by a preamplifier, A/D converter, demodulator, and beamformer (adder), etc. The preamplifier amplifies the echo signal received by the ultrasonic probe 11 for each channel and performs gain correction processing. The A/D converter converts the gain-corrected echo signal into a digital signal. The demodulator demodulates the digital signal. The beamformer, for example, adds multiple digital signals with the necessary delay time to determine the reception directivity to the demodulated digital signal. The beamformer's addition process generates beam data in which the reflected component from the direction corresponding to the reception directivity is emphasized. Note that reception control parameters are a type of control parameter.

The transmit/receive control circuit 14 has a processor that controls the main unit 10. The transmit/receive control circuit 14 transmits and sets various control data to the ultrasonic probe 11, transmit circuit 12, receive circuit 13, signal processing circuit 15, memory 16, and power supply circuit 17, etc., according to commands from the host control circuit 21. In this case, the transmit/receive control circuit 14 may temporarily store various control parameters in the memory 16 and read them from the memory 16 at an appropriate timing and transmit them to the ultrasonic probe 11, transmit circuit 12, receive circuit 13, signal processing circuit 15, memory 16, and power supply circuit 17, etc.

Specifically, the transmit/receive control circuit 14 receives control data related to transmit/receive control parameters such as image mode, beam count, frame rate, and diagnostic depth, as instructed by the host control circuit 21, and determines the PRF based on these transmit/receive control parameters. The transmit/receive control circuit 14 transmits control data related to transmit control parameters such as transmit/receive position information, transmit aperture, and transmit delay, stored in the memory 16, to the transmit circuit 12. The transmit/receive control circuit 14 transmits control data related to receive control parameters such as receive aperture information and receive delay, stored in the memory 16, to the receive circuit 13. The transmit/receive control circuit 14 transmits control data related to signal processing control parameters such as digital filter processing conditions, stored in the memory 16, to the signal processing circuit 15. The transmit/receive control circuit 14 transfers the beam data received from the signal processing circuit 15 to the storage device 23 under the control of the host control circuit 21.

Memory 16 is a storage device that temporarily stores various control data from the transmit/receive control circuit 14. Based on information such as various ultrasonic scan modes, the connected ultrasonic probe 11, and the number of simultaneous parallel receptions, Memory 16 stores control data related to various control parameters that are transferred to and set by the transmit circuit 12, the receive circuit 13, and the signal processing circuit 15. The control parameters of the control data stored here include, for example, frame information, vector information, beam information, transmitting element position, transmission delay, transmitting aperture, receiving element position, reception delay, receiving aperture, header information, and digital filter coefficients. Memory 16 can be constructed using semiconductor memory elements such as ROM (Read Only Memory), RAM (random access memory), EEPROM (registered trademark) (Electrically Erasable Programmable Read Only Memory), flash memory, or a hard disk.

The power supply circuit 17 supplies power to hardware devices connected to or housed in the main unit 10, such as the ultrasound probe 11, transmitting circuit 12, receiving circuit 13, transmitting/receiving control circuit 14, signal processing circuit 15, memory 16, and hardware timer 31. In this embodiment, as an example, the power supply circuit 17 supplies power to the ultrasound probe 11, transmitting circuit 12, receiving circuit 13, signal processing circuit 15, memory 16, and hardware timer 31 via the transmitting/receiving control circuit 14. The power supply circuit 17 operates according to control data related to power control parameters, such as the type of image mode and the transmission voltage value for each image mode, supplied from the transmitting/receiving circuit 14. Any type of image mode used in general ultrasound diagnostic imaging can be applied, but examples include B-mode, C-mode, and PW-mode.

The hardware timer 31 is a hardware device that counts time based on a clock signal of a fixed period generated by a crystal oscillator or a frequency-divided signal of said clock signal. As shown in Figure 1, the hardware timer 31 is provided in the transmit/receive control circuit 14, which functions as a destination or relay for control data. The hardware timer 31 may be provided in any hardware device connected to or housed in the main unit 10, such as the ultrasonic probe 11, transmit circuit 12, receive circuit 13, signal processing circuit 15, or memory 16, which are destinations for control data.

The host unit 20 includes hardware components such as a host control circuit 21, an image generation circuit 22, a storage device 23, a display device 24, an operating device 25, and a power supply circuit 26.

The host control circuit 21 is a processor that controls the ultrasound diagnostic device 100. For example, the host control circuit 21 controls the entire ultrasound diagnostic device 100 based on the diagnostic mode and various control data set by the operating device 25. The host control circuit 21, as an example, includes a CPU (hereinafter referred to as the host CPU) 51 and memory such as ROM or RAM (hereinafter referred to as the host memory) 52. The host CPU 51 and host memory 52 are mounted on a motherboard conforming to any standard.

The host CPU 51 is equipped with power management functionality. Such a host CPU 51 could be, for example, a commercially available ATX (Advanced Technology eXtended) or a CPU conforming to an ATX standard developed for ultrasound diagnostic equipment. Specifically, the host CPU 51 includes a CPU core 53, a chipset 54, and a power control circuit 55. The CPU core 53 reads and interprets various software programs stored in the host memory 52, and executes the various processes described in those software programs. An example of such a software program is an image diagnostic program for performing ultrasound image diagnosis. Upon execution of the image diagnostic program, the CPU core 53 transmits a series of control data to various hardware devices via the chipset 54. The CPU core 53 can also execute other software programs, such as a software timer, which is a software program that counts time.

The chipset 54 is an integrated circuit that controls data transmission between the CPU core 53 and an external bus (not shown). The external bus is a data transmission path (bus) that transmits and receives various types of data between the CPU core 53 and peripheral devices such as the main unit 10, image generation circuit 22, storage device 23, display device 24, operation device 25, power supply circuit 26, and biometric information collector 200.

The power control circuit 55 is an integrated circuit that monitors and controls the operation of each device within the ultrasound diagnostic apparatus 100 in order to reduce power consumption. This function is called the power management function. By implementing the power management function, the power control circuit 55 controls the supply of power from the power supply circuit 26 of the host unit 20 to various hardware devices of the host unit 20, such as the image generation circuit 22, storage device 23, display device 24, operating device 25, biological information collector 200, host memory 52, CPU core 53, and chipset 54, according to the usage status of the hardware devices.

The configuration of the host CPU 51 is not limited to the above configuration. The host CPU 51 may also implement other components such as registers, memory control devices, and a GPU (Graphical Processing Unit).

The image generation circuit 22 is a processor that generates ultrasound images. The image generation circuit 22 scan-converts the beam data stored in the memory device 23 to generate two-dimensional or three-dimensional B-mode images or color Doppler images.

The storage device 23 is composed of a large-capacity HDD (Hard Disk Drive), SSD (Solid State Drive), flash memory, etc. For example, the storage device 23 stores beam data supplied from the transmit/receive control circuit 14. Another example is that the storage device 23 stores ultrasound images and additional information supplied from the image generation circuit 22.

The display device 24 is any display such as a liquid crystal display, organic EL display, LED display, plasma display, or CRT display. As an example, the display device 24 displays the ultrasound image output from the image generation circuit 22. As another example, the display device 24 displays various diagnostic parameters.

The operating device 25 is a man-machine interface that receives various instructions from the operator. Specifically, the operating device 25 includes a mouse, keyboard, panel switches, slider switches, trackball, rotary encoder, control panel, and touch command screen (TCS). The operating device 25 inputs various diagnostic modes and associated parameters to the ultrasound diagnostic device 100.

The power supply circuit 26 supplies power to hardware devices housed in or connected to the host unit 20, such as the host control circuit 21, image generation circuit 22, storage device 23, display device 24, operation device 25, and biometric information collector 200. In this embodiment, as an example, the power supply circuit 26 supplies power to the image generation circuit 22, storage device 23, display device 24, operation device 25, and biometric information collector 200 via the host control circuit 21.

The biometric information collector 200 is connected to the host unit 20 via wired or wireless communication. The biometric information collector 200 collects biological information such as the subject's blood pressure and pulse rate. The biometric information collector 200 is equipped with a hardware timer 201. The configuration of the hardware timer 201 is the same as that of the hardware timer 31. The biometric information collector 200 may also be connected to the main unit 10.

The main unit 10 and the biometric information collector 200 can be classified as equipment units. The equipment units include hardware devices and hardware timers used for ultrasound imaging. Examples of hardware devices include the ultrasound probe 11, transmission circuit 12, reception circuit 13, transmission/reception control circuit 14, signal processing circuit 15, memory 16, power supply circuit 17, hardware timer 31, and biometric information collector 200. Examples of hardware timers include the hardware timer 31 included in the transmission/reception control circuit 14 and the hardware timer 201 included in the biometric information collector 200. The host unit 20 is connected to the equipment units and transmits control data to the hardware devices.

The following describes the details of the ultrasound diagnostic apparatus 100 according to this embodiment.

As described above, the host control circuit 21 transmits a series of control data to various hardware devices housed in or connected to the ultrasound diagnostic device 100. The host control circuit 21 and the main unit 10 are connected by a high-speed external bus. For example, PCI Express (hereinafter referred to as PCIe), which enables high-speed serial communication, is used as such an external bus. On the other hand, connections between hardware devices within the main unit 10, between the main unit 10 and the ultrasound probe 11, and between the host unit 20 and the biometric information collector 200 are made using low-speed serial communication, which has a lower data transfer speed compared to PCIe. Therefore, when the host control circuit 21 transmits a series of control data to the hardware devices of the main unit 10, it is necessary to leave a predetermined time interval (hereinafter referred to as waiting time) between control data to avoid congestion of control data.

Furthermore, to reduce power consumption, the power management function of the power control circuit 55 reduces or stops the power supply to hardware devices housed in or connected to the host control circuit 21 when they are not in use or are used infrequently. Even if power is resumed to transition from a stopped state (hibernation state) to an operational state, it takes time for the hardware device to become stable and operational. During this transition period, the system waits for the control data to be set for the hardware device. This transition period affects the pre-set waiting time between consecutive control data. Therefore, the changed waiting time is corrected. The waiting time between control data varies depending on the hardware device being controlled, but it is often set to a value between a few usec and a few milliseconds.

Here, we present two specific examples of problems in the control data setting process. Specific Example 1: The biometric information collector 200 is an independently controlled microcontroller-controlled device. When power is supplied or desupplied from the power supply circuit 26, the microcontroller of the biometric information collector 200 starts up. The transition time from a stopped state to an operational state takes several usecs to several milliseconds. If the host control circuit 21 sends a biometric information collection start command before the microcontroller has fully started up, the biometric information collector 200 may lose that command. Specific Example 2: As described above, the host control circuit 21 and the main unit 10 are connected by high-speed PCIe, but the hardware devices within the main unit are connected using a communication method with a slower data transfer speed compared to PCIe communication. When reading/writing to slow communication, a waiting time is necessary until the communication is complete, taking the communication speed into consideration. If the next access is performed without waiting, the data being transferred may be altered, or the read value may be incorrect, potentially causing malfunction of the hardware device.

Here, with reference to Figure 6, the problems with the control data setting process in a comparative example to this embodiment will be explained. Figure 6 is a diagram showing the flow of the control data setting process in a comparative example. More specifically, Figure 6 shows the flow when a series of control data D1 and control data D2 are set in a hardware device of the ultrasound diagnostic apparatus 100 with a waiting time WT. The hardware device may be any device housed in or connected to the ultrasound diagnostic apparatus 100, such as the ultrasound probe 11, transmission circuit 12, reception circuit 13, transmission/reception control circuit 14, signal processing circuit 15, memory 16, power supply circuit 17, and biological information collector 200. The host CPU 51 is described separately for devices in a stopped state and devices in an operational state. A chipset 54 is described as an example of a device in a stopped state, and software is described as an example of a device in an operational state. Since the software is implemented by the CPU core 53 of the host CPU 51, the hardware refers to the CPU core 53.

When the operator instructs the ultrasound diagnostic device to change its mode via the control device 25, the CPU core 53 executes software such as an image diagnostic program. The chipset 54 cannot instantly return from a stopped state to an operational state due to the power control circuit 55; it is assumed to be in a transitional period from a stopped state to an operational state. The software first sends a command to the chipset 54 to set the control data D1 in order to send it to the target hardware device (step SZ1). Since the chipset 54 is not in an operational state, it cannot send the control data D1 to the hardware device. After step SZ1, the host CPU software starts counting the waiting time WT using a software timer (step SZ2). For example, the C language sleep function is used as the software timer. After step SZ2, the chipset 54 is assumed to return to an operational state.

Upon returning to an operational state, the chipset 54 transmits control data D1 to the target hardware device via an external bus such as PCIe, according to the setting command. When the hardware device receives control data D1, it is set on that hardware device. When the waiting time WT count is complete (step SZ4), the software supplies a setting command for control data D2 to the chipset 54 (step SZ5). The chipset 54 then supplies control data D2 to the target hardware device via an external bus such as PCIe, according to the setting command, and sets it on that hardware device.

As described above, in the comparative example, the CPU core 53 attempts to ensure a waiting time WT by using a software timer. Since it takes time to transition from a stopped state to an operational state, a time lag may occur between the time the software issues a setting command for control data D1 (step SZ1) and the time the chipset 54, etc., actually executes this command and transmits it to hardware devices such as the main unit 10 via an external bus such as PCIe (step SZ3). On the other hand, after issuing the setting command (step SZ1), the software counts the waiting time WT (step SZ2). Therefore, the time interval between the time the control data D1 is actually transmitted to the hardware device (step SZ3) and the time the control data D2 is transmitted to the hardware device (step SZ6) becomes shorter than the waiting time WT. This may cause the target hardware device to malfunction.

The ultrasound diagnostic apparatus 100 according to this embodiment comprises a main unit 10 and a host control circuit 21. The main unit 10 includes hardware equipment used for ultrasound image diagnosis and a hardware timer 31. When the host control circuit 21 transmits second control data after a predetermined waiting time has elapsed since the transmission of first control data, it counts the predetermined waiting time in cooperation with hardware timers 31 and 201, triggered by the transmission of the first control data, and transmits the second control data upon completion of the counting of the predetermined waiting time. This configuration attempts to reliably ensure the waiting time. The following describes in detail an example of the control data setting process according to this embodiment. For the purposes of the following description, the hardware equipment to which the control data is set is assumed to be the transmit/receive control circuit 14 of the main unit 10, or the ultrasound probe 11, transmit circuit 12, receive circuit 13, signal processing circuit 15, memory 16, power supply circuit 17, etc., connected to the transmit/receive control circuit 14, and the hardware timer is assumed to be the hardware timer 31 provided in the transmit/receive control circuit 14. This embodiment is similarly applicable to other hardware equipment and other hardware timers.

(Example 1)
The host control circuit 21 in Embodiment 1 counts the waiting time WT through the cooperation of a hardware timer 31 and a software timer. More specifically, the host control circuit 21 counts the waiting time WT based on time counting by the software timer and polling of the hardware timer 31. The hardware timer 31 in Embodiment 1 is assumed to be a counter with units of 1 usec or 1 msec, for example. The hardware timer 31 is configured to count by incrementing.

Figure 3 shows an example of the control data setting process according to Embodiment 1. The setting process in Figure 3 illustrates the process of setting a series of control data D1 and control data D2 to a hardware device. Before step SA1, the chipset 54 of the host CPU 51 is in a stopped state due to the power control circuit 55. Upon a mode change instruction from the operator via the operating device 25, the power control circuit 55 begins to return to an operational state. However, it is assumed that the chipset 54 is in the process of transitioning from the stopped state to the operational state at the start of step SA1. The CPU core 53 is assumed to be in an operational state at the start of step SA1.

As shown in Figure 3, first, the software (CPU core 53) of the host CPU 51 of the host control circuit 21 sends a setting command for control data D1 to the chipset 54 in order to transmit the control data D1 to the target hardware device, in accordance with the instructions from the operator via the operating device 25 (step SA1). At step SA1, the chipset 54 is not in an operational state and therefore cannot transmit the control data D1 to the hardware device.

Once step SA1 is completed, the software uses a software timer to start counting the waiting time WT (step SA2). The waiting time WT is preset according to the types of control data D1 and D2.

When step SA2 is performed, the software sends a request command for time information HT1 from the hardware timer 31 to the chipset (step SA3). Assume that the chipset 54 has not yet returned to an operational state at step SA3 and has not yet sent the request for time information HT1 to the hardware device.

After step SA3, the chipset 54 returns to an operational state. Upon returning to an operational state, the chipset 54 transmits control data D1 to the hardware device according to the setting command in step SA1 (step SA4). When the hardware device receives the control data D1, the control data D1 is set on that hardware device.

Furthermore, the chipset 54 requests time information HT1 from the hardware timer 31 in accordance with the request instruction in step SA3 (step SA5). In response to this request, the hardware timer 31 supplies the time of the request or a time close to it as time information HT1 to the chipset (step SA6). Time information HT1 can be considered equivalent to the time when control data D1 was transmitted to the hardware device. The chipset 54 supplies time information HT1 to the software (step SA7). The software retains time information HT1.

Subsequently, the software completes the counting of the waiting time WT by the software timer (step SA8). Upon completion of step SA8, the software sends a request for time information HT2 from the hardware timer 31 to the chipset 54 (step SA9). The chipset 54 then requests the time information HT2 from the hardware timer 31 according to this request (step SA10). In response to this request, the hardware timer 31 sends the time of the request as time information HT2 to the chipset 54 (step SA11), and the chipset 54 sends the time information HT2 to the software (step SA12).

When step SA12 is performed, the software determines whether the difference between time information HT2 and time information HT1 is greater than or equal to the waiting time WT (step SA13). If it is determined that the difference is not greater than or equal to the waiting time WT (step SA13: NO), the software repeats steps SA9 to SA12 and requests the latest time information HT2 from the hardware timer 31. If it is determined in step SA13 that the difference between time information HT2 and time information HT1 is greater than or equal to the waiting time WT (step SA13: YES), the software sends a command to set control data D2 to the chipset 54 (step SA14), and the chipset 54 sends the control data D2 to the hardware device according to the request (step SA15).

The control data setting process according to Embodiment 1 is now complete. Note that the time series shown in Figure 3 is an example and is not limited thereto. The time it takes for the chipset 54 to return from an inactive state to an active state varies considerably depending on the circumstances. The time at which the control data D1 and time information HT1 are transmitted to the hardware device is not limited to after the request command (step SA3) as shown in Figure 3. It may also be between the start of the waiting time WT count (step SA2) and the request command (step SA3), or between the setting command (step SA1) and the start of the waiting time WT count (step SA2).

As described above, the host control circuit 21 in Embodiment 1, upon transmission of control data D1, starts counting the waiting time WT using a software timer and simultaneously collects time information HT1 from the hardware timer 31. Upon completion of the waiting time WT count using the software timer, the host control circuit 21 collects time information HT2 from the hardware timer 31. If the difference between time information HT1 and time information HT2 is not greater than or equal to the waiting time WT, the host control circuit 21 collects the waiting time WT again after a predetermined time has elapsed. If the difference is greater than or equal to the waiting time WT, it transmits control data D2 to the hardware device. In this way, the host control circuit 21 confirms the completion of the waiting time WT count by the software timer and secures the waiting time WT by polling the hardware timer 31 installed on the hardware device to which control data D1 and D2 are supplied. This ensures that a waiting time WT is reliably secured between control data D1 and control data D2, even immediately after the host CPU 51 transitions from a stopped state to an operational state.

(Example 2)
The host control circuit 21 in Embodiment 2 counts the waiting time using an interrupt triggered by the completion of the waiting time count by the hardware timer 31. The hardware timer 31 in Embodiment 2 is configured to count by decrementing. In the case of a decrement counter, the hardware timer 31 notifies the host CPU of the host control circuit 21 that the count has been completed by sending an interrupt when the value becomes 0.

Figure 4 shows an example of the control data setting process according to Embodiment 2. The setting process in Figure 4, similar to the setting process in Figure 3, illustrates the process of setting a series of control data D1 and control data D2 to hardware devices provided in the main unit 10, such as the transmit/receive control circuit 14. Before step SB1, the chipset 54 of the host CPU 51 is in a stopped state due to the power control circuit 55. Upon a mode change instruction from the operator via the operating device 25, the power control circuit 55 begins to return to an operational state. However, it is assumed that the chipset 54 is in the process of transitioning from the stopped state to the operational state at the start of step SB1. The CPU core 53 is assumed to be in an operational state at the start of step SB1.

As shown in Figure 4, first, the software of the host CPU 51 of the host control circuit 21 sends a setting command for control data D1 to the chipset 54 (step SB1) in order to send the control data D1 to the target hardware device, following instructions from the operator via the operating device 25. At step SB1, the chipset 54 has not yet returned to an operational state and cannot send the control data D1 to the hardware device.

When step SB1 is performed, the software sends the waiting time WT to the hardware timer 31, and therefore sends a count command along with the waiting time WT to the chipset 54 (step SB2). It is assumed that the chipset 54 has not yet returned to an operational state at the time of step SB2 and is therefore unable to send the count command to the hardware timer 31.

After step SB2, the chipset 54 transitions to an operational state. Upon returning to the operational state, the chipset 54 transmits control data D1 to the hardware device according to the setting command in step SB1 (step SB3). When the hardware device receives control data D1, it is configured on that hardware device.

Furthermore, the chipset 54, in accordance with the counting instruction in step SB2, sends a waiting time WT to the hardware timer 31 to instruct it to count (step SB4). Once step SB4 is performed, the hardware timer 31 begins counting the waiting time WT (step SB5). The hardware timer 31 counts by decrementing the waiting time WT. When the waiting time WT reaches 0, the hardware timer 31 completes the counting of the waiting time WT (step SB6).

When step SB6 is performed, the hardware timer 31 sends completion information to the software via the chipset 54, indicating that the count has been completed. Specifically, the hardware timer 31 sends the completion information to the chipset 54 (step SB7), and the chipset sends the completion information to the software (step SB8). When step SB8 is performed, the software supplies a setting command for control data D2 to the chipset 54 (step SB9), and the chipset 54 supplies the control data D2 to the hardware device according to the request (step SB10).

The control data setting process according to Embodiment 2 is now complete. Note that the time series shown in Figure 4 is an example and is not limited thereto. The time it takes for the chipset 54 to return from an inactive state to an active state varies depending on the circumstances, and the time at which the control data D1 is transmitted to the hardware device is not limited to after the count command (step SB2) as shown in Figure 4, but may also be between the setting command (step SB1) and the count command (step SB2).

As described above, the host control circuit 21 in Embodiment 2, upon transmission of control data D1, sends a request to the hardware timer 31 to count the waiting time WT. Upon receiving this request, the hardware timer 31 begins counting the waiting time WT, and upon completion of the count, transmits completion information indicating that the count is complete. Upon receiving the completion information, the host control circuit 21 transmits control data D2 to the hardware device. In this way, the host control circuit 21 causes the hardware timer 31, to which control data D1 and D2 are supplied, to count the waiting time WT, and the hardware timer 31 notifies the host control circuit 21 of the completion of the count via an interrupt, thereby ensuring the waiting time WT is secured. This makes it possible to reliably secure the waiting time WT between control data D1 and control data D2, even immediately after the host CPU 51 transitions from a stopped state to an operational state.

(Example 3)
The host control circuit 21 according to Embodiment 3 sets multiple types of control data sequences on hardware devices. The number of types of control data sequences can be any number, as long as it is two or more. The hardware devices to be set may be the same device or different devices. The main unit 10 according to Embodiment 3 has multiple hardware timers 31 as hardware timers 31. When the host control circuit 21 transmits multiple control data sequences with multiple waiting times, it uses the multiple hardware timers 31 to count the multiple waiting times.

As an example, the host control circuit 21 transmits a first type of control data sequence DA and a second type of control data sequence DB to a single hardware device. For control data DA, the first control data DA1 and the second control data DA2 following the first control data DA1 are set with a waiting time WTA in between. For control data DB, the first control data DB1 and the second control data DB2 following the first control data DB1 are set with a waiting time WTB in between.

Figure 5 shows an example of the setting process for multiple control data according to Embodiment 3. As shown in Figure 5, the host control circuit 21 executes the setting process according to Embodiment 1 in parallel for the control data sequence DA and the control data sequence DB. The hardware timer 31 for the control data sequence DA is denoted as "Hardware Timer A," and the hardware timer 31 for the control data sequence DB is denoted as "Hardware Timer B." Hardware Timer A and Hardware Timer B have different counting units. More specifically, the unit time for Hardware Timer A is 1 usec, and the unit time for Hardware Timer B is 1 msec. Also, before step SC1 in Figure 5, the chipset 54 of the host CPU 51 is in an inoperable state due to the power control circuit 55, and the power control circuit 55 starts to return to an operable state in response to a mode change instruction from the operator via the operating device 25. However, the chipset 54 is assumed to be in the process of transitioning from the inoperable state to the operable state at the start of step SC1. The CPU core 53 is assumed to be in an operable state at the start of step SC1. Note that in Figure 5, for simplicity, the chipset 54 and the software are not shown separately; instead, the host control circuit 51, which encompasses both the chipset 54 and the software, is shown, and consequently, the time lag is also omitted from the diagram.

As shown in Figure 5, the host control circuit 21 supplies control data DA1 to the hardware device (step SC1). After step SC1, the host control circuit 21 starts counting the waiting time WTA using a software timer (step SC2). Simultaneously with the counting of the waiting time WTA, the host control circuit 21 requests time information HTA1 from the hardware timer A (step SC3), and the hardware timer A transmits the first time information HTA1 to the host control circuit 21 (step SC4). The host control circuit 21 holds the received first time information HTA1.

Furthermore, after supplying control data DA1 (step SC1), the host control circuit 21 supplies control data DB1 to the hardware device (step SD1). Once step SD1 is performed, the host control circuit 21 starts counting the waiting time WTB using a software timer (step SD2). Simultaneously with the counting of the waiting time WTB, the host control circuit 21 requests time information HTB1 from the hardware timer B (step SD3), and the hardware timer B transmits the first time information HTB1 to the host control circuit 21 (step SD4). The host control circuit 21 holds the received first time information HTB1.

Once the waiting time WTA count is complete (step SC5), the host control circuit 21 requests time information HTA2 from hardware timer A (step SC6), and hardware timer A transmits the second time information HTA2 to the host control circuit 21 (step SC7). The host control circuit 21 then determines whether the difference between time information HTA2 and time information HTA1 is greater than or equal to the waiting time WTA (step SC8). If it is determined that the difference is not greater than or equal to the waiting time WTA (step SC8: NO), the host control circuit 21 repeats steps SC6-SC7 and requests the latest time information HTA2 from hardware timer 31. If it is determined in step SC8 that the difference between time information HTA2 and time information HTA1 is greater than or equal to the waiting time WTA (step SC8: YES), the host control circuit 21 supplies control data DA2 to the hardware device (step SC9).

Once the waiting time WTB count is complete (step SD5), the host control circuit 21 requests time information HTB2 from the hardware timer B (step SD6), and the hardware timer B transmits the second time information HTB2 to the host control circuit 21 (step SD7). The host control circuit 21 then determines whether the difference between time information HTB2 and time information HTB1 is greater than or equal to the waiting time WTB (step SD8). If it is determined that the difference is not greater than or equal to the waiting time WTB (step SD8: NO), the host control circuit 21 repeats steps SD6-SD7, requesting the latest time information HTB2 from the hardware timer 31. If it is determined in step SD8 that the difference between time information HTB2 and time information HTB1 is greater than or equal to the waiting time WTB (step SD8: YES), the host control circuit 21 supplies control data DB2 to the hardware device (step SD9).

This concludes the setting process for the multiple control data according to Example 3.

The setting process for multiple control data is not limited to the above example. For example, the host control circuit 21 may execute the setting process according to Example 2 in parallel for control data series DA and control data series DB. Also, although hardware timers A and B were given different unit times, they may be the same. Furthermore, Example 3 may use only one hardware timer to count the waiting times WTA and WTB. The host control circuit 21 in Example 3 may execute the setting process of Example 1 or Example 2 in parallel for three or more control data series.

(Summary)
The ultrasound diagnostic apparatus 100 according to this embodiment solves the problem of not being able to secure sufficient waiting time due to delays in setting control data that occur when using a host CPU 21 with enhanced power management. Consequently, it is possible to avoid or reduce malfunctions of the ultrasound diagnostic apparatus 100 that occurred due to the inability to secure sufficient waiting time.

It is possible to resolve the above problem by disabling or temporarily suspending the power management of the host CPU 21. However, if power management is disabled, the function to reduce power consumption will not work, and therefore the request to reduce power consumption cannot be met. Furthermore, if power management is temporarily suspended, the BIOS (Basic Input/Output System) needs to be modified, making it impossible to use commercially available ATX motherboards. A custom ATX motherboard must be developed, increasing the development cost of the host CPU 21.

The host CPU 51 in this embodiment can use a commercially available CPU compliant with the ATX standard. Therefore, it is possible to satisfy the requirements for low power consumption while also satisfying the specifications for control data settings, ultimately realizing a low-cost, low-power, and stable ultrasound diagnostic device 100.

According to at least one embodiment described above, it is possible to reliably ensure a predetermined waiting time between control data when setting control data sequentially.

In the above description, the term "processor" refers to circuits such as CPUs, GPUs, or Application Specific Integrated Circuits (ASICs), programmable logic devices (e.g., Simple Programmable Logic Devices (SPLDs), Complex Programmable Logic Devices (CPLDs), and Field Programmable Gate Arrays (FPGAs)). The processor functions by reading and executing programs stored in memory circuits. Alternatively, instead of storing programs in memory circuits, the processor may be configured to directly incorporate programs into its circuits. In this case, the processor functions by reading and executing programs incorporated into the circuits. On the other hand, if the processor is an ASIC, for example, instead of storing programs in memory circuits, the functions are directly incorporated as logic circuits within the processor's circuits. It should be noted that each processor in this embodiment is not limited to being configured as a single circuit; multiple independent circuits may be combined to form a single processor, and its functions may be realized in this configuration. Furthermore, the multiple components shown in Figure 1 may be integrated into a single processor to realize their functions.

While several embodiments have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, modifications, and combinations of embodiments are possible without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, as well as within the scope of the claims and its equivalents.

10 Main unit 11 Ultrasonic probe 12 Transmitting circuit 13 Receiving circuit 14 Transmitting/receiving control circuit 15 Signal processing circuit 16 Memory 17 Power supply circuit 20 Host unit 21 Host control circuit 22 Image generation circuit 23 Storage device 24 Display device 25 Operating device 26 Power supply circuit 31 Hardware timer 51 Host control circuit 52 Host memory 53 CPU core 54 Chipset 55 Power control circuit 100 Ultrasonic diagnostic device 200 Biological information collector 201 Hardware timer

Claims (8)

A device unit having hardware equipment and a hardware timer used for ultrasound imaging diagnosis,
The system comprises a control unit connected to the aforementioned equipment unit and transmitting control data to the aforementioned hardware equipment,
The control unit,
When transmitting second control data after a predetermined time interval has elapsed since the first control data, the transmission of the first control data triggers the start of counting the predetermined time interval using a software timer that counts time by software, and the first time information is collected from the hardware timer.
Upon completion of the counting of the predetermined time interval using the software timer, a second time information is collected from the hardware timer.
If the difference between the first time information and the second time information is not greater than or equal to the predetermined time interval, the second time information is collected again.
If the difference is greater than or equal to the predetermined time interval, the second control data is transmitted to the hardware device.
Ultrasound diagnostic equipment. A device unit having hardware equipment and a hardware timer used for ultrasound imaging diagnosis,
The system comprises a control unit connected to the aforementioned equipment unit and transmitting control data to the aforementioned hardware equipment,
The control unit,
When transmitting the second control data after a predetermined time interval has elapsed since the first control data, the transmission of the first control data triggers a request to the hardware timer to count the predetermined time interval.
The hardware timer, upon receiving the request, starts counting for the predetermined time interval, and upon completion of the counting for the predetermined time interval, transmits completion information indicating that the counting is complete.
The control unit transmits the second control data to the hardware device upon receiving the completion information.
Ultrasound diagnostic equipment. A device unit having hardware equipment and a hardware timer used for ultrasound imaging diagnosis,
The system comprises a control unit connected to the aforementioned equipment unit and transmitting control data to the aforementioned hardware equipment,
When the control unit transmits the second control data after a predetermined time interval has elapsed since the first control data, it counts the predetermined time interval in cooperation with the hardware timer upon the transmission of the first control data, and transmits the second control data upon completion of the counting of the predetermined time interval.
The equipment unit and the control unit are connected by a first data transmission path.
The hardware components of the aforementioned equipment unit are connected by a second data transmission path.
The data transfer rate of the second data transmission line is lower than that of the first data transmission line.
Ultrasound diagnostic equipment. The aforementioned device unit has a plurality of hardware timers as the hardware timers,
When the control unit transmits multiple control data sequences at multiple predetermined time intervals, it uses the multiple hardware timers to count the multiple predetermined time intervals.
An ultrasound diagnostic apparatus according to any one of claims 1 to 3 . The ultrasound diagnostic apparatus according to claim 4 , wherein the plurality of hardware timers count time in a plurality of units of time. The ultrasonic diagnostic apparatus according to any one of claims 1 to 3 , wherein the hardware equipment includes one of an ultrasonic probe, a transmitting circuit, a receiving circuit, a transmitting/receiving control circuit, a signal processing circuit, a power supply circuit, and a memory. The ultrasound diagnostic apparatus according to claim 6 , wherein the hardware equipment includes either the equipment unit or a biological information collector connected to the control unit. The control unit has a power management function, as described in any one of claims 1 to 3 .