JP7538275B2 - HIGH POWER MMIC DEVICE WITH BYPASS-GATED TRANSISTORS - Patent application - Google Patents

Description

The inventive concepts described herein relate to microelectronic devices, and more particularly to high power, high frequency transistors having unit cell based structures.

In recent years, electrical circuits that require high power handling capabilities while operating at high frequencies, such as radio frequencies (500 MHz), S-band (3 GHz), and X-band (10 GHz), have become more prevalent. The increase in high power, high frequency circuits has led to a corresponding increase in the demand for transistors that can operate reliably at radio and microwave frequencies and still handle higher power loads.

To provide increased output power, transistors with larger gate perimeters have been developed. One technique for increasing the effective gate perimeter of a transistor is to provide multiple transistor cells connected in parallel. For example, a high-power transistor may have multiple gate fingers extending in parallel between respective elongated source and drain contacts, as shown in FIG. 1.

In particular, FIG. 1 illustrates a metal layout of a conventional transistor structure 10, comprising a gate pad 12, a source pad 22, and a drain pad 32 on a semiconductor structure 20. FIG. 1 illustrates a plan view of the device (i.e., looking down on the device). As illustrated in FIG. 1, in a conventional transistor 10, a gate pad 12 is connected to a plurality of gate fingers 16 that extend in parallel in a first direction (e.g., the y-direction shown in FIG. 1) through a gate bus 14. A source pad 22 is connected to a plurality of parallel source contacts 26 through a source bus 24, and a drain pad 32 is connected to a plurality of drain contacts 36 through a drain bus 34. Each gate finger 16 runs along the y-direction between a pair of adjacent source contacts 26 and drain contacts 36. A unit cell of the transistor 10 is illustrated by a box 40, comprising a gate finger 16 that extends between adjacent source contacts 26 and drain contacts 36. "Gate length" refers to the distance of the gate metallization in the x-direction, while "gate width" is the distance that the source and drain contacts 26 run parallel in the y-direction. That is, the "width" of a gate finger 16 refers to the dimension (distance along the y-direction) of the gate finger 16 that runs parallel to an adjacent source/drain contact 26/36. The gate perimeter of a device refers to the sum of the gate widths of each gate finger 16 of the device 10.

In addition to adding unit cells, the gate perimeter of a multi-cell transistor device can be increased by making the gate fingers wider (i.e., longer in the y-direction). However, making the gate fingers of a device wider can adversely affect the high frequency performance of the device. Furthermore, making the gate fingers wider usually means that the gate fingers must handle increased current densities, which can lead to electromigration of the gate finger metallization.

US Patent Application Publication No. 2002/0066908(A1) U.S. Patent Application Publication No. 2002/0167023(A1) US Patent Application Publication No. 2004/0061129 U.S. Patent No. 7,906,799 U.S. Patent No. 6,316,793 U.S. Patent Application Publication No. 2003/0102482(A1)

In one embodiment, a transistor device includes a source contact extending in a first direction, a gate finger extending in the first direction adjacent the source contact, and a drain contact adjacent the gate finger. The gate finger is between the drain contact and the source contact. A gate pad is electrically connected to the gate finger at multiple locations along the gate finger.

The device further includes a gate jumper extending in the first direction and conductively connected to the gate pad. The gate pad is conductively connected to at least one of a plurality of locations along the gate finger via the gate jumper.

The device may further include a gate bus connected to the gate jumpers and the gate fingers, and a gate signal distribution bar spaced in the first direction from the gate bus and connecting the gate jumpers to the gate fingers.

A transistor device according to a further embodiment includes a gate pad, a gate finger in conductive contact with the gate pad at a first location on the gate finger and extending in a first direction, and a gate jumper in conductive contact with the gate pad and extending in the first direction. The gate jumper is conductively connected to the gate finger at a second location on the gate finger spaced apart from the first location such that a gate signal received at the gate pad is applied to the gate finger at the first location and the second location.

A transistor device according to a further embodiment includes a gate bus, a gate finger in contact with the gate bus and extending in a first direction, and a gate jumper in contact with the gate bus and extending in the first direction, where the gate jumper is in conductive contact with the gate finger at a location along the gate finger that is spaced from the gate bus in the first direction.

A transistor device according to a further embodiment comprises a substrate, a gate bus on the substrate, and first and second source contact segments extending in a first direction on the substrate, the first and second source contact segments being separated from one another in the first direction by a gap. The device further comprises a gate finger connected to the gate bus on the substrate, the gate finger extending in the first direction and adjacent to the source contact segment. The device further comprises a drain contact on the substrate adjacent to the gate finger, where the gate finger is between the drain contact and the source contact segment, and a gate jumper connected to the gate bus, where the gate jumper is provided over the source contact segment and extends in the first direction,
A gate signal distribution bar extends over the substrate from a gap between the first source contact segment and the second source contact segment to the gate finger, the gate signal distribution bar contacts the gate finger at a gate signal distribution location spaced from the gate bus in the first direction, and the gate signal distribution bar is conductively connected to the gate jumper.

A further embodiment of a transistor includes a drain contact extending along a first axis, a source contact extending along a second axis parallel to the first axis, gate fingers extending between the source and drain contacts, and a plurality of spaced apart gate resistors electrically connected to the gate fingers. At least a first gate resistor is disposed in a portion of the region between the first and second axes, between the first and second ends of the gate fingers, when the transistor is viewed from above.

In one embodiment, the gate finger may comprise a plurality of discontinuous, collinear gate finger segments electrically connected to one another. The transistor may further comprise a gate jumper electrically connected between the gate bus and the first gate finger segment. The first gate resistor may be interposed along an electrical path between the gate jumper and the first gate finger segment. The transistor may also comprise a first gate signal distribution bar interposed along an electrical path between the gate jumper and the first gate finger segment. The first gate resistor may be interposed along an electrical path between the first gate signal distribution bar and the first gate finger segment. Each gate finger segment may be part of a respective gate split, and the transistor may further comprise an odd mode resistor disposed between two adjacent gate splits.

In one embodiment, the source contact comprises a plurality of collinear, discontinuous source contact segments over which the gate jumper extends. The first gate signal distribution bar can extend into a gap between two adjacent source contact segments. The odd-mode resistor can be interposed between the first gate signal distribution bar and a second gate signal distribution bar that is collinear with the first gate signal distribution bar. Additionally, the transistor can comprise a second source contact comprising a plurality of collinear, discontinuous source contact segments over which the gate jumper does not extend, and the odd-mode resistor can be between two adjacent ones of the source contact segments of the second source contact.

In yet another embodiment, a transistor includes a gate finger having a source contact extending in a first direction, a gate jumper extending in the first direction, and a plurality of discontinuous gate finger segments that may be collinear with one another. The transistor further includes a plurality of spaced apart gate resistors electrically connected to the gate jumper. A first gate finger segment is connected to the gate jumper through the first gate resistor.

In one embodiment, the source contact comprises a plurality of discontinuous source contact segments, and the first gate resistor is in a gap between two adjacent source contact segments. The gate jumper may extend over at least a portion of the source contact segments. The transistor further comprises a drain contact extending in a first direction adjacent to the gate finger such that the gate finger extends between the source contact and the drain contact, a second gate finger comprising a plurality of discontinuous, collinear gate finger segments extending in the first direction such that the drain contact extends between the gate finger and the second gate finger, and a second source contact comprising a plurality of discontinuous source contact segments extending in the first direction adjacent to the second gate finger. The odd-mode resistor may be provided in a gap between two adjacent source contact segments of the second source contact.

The gate signal distribution bar may extend between the gate jumper and the first gate finger segment of the first gate finger, and between the gate jumper and the first gate finger segment of the second gate finger. The gate signal distribution bar may be disposed in a gap between two adjacent source contact segments of the source contact. The odd-mode resistor may be connected between the gate signal distribution bar and a second gate signal distribution bar that connects the gate finger segments of a further plurality of gate fingers to the second gate jumper.

A transistor according to a further embodiment comprises a plurality of gate fingers extending in a first direction and spaced apart from one another in a second direction perpendicular to the first direction. Each of the gate fingers comprises first and second substantially collinear gate finger segments spaced apart from one another, where the first gate finger segment is separated in the first direction from the second gate finger segment by a gap region extending in the second direction. A resistor is disposed in the gap region.

In one embodiment, the transistor further comprises a plurality of source contacts extending in a first direction, each source contact comprising a plurality of discontinuous source contact segments, each source contact comprising a source contact extending between a respective pair of gate fingers, and a plurality of drain contacts extending in the first direction, each drain contact comprising a drain contact extending between a respective pair of gate fingers. A gate bus may be electrically connected to the gate fingers, and a gate jumper may be electrically connected to the gate bus, where the gate jumper is interposed along an electrical path between at least a portion of the gate finger segments and the gate bus.

In some embodiments, the resistor may be an odd-mode resistor disposed between two adjacent ones of the source contact segments of one of the source contacts. In other embodiments, the resistor may be a gate resistor interposed along the electrical path between the gate jumper and the first gate finger segment of the first gate finger. In these embodiments, the gate resistor may be interposed along a first gate signal distribution bar that extends between the gate jumper and the first gate finger segment of the first gate finger.

According to a further embodiment of the present invention, a monolithic microwave integrated circuit is provided comprising a substrate having a transistor and at least one additional circuit formed thereon. The transistor comprises a drain contact extending in a first direction, a source contact extending in the first direction parallel to the drain contact, a gate finger extending in the first direction between the source contact and the drain contact, and a gate jumper extending in the first direction. The source contact is spaced apart from the drain contact in a second direction perpendicular to the first direction. The gate jumper conductively connects to the gate finger at two or more locations spaced apart from one another along the first direction. A cross-sectional area of the gate jumper in a plane extending in the second direction and perpendicular to the first direction is at least five times larger than a cross-sectional area of the gate finger in the plane. In some embodiments, this cross-sectional area of the gate jumper is ten, twenty, or even thirty times larger than a corresponding cross-sectional area of the gate finger.

In one embodiment, the at least one additional circuit may be an impedance matching circuit, and the transistor may be a high electron mobility transistor.

In one embodiment, the gate finger comprises a plurality of physically discontinuous gate finger segments that are electrically connected to one another via gate jumpers. The discontinuous gate finger segments may be collinear.

In one embodiment, the gate jumpers may be at a different level above the substrate than the gate fingers.

In some embodiments, the source contact may comprise a plurality of discontinuous source contact segments that are electrically connected to one another. In such embodiments, the gate jumper may extend over at least one of the source contact segments and may be electrically isolated from the source contact. The gate jumper need not extend over all of the source contact segments.

In one embodiment, the monolithic microwave integrated circuit can be an amplifier. The amplifier can include at least one driver stage and an output stage, and the output stage can include at least one transistor.

In one embodiment, the gate jumper can be vertically parallel to at least one of the drain contact, the source contact, and/or the gate finger.

According to a further embodiment of the present invention, a monolithic microwave integrated circuit is provided comprising a substrate having transistors and at least one additional circuit formed thereon. At least one transistor comprises a plurality of gate fingers extending in a first direction and spaced apart from one another in a second direction perpendicular to the first direction, each of the gate fingers comprising first and second gate finger segments spaced apart and substantially collinearly arranged and electrically connected to one another, wherein the first gate finger segment is separated in the first direction from the second gate finger segment by a gap region extending in the second direction. The gate jumper may be vertically parallel to at least one of the drain contact, the source contact, and/or the gate fingers.

In one embodiment, the transistor further comprises a plurality of source contacts extending in the first direction, each source contact extending between a respective pair of gate fingers, and a plurality of drain contacts extending in the first direction, each drain contact extending between a respective pair of gate fingers. The monolithic microwave integrated circuit may further comprise a gate bus electrically connected to the gate fingers, and a gate jumper electrically connected to the gate bus, where the gate jumper is interposed along the electrical path between at least one of the second gate finger segments and the gate bus. A cross-sectional area of the gate jumper in a plane extending in the second direction and perpendicular to the first direction is at least five times larger than a cross-sectional area of the gate finger in the plane. In other embodiments, the cross-sectional area of the gate jumper may be ten times, twenty times, or even thirty times larger than a corresponding cross-sectional area of the gate finger. The gate jumper may be at a different level above the substrate than the gate fingers. The gate jumper may extend over at least a portion of the first source contact. In some embodiments, the first source contact may comprise a plurality of discontinuous source contact segments. In such embodiments, the gate jumper may not extend over one of the source contact segments that is furthest from the gate bus.

In one embodiment, the at least one additional circuit may be an impedance matching circuit. The monolithic microwave integrated circuit includes an amplifier. The amplifier may include at least one driver stage and an output stage, where the output stage includes a transistor.

In one embodiment, the transistor may be a high electron mobility transistor.

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate certain embodiments of the invention.

FIG. 1 is a plan view of a metal layout of a conventional multi-cell transistor. FIG. 2 is a plan view of a metal layout of a transistor according to an embodiment. FIG. 3 is a partial isometric view of the transistor of FIG. 2 . 3 is a partial cross-sectional view of the transistor of FIG. 2 taken along line A-A' of FIG. 2; FIG. 3 is a plan view of a larger version of the transistor of FIG. FIG. 6 is a detailed plan view of a small portion of the transistor of FIG. 5. 3 is a cross-sectional view of a unit cell of the transistor device taken along line B-B' in FIG. 2. 3 is a cross-sectional view of a unit cell of the transistor device taken along line C-C' of FIG. 2. FIG. 13 is a plan view of a metal layout of a transistor according to a further embodiment. FIG. 9 is a partial cross-sectional view taken along line A-A' in FIG. 8. FIG. 9 is a partial cross-sectional view taken along line B-B' in FIG. 8. FIG. 9 is a plan view of a larger version of the transistor of FIG. FIG. 11 is a detailed plan view of a small portion of the transistor of FIG. 10. FIG. 13 is a plan view of a metal layout of a transistor according to a further embodiment. FIG. 13 is a plan view of a metal layout of a transistor according to yet a further embodiment. FIG. 13 is a plan view of a metal layout of a transistor, also according to another embodiment. FIG. 13 is a plan view of a metal layout of a transistor according to a further embodiment. 1 is a schematic diagram of a conventional wafer having a number of MMIC devices formed thereon. FIG. 1 is a plan view of a conventional two-stage MMIC amplifier. FIG. 1 is a schematic plan view of a conventional two-stage MMIC amplifier. FIG. 1 is a schematic plan view of an MMIC amplifier with a FET driver stage and a FET output stage, each of which comprises a unit cell FET transistor with segmented gate fingers. FIG. 18B is a schematic diagram of the conventional two-stage MMIC amplifier of FIG. 18A. 18B is a schematic diagram comparing the relative sizes of the conventional two-stage MMIC amplifier of FIG. 18A and a two-stage MMIC amplifier according to an embodiment of the present invention. 5A-5C are schematic diagrams of several exemplary MMIC amplifiers in accordance with further embodiments of the present invention; 5A-5C are schematic diagrams of several exemplary MMIC amplifiers in accordance with further embodiments of the present invention; 5A-5C are schematic diagrams of several exemplary MMIC amplifiers in accordance with further embodiments of the present invention; 4 is a schematic diagram of an MMIC switch according to a further embodiment of the present invention;

Examples of the inventive concepts are described more fully below with reference to the accompanying drawings illustrating examples of the invention. However, the inventive concepts may be embodied in many different forms and should not be construed as limited to the examples set forth herein. Rather, these examples are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concepts to those skilled in the art. Like numbers refer to like elements throughout.

An embodiment of the inventive concept provides a multi-cell transistor device having a large effective gate width. By providing gate signals to the gate fingers at multiple locations along the width of the gate fingers, the high frequency gain performance of the transistor can be improved and electromigration concerns typically associated with wide gate fingers can be mitigated. According to an embodiment, the larger gate width of the multi-cell transistor device can be accommodated by adding a second metal layer over the source regions of the unit cells to act as gate jumpers. The gate jumpers are connected to the gate fingers at various locations along the gate fingers, effectively dividing the gate fingers into multiple segments. The gate jumpers can be provided using a second layer of metal over and extending over the source contacts. The gate jumpers can be interposed between the gate pads and at least a portion of the gate finger segments, electrically connecting the gate pads to the gate finger segments. In one embodiment, the gate jumper can extend over and over the drain contact or gate finger, rather than over and over the source contact.

By effectively dividing the gate fingers into segments and distributing the gate signal to each gate finger segment using gate jumpers, the gain performance of the transistor can be improved and electromigration concerns can be mitigated.

Thus, an embodiment of the inventive concept provides a transistor layout that defines multiple unit cells in series per gate finger. Individually, each unit cell has a shorter effective gate width. However, when the unit cells are connected in series, the effective width of a single gate finger can be increased. The gate fingers of the unit cells connected in series are connected to a gate bus using a second metal bridge that runs over the source contacts of the unit cells. The metal bridge is connected between the source contacts to a connection bar that runs along the surface of the substrate between the source contacts and connects to the gate fingers.

Transistors having the layout described herein can have higher frequency performance and greater output power while simultaneously reducing current density and improving device reliability.

According to further embodiments of the present invention, a multi-cell transistor having a large effective gate width is provided in which multiple series gate resistors (also referred to herein as "gate resistors") are distributed throughout the device. For example, the transistor may have segmented gate fingers, and a series gate resistor may be provided for each gate finger segment or pair of gate finger segments. This approach breaks up long feedback loops within the gate fingers and drains of the transistor structure by making the feedback loops lossy enough to avoid high levels of instability. The distributed series gate resistors may be located, for example, in gap regions provided between the gate finger segments of the gate fingers.

Thus, in one embodiment, a transistor is provided that includes a drain contact extending along a first axis, a source contact extending along a second axis parallel to the first axis, and a gate finger extending between the source and drain contacts. The gate finger may include a plurality of physically discontinuous, collinear gate finger segments that are electrically connected to one another using one or more other structures (e.g., gate jumpers). The transistor further includes a plurality of spaced apart gate resistors electrically connected to the gate fingers. At least one gate resistor is disposed in a portion of the region between the first and second axes, between the first and second ends of the gate finger, when the transistor is viewed from above. In one embodiment, the gate jumper may be electrically connected to the gate finger, and the gate jumper may be electrically connected to a gate bus. A gate jumper can be interposed along the electrical path between the first gate finger segment and the gate bus, and a first gate resistor can be interposed along the electrical path between the gate jumper and the first gate finger segment.

In another embodiment, a transistor is provided that includes a source contact extending in a first direction, a gate jumper extending in the first direction, and a gate finger having a plurality of discontinuous gate finger segments extending in the first direction. The transistor further includes a plurality of spaced apart gate resistors, each of which is electrically connected to the gate jumper. A first gate finger segment is connected to the gate jumper through the first gate resistor.

According to yet another embodiment of the present invention, a multi-cell transistor having a large effective gate width is provided in which multiple odd-mode resistors are distributed throughout the device. In an exemplary embodiment, the odd-mode resistors may be provided in gap regions formed between "gate splits," where a gate split refers to a region in which multiple gate finger segments extend in parallel to one another. To further improve the stability of the transistor, odd-mode resistors may be distributed throughout these gap regions. The gate resistors described above may be located within these gap regions.

Accordingly, in a further embodiment, a transistor is provided that includes a plurality of gate fingers extending in a first direction and spaced apart from one another in a second direction perpendicular to the first direction, each of the gate fingers including first and second gate finger segments that are at least spaced apart and substantially collinearly arranged and electrically connected to one another, where the first gate finger segment is separated in the first direction from the second gate finger segment by a gap region extending in the second direction. At least one resistor is disposed in the gap region. The at least one resistor may be an odd mode resistor and/or a series gate resistor.

Transistors according to embodiments of the inventive concepts may have larger effective gate widths, support increased power density levels, and exhibit improved frequency response, as compared to conventional transistors. Furthermore, gate series resistors and odd-mode resistors, if provided, may help prevent feedback loops that may generate undesirable signals at sufficiently low frequencies close to or within the operating frequency range of the transistor. Thus, the transistors may also exhibit increased stability, thus improving production yields and/or enhancing reliability.

It will be appreciated that the above embodiments may be combined in any manner. For example, a transistor may be provided that includes both a distributed gate resistor and a distributed odd-mode resistor. Similarly, a transistor that includes non-segmented gate fingers may include either or both a distributed gate resistor and a distributed odd-mode resistor.

According to yet another embodiment of the present invention, a FET-based MMIC device is provided that uses one or more bypass-gated transistors. For example, an MMIC amplifier is provided that uses bypass-gated transistors in one or more stages of the amplifier. In an exemplary embodiment, the MMIC amplifier can include an input impedance matching network, a FET driver stage, an interstage impedance matching network, a FET output stage, and an output impedance matching network. At least the FET output stage can include bypass-gated transistors. Because the gate bypass transistors can increase the gate width compared to conventional FET transistors, the MMIC amplifier can include a physically larger FET output stage, and therefore improved power handling capabilities.

An exemplary embodiment of a bypass gated transistor according to an embodiment of the present invention will now be described in more detail with reference to Figures 2-15.

Figure 2 is a plan view of a metal layout of a transistor 100, according to one embodiment. The transistor is formed on a semiconductor structure 120 that includes one or more device epitaxial layers, which are described in more detail below. The layout of Figure 2 is simplified for ease of understanding and includes a gate pad 112 connected to a gate bus 114, and a drain pad 132 connected to a drain bus 134. For clarity, the source pad and source bus have been omitted from Figure 2, but are shown in Figures 5 and 6.

A number of gate fingers 116 are connected to the gate bus 114 and extend in the y-direction. Similarly, a number of drain contacts 136 are connected to the drain bus 134 and extend in parallel and adjacent to each of the gate fingers 116. Although only four gate fingers 116 and three drain contacts 136 are shown in FIG. 2, it will be understood that the transistor 100 may include many more gate fingers 116 and drain contacts 136, and thus the transistor may include multiple unit cells.

A source contact 162 is also provided and extends in the y-direction in parallel with adjacent ones of the gate fingers 116. The source contact 162 is divided in the y-direction into respective source contact segments 162a, 162b, and 162c. The source contact segments may be connected by a source contact bar that extends laterally (in the x-direction) across the device structure. The source contact segments 162a, 162b, 162c may also be connected by other means. For example, a source contact plug may be provided that electrically connects each source contact segment 162a, 162b, 162c to a common conductive layer, for example located at a lower level of the device.

Adjacent ones of the source contact segments 162a-162c are separated by a gap 162g. Although FIG. 2 shows three source contact segments 162a-162c per source contact 162, it will be understood that the inventive concept is not limited to such a configuration and that the source contact 162 may include two or more source contact segments 162a-162c.

The gate fingers 116 may extend parallel to the source contacts 162 for the entire length of the source contacts 162. However, the source contacts 162 are divided into source contact segments 162a-162c such that the source contact segments 162a, 162b, and 162c define a number of unit cells 40a, 40b, and 40c in series for each of the gate fingers 116. That is, each gate finger 116 serves as a gate contact for a number of unit cells 40a, 40b, and 40c that are laid out in the direction along which the gate finger 116 extends (the y-direction) and that define the width of the gate finger 116. Thus, the total width that each gate finger 116 contributes to the gate perimeter of the overall device is equal to the distance that the gate finger 116 is parallel to the adjacent source contact segments 162a, 162b, and 162c in the y-direction.

The transistor 100 further comprises a plurality of gate jumpers 172 extending along the y-direction in parallel with the gate fingers 116. The gate jumpers 172 may be formed over the source contacts 162 and may be insulated from the source contacts 162, for example, by a dielectric layer and/or an air gap. Thus, each gate jumper 172 may be "vertically parallel" to each of the source contacts 162, meaning that an axis perpendicular to the major surface of the substrate extends through each gate jumper 172 and at least one of the source contacts 162. In other embodiments, each gate jumper 172 may additionally and/or alternatively be vertically parallel to a respective drain contact 126 and/or a respective gate finger 116, as described in more detail below. The gate jumpers 172 are electrically connected to the gate bus 114 and connect each gate finger 116 to the gate bus 114 at multiple locations along the gate fingers 116.

Specifically, the gate jumpers 172 are provided at multiple locations along the width of the device and connect to the gate fingers 116 via gate signal distribution bars 174 that extend laterally (x-direction) within the gaps 162g between adjacent ones of the source contact segments 162a, 162b, and 162c. The gate signal distribution bars 174 contact the gate fingers 116 at respective gate signal distribution points 176. Thus, an electrical signal applied to the gate pad 112 (the "gate signal") is propagated to the gate bus 114 and then to the gate jumpers 172, which distribute the gate signal to the gate fingers 116 at multiple locations (the gate signal distribution points 176) along the width of the gate fingers 116. One end of each gate finger 116 may also be directly connected to the gate bus 114, as shown in FIG. 2. Thus, in the embodiment of FIG. 2, rather than having the gate fingers 116 propagate the gate signal across the entire width of the device, the gate signal may travel from the gate bus 114 onto each gate finger 116, or through the gate jumpers 172, propagate across most of the width of the device, and then be distributed to the gate fingers 116 at various locations along the width of the device.

The gate jumper 172 may have a larger cross-sectional area than the gate finger 116 and therefore may be better able to handle a larger current density than the gate finger 116 without the problems typically associated with increased gate width, such as electromigration and reduced high frequency gain performance. For example, in one embodiment, the cross-sectional area of the gate jumper 172 in a first plane extending in the x-axis and z-axis directions (i.e., a plane extending in the x-axis direction and perpendicular to the y-axis direction) is at least 5 times larger than the cross-sectional area of the gate finger 116 in the first plane. In other embodiments, this cross-sectional area of the gate jumper 172 in the first plane may be 10, 20, or even 30 times larger than the corresponding cross-sectional area of the gate finger 116 in the first plane. It will be appreciated that the gate jumper 172 may be designed to have such an increased cross-sectional area as compared to the cross-sectional area of the gate finger 116 by extending the gate jumper 172 further in either the x-axis direction and/or the z-axis direction than the gate finger 116. In some embodiments, it may be most advantageous to design the gate jumper 172 to extend further in both the x-axis direction and/or the z-axis direction than the gate finger 116. For example, in some embodiments, the length of the gate jumper 172 in the x-axis direction may be at least twice the length of the corresponding gate finger 116 in the x-axis direction. In other embodiments, the length of the gate jumper 172 in the x-axis direction may be at least three times the length of the corresponding gate finger 116 in the x-axis direction. In yet other embodiments, the length of the gate jumper 172 in the x-axis direction may be at least five times the length of the corresponding gate finger 116 in the x-axis direction. FIG. 7A, discussed below, illustrates how the cross-sectional area of the gate jumper 172 in the first plane can be larger than the cross-sectional area of the gate finger 116 in the first plane. In FIG. 7A, the cross-sectional area of the gate jumper 172 is perhaps 5 times larger than the cross-sectional area of the gate finger 116. As noted above, in other embodiments, this difference in cross-sectional area can be much larger (e.g., a difference of 10, 20, 30, or even 50 times). In all embodiments disclosed herein, the gate jumper can have such an enlarged cross-sectional area relative to the corresponding gate finger.

Figure 3 is a partial isometric view of the metal layout of transistor 100, and Figure 4 is a partial cross-sectional view taken along line A-A' in Figure 2. As can be seen in Figures 3 and 4, gate jumper 172 is formed at a higher metal level than the metal levels of source contact segments 162a, 162b, 162c, gate finger 116, gate bus 114, and gate signal distribution bar 174. Gate jumper 172 is connected to gate bus 114 and gate signal distribution bar 174 by vertical contact plug 178.

The gate jumpers 172, gate buses 114, vertical contact plugs 178, and gate signal distribution bars 174 may be formed of conductive materials such as copper or aluminum that have very low resistivity.

5 is a plan view of a larger version of transistor 100, and FIG. 6 is a detailed plan view of a small portion 150 of the metal layout of FIG. 5 (i.e., the portion within the dotted box in FIG. 5). Transistor 100 comprises a number of unit cells 40 extending vertically (y-direction). Each unit cell 40 has one gate finger 116 extending across the entire width of the device and is subdivided into series unit cells 40a, 40b, 40c arranged vertically (y-direction) as described above. In the embodiment shown in FIGS. 5 and 6, each unit cell 40 has an overall width of 1120 microns, and series unit cells 40a, 40b, and 40c have widths of 370 microns, 380 microns, and 370 microns, respectively, although the concept of the present invention is not limited to these particular dimensions. In this manner, the effective gate width of the device can be increased.

6, a gate pad 112 and gate bus 114 are provided at one end of the structure, while a drain pad 132 and drain bus 134 are provided at the other end of the structure. A source pad 122 is provided on the side of the structure and is connected to a source bus 124. The source bus 124 is connected to a number of source contact bars that extend laterally (x-direction) to contact the source contact segments 162a, 162b, 162c. As noted above, the source contact segments 162a, 162b, 162c can be electrically connected in other ways, such as by use of source contact plugs that electrically connect each source contact segment 162a, 162b, 162c to a common conductive layer.

The detailed view of portion 150 of the device layout of transistor 100 in FIG. 6 also shows gate fingers 116, gate jumpers 172, gate signal distribution bars 174, and gate signal distribution points 176 where gate signal distribution bars 174 contact gate fingers 116.

7A is a cross-sectional view of a unit cell 40 of the transistor device 100 taken along line B-B' in FIG. 2. FIG. 7B is a cross-sectional view of the unit cell 40 taken along line C-C' in FIG. 2. As shown in FIGS. 7A-7B, the transistor structure 100 comprises a semiconductor structure 120 comprising a substrate 200, which may include, for example, 4H-SiC or 6H-SiC. A channel layer 210 is formed on the substrate 200, and a barrier layer 220 is formed on the channel layer 210. The channel layer 210 and the barrier layer 220 may include Group III-nitride based materials, with the material of the barrier layer 220 having a higher bandgap than the material of the channel layer 210. For example, the channel layer 210 may include GaN, while the barrier layer 220 may include AlGaN.

Due to the band gap difference between the barrier layer 220 and the channel layer 210 and the piezoelectric effect at the interface between the barrier layer 220 and the channel layer 210, a two dimensional electron gas (2DEG) is induced in the channel layer 210 at the junction between the channel layer 210 and the barrier layer 220. The 2DEG acts as a highly conductive layer that allows conduction between the source and drain regions of the device, which are located under the source contact segment 162b and the drain contact 136, respectively. The source contact segment 162b and the drain contact 136 are formed on the barrier layer 220. The gate finger 116 is formed on the barrier layer 220 between the drain contact 136 and the source contact segment 162b. The gate jumper 172 is provided over the source contact segment 162b and is connected to the gate finger 116 via a vertical contact plug 178 and a gate signal distribution bar 174. The vertical contact plugs 178 and the gate signal distribution bars 174 are disposed within the gaps 162g between adjacent ones of the source contact segments 162a-162c and are not in physical contact with the source contact segments 162a-162c.

A first interlayer insulating layer 232 is formed over the drain contact 136, the gate finger 116, the source contact segment 162b, and the gate signal distribution bar 174. The interlayer insulating layer 232 may include a dielectric material such as SiN, _SiO2 , etc. A vertical contact plug 178 passes through the first interlayer insulating layer 232. The gate jumper 172 is formed on the first interlayer insulating layer 232 insulating the gate jumper 172 from the source contact segment 162b. A second interlayer insulating layer 234 may be formed over the first interlayer insulating layer 232 and the gate jumper 172. The second interlayer insulating layer 234 may include a dielectric material such as SiN, _SiO2 , etc.

The material of the gate fingers 116 may be selected based on the composition of the barrier layer 220. However, in certain embodiments, conventional materials capable of making Schottky contact to nitride-based semiconductor materials may be used, such as Ni, Pt, NiSi _x , Cu, Pd, Cr, W, and/or WSiN. The drain contact 136 and source contact segments 162 may include a metal, such as TiAlN, capable of forming an ohmic contact to GaN.

Series gate resistors and odd-mode resistors can be included in high power transistors according to embodiments of the present invention to stabilize the feedback loop in the gate finger and drain of the device. In high power devices, the gate may have a long gate width to increase the gate perimeter of the device, resulting in a long feedback loop. Because such high power transistors have large transconductance values, the feedback loop may be prone to instability. In particular, the feedback loop may generate undesirable signals that may be within or outside the frequency band of operation of the transistor. In either case, the generation of such signals may be problematic and may render the transistor unusable. Feedback loop instability tends to increase with the length of the feedback loop.

According to further embodiments of the present invention, a high power transistor is provided with multiple series gate resistors and/or odd mode resistors distributed throughout the device, particularly along long gate fingers. Distributed series gate resistors and/or odd mode resistors may be particularly advantageous in transistors with segmented gate fingers, since such devices may have "gate split" gap regions that are natural locations for placing series gate resistors and/or odd mode resistors along the width of the gate fingers. As used herein, the term "gate split" refers to a shorter array of gate finger segments that is created when a long gate finger is segmented into multiple gate finger segments, as discussed above with reference to Figures 2-7. As discussed in more detail below, the gap regions that exist between adjacent gate splits may be convenient locations for implementing distributed series gate resistors and odd mode resistors.

It has been found that by distributing the series gate resistors and/or odd-mode resistors along the extended width of the gate fingers, the losses in the feedback loop can be large enough to overcome potential instabilities. Thus, by distributing the series gate resistors and/or odd-mode resistors along the extended width of the gate fingers, it may be possible to improve device yield and/or reduce device failure rates in the field. Furthermore, when the series gate resistors and/or odd-mode resistors are distributed along and between the gate finger segments of a segmented gate finger, a relatively small resistance level can be used. For example, when a transistor has three gate divisions, the resistance level can be about one-third the size of the resistance level used when the gate fingers are not segmented. Furthermore, in practice, it has been found that the reduction in resistance value is even greater. For example, when three gate divisions are used, the resistance value of the series resistors provided along each gate segment can be one-quarter to one-fifth the resistance value of the series gate resistor implemented on the gate pad. Using resistors with lower resistance values reduces losses, which results in a transistor with higher gain while also exhibiting improved stability.

8 is a plan (top) view of a metal layout of a transistor 300 according to a further embodiment, which implements both a series gate resistor and odd-mode resistance in a distributed manner as discussed above. The transistor 300 is formed on a semiconductor structure 320 comprising one or more device epitaxial layers. The semiconductor structure 320 may be the same as the semiconductor structure 120 discussed above with reference to FIGS. 7A and 7B. As with the previous figures, the layout of FIG. 8 is simplified for ease of understanding and includes a pair of gate pads 312 connected to a respective pair of gate buses 314, as well as a drain pad 332 connected to a drain bus 334. The transistor 300 also includes a source pad 322 and a source bus, which are omitted from FIG. 8 for clarity. The source pad 322 is shown in FIG. 10.

A number of gate fingers 316 are connected to each gate bus 314 and extend in the y-direction. Each gate finger 316 is divided in the y-direction into three gate finger segments 316a, 316b, and 316c. The first gate finger segment can be (but need not be) connected directly to the gate bus 314 without a gate jumper 372 interposed therebetween. A gate jumper can be interposed between the gate finger segments 316b, 316c and the gate bus 314. As described below, the gate finger segments 316a, 316b, 316c of each gate finger 316 can be electrically connected to each other via a gate jumper 372, a gate signal distribution bar 374, and a vertical contact plug 378 (FIG. 9A). A plurality of drain contacts 336 are connected to the drain bus 334 and extend in parallel with and adjacent to each of the gate fingers 316. A gate signal distribution bar 374 may be formed at a different vertical level in the device than the gate distribution bar 174 of the transistor 100, as described below, to allow the gate signal distribution bar 374 to pass over the drain contacts 336. A source contact 362 is also provided and extends in the y-direction in parallel with adjacent ones of the gate fingers 316. The source contact 362 is also divided in the y-direction into respective source contact segments 362a, 362b, and 362c. The source contact segments 362a, 362b, 362c may be electrically connected to one another via a source contact plug 364. Each source contact plug 364 may electrically connect the respective source contact segments 362a, 362b, 362c to a common conductive layer that functions as a source bus. This source bus may be located, for example, in a lower level of the device. In some embodiments, multiple source contact plugs 364 may be provided for each source contact segment 362a, 362b, 362c. In FIG. 8, two exemplary source contact plugs 364 are shown on one source contact segment 362c. The source contact plugs 364 of the other source contact segments 362a, 362b, 362c have been omitted from FIG. 8 (as well as from FIGS. 9A-9B and 12-13) to simplify the drawing. FIGS. 10 and 11, for example, show how one pair of source contact plugs 364 may be provided for each source contact segment 362a, 362b, 362c. The source contact segments 362a, 362b, 362c may also be electrically connected by other means, such as, for example, a source contact bar. In FIG. 8, a total of 16 segmented gate fingers 316, eight segmented source contacts 362, and eight drain contacts 336 are shown. However, it will be appreciated that the transistor 300 may include many more gate fingers 316, source contacts 362, and drain contacts 336, such that the transistor 300 includes multiple unit cells. In other embodiments, fewer gate fingers 316, source contacts 362, and drain contacts 336 may be provided.

Adjacent ones of the gate finger segments 316a-316c are separated by gaps 316g, and adjacent ones of the source contact segments 362a-362c are separated by gaps 362g. Although FIG. 8 shows three gate finger segments 316a-316c and three source contact segments 362a-362c for each gate finger 316 and source contact 362, the inventive concept is not limited to such an arrangement. Thus, it will be understood that the gate fingers 316 can include two or more gate finger segments, and the source contacts 362 can include two or more source contact segments.

The gate fingers 316 may extend parallel to the source contacts 362 for the entire length of the source contacts 362. The gate fingers 316 and the source contacts 362 are segmented such that a number of unit cells 340a, 340b, 340c are defined along each gate finger 316. That is, each gate finger segment 316a-316c serves as a gate contact for a respective unit cell 340a, 340b, 340c laid out along the direction along which the gate finger 316 extends (the y-direction). The sum of the widths of the gate finger segments 316a-316c defines the overall width of each gate finger 316. That is, the total width that each gate finger 316 contributes to the overall gate perimeter of the device is equal to the sum of the widths of the gate finger segments 316a-316c in the y-direction.

The transistor 300 further comprises a number of gate jumpers 372 extending along the y-direction in parallel with the gate fingers 316. The gate jumpers 372 may be formed at a metal level higher than the metal levels of the source contact segments 362, the gate fingers 316, and the gate bus 314. The gate jumpers 372 may be formed above the source contacts 362 and may be insulated from the source contacts 362, for example, by a dielectric layer and/or an air gap. The gate jumpers 372 need not extend above the source contact segment 362c that is furthest from the gate bus 314. The gate jumpers 372 are electrically connected to the gate bus 314. The gate jumpers 372 may electrically connect some or all of the gate finger segments 316a-316c of each gate finger 316 to one of the gate buses 314. In the embodiment shown in FIG. 8, each gate jumper 372 electrically connects gate finger segments 316b and 316c to gate bus 314, while gate finger segment 316a is connected to gate bus 314 via a more direct connection. In other embodiments, gate finger segment 316a may be connected to gate bus 314 via gate jumper 372. In some embodiments, gate jumper 372 may be positioned over drain contact 336 or gate finger 316 rather than over source contact 362.

9A is a partial cross-sectional view taken along line A-A' in FIG. 8. FIG. 9B is a partial cross-sectional view taken along line B-B' in FIG. 8. As can be seen in FIGS. 8 and 9A, a plurality of gate jumpers 372, gate signal distribution bars 374, and vertical contact plugs 378 are provided. The gate jumpers 372 are connected to the gate bus 314 and the gate signal distribution bars 374 by vertical contact plugs 378. The gate jumpers 372, gate signal distribution bars 374, and vertical contact plugs 378 are used to connect each gate finger segment 316b-316c to one of the gate buses 314. The gate signal distribution bars 374 may be formed in a higher metal layer in the device than the gate fingers 316. For example, the gate signal distribution bars 374 may be formed in the same metal layer of the device as the gate jumpers 372, as shown in FIG. 9A. A vertical contact plug 378 can connect the gate jumper 372 to the gate bus 314. Further vertical contact plugs 378 (not visible in the cross section of FIG. 9A, but located in the plan view of FIG. 8 where each gate signal distribution bar passes over a gate resistor 380) can physically and electrically connect the gate signal distribution bar 374 to the gate resistors and the gate finger segments 316a-c that connect to the gate resistors. As noted above, the gate jumper 372 can extend over and over the source contacts 362. As can be seen in FIG. 8, the gate jumper 372 is provided over every other source contact 362, in contrast to the transistor 100 of FIGS. 2-7, which has a gate jumper 172 that extends over every source contact 162. Thus, each gate jumper 372 in transistor 300 of FIGS. 8-9B feeds four gate fingers 316 instead of the two gate fingers 116 of transistor 100. Gate signal distribution bars 374 are formed in a metal layer within the device that is higher than gate distribution bar 174 of transistor 100, allowing each gate signal distribution bar 374 to pass over two drain contacts 336 to connect to the outer ones of the four gate finger segments 316a-316c.

The gate jumpers 372, gate buses 314, vertical contact plugs 378, and gate signal distribution bars 374 may be formed of conductive materials such as copper or aluminum that have very low resistivity.

8 and 9A, the gate signal distribution bar 374 extends laterally (x-direction) within the gap 362g between adjacent ones of the source contact segments 362a, 362b, and 362c. The gate signal distribution bar 374 coupled to the first gate finger segment 316a may be coupled to two of the gate finger segments 316a. Each of the gate signal distribution bars 374 coupled to the second or third gate finger segments 316b, 316c may be coupled to four of the gate finger segments 316b or 316c. As can be seen in FIG. 8, each gate signal distribution bar 374 coupled to the first gate finger segment 316a may be connected to one of the gate buses 314 via a gate resistor 380. The gate signal distribution bars 374 that connect to the gate finger segments 316a may be part of the same metal layer as the gate fingers 316 or part of the same metal layer as the gate jumpers 372, since they do not need to cross the drain contacts 336. Each gate signal distribution bar 374 that is coupled to either the second gate finger segment 316b or the third gate finger segment 316c may be connected to one of the gate buses 314 through one of the gate jumpers 372, as seen in Figures 8 and 9A, and may be connected to the gate finger segments 316b, 316c through respective vertical contact plugs 378. A series gate resistor 380 is provided in the electrical path between each gate finger segment 316b, 316c and its associated gate signal distribution bar 374.

8 and 9A, we will now discuss the distribution of an electrical signal applied to the left gate pad 312 of FIG. 8 to the leftmost gate finger segments 316a, 316b, 316c of FIG. 8. When a gate signal is applied to the gate pad 312, it is propagated to the left gate bus 314. From the left gate bus 314, the gate signal travels through the first gate signal distribution bar 374 and the first series gate resistor 380 to the first gate finger segment 316a. The gate signal also travels from the left gate bus 314 through a first vertical contact plug 378 that connects to the gate bus 314 to the gate jumper 372, through the gate jumper 372 to the second gate signal distribution bar 374, and through the second gate signal distribution bar 374 to the second vertical contact plug 378 that connects to the leftmost second gate finger segment 316b through the second series gate resistor 380. The gate signal similarly travels from the left gate bus 314 through the first vertical contact plug 378 to the gate jumper 372, through the gate jumper 372 to the third gate signal distribution bar 374, and through the third gate signal distribution bar 374 to the third vertical contact plug 378 that connects to the leftmost third gate finger segment 316c through the third series gate resistor 380.

8 and 9A, the gate signal does not travel the entire width of every gate finger 316, but instead only travels along the width of the gate finger segment (e.g., gate finger segment 316a), or along the width of the gate finger segment and a portion of the gate jumper 372 (e.g., gate finger segment 316b), or along the width of the gate finger segment and the entire width of the gate jumper 372 (e.g., gate finger segment 316c). As noted above, the gate jumper 372 may have a larger cross-sectional area than the gate fingers 316 and may therefore be better able to handle a larger current density than the gate fingers 316 without the problems typically associated with increased gate width, such as electromigration and reduced high frequency gain performance. The gate signal also travels along a portion of the gate signal distribution bar 374 and the vertical contact plug 378. However, it should be noted that FIG. 8 is not drawn to scale, and that the distance that a gate signal travels along any gate signal distribution bar 374 can be very short (e.g., less than 5%) compared to the width of the gate finger segment in the y-direction, as can be seen in FIGS. 10-11. The distance traveled along the vertical contact plug 378 is also very short. Thus, the distance that the gate signal travels along the narrow conductive trace can be short.

As discussed above, the transistor 300 includes a plurality of series gate resistors 380 distributed throughout the device. Specifically, a series gate resistor 380 is provided at or near one end of each gate finger segment 316a, 316b, 316c. As shown in FIG. 8, the gate finger 316 is divided into three "gate splits", a first gate split 382a comprising gate finger segment 316a, a second gate split 382b comprising gate finger segment 316b, and a third gate split 382c comprising gate finger segment 316c. A first gap region 384a is provided between the gate bus 314 and the first gate split 382a, a second gap region 384b is provided between the gate splits 382a and 382b, and a third gap region 384c is provided between the gate splits 382b and 382c.

8, a series gate resistor 380 may be formed within the gap regions 384a-384c. The series gate resistor 380 may be formed, for example, by depositing a conductive material with a higher resistivity compared to the conductive material used to form the gate fingers 316, the drain contact 336, the source contact 362, etc. The series gate resistor 380 may be provided at any suitable vertical level of the transistor 300. In an exemplary embodiment, the series gate resistor 380 may be formed at the same metallization level as the source contact 362, the drain contact 336, and the gate fingers 316, as can be seen or inferred from FIGS. 8 and 9A. It will also be appreciated that the gate resistor 380 (or odd-mode resistor 390 discussed below) may be replaced with other lossy elements that can function as the functional equivalent of a resistor, such as, for example, a series circuit of an inductor and a capacitor.

As discussed below with reference to FIG. 12, instead of the distributed series gate resistors 380 provided in the transistor according to certain embodiments of the present invention, a single series gate resistor 80 can be provided between each gate pad 312 and its associated gate bus 314. If the series gate resistors are implemented as a single series gate resistor 80 between each gate pad 312 and its corresponding gate bus 314, each series gate resistor 80 may require a relatively high resistance value to reduce or prevent device instability. In the transistor 300, multiple series gate resistors 380 are disposed between the gate splits 382 of the device. Each gate resistor 380 can be of a much smaller resistance value compared to the gate resistor 80 that would be required if the gate resistors 80 were disposed only between the gate pad 312 and the gate bus 314.

In some embodiments, a series gate resistor 380 may be provided for each gate finger segment 316a, 316b, 316c, while in other embodiments, several gate finger segments may share a series gate resistor 380. In the particular embodiment shown in FIG. 8, all of the gate finger segments 316b, 316c have their own associated series gate resistor 380, while the pair of gate finger segments 316a share a single series gate resistor 380. It will also be appreciated that in other embodiments, some of the gate finger segments 316a-316 may not have associated gate resistors 380.

By distributing the series gate resistors at two or more locations along the gate finger 316, the feedback loops in the gate finger and drain of the transistor can be made lossy enough to reduce or eliminate instability, thereby improving device yield and/or reducing the incidence of field device failure. Furthermore, as discussed above and as can be seen in FIG. 8, the current path along any particular gate finger segment 316a, 316b, 316c only needs to traverse a single series gate resistor 380. Because the series gate resistor 380 can have a relatively small resistance, power losses are reduced and thus the transistor 300 can support higher gain levels for a given size device.

As can be seen in FIG. 8, the transistor 300 includes a drain contact 336 extending in the y-direction along a first axis, a source contact 362 extending in the y-direction along a second axis parallel to the first axis, and a gate finger 316 extending between the source contact 362 and the drain contact 336. The gate finger 316 includes a plurality of discontinuous, collinear gate finger segments 316a, 316b, 316c electrically connected to one another. The transistor 300 further includes a plurality of spaced apart gate resistors 380 electrically connected to the gate finger 316. Each gate resistor 380 may be coupled between a respective one of the gate finger segments 316a, 316b, 316c and a respective one of the gate signal distribution bars 374. At least one of the gate resistors 380 is disposed between the first axis and the second axis. A gate jumper 372 is interposed along the electrical path between the gate bus 314 and the gate finger 316. The gate jumper 372 is interposed along each electrical path between the gate finger segments 316b and 316c and the gate bus 314, and each gate resistor 380 is interposed along each electrical path between the gate jumper 372 and the gate finger segments 316b, 316c.

8, the transistor 300 includes a gate finger 316 including a source contact 362 extending in the y-direction, a gate jumper 372 extending in the y-direction, and a plurality of discontinuous, electrically connected gate finger segments 316a, 316b, 316c. The transistor 300 further includes a plurality of spaced apart gate resistors 380. The gate finger segments 316b and 316c are connected to the gate jumper 372 via first and second gate resistors 380, respectively. The pair of gate finger segments 316a are connected to the gate bus 314 via respective gate resistors 380.

As further shown in FIG. 8, odd-mode resistors 390 are also provided in the transistor 300. The odd-mode resistors 390 are provided to break long odd-mode unstable feedback loops in the device. Specifically, as the number of gate fingers 316 powered using the gate jumpers 372 increases, instability may occur. For example, when the gate jumpers 372 power four gate fingers 316, the transistor may be stable, but when the gate jumpers 372 power eight gate fingers 316, it may begin to exhibit instability. When instability occurs, it may be a function of the width of the gate fingers and the operating frequency of the device. The odd-mode resistors 390 may be interposed between adjacent gate signal distribution bars 374. When the transistor 300 operates normally, the voltage on both sides of each odd-mode resistor 390 should be the same, and therefore no current should flow between adjacent gate signal distribution bars 374.

The odd-mode resistor 390 may be provided in the gap region 384 between adjacent gate splits 382. As shown in FIGS. 8 and 9B, the odd-mode resistor 390 may be implemented, for example, on the same metallization level as the gate signal distribution bar 374 and the source contact 362, and may be directly connected between two adjacent gate distribution bars 374. The odd-mode resistor 390 may also be interposed between adjacent gate buses 314.

Thus, the transistor 300 may include a plurality of gate fingers 316 extending in the y-direction and spaced apart from one another in the x-direction. Each gate finger 316 may include a plurality of spaced apart, substantially collinear gate finger segments 316a, 316b, 316c electrically connected to one another, where the gate finger segments 316a, 316b, 316c are disposed within respective gate splits 382a, 382b, 382c separated by gap regions 384b, 384c. An odd-mode resistor 390 is disposed within the gap regions 384b, 384c. In an exemplary embodiment, the odd-mode resistor 390 may be interposed between adjacent gate signal distribution bars 374.

It will also be appreciated that in some embodiments, the source contacts 362 need not be segmented. In particular, both the gate resistor 380 and the odd-mode resistor may be implemented in the same metal layer as the gate signal distribution bar 374 and the gate jumper 372. In such implementations, the source contacts 362 need not be segmented. That is, it will be appreciated that in other embodiments, the resistors 380, 390 may be implemented directly above, or above and to the side of, the source contacts 362 in other embodiments, and each source contact 362 may be a single continuous (i.e., non-segmented) source contact 362.

8 illustrates a transistor 300 with segmented gate fingers 316 and segmented source contacts 362, it will be understood that embodiments of the present invention are not so limited. For example, in other embodiments, the drain contacts 336 can be segmented in a similar manner, such that each drain contact comprises, for example, three separate segments. If the drain contacts 336 are segmented, the segmented drain contacts can be electrically connected to each other, for example, via a drain contact plug and another metallization layer in the device. In embodiments in which the drain contacts are segmented, the source contacts 362 may or may not be segmented. Additionally, the gate fingers 316 may be segmented, as shown in FIG. 8, or may not be segmented, as shown in FIG. 2 (as well as FIGS. 14-15). Segmenting the drain contacts can provide additional space for gate resistors 380 and/or odd-mode resistors 390 in the areas between the gate splits. As one simple example of such an embodiment with segmented drain contact 336, transistor 300 of FIG. 8 can be modified such that reference numbers 332, 334, and 336 are source pad, source bus, and source contact, respectively, and reference numbers 362, 362a/362b/362c, and 364 are drain contact, drain contact segment, and drain contact plug, respectively. In other words, FIG. 8 can also be viewed as an embodiment with segmented gate fingers 316 and segmented drain contact 362 by simply reversing the source and drain characteristics.

Figure 10 is a plan view of a larger version of the transistor 300 of Figure 8. Figure 11 is a detailed plan view of a small portion 302 of the transistor 300 of Figure 10.

10 and 11, the transistor 300 comprises a number of unit cells extending vertically (y-direction). Each unit cell comprises a gate finger 316 that extends across the entire width of the device and is subdivided into series unit cells 340a, 340b, 340c arranged vertically (y-direction) as described above. In the embodiment shown in FIGS. 10-11, each of the unit cells 340 has an overall width of 1120 microns, and the series unit cells 340a, 340b, and 340c have widths of 370 microns, 380 microns, and 370 microns, respectively, although the inventive concept is not limited to these particular dimensions.

A number of gate buses 314 are provided at one end of the structure, while a drain bus 334 is provided at the other end of the structure. A source pad 322 is provided on the side of the structure and is connected to a source bus (not shown), for example located on a lower metallization layer of the device. Source contact segments 362a, 362b, 362c are connected to the source bus via contact plug 364.

In FIG. 11, a detailed view of a portion 302 of the device layout of transistor 300 also shows gate fingers 316, gate jumpers 372, gate signal distribution bars 374, series gate resistors 380, and odd-mode resistors 390.

Transistors according to embodiments of the inventive concept may comprise a semiconductor structure that is a multi-layer structure. For example, as discussed above with reference to Figures 7A and 7B, the semiconductor structure 120 of the transistor 100 may comprise a substrate 200 (e.g., 4H-SiC or 6H-SiC) on which at least a channel layer 210 and a barrier layer 220 are formed. The same is true with respect to other transistors according to embodiments of the inventive concept shown herein. Thus, it will be understood that the discussion of the semiconductor structure 120 in Figures 7A and 7B applies equally to the semiconductor structures of each of the other embodiments described herein, although the metallization and other aspects of the device will vary based on the differences between the various embodiments depicted in the figures. Thus, for example, all of the transistors described herein may comprise a silicon carbide substrate and Group III nitride-based channel and barrier layers, and it will be understood that the semiconductor structures of such transistors may operate in the manner described with reference to Figures 7A and 7B.

12 is a plan view of a metal layout of a transistor 400 in accordance with a further embodiment of the inventive concept. Transistor 400 is similar to transistor 300 discussed above with reference to FIGS. 8-11, except that transistor 400 uses a series gate resistor 80 connected between each gate pad 312 and a respective gate bus 314 instead of the distributed series gate resistor 380 provided in transistor 300. Apart from this modification, the two transistors 300, 400 may otherwise be essentially identical, and therefore further discussion of transistor 400 will be omitted.

13 is a plan view of a metal layout of a transistor 500 according to yet another embodiment of the inventive concept. The transistor 500 is again similar to the transistor 300 discussed above with reference to FIGS. 8-11, except that the transistor 500 uses a single odd-mode resistor 90 between each pair of adjacent gate buses 314 and does not include the distributed odd-mode resistors 390 provided in the gap regions 384b, 384c of the transistor 300 of FIG. 8. Apart from this modification, the two transistors 300, 500 may otherwise be essentially identical, and therefore further discussion of the transistor 500 will be omitted.

It will be appreciated that features of the above-described embodiments can be combined in any manner to create further embodiments. For example, FIG. 14 is a plan view of a metal layout of a transistor 100' that is the same as transistor 100 described above, except that it has been modified to include a series gate resistor 180, which may be the same as series gate resistor 380 of FIG. 8. As another example, FIG. 15 is a plan view of a metal layout of a transistor 300' that is similar to transistor 300 described above, except that gate fingers 316 are no longer segmented, and the location of series gate resistor 380 has been modified accordingly. It will be appreciated that FIGS. 14 and 15 are provided to illustrate some of the possible combinations of the various embodiments that result in further embodiments.

Embodiments of the inventive concept may be particularly suitable for use in connection with Group III nitride-based high electron mobility transistor (HEMT) devices. As used herein, the term "Group III nitrides" refers to those semiconductor compounds formed between nitrogen and elements in Group III of the periodic table, usually aluminum (Al), gallium (Ga), and/or indium (In). The term Group III nitrides also refers to ternary and quaternary compounds such as AlGaN and AlInGaN. All such compounds have an empirical formula in which one mole of nitrogen is combined with one mole of the total Group III elements.

A suitable structure for a GaN-based HEMT in which embodiments of the present invention can be utilized is described, for example, in commonly assigned U.S. Patent Application Publication No. 2002/0066908(A1), published June 6, 2002, entitled "Aluminum Gallium Nitride/Gallium Nitride High Electron Mobility Transistors Having a Gate Contact On a Gallium Nitride Based Cap Segment and Methods of Fabricating a GaN-based HEMT." "Group-III Nitride Based High Electron Mobility Transistor (HEMT) With Barrier/Spacer Layer"; U.S. Patent Application Publication No. 2002/0167023(A1) published on November 14, 2002; "Nitride-Based Transistors and Methods Of Fabrication Thereof Using Non-Etched Contact"; No. 7,906,799, issued on March 15, 2011, entitled "Nitride-Based Transistors With A Protective Layer And A Low-Damage Recess," and U.S. Pat. No. 6,316,793, issued on November 13, 2001, entitled "Nitride-Based Transistors On Semi-Insulating Silicon Carbide Substrates," the disclosures of which are hereby incorporated by reference in their entireties.

In certain embodiments of the present invention, the substrate 200 may be a semi-insulating silicon carbide (SiC) substrate, which may be, for example, the 4H polytype of silicon carbide. Other candidate polytypes of silicon carbide include the 3C, 6H, and 15R polytypes.

Optionally, a buffer layer, nucleation layer, and/or transition layer (not shown) may be provided on the substrate 200 below the channel layer 210. For example, an AlN buffer layer may be provided to provide a suitable crystal structure transition between the silicon carbide substrate and the remainder of the device. Additionally, a strain balancing transition layer may also be provided, as described, for example, in commonly assigned U.S. Patent Application Publication No. 2003/0102482(A1), entitled "Strain Balanced Nitride Heterojunction Transistors and Methods Of Fabricating Strain Balanced Nitride Heterojunction Transistors," published June 5, 2003, the disclosure of which is incorporated herein by reference as if fully set forth herein. Additionally, one or more capping layers, such as a SiN capping layer, may be provided on the barrier layer 220.

Silicon carbide has a much closer crystal lattice match to III-nitrides than sapphire (Al ₂ O ₃ ), a very common substrate material for III-nitride devices. The closer lattice match of SiC allows for higher quality III-nitride films than are typically obtained on sapphire. Silicon carbide also has a very high thermal conductivity, so that the total power output of a III-nitride device on silicon carbide is not typically limited by the heat dissipation of the substrate as is the case for the same device formed on sapphire. The availability of semi-insulating silicon carbide substrates also allows for device isolation and reduced parasitic capacitance. Suitable SiC substrates are manufactured, for example, by Cree, Inc. of Durham, North Carolina, the assignee of the present invention.

Although silicon carbide may be used as the substrate material, embodiments of the present invention may utilize any suitable substrate, such as sapphire, aluminum nitride, aluminum gallium nitride, gallium nitride, silicon, GaAs, LGO, ZnO, LAO, InP, etc. In certain embodiments, a suitable buffer layer may also be formed.

In one embodiment of the present invention, the channel layer 210 is a group III nitride such as _{AlxGa1 -} xN, where 0 < x < 1, provided that the energy of the conduction band edge of the channel layer 210 is less than the energy of the conduction band edge of the barrier layer 220 at the interface between the channel layer and the barrier layer. In a particular embodiment of the present invention, x = 0, indicating that the channel layer 210 is GaN. The channel layer 210 may be other group III nitrides such as InGaN, AlInGaN, etc. The channel layer 210 may be undoped or unintentionally doped, and may be grown to a thickness greater than about 20 Å. The channel layer 210 may also be a multi-layer structure such as a superlattice or a combination of GaN, AlGaN, etc.

The channel layer 210 can have a bandgap smaller than that of the barrier layer 220, and the channel layer 210 can also have a larger electron affinity than the barrier layer 220. In a particular embodiment of the inventive concept, the barrier layer 220 is AlN, AlInN, AlGaN, or AlInGaN having a thickness between about 0.1 nm and about 10 nm. In a particular embodiment of the inventive concept, the barrier layer 22 is doped to be thick enough and have a high enough Al composition to induce a significant carrier concentration at the interface between the channel layer 210 and the barrier layer 220.

The barrier layer 220 may be a Group III nitride and has a bandgap larger than that of the channel layer 210 and an electron affinity smaller than that of the channel layer 210. Thus, in certain embodiments of the present invention, the barrier layer 220 may comprise AlGaN, AlInGaN, and/or AlN, or a combination of layers thereof. The barrier layer 220 may be, for example, from about 0.1 nm to about 30 nm thick. In certain embodiments of the present invention, the barrier layer 220 is undoped or doped with an n-type dopant to a concentration less than about 10 ¹⁹ cm ⁻³ . In some embodiments of the present invention, the barrier layer 220 is Al _x Ga _1-x N, where 0<x<1. In certain embodiments, the aluminum concentration is about 25%. However, in other embodiments of the present invention, the barrier layer 220 comprises AlGaN having an aluminum concentration between about 5% and about 100%. In certain embodiments of the present invention, the aluminum concentration is greater than about 10%.

Although exemplary embodiments of bypass-gated transistors according to embodiments of the present invention are shown with reference to GaN high electron mobility transistor (HEMT) structures, the inventive concepts are not limited to such devices. Thus, embodiments of the present invention may include other transistor devices with multiple unit cells and control electrodes. Embodiments of the present invention may be suitable for use in any semiconductor device where broader control of the electrodes is desired and where there are multiple unit cells of the device. Thus, for example, embodiments of the present invention may be suitable for use in various types of devices, such as MESFETs, MMICs, SITs, LDMOS, BJTs, pHEMTs, etc., fabricated using SiC, GaN, GaAs, silicon, etc.

In accordance with further embodiments of the inventive concepts, monolithic microwave integrated circuit (MMIC) devices are provided that can support significantly higher output power levels. Such MMIC devices may also exhibit high output power density for a given operating frequency. In certain embodiments, the MMIC devices can support the same output power levels comparable to conventional MMIC devices, but in a significantly smaller package. MMIC devices according to embodiments of the present invention may exhibit enhanced performance, provide significant cost savings, and/or have improved reliability.

MMIC devices are used in a wide variety of applications including radar, cellular communications, satellite communications, electronic warfare applications, and the like. MMIC devices are high frequency devices (i.e., devices operating in the microwave frequency range extending from about 300 MHz to about 300 GHz) and many applications in which they are used must be capable of handling high output power levels. Currently, most MMIC devices are formed in wide bandgap semiconductor material systems, such as silicon carbide, gallium arsenide, and/or gallium nitride based semiconductor material systems. MMIC devices formed in such semiconductor material systems generally operate at higher frequencies and can handle higher power density levels.

A wide variety of MMIC devices include field effect transistors (FETs), such as metal oxide semiconductor field effect transistors (MOSFETs) and high electron mobility transistors (HEMTs). For example, high power RF amplifiers, low noise RF amplifiers, RF switches, RF limiters, RF mixers, and various other circuits may comprise one or more FETs. Typically, each of the above MMIC devices will have a unit cell structure in which multiple individual FET transistor cells are connected in parallel. The unit cell structure allows the MMIC device to support higher output power levels. The actual output power levels that an MMIC device can support may be limited by several factors, including the length of "good gate area" available for fabrication of the output stage of the device, the operating frequency of the device, and the thermal environment in which the MMIC device operates.

The output power level supported by a FET-based MMIC device is based on the current carrying capability of the output stage of the MMIC device. The current carrying capability of the output stage may be directly proportional to the physical size (area) of the output stage when viewed in plan view. The "good gate area" of a FET-based MMIC device refers to the portion of the device in which the FET output stage is formed.

The good gate area of an MMIC device may be constrained because the equipment used in wafer level fabrication processes can only form fine patterns over a limited area in the device. Typically, the main constraint on the size of the good gate area is in the direction perpendicular to the direction in which the gate fingers of the FET transistors extend in each unit cell. This direction, which corresponds to the x-axis direction in Figures 16-20D below, determines how many unit cell transistors can be included in a FET output stage. (This direction is referred to herein as the "length" of the good gate area, and the y-axis direction is referred to as the "width" of the good gate area, since the width of the gate fingers refers to the distance they extend in the y-axis direction, as discussed above with reference to Figure 1.) Typically, the length of the good gate area is much shorter than the diameter of the wafer on which the MMIC devices are formed, so that a large number of individual MMIC devices can be formed on the wafer. Conventional high power MMIC devices often use the entire length of the good gate area to form the FET output stage, so to expand the good gate area requires obtaining processing equipment capable of forming fine patterns over larger areas, if such equipment is even available.

The physical size of the output stage, and therefore the output power level it can support, can also be increased by increasing the width of the gate fingers of the output stage, which acts to increase the size of the output stage in the y-axis direction. However, the width of the gate fingers may be limited because the resistance of each unit cell FET transistor is directly proportional to the width of the gate fingers of the FET transistor, and increasing resistance also increases power loss. Thus, the width of the gate fingers of the output stage may be effectively limited by power loss concerns. Resistance is also a function of the frequency of the microwave signal (increasing frequency corresponds to increasing resistance), and therefore the frequency of the microwave signal (along with other desired or required performance parameters) may effectively dictate the maximum width of the gate fingers.

The thermal operating environment of the MMIC device also influences the maximum output power level that the device can support, since it typically determines the minimum gate finger spacing required to avoid excessive mutual heating that can degrade the performance of the MMIC device. The thermal operating environment may vary depending on one or more parameters, such as the type of MMIC device, the efficiency of the device, and the mode of operation (e.g., pulsed or continuous wave operation of an MMIC amplifier). Again, these parameters are typically determined by the intended application of the MMIC device and the specific performance parameters. Thus, the maximum output power level that various MMIC devices can support may be fundamentally determined by various constraints, such as the length of the favorable gate area, the operating frequency of the device, and the thermal operating environment of the device. In many cases, MMIC devices that support higher output power levels are required, if such devices can be manufactured. As discussed in detail below, MMIC devices according to certain embodiments of the present invention may be capable of supporting significantly higher output power levels than comparable conventional MMIC devices. Exemplary embodiments of such MMIC devices will now be discussed in more detail with reference to Figures 16-20D.

FIG. 16 is a schematic diagram of a conventional wafer 600 with a number of MMIC devices formed thereon. The wafer may include, for example, a silicon carbide or sapphire wafer with a number of gallium nitride-based layers (e.g., GaN, AlGaN, etc.) and metallization layers formed thereon. As shown in FIG. 16, the wafer 600 is typically divided into a grid pattern 610, and an MMIC device 630 is formed in each "cell" 620 of the grid pattern 610 (only three MMIC devices 630 are depicted in FIG. 16 to simplify the drawing). The size of each cell 620 may be based on available processing equipment. For example, the dimensions of each cell 620 may be a square of 10 mm by 10 mm in an exemplary embodiment. In another exemplary embodiment, the dimensions of each cell 620 may be 6 mm by 6 mm. The cells 620 may have other dimensions, and the length and width need not be the same. It will also be understood that only a certain portion of the MMIC device needs to be accommodated within the cells 620. For example, in an MMIC amplifier, the FET amplification stage may be contained within cell 620, but the input and/or output impedance matching circuitry may be formed external to cell 620, since such circuitry may be formed without fine patterning.

As noted above, limitations on the size of each cell 620, particularly the length of each cell in the x-axis direction, can act to limit the maximum output power that each MMIC device 630 can support. This can be seen with reference to FIG. 17, which is a plan view of a conventional two-stage MMIC amplifier 700. The MMIC amplifier 700 shown in FIG. 17 can be an MMIC device 630 in one or more cells 620 of the wafer 600 of FIG. 16.

As shown in FIG. 17, the MMIC amplifier 700 includes a FET driver stage 710 and a FET output stage 720, which represent the two amplification stages of the two-stage MMIC amplifier 700. The MMIC amplifier 700 further includes an input impedance matching circuit 730, an inter-stage impedance matching circuit 740, and an output impedance matching circuit 750. An input pad 760 and an output pad 762 may also be provided, along with other pads 764 that provide power and ground connections to the MMIC device 700. As discussed above, the maximum output power that the MMIC amplifier 700 can support is based on the maximum current level that the FET output stage 720 can support.

An input signal in the form of a microwave signal (e.g., a 700 MHz RF signal) may be input to the MMIC amplifier 700 at input pad 760. The input RF signal passes through an input stage impedance matching circuit 730, which matches the impedance at the input of the FET driver stage 710 to the impedance seen at the input pad 760. The FET driver stage 710 amplifies the RF signal input to it to provide a higher power RF signal. The higher power RF signal output by the FET driver stage 710 may be provided (after appropriate impedance matching by the interstage impedance matching circuit 740) as an input signal to the FET output stage 720. The FET output stage 720 amplifies the RF signal input to it to further increase its power. The high power RF signal output by the FET output stage 720 passes through an output stage impedance matching circuit 750 and is output from the MMIC device 700 at output pad 762. The FET driver stage 710 may be implemented, for example, as a plurality of unit cell FET transistors 712 (e.g., HEMT transistors) electrically connected in parallel with each other. The FET output stage 720 may similarly be implemented, for example, as a plurality of unit cell FET transistors 712 (e.g., HEMT transistors) electrically connected in parallel with each other. As shown in FIG. 17, the FET output stage 720 typically includes more unit cell FET transistors 712 than the FET driver stage 710 to improve the efficiency of the MMIC amplifier 700.

The input impedance matching circuit 730 may comprise, for example, one or more capacitors, inductors, resistors, and/or other circuit elements arranged to match the impedance at the input pad 760 of the RF signal input to the MMIC amplifier 700 to the impedance seen at the input of the FET driver stage 710. Similarly, the inter-stage impedance matching circuit 740 may comprise, for example, one or more capacitors, inductors, resistors, and/or other circuit elements arranged to match the impedance of the signal output from the FET driver stage 710 to the impedance seen at the input of the FET output stage 720. The output impedance matching circuit 750 may comprise, for example, one or more capacitors, inductors, resistors, and/or other circuit elements arranged to match the impedance of the signal output from the FET output stage 720 to the impedance seen at the output pad 762 of the MMIC amplifier 700.

As discussed above, the maximum output power level supported by an MMIC amplifier, such as the two-stage MMIC amplifier 700 of FIG. 17, is a function of (1) the number of unit cell FET transistors 712 in the FET output stage 720 and (2) the power supported by each unit cell FET transistor 712 in the FET output stage 720. The number of unit cell FET transistors 712 in the FET output stage 720 may be determined by (1) the "length" of the good gate area (which is the length of the MMIC device 700 in the x-axis direction of FIG. 17) and (2) the spacing between the gate fingers of adjacent unit cell FET transistors 712. As discussed above, the length of the good gate area is set by the size of the cell 620 (see FIG. 16), which may be a function of the processing equipment, and the minimum spacing of the gate fingers may be set based on thermal considerations, which may be a function of the amplifier design criteria. As a result, the number of unit cell FET transistors 712 in the FET output stage 720 cannot be easily increased beyond the limits set by the size of the cells 620 and the amplifier design criteria.

The power supported by each unit cell FET transistor 712 of the FET output stage 720 is a function of the gate finger width (i.e., the distance the gate finger extends in the y-axis direction), with larger gate finger widths supporting increased output power levels. The length of each gate finger (i.e., the distance the gate finger extends in the x-axis direction) is typically made very short to allow each unit cell FET transistor 712 to switch at high frequencies. As a result, as the gate finger width increases, the resistance of each gate finger also increases, resulting in increased power loss. At various microwave frequencies (e.g., 3 GHz), power loss concerns may limit the gate finger width to, for example, about 500 microns. Thus, in a particular MMIC amplifier design, the above physical constraints and considerations may impose practical limits on the maximum output power supported by the device.

As described above with reference to Figures 2-15, multi-cell FET transistors having increased gate widths can be provided in accordance with embodiments of the present invention. As described above, segmented gate fingers and/or gate jumpers can be used to achieve the larger gate widths. Such multi-cell transistors can be used in place of conventional multi-cell transistors in MMIC devices, such as the two-stage MMIC amplifier described above, to increase their maximum possible output power.

For example, Figures 18A and 18B are schematic plan views of the conventional two-stage MMIC amplifier 700 of Figure 17 and an MMIC amplifier 800 with a FET driver stage and a FET output stage, each implemented using unit cell FET transistors with segmented gate fingers and/or gate jumpers. Figures 18A and 18B are drawn to the same relative scale to allow visual comparison of the sizes of the various regions of each MMIC amplifier, and the overall size of each MMIC amplifier.

As described above, as shown generally in FIG. 18A, a conventional MMIC amplifier 700 includes a FET amplifier stage 710 and a FET output stage 720, each of which includes a unit cell FET transistor 712 having a gate finger width of 500 microns. The FET driver stage 710 and the FET output stage 720 occupy a relatively small device area, such as perhaps 20% to 30%. As shown in FIG. 18B, an MMIC amplifier 800 according to an embodiment of the present invention may include a FET driver stage 810, a FET output stage 820, an input impedance matching circuit 830, an interstage impedance matching circuit 840, and an output impedance matching circuit 850. The FET driver stage 810 and the FET output stage 820 each include a unit cell FET transistor 812 with segmented gate fingers and/or gate jumpers according to an embodiment of the present invention. In the illustrated MMIC amplifier 800, each unit cell FET transistor 812 has a gate finger with three 250 micron gate finger segments. In other embodiments, gate finger segments with larger widths (e.g., 400 microns each) can be used. Because the unit cell FET transistors 812 have gate fingers with 50% larger gate widths than the unit cell FET transistors 712 of the conventional MMIC amplifier 700, the maximum output power that can be supported by the MMIC amplifier 800 can be approximately 50% greater than the maximum output power that can be supported by the conventional MMIC amplifier 700. Thus, MMIC amplifiers (and other MMIC devices) according to embodiments of the present invention can support power levels that could not be achieved using conventional techniques.

Furthermore, as can be seen from FIGS. 18A and 18B, MMIC amplifiers and other devices according to embodiments of the present invention can achieve these enhanced output power levels without a proportional increase in device size. In particular, while the size of the impedance matching circuitry typically increases with increasing output power levels, this increase need not be proportional to the corresponding increase in maximum output power level. Thus, as can be seen from the schematic diagrams of FIGS. 18A and 18B, an MMIC amplifier 800 according to embodiments of the present invention that supports a 50% higher output power level may, for example, be only perhaps 20% larger in area.

19A and 19B provide another comparison showing how MMIC devices according to embodiments of the present invention can provide improved performance compared to conventional MMIC devices while having a smaller physical footprint. Specifically, FIG. 19A is a schematic diagram of the conventional two-stage MMIC amplifier 700 of FIG. 18A. FIG. 19B is a schematic diagram of a two-stage MMIC amplifier 900 according to embodiments of the present invention, which occupies a smaller area while supporting higher output power levels than MMIC device 700. FIGS. 19A and 19B are drawn to the same relative scale to allow visual comparison of the sizes of various regions of each MMIC amplifier, as well as the overall size of each MMIC amplifier.

19B, the MMIC amplifier 900 includes a FET driver stage 910 and a FET output stage 920, each of which includes a unit cell FET transistor 912 with segmented gate fingers and/or gate jumpers according to an embodiment of the present invention. The MMIC amplifier 900 further includes an input impedance matching circuit 930, an interstage impedance matching circuit 940, and an output impedance matching circuit 950. In the MMIC amplifier 900, each unit cell FET transistor 912 includes a gate finger with three 250 micron gate finger segments, which is 50% larger than the width of the gate fingers of the unit cell FET transistor 712 of the conventional MMIC amplifier 700. However, the MMIC amplifier 900 extends in the x-direction about 25% less than the MMIC amplifier 700. Therefore, the maximum output power that the MMIC amplifier 900 can support can be approximately 25% greater than the maximum output power that the conventional MMIC amplifier 700 can support, and this output power is achieved with an MMIC amplifier that is approximately 25% smaller than the MMIC amplifier 700.

The improved performance shown by the MMIC amplifier 900 of FIG. 19B can be achieved by forming the FET driver stage 910 and the FET output stage 920 using unit cell FET transistors 912 with segmented (or "bypassed") gate fingers and/or gate jumpers. The use of such bypass-gated FET transistors increases the size of each unit cell 912, which can increase the output power per unit cell by, for example, 50%. Thus, as shown in FIGS. 19A and 19B, the MMIC amplifier 900 can be smaller than the MMIC amplifier 700 and still support higher output current and output power levels. The MMIC amplifier 900 can support higher output power levels despite the smaller size of the MMIC amplifier 900, because the physical area of the FET output stage 920 can be larger than the physical area of the FET output stage 720 of the MMIC amplifier 700 due to the longer gate width of the FET transistors 912 included in the FET output stage 920 of the MMIC amplifier 900.

The cost of an MMIC device may be directly proportional to the size of the device, since much of the processing of the MMIC device is done at the wafer level, and the more MMIC devices contained on a wafer, the lower the cost of each MMIC device. As a result, MMIC devices according to embodiments of the present invention may have significant cost advantages compared to conventional MMIC devices while providing comparable or even improved performance. Smaller device size (for a given supported output power level) may also be advantageous in terms of system integration in various applications, such as phased array radar systems and large MIMO beamforming antenna arrays, where a large number of MMIC devices are used in a device with a relatively small system footprint. This will become increasingly true as more applications move to higher microwave frequencies, such as the 28 GHz and 80 GHz bands, where each individual radiating element becomes very small.

It will be appreciated that FET transistors according to embodiments of the present invention with increased gate finger widths can be used in a wide variety of MMIC devices, not just two-stage MMIC amplifiers. For example, FIGS. 20A-20D show several exemplary MMIC devices according to further embodiments of the present invention. As shown in FIG. 20A, a single-stage MMIC amplifier 1000 can be provided using multi-cell FET transistors according to embodiments of the present invention with segmented gate fingers and/or gate jumpers. The exemplary single-stage MMIC amplifier 1000 shown in FIG. 20A includes an input impedance matching stage 1030, a FET amplification/output stage 1020 with bypass-gated transistors according to embodiments of the present invention, and an output impedance matching stage 1050.

As shown in FIG. 20B, an MMIC amplifier with three or more stages can also be provided. Specifically, the MMIC amplifier 1100 of FIG. 20B includes a total of four amplifier stages, namely, first to third FET driver stages 1110, 1114, 1116, and a FET output stage 1120. The MMIC amplifier 1100 further includes an input impedance matching circuit 1130, an output impedance matching circuit 1150, and first to third interstage impedance matching circuits 1140, 1142, 1144. It will be appreciated that in other embodiments (not shown), a three-stage MMIC amplifier or an MMIC amplifier with five or more amplifier stages can be provided. One or more of the first to third FET driver stages 1110, 1114, 1116, and the FET output stage 1120 can include bypass-gated transistors according to embodiments of the present invention.

It will also be appreciated that not all of the FET transistors included in an MMIC device according to an embodiment of the present invention need to use the bypass-gated transistor design disclosed herein. For example, FIG. 20C is a schematic plan view of an MMIC amplifier 1200 according to an embodiment of the present invention, including a FET output stage 1220 formed using a bypass-gated unit cell FET transistor 1222 according to an embodiment of the present invention, and a FET driver stage 1210 formed using a conventional FET transistor 1212. The conventional FET transistor 1212 can be used in the FET driver stage 1210 because a good gate length is sufficient to allow for an adequate number of conventional unit cell FET transistors 1212. The MMIC amplifier 1200 further includes an input impedance matching circuit 1230, an interstage impedance matching circuit 1240, and an output impedance matching circuit 1250.

In yet another embodiment, as shown in FIG. 20D, an MMIC switch 1300 may be provided that exhibits improved power handling capability for a given operating frequency or has a reduced physical size compared to conventional RF switches. The MMIC switch 1300 may, for example, include an RF input 1302, multiple RF outputs 1304, and a control input 1306. The MMIC switch 1300 may include multiple individual RF switches 1310. Some or all of the RF switches 1310 may be implemented using bypass gated transistors according to embodiments of the present invention. The MMIC switch 1300 may be used, for example, in an RF switching network of a phased array antenna.

As discussed above, the maximum output power supported by state of the art MMIC amplifiers is constrained due to the limited available good gate area and gate width limitations based on loop stability and power loss considerations. MMIC amplifiers according to embodiments of the present invention can achieve, for example, a three-fold increase in maximum power density for amplifiers operating at frequencies up to 6 GHz, and a two-fold increase in maximum power density for amplifiers operating at frequencies between 6 and 15 GHz. FET-based MMIC devices according to embodiments of the present invention can implement the FET transistors they comprise using any of the bypass-gated transistor designs disclosed herein. For example, each of the FET-based MMIC devices according to embodiments of the present invention disclosed herein can use any of the bypass-gated transistors discussed above, with reference to Figures 2-7, 8-9B, 10-11, 12, 13, 14, and/or 15, along with the respective modifications to the embodiments discussed above.

Although terms such as first, second, etc. may be used herein to describe various elements, it will be understood that such elements should not be limited by such terms. Such terms are used only to distinguish one element from another. For example, a first element can be referred to as a second element, and similarly, a second element can be referred to as a first element, without departing from the scope of the present invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and/or "including" as used herein specify the presence of stated features, wholes, steps, operations, elements, and/or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which this invention belongs. Furthermore, it will be understood that terms used herein should be interpreted to have a meaning consistent with their meaning in the context of this specification and related art, and should not be interpreted in an idealized or overly formal sense unless expressly defined as such in this specification.

When an element, such as a layer, region, or substrate, is said to be "on" or extend "upon" another element, it will be understood that the element can be directly on or extend directly onto the other element, or intervening elements may also be present. In contrast, when an element is said to be "directly on" or extend "directly onto" another element, there are no intervening elements. When an element is said to be "connected" or "coupled" to another element, it will also be understood that the element can be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is said to be "directly connected" or "directly coupled" to another element, there are no intervening elements.

Relative terms such as "below," "above," "upper," "lower," "horizontal," "lateral," or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region shown in the figures. It will be understood that these terms are intended to encompass various orientations of the device in addition to the orientation depicted in the figures.

Embodiments of the present invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention. The thicknesses of layers and regions in the drawings may be exaggerated for clarity. Additionally, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein but should include, for example, variations in shapes that result from manufacturing.

In the drawings and specification, exemplary embodiments of the invention have been disclosed and, although specific terms have been employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being indicated in the following claims.

Claims (10)

a plurality of gate fingers extending in a first direction and spaced apart from one another in a second direction perpendicular to the first direction;
Gate Bus and
a first resistor interposed between the gate bus and a first segment of a first gate finger of the plurality of gate fingers;
a second resistor interposed between the gate bus and a second segment of the first gate finger;
A transistor comprising: The transistor of claim 1, further comprising a gate jumper electrically connecting the gate bus to the second segment of the first gate finger. The transistor of claim 2, wherein the second resistor is interposed between the gate bus and the gate jumper. 4. A transistor as claimed in claim 2 or 3, further comprising a source contact, said gate jumper extending over said source contact. 4. The transistor of claim 1, wherein the first and second segments of the first gate finger are separated from each other in the first direction by a gap region. 3. The transistor of claim 2 further comprising a gate signal distribution bar extending between said gate jumper and said second segment of said first gate finger. The transistor of claim 6, wherein the gate signal distribution bar extends in the second direction. The transistor of claim 6, wherein the second resistor is interposed along the gate signal distribution bar. The transistor of claim 1, wherein the second resistor is disposed adjacent to a first end of the second segment of the first gate finger. The transistor of claim 2, wherein the first resistor is also interposed between the gate bus and a first segment of a second gate finger in the plurality of gate fingers.