JP7528217B2 - Ｇｐｕパケット集約システム - Google Patents

Ｇｐｕパケット集約システム Download PDF

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Publication number
JP7528217B2
JP7528217B2 JP2022534186A JP2022534186A JP7528217B2 JP 7528217 B2 JP7528217 B2 JP 7528217B2 JP 2022534186 A JP2022534186 A JP 2022534186A JP 2022534186 A JP2022534186 A JP 2022534186A JP 7528217 B2 JP7528217 B2 JP 7528217B2
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Prior art keywords
packet
input
output
gpu
response
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JP2022534186A
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Japanese (ja)
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JP2023505783A (ja
JP2023505783A5 (enExample
Inventor
マーティン トッド
リトウィラー タッド
パータク ニシャンク
ピー． ニジャシャー マンゲッシュ
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17337—Direct connection machines, e.g. completely connected computers, point to point communication networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H04L47/62—Queue scheduling characterised by scheduling criteria
    • H04L47/625—Queue scheduling characterised by scheduling criteria for service slots or service orders
    • H04L47/6255—Queue scheduling characterised by scheduling criteria for service slots or service orders queue load conditions, e.g. longest queue first
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9057—Arrangements for supporting packet reassembly or resequencing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2200/00—Indexing scheme for image data processing or generation, in general
    • G06T2200/28—Indexing scheme for image data processing or generation, in general involving image processing hardware
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2212/00—Encapsulation of packets

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
JP2022534186A 2019-12-13 2020-12-09 Ｇｐｕパケット集約システム Active JP7528217B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16/713,472 2019-12-13
US16/713,472 US11210757B2 (en) 2019-12-13 2019-12-13 GPU packet aggregation system
PCT/US2020/063923 WO2021119072A1 (en) 2019-12-13 2020-12-09 Gpu packet aggregation system

Publications (3)

Publication Number Publication Date
JP2023505783A JP2023505783A (ja) 2023-02-13
JP2023505783A5 JP2023505783A5 (enExample) 2023-11-28
JP7528217B2 true JP7528217B2 (ja) 2024-08-05

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Family Applications (1)

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JP2022534186A Active JP7528217B2 (ja) 2019-12-13 2020-12-09 Ｇｐｕパケット集約システム

Country Status (6)

Country Link
US (1) US11210757B2 (enExample)
EP (1) EP4073639B1 (enExample)
JP (1) JP7528217B2 (enExample)
KR (1) KR102709341B1 (enExample)
CN (1) CN114902181A (enExample)
WO (1) WO2021119072A1 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12106112B2 (en) * 2020-12-03 2024-10-01 Intel Corporation Methods and apparatus to generate graphics processing unit long instruction traces
CN113626369B (zh) * 2021-08-14 2023-05-26 苏州浪潮智能科技有限公司 一种多节点集群环形通信的方法、装置、设备及可读介质
US20260121987A1 (en) * 2024-10-29 2026-04-30 Avago Technologies International Sales Pte. Limited Systems and methods for managing packet data with variable metadata size

Citations (3)

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JP2010055214A (ja) 2008-08-26 2010-03-11 Sanyo Electric Co Ltd データ処理装置
JP2015502618A (ja) 2011-12-14 2015-01-22 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドＡｄｖａｎｃｅｄ Ｍｉｃｒｏ Ｄｅｖｉｃｅｓ Ｉｎｃｏｒｐｏｒａｔｅｄ シェーダコアにおけるシェーダリソース割当てのポリシー
US20160283416A1 (en) 2015-03-23 2016-09-29 Samsung Electronics Co., Ltd. Bus interface device, semiconductor integrated circuit device including the same, and method of operating the same

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US7433409B2 (en) * 2000-07-10 2008-10-07 Matsushita Electric Industrial Co., Ltd. Apparatus and method of multiple decoding
WO2005053216A2 (en) * 2003-11-25 2005-06-09 Dg2L Technologies Methods and systems for reliable distribution of media over a network
US7209139B1 (en) * 2005-01-07 2007-04-24 Electronic Arts Efficient rendering of similar objects in a three-dimensional graphics engine
US7839876B1 (en) 2006-01-25 2010-11-23 Marvell International Ltd. Packet aggregation
CN101471826B (zh) * 2007-12-27 2012-12-12 华为技术有限公司 命令行接口的测试方法及装置
US8374986B2 (en) 2008-05-15 2013-02-12 Exegy Incorporated Method and system for accelerated stream processing
JP2013541748A (ja) * 2010-07-19 2013-11-14 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 多重処理ユニット内のオンチップメモリを用いるデータ処理
CN102323917B (zh) * 2011-09-06 2013-05-15 中国人民解放军国防科学技术大学 一种基于共享内存实现多进程共享gpu的方法
US20130162661A1 (en) * 2011-12-21 2013-06-27 Nvidia Corporation System and method for long running compute using buffers as timeslices
US9509616B1 (en) * 2014-11-24 2016-11-29 Amazon Technologies, Inc. Congestion sensitive path-balancing
US9830731B2 (en) 2015-04-01 2017-11-28 Mediatek Inc. Methods of a graphics-processing unit for tile-based rendering of a display area and graphics-processing apparatus
US10320695B2 (en) 2015-05-29 2019-06-11 Advanced Micro Devices, Inc. Message aggregation, combining and compression for efficient data communications in GPU-based clusters
US20170300361A1 (en) * 2016-04-15 2017-10-19 Intel Corporation Employing out of order queues for better gpu utilization
JP7100624B2 (ja) * 2016-08-29 2022-07-13 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 優先プリミティブバッチのビニング及びソートを用いたハイブリッドレンダリング
US10572258B2 (en) * 2017-04-01 2020-02-25 Intel Corporation Transitionary pre-emption for virtual reality related contexts
CN110223216B (zh) * 2019-06-11 2023-01-17 西安芯瞳半导体技术有限公司 一种基于并行plb的数据处理方法、装置及计算机存储介质
CN110415161B (zh) * 2019-07-19 2023-06-27 龙芯中科(合肥)技术有限公司 图形处理方法、装置、设备及存储介质

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010055214A (ja) 2008-08-26 2010-03-11 Sanyo Electric Co Ltd データ処理装置
JP2015502618A (ja) 2011-12-14 2015-01-22 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドＡｄｖａｎｃｅｄ Ｍｉｃｒｏ Ｄｅｖｉｃｅｓ Ｉｎｃｏｒｐｏｒａｔｅｄ シェーダコアにおけるシェーダリソース割当てのポリシー
US20160283416A1 (en) 2015-03-23 2016-09-29 Samsung Electronics Co., Ltd. Bus interface device, semiconductor integrated circuit device including the same, and method of operating the same

Also Published As

Publication number Publication date
WO2021119072A1 (en) 2021-06-17
EP4073639B1 (en) 2026-03-04
KR102709341B1 (ko) 2024-09-25
CN114902181A (zh) 2022-08-12
US20210183004A1 (en) 2021-06-17
KR20220113710A (ko) 2022-08-16
JP2023505783A (ja) 2023-02-13
EP4073639A4 (en) 2024-01-10
US11210757B2 (en) 2021-12-28
EP4073639A1 (en) 2022-10-19

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