JP7525624B2 - グラフィックス処理ユニットのためのクロック制御スキーム - Google Patents

グラフィックス処理ユニットのためのクロック制御スキーム Download PDF

Info

Publication number
JP7525624B2
JP7525624B2 JP2022550173A JP2022550173A JP7525624B2 JP 7525624 B2 JP7525624 B2 JP 7525624B2 JP 2022550173 A JP2022550173 A JP 2022550173A JP 2022550173 A JP2022550173 A JP 2022550173A JP 7525624 B2 JP7525624 B2 JP 7525624B2
Authority
JP
Japan
Prior art keywords
frequency
clock signal
gpu
engine modules
counter data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2022550173A
Other languages
English (en)
Japanese (ja)
Other versions
JP2023516574A (ja
JP2023516574A5 (https=
Inventor
クマール サジャ ランジート
ゴーディ スリーカント
アール. アチャリャ アニルーダ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of JP2023516574A publication Critical patent/JP2023516574A/ja
Publication of JP2023516574A5 publication Critical patent/JP2023516574A5/ja
Priority to JP2024114543A priority Critical patent/JP7793690B2/ja
Application granted granted Critical
Publication of JP7525624B2 publication Critical patent/JP7525624B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08Clock generators with changeable or programmable clock frequency
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10Distribution of clock signals, e.g. skew
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12Synchronisation of different clock signals provided by a plurality of clock generators
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16Constructional details or arrangements
    • G06F1/20Cooling means
    • G06F1/206Cooling means comprising thermal management
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3228Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234Power saving characterised by the action undertaken
    • G06F1/324Power saving characterised by the action undertaken by lowering clock frequency
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234Power saving characterised by the action undertaken
    • G06F1/3243Power saving in microcontroller unit
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/34Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3409Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/34Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3409Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
    • G06F11/3433Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment for load management
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/34Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466Performance evaluation by tracing or monitoring
    • G06F11/348Circuit details, i.e. tracer hardware
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/50Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G06F9/505Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the load
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/88Monitoring involving counting
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Software Systems (AREA)
  • Human Computer Interaction (AREA)
  • Power Sources (AREA)
  • Executing Machine-Instructions (AREA)
JP2022550173A 2020-03-06 2021-03-05 グラフィックス処理ユニットのためのクロック制御スキーム Active JP7525624B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2024114543A JP7793690B2 (ja) 2020-03-06 2024-07-18 グラフィックス処理ユニットのためのクロック制御スキーム

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US202062985985P 2020-03-06 2020-03-06
US62/985,985 2020-03-06
US202063050527P 2020-07-10 2020-07-10
US63/050,527 2020-07-10
US17/032,701 2020-09-25
US17/032,701 US11442495B2 (en) 2020-03-06 2020-09-25 Separate clocking for components of a graphics processing unit
PCT/US2021/021046 WO2021178775A1 (en) 2020-03-06 2021-03-05 Clock control schemes for a graphics processing unit

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2024114543A Division JP7793690B2 (ja) 2020-03-06 2024-07-18 グラフィックス処理ユニットのためのクロック制御スキーム

Publications (3)

Publication Number Publication Date
JP2023516574A JP2023516574A (ja) 2023-04-20
JP2023516574A5 JP2023516574A5 (https=) 2024-02-26
JP7525624B2 true JP7525624B2 (ja) 2024-07-30

Family

ID=77554792

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2022550173A Active JP7525624B2 (ja) 2020-03-06 2021-03-05 グラフィックス処理ユニットのためのクロック制御スキーム
JP2024114543A Active JP7793690B2 (ja) 2020-03-06 2024-07-18 グラフィックス処理ユニットのためのクロック制御スキーム

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2024114543A Active JP7793690B2 (ja) 2020-03-06 2024-07-18 グラフィックス処理ユニットのためのクロック制御スキーム

Country Status (6)

Country Link
US (3) US11442495B2 (https=)
EP (1) EP4115262A4 (https=)
JP (2) JP7525624B2 (https=)
KR (1) KR102686452B1 (https=)
CN (1) CN115427912A (https=)
WO (1) WO2021178775A1 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11442495B2 (en) * 2020-03-06 2022-09-13 Advanced Micro Devices, Inc. Separate clocking for components of a graphics processing unit
KR20220064105A (ko) * 2020-11-11 2022-05-18 삼성전자주식회사 반도체 장치
US20250370949A1 (en) * 2024-05-30 2025-12-04 Xilinx, Inc. Decoupling processing and interface clocks in an ipu

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013542492A (ja) 2010-09-14 2013-11-21 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 処理ノードにおける電力消費を制御するための機構
US20140089699A1 (en) 2012-09-27 2014-03-27 Advanced Micro Devices Power management system and method for a processor
US20140184619A1 (en) 2013-01-03 2014-07-03 Samsung Electronics Co., Ltd. System-on-chip performing dynamic voltage and frequency scaling
US20170011550A1 (en) 2015-07-06 2017-01-12 Mediatek Inc. Apparatus for performing tessellation operation and methods utilizing the same
US20170199542A1 (en) 2016-01-11 2017-07-13 Qualcomm Incorporated Energy aware dynamic adjustment algorithm
US20180210530A1 (en) 2017-01-26 2018-07-26 Ati Technologies Ulc Adaptive power control loop
JP2019510319A (ja) 2016-03-28 2019-04-11 クゥアルコム・インコーポレイテッドQualcomm Incorporated プロセッサ周波数およびバス帯域幅のアクティブおよびストールサイクルベースの動的スケーリング
US20190129463A1 (en) 2017-10-26 2019-05-02 Advanced Micro Devices, Inc. Fine-grained speed binning in an accelerated processing device

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6919908B2 (en) * 2003-08-06 2005-07-19 Ati Technologies, Inc. Method and apparatus for graphics processing in a handheld device
US7539893B1 (en) * 2005-09-16 2009-05-26 Pmc-Sierra, Inc. Systems and methods for speed binning of integrated circuits
US7739533B2 (en) * 2006-09-22 2010-06-15 Agere Systems Inc. Systems and methods for operational power management
WO2008066548A1 (en) * 2006-11-29 2008-06-05 Agere Systems Inc. Speed binning for dynamic and adaptive power control
US9142057B2 (en) * 2009-09-03 2015-09-22 Advanced Micro Devices, Inc. Processing unit with a plurality of shader engines
US8566836B2 (en) * 2009-11-13 2013-10-22 Freescale Semiconductor, Inc. Multi-core system on chip
KR101723127B1 (ko) 2010-07-13 2017-04-04 어드밴스드 마이크로 디바이시즈, 인코포레이티드 그래픽 프로세서 내의 simd 유닛들의 동적 인에이블링 및 디스에이블링
US8736619B2 (en) * 2010-07-20 2014-05-27 Advanced Micro Devices, Inc. Method and system for load optimization for power
US8842122B2 (en) * 2011-12-15 2014-09-23 Qualcomm Incorporated Graphics processing unit with command processor
US9285858B2 (en) * 2013-01-29 2016-03-15 Blackberry Limited Methods for monitoring and adjusting performance of a mobile computing device
KR20140128118A (ko) * 2013-04-26 2014-11-05 삼성전자주식회사 애플리케이션 프로세서 및 이의 동적 온도 관리 방법
EP3058552A4 (en) * 2013-10-14 2017-05-17 Marvell World Trade Ltd. Systems and methods for graphics process units power management
US9395796B2 (en) * 2013-12-19 2016-07-19 Intel Corporation Dynamic graphics geometry preprocessing frequency scaling and prediction of performance gain
US9678556B2 (en) * 2014-02-10 2017-06-13 Qualcomm Incorporated Dynamic clock and voltage scaling with low-latency switching
US9933845B2 (en) * 2014-11-24 2018-04-03 Intel Corporation Apparatus and method to provide multiple domain clock frequencies in a processor
US9836869B2 (en) 2015-04-01 2017-12-05 Mediatek Inc. Graphics-processing method of a graphics-processing unit and graphics-processing apparatus
US9904612B2 (en) * 2015-07-08 2018-02-27 Futurewei Technologies, Inc. Dynamic voltage/frequency scaling for multi-processors using end user experience metrics
US10013392B2 (en) * 2016-01-26 2018-07-03 Intel Corporation Providing access from outside a multicore processor SoC to individually configure voltages
CN107194891B (zh) * 2017-05-18 2020-11-10 上海兆芯集成电路有限公司 改善图像质量的方法及虚拟实境装置
US10606305B2 (en) 2018-04-30 2020-03-31 Qualcomm Incorporated Processor load step balancing
US11611366B2 (en) * 2019-05-28 2023-03-21 Man & Machine Method and apparatus to thermally optimize a protective case for temperature regulation and heat transfer to or from a mobile device
US11442495B2 (en) * 2020-03-06 2022-09-13 Advanced Micro Devices, Inc. Separate clocking for components of a graphics processing unit

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013542492A (ja) 2010-09-14 2013-11-21 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 処理ノードにおける電力消費を制御するための機構
US20140089699A1 (en) 2012-09-27 2014-03-27 Advanced Micro Devices Power management system and method for a processor
US20140184619A1 (en) 2013-01-03 2014-07-03 Samsung Electronics Co., Ltd. System-on-chip performing dynamic voltage and frequency scaling
US20170011550A1 (en) 2015-07-06 2017-01-12 Mediatek Inc. Apparatus for performing tessellation operation and methods utilizing the same
US20170199542A1 (en) 2016-01-11 2017-07-13 Qualcomm Incorporated Energy aware dynamic adjustment algorithm
JP2019510319A (ja) 2016-03-28 2019-04-11 クゥアルコム・インコーポレイテッドQualcomm Incorporated プロセッサ周波数およびバス帯域幅のアクティブおよびストールサイクルベースの動的スケーリング
US20180210530A1 (en) 2017-01-26 2018-07-26 Ati Technologies Ulc Adaptive power control loop
US20190129463A1 (en) 2017-10-26 2019-05-02 Advanced Micro Devices, Inc. Fine-grained speed binning in an accelerated processing device

Also Published As

Publication number Publication date
WO2021178775A1 (en) 2021-09-10
EP4115262A1 (en) 2023-01-11
US20210278873A1 (en) 2021-09-09
US20240345617A1 (en) 2024-10-17
CN115427912A (zh) 2022-12-02
JP2023516574A (ja) 2023-04-20
KR102686452B1 (ko) 2024-07-22
US11442495B2 (en) 2022-09-13
US11947380B2 (en) 2024-04-02
EP4115262A4 (en) 2024-03-27
JP2024138525A (ja) 2024-10-08
JP7793690B2 (ja) 2026-01-05
US20230096002A1 (en) 2023-03-30
US12498752B2 (en) 2025-12-16
KR20220147096A (ko) 2022-11-02

Similar Documents

Publication Publication Date Title
JP7793690B2 (ja) グラフィックス処理ユニットのためのクロック制御スキーム
WO2014099741A1 (en) Idle phase prediction for integrated circuits
US20220084276A1 (en) Texture Filtering with Dynamic Scheduling in Computer Graphics
JP2009053989A (ja) 半導体回路設計方法
JP3722351B2 (ja) 高位合成方法およびその実施に使用される記録媒体
US8933734B2 (en) Hierarchical global clock tree
US11061429B2 (en) Fine-grained speed binning in an accelerated processing device
KR20160049496A (ko) 저전력 모드 지원 컴퓨터 시스템 및 그것의 방법
JP5630870B2 (ja) 半導体集積回路のレイアウト方法及びプログラム
US9563227B2 (en) Approach to clock frequency modulation of a fixed frequency clock source
TW201448470A (zh) 固定頻率時脈來源之時脈頻率調變的方法
KR101993916B1 (ko) 프로세서 코어 동작들 조절
US8305124B2 (en) Reset signal distribution
JP2019113984A (ja) 計算制御プログラム、計算制御方法及び画像形成装置
KR102063557B1 (ko) 시간할당 알고리즘 기반의 인터폴레이션 필터
JP2017199091A (ja) 情報処理装置、情報処理方法およびプログラム
JP7806459B2 (ja) 制御プログラム、情報処理装置および制御方法
JP2012181824A (ja) 再構成デバイス、処理割当て方法及びプログラム
JPWO2018167940A1 (ja) 情報処理装置、情報処理方法及び情報処理プログラム
Melikyan Design of High-performance Heterogeneous Integrated Circuits
JP2013131070A (ja) 回路設計支援装置、回路設計支援方法、及び回路設計支援プログラム

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20221024

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20240215

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20240215

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20240215

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20240305

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20240527

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20240618

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20240718

R150 Certificate of patent or registration of utility model

Ref document number: 7525624

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150