JP7516605B2 - Manufacturing method for multilayer ceramic electronic components - Google Patents

Description

The present invention relates to a method for manufacturing multilayer ceramic electronic components.

In recent years, with the miniaturization and high performance of electronic devices, there has been an increasing demand for miniaturization and high capacitance of multilayer ceramic capacitors used in electronic devices. In order to meet this demand, attempts have been made to make the margins around the internal electrodes in the ceramic body thinner and to increase the crossing area of the internal electrodes and the number of layers.
For example, Patent Document 1 describes a multilayer ceramic capacitor in which the average thickness of the side margin portion is 18 μm or less.

JP 2014-204114 A

However, as the thickness of the margins of multilayer ceramic electronic components becomes thinner, the mechanical strength against external forces decreases, and there is a problem in that reliability cannot be sufficiently ensured.

In view of the above circumstances, the object of the present invention is to provide a method for manufacturing small, highly reliable multilayer ceramic electronic components.

In order to achieve the above object, a multilayer ceramic electronic component according to one aspect of the present invention includes a capacitance forming portion and a peripheral portion.
The capacitance forming portion has a plurality of internal electrodes laminated in a first direction with ceramic layers interposed therebetween.
The peripheral portion has a cover portion, a side margin portion, and a grain growth region, is provided around the capacitance forming portion, and is made of insulating ceramics.
The cover portion is provided outwardly of the capacitance generating portion in the first direction.
The side margin portion is provided outward in a second direction perpendicular to the first direction of the capacitance generating portion.
The grain growth region is formed in the boundary between the cover portion and the side margin portion, and has an average grain size of the insulating ceramic crystal grains larger than that of the central portion of the side margin portion.

The laminated ceramic electronic component has a grain growth region in which the average grain size of the ceramic crystal grains is large at the boundary between the cover portion and the side margin portion, so that the number of grain boundaries that can be the starting point of cracks can be reduced in that region. This makes it possible to suppress the occurrence and progression of cracks at the boundary between the cover portion and the side margin portion when an external force is applied to the laminated ceramic electronic component. Therefore, even when the peripheral portion is configured to be thin, the mechanical strength of the laminated ceramic electronic component against external forces can be increased, and a compact and highly reliable laminated ceramic electronic component can be provided.

Specifically, the average grain size of the crystal grains of the insulating ceramic in the grain growth region may be 300 nm or more.
This makes it possible to sufficiently increase the mechanical strength of the multilayer ceramic electronic component against external forces.

The peripheral portion may be configured to be very thin, and for example, the thickness dimension of the side margin portion in the second direction may be 20 μm or less.
The cover portion may have a thickness dimension in the first direction of 20 μm or less.
Even when the peripheral portion is thinned in this manner, sufficient mechanical strength against external forces can be ensured.

Furthermore, the grain growth region may have a larger average grain size of the crystal grains of the insulating ceramic than the central portion of the cover portion.
This makes it possible to further increase the mechanical strength of the multilayer ceramic electronic component against external forces.

The internal electrodes may have ends aligned in a second direction perpendicular to the first direction so as to be aligned to within a range of 0.5 μm in the second direction.
This makes it possible to increase the area over which the internal electrodes intersect within the multilayer ceramic electronic component, thereby providing a multilayer ceramic electronic component that is small in size yet has high performance.

As described above, the present invention can provide a small, highly reliable multilayer ceramic electronic component.

1 is a perspective view of a multilayer ceramic capacitor in accordance with a first embodiment of the present invention; 2 is a cross-sectional view of the multilayer ceramic capacitor taken along line A-A' in FIG. 1. 2 is a cross-sectional view of the multilayer ceramic capacitor taken along line B-B' in FIG. 1. 4 is an enlarged view showing a region IV of the multilayer ceramic capacitor shown in FIG. 3. 4 is a flowchart showing a method for manufacturing the multilayer ceramic capacitor. 3A to 3C are perspective views showing a manufacturing process of the multilayer ceramic capacitor. 3A to 3C are perspective views showing a manufacturing process of the multilayer ceramic capacitor. 3A to 3C are cross-sectional views showing a manufacturing process of the multilayer ceramic capacitor. 3A to 3C are cross-sectional views showing a manufacturing process of the multilayer ceramic capacitor. 3A to 3C are cross-sectional views showing a manufacturing process of the multilayer ceramic capacitor. FIG. 4 is a cross-sectional view of a multilayer ceramic capacitor according to a second embodiment of the present invention. 12 is an enlarged view showing region XII of the multilayer ceramic capacitor shown in FIG. 11. 3A to 3C are perspective views showing a manufacturing process of the multilayer ceramic capacitor.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
In the drawings, an X-axis, a Y-axis, and a Z-axis that are mutually orthogonal are shown as appropriate. The X-axis, the Y-axis, and the Z-axis are common to all the drawings.

First Embodiment
[Basic Configuration of Multilayer Ceramic Capacitor 10]
1 to 3 are diagrams showing a multilayer ceramic capacitor 10 according to a first embodiment of the present invention. Fig. 1 is a perspective view of the multilayer ceramic capacitor 10. Fig. 2 is a cross-sectional view of the multilayer ceramic capacitor 10 taken along line AA' in Fig. 1. Fig. 3 is a cross-sectional view of the multilayer ceramic capacitor 10 taken along line BB' in Fig. 1.

The multilayer ceramic capacitor 10 comprises a ceramic body 11, a first external electrode 14, and a second external electrode 15.

The ceramic body 11 has, for example, two end faces 11a facing the X-axis direction and a peripheral surface 11e connected to the end faces 11a. The peripheral surface 11e includes two side faces 11b facing the Y-axis direction, two main faces 11c facing the Z-axis direction, and a curved surface 11d connecting the side faces 11b and the main faces 11c. The end faces 11a, the side faces 11b, and the main faces 11c are all configured as substantially flat surfaces. The ridges connecting the end faces 11a and the peripheral surface 11e may be configured as curved surfaces, similar to the curved surfaces 11d. The ceramic body 11 is not limited to a rectangular parallelepiped shape as shown in Figures 1 to 3.

The external electrodes 14, 15 are provided on the end surface 11a and face each other in the X-axis direction with the ceramic body 11 in between. The external electrodes 14, 15 each extend from the end surface 11a of the ceramic body 11 to the peripheral surface 11e. As a result, the cross sections of the external electrodes 14, 15 parallel to the X-Z plane and the cross sections parallel to the X-Y plane are both U-shaped.

The ceramic body 11 has a capacitance forming portion 16 and a peripheral portion 17 provided around the capacitance forming portion 16.

The capacitance forming portion 16 has internal electrodes 12, 13 that are alternately stacked in the Z-axis direction via a plurality of ceramic layers 18 (see FIG. 2), and is configured as a laminated body having a substantially rectangular parallelepiped shape. The ends of the internal electrodes 12, 13 in the outermost layer of the capacitance forming portion 16 in the Y-axis direction and the Z-axis direction are referred to as ends 16d.

The internal electrodes 12, 13 extend along the X-Y plane and are formed across the entire width of the capacitance forming portion 16 in the Y-axis direction. The positions of the ends of the internal electrodes 12, 13 in the Y-axis direction are aligned with each other within a range of, for example, 0.5 μm in the Y-axis direction. The internal electrodes 12, 13 are formed from a good electrical conductor. Typical examples of good electrical conductors that form the internal electrodes 12, 13 include nickel (Ni), as well as metals or alloys whose main components are copper (Cu), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), etc.

The first internal electrode 12 extends in the X-axis direction to the end face 11a that contacts the first external electrode 14, and is spaced apart from the second external electrode 15. The second internal electrode 13 extends in the X-axis direction to the end face 11a that contacts the second external electrode 15, and is spaced apart from the first external electrode 14. As a result, the first internal electrode 12 is connected only to the first external electrode 14, and the second internal electrode 13 is connected only to the second external electrode 15.

With this configuration, when a voltage is applied between the first external electrode 14 and the second external electrode 15 in the multilayer ceramic capacitor 10, the voltage is applied to the multiple ceramic layers 18 between the first internal electrode 12 and the second internal electrode 13. As a result, a charge corresponding to the voltage between the first external electrode 14 and the second external electrode 15 is stored in the multilayer ceramic capacitor 10.

The ceramic layers 18 are made of, for example, a dielectric ceramic having a high dielectric constant, which can increase the capacitance of each ceramic layer 18. Examples of dielectric ceramics having a high dielectric constant include materials having a perovskite structure containing barium (Ba) and titanium (Ti), such as barium titanate (BaTiO ₃ ).

The ceramic layer 18 may be composed of a strontium titanate ( _SrTiO3 )-based, calcium titanate ( _CaTiO3 )-based, magnesium titanate ( _MgTiO3 )-based, calcium zirconate ( _CaZrO3 )-based, calcium zirconate titanate (Ca(Zr,Ti) _O3 )-based, barium zirconate ( _BaZrO3 )-based, titanium oxide ( _TiO2 )-based, or the like.

[Detailed configuration of peripheral portion 17]
FIG. 4 is an enlarged view of region IV in FIG. 3, and is an enlarged cross-sectional view showing the vicinity of the boundary between the cover portion 19 and the side margin portion 20. As shown in FIG.

The peripheral portion 17 has the function of protecting the capacitance forming portion 16 and ensuring the insulation of the internal electrodes 12, 13. The peripheral portion 17 is configured as a ceramic sintered body and includes a plurality of crystal grains 17r of insulating ceramic. The peripheral portion 17 may be formed of an insulating ceramic different from that of the ceramic layer 18, but from the viewpoint of suppressing internal stress in the ceramic body 11, it is preferably formed of the same dielectric ceramic as that of the ceramic layer 18.

The peripheral portion 17 has a cover portion 19, a side margin portion 20, and a grain growth region R. The surface of the peripheral portion 17 constitutes the peripheral surface 11e of the ceramic body 11.

The cover portion 19 is provided outside the capacitance forming portion 16 in the Z-axis direction, and covers the outermost layer of the capacitance forming portion 16 from the Z-axis direction. As shown in FIG. 4, the thickness dimension D1 of the cover portion 19 along the Z-axis direction is, for example, 20 μm or less, and preferably 10 μm or more and 20 μm or less. The thickness dimension D1 is the dimension along the Z-axis direction from the center of the main surface 11c in the X-axis and Y-axis directions to the capacitance forming portion 16.

The side margin portion 20 is provided outside the capacitance forming portion 16 in the Y-axis direction, and in this embodiment, covers the capacitance forming portion 16 and the cover portion 19 from the Y-axis direction. As shown in FIG. 4, the thickness dimension D2 along the Y-axis direction of the side margin portion 20 is, for example, 20 μm or less, and preferably 10 μm or more and 20 μm or less. The thickness dimension D2 is the dimension along the Y-axis direction from the center of the side surface 11b in the X-axis direction and Z-axis direction to the capacitance forming portion 16.

The grain growth region R is a region in which the average crystal grain size of the insulating ceramic crystal grains 17r is larger than that of the central portion of the cover portion 19 in the Y-axis direction. The average crystal grain size of the grain growth region R is preferably 300 nm or more, and more preferably 500 nm or more. The average crystal grain size of the grain growth region R is formed to be, for example, 50% or more larger than the average crystal grain size of the central portion of the cover portion 19. The central portion of the cover portion 19 refers to the central portion of the cover portion 19 in the X-axis direction, Y-axis direction, and Z-axis direction. The average crystal grain size of the central portion of the cover portion 19 is not particularly limited, but is, for example, 100 nm to 300 nm.

Furthermore, the grain growth region R may have a larger average crystal grain size of the ceramic crystal grains 17r than the central portion of the side margin portion 20. The central portion of the side margin portion 20 refers to the central portion of the side margin portion 20 in the X-axis direction, the Y-axis direction, and the Z-axis direction.

The average crystal grain size is calculated as follows. First, a scanning electron microscope or a transmission electron microscope is used to image the cross section of the grain growth region R. At this time, the magnification is adjusted so that approximately 1,000 to 3,000 crystal grains 17r can be imaged in one image, and the crystal grain sizes of a total of 10,000 or more crystal grains 17r are measured using multiple images. The crystal grain size is calculated as the diameter of a circle having the same cross-sectional area by measuring the cross-sectional area of the crystal grain. The median crystal grain size of the measured 10,000 or more crystal grains 17r is taken as the average crystal grain size.

The grain growth region R is formed, for example, between the end 16d of the capacitance forming portion 16 and the peripheral surface 11e of the ceramic body 11. The grain growth region R may be formed between the end 16d and the curved surface 11d. The grain growth region R is typically formed so as to reach the peripheral surface 11e from the end 16d, but it does not have to reach the peripheral surface 11e and may be spaced apart from the end 16d.

When viewed from the X-axis direction, the grain growth region R extends, for example, along a straight line La that forms an acute angle α of 0 degrees or more and 45 degrees or less with a straight line Lz that extends from the end portion 16d and is parallel to the Z-axis direction. The straight line La may be a straight line that forms an acute angle α from the straight line Lz toward the cover portion 19, or a straight line that forms an acute angle α from the straight line Lz toward the side margin portion 20.

The cross-sectional shape of the grain growth region R as viewed in the X-axis direction is not limited to a band extending with approximately the same width, but may extend toward the cover portion 19 side and the side margin portion 20 side in the intermediate portion between the end portion 16d and the peripheral surface 11e. Alternatively, it may be a shape that bulges toward at least one of the peripheral surface 11e side and the end portion 16d side.

Here, the grain boundaries between the ceramic crystal grains 17r have a lower mechanical strength than the grains 17r themselves. In other words, when the multilayer ceramic capacitor 10 is subjected to an external force, the grain boundaries are likely to become the starting points for cracks, and when cracks occur, they tend to progress along the grain boundaries.

In the grain growth region R, the crystal grains 17r are large, so there are few grain boundaries that could be the starting point of cracks, and the occurrence and progression of cracks can be suppressed.

Furthermore, a curved surface 11d is present in and near the grain growth region R. External forces are easily applied to the curved surface 11d, and cracks are particularly likely to occur on the curved surface 11d. In this embodiment, by providing the grain growth region R on and near the curved surface 11d, it is possible to effectively prevent cracks from occurring.

If at least one of the cover portion 19 and the side margin portion 20 is configured to be very thin, at 20 μm or less, cracks will easily reach the capacitance forming portion 16. If cracks reach the capacitance forming portion 16, they will reduce the insulation and environmental resistance of the multilayer ceramic capacitor 10 and may cause a short circuit. By providing the grain growth region R in the peripheral portion 17, it is possible to prevent cracks from reaching the capacitance forming portion 16 even if the peripheral portion 17 is thin. Therefore, it is possible to achieve both miniaturization of the multilayer ceramic capacitor 10 and improved reliability.

The thickness of the peripheral portion 17 near the end 16d of the capacitance forming portion 16 tends to be particularly thin. Therefore, the curved surface 11d may include an extension portion 11f that extends inward in the Y-axis direction beyond the end 16d and rises from the main surface 11c in the Z-axis direction. This ensures a sufficient thickness of the peripheral portion 17 near the end 16d of the capacitance forming portion 16, and ensures the insulation and environmental resistance of the multilayer ceramic capacitor 10.

When the curved surface 11d includes the extension 11f, the grain growth region R may be formed to reach the extension 11f of the curved surface 11d. This can suppress the occurrence and progression of cracks near the end 16d, and improve the insulation and environmental resistance of the multilayer ceramic capacitor 10.

As described above, according to this embodiment, it is possible to provide a multilayer ceramic capacitor 10 that is small and has high insulation and environmental resistance. In other words, it is possible to improve the reliability of the multilayer ceramic capacitor 10 and to extend its lifespan.

[Method of Manufacturing Multilayer Ceramic Capacitor 10]
Fig. 5 is a flowchart showing a method for manufacturing the multilayer ceramic capacitor 10. Figs. 6 to 10 are diagrams that typically show the manufacturing process of the multilayer ceramic capacitor 10. The method for manufacturing the multilayer ceramic capacitor 10 will be described below along Fig. 5 with appropriate reference to Figs. 6 to 10.

(Step S01: Fabricating stacked chips)
In step S01, a first ceramic sheet 101 and a second ceramic sheet 102 for forming the capacitance forming portion 16 and a third ceramic sheet 103 for forming the cover portion 19 are prepared, and these are stacked and cut as shown in Figure 6 to produce the unsintered laminated chip 21 shown in Figure 7.

The ceramic sheets 101, 102, and 103 are unsintered dielectric green sheets whose main component is dielectric ceramics, and are large sheets for producing multiple laminated chips 21. An unsintered first internal electrode 12 is formed on the first ceramic sheet 101. An unsintered second internal electrode 13 is formed on the second ceramic sheet 102. No internal electrode is formed on the third ceramic sheet 103.

In step S01, the first ceramic sheet 101 and the second ceramic sheet 102 are alternately stacked, and the third ceramic sheet 103 is stacked on the top and bottom surfaces in the Z-axis direction of the stack of the ceramic sheets 101 and 102. The number of third ceramic sheets 103 is not limited to the example shown in FIG. 6, and can be adjusted, for example, so that the thickness dimension in the Z-axis direction of the cover portion 19 after firing is 20 μm or less.

Next, the stacked ceramic sheets 101, 102, and 103 are pressed together, and the pressed sheets are cut into individual pieces. This results in a stacked chip 21 with an unfired capacitance forming portion 16 and a cover portion 19, as shown in FIG. 7.

(Step S02: Forming side margins)
In step S02, unsintered side margin portions 20 are provided on side surfaces S of the laminated chips 21 produced in step S01, thereby producing unsintered ceramic body 11. Hereinafter, an example of a method for providing unsintered side margin portions 20 on side surfaces S of laminated chips 21 in step S02 will be described.

First, as shown in FIG. 8, a ceramic sheet 20s is placed on a flat base member E, and the other side S of the laminated chip 21, one side S of which is held by tape T, is placed opposite the ceramic sheet 20s. The base member E is made of a soft material with a low Young's modulus, such as a silicone-based elastomer.

A paste P containing titanium oxide (TiO ₂ ) is applied to the side of the cover portion 19 facing the ceramic sheet 20s. The titanium oxide-containing paste P enhances the adhesion between the ceramic sheet 20s and the laminated chip 21 and promotes the formation of grain growth regions R, as described later.

The ceramic sheet 20s is configured as a large dielectric green sheet for forming the unsintered side margin portion 20. The ceramic sheet 20s can be formed into a flat sheet of uniform thickness, for example, by using a roll coater or a doctor blade. The thickness dimension of the ceramic sheet 20s is adjusted, for example, so that the thickness dimension of the side margin portion 20 after firing is 20 μm or less.

Next, as shown in FIG. 9, the side surface S of the laminated chip 21 presses against the ceramic sheet 20s. The laminated chip 21 sinks deeply locally into the base member E together with the ceramic sheet 20s. As a result, the portion of the ceramic sheet 20s that sinks together with the laminated chip 21 is separated as the side margin portion 20, and an unfired ceramic body 11 is produced that includes an unfired capacitance forming portion 16 and an unfired peripheral portion 17 (cover portion 19 and side margin portion 20).

In addition, by using a soft material for the base member E, the stacked chip 21 sinks deeply into the ceramic sheet 20s, and the corners of the ends of the side margin portion 20 are crushed by the pressing force from the base member E. This causes the ends of the side margin portion 20 to become rounded, forming a curved surface 11d. Furthermore, when the end of the curved surface 11d is cut off from the ceramic sheet 20s, it is stretched along the stacked chip 21, forming an extension portion 11f.

(Step S03: Firing)
In step S03, the green ceramic body 11 obtained in step S02 is fired to produce the ceramic body 11 of the multilayer ceramic capacitor 10 shown in FIGS.

The firing temperature in step S03 can be determined based on the sintering temperature of the ceramic body 11. For example, when a barium titanate (BaTiO ₃ ) based material is used, the firing temperature can be about 1000 to 1300° C. Furthermore, the firing can be performed, for example, in a reducing atmosphere or a low oxygen partial pressure atmosphere.

Firing causes the ceramic crystal grains to grow and become denser in the ceramic body 11. Titanium (Ti) and oxygen ( _O2 ) contained in the applied titanium oxide-containing paste P diffuse near the boundary between the cover portion 19 and the side margin portion 20. As a result, the ceramic crystal grains take in these atoms, promoting grain growth in particular, and a grain growth region R is formed at the boundary.

The method of forming the grain growth region R is not limited to applying the titanium oxide-containing paste P. For example, grain growth can be promoted by controlling the shrinkage behavior of the cover portion 19 and the side margin portion 20 during firing and applying internal stress to the boundary between them.

(Step S04: Forming external electrodes)
In step S04, external electrodes 14, 15 are formed on both ends in the X-axis direction of the ceramic body 11 obtained in step S03, thereby producing the multilayer ceramic capacitor 10 shown in Figures 1 to 3. The method for forming the external electrodes 14, 15 in step S04 can be arbitrarily selected from known methods.

The external electrodes 14, 15 may be fired simultaneously with the unfired ceramic body 11. That is, after step S02, unfired external electrodes may be formed on both ends of the unfired ceramic body 11 in the X-axis direction, and then in step S03, the external electrodes 14, 15 may be formed by firing them simultaneously with the unfired ceramic body 11.

The multilayer ceramic capacitor 10 is thus completed. In this manufacturing method, the side margin portion 20 is attached to the side surface S of the multilayer chip 21 where the internal electrodes 12, 13 are exposed, so that the Y-axis positions of the ends of the multiple internal electrodes 12, 13 in the ceramic body 11 are aligned along the Z-axis with a variation of less than 0.5 μm.

To confirm that the multilayer ceramic capacitor 10 actually has high mechanical strength, the following two types of samples were produced as examples and comparative examples.

First, as an example, a sample of a multilayer ceramic capacitor in which a grain growth region was formed based on the above manufacturing method was produced. This sample was designed so that the dimension of the ceramic body in the X-axis direction after firing was 1 mm, the dimensions in the Y-axis direction and the Z-axis direction were 0.5 mm, the thickness dimension D1 of the cover portion was 20 μm, and the thickness dimension D2 of the side margin portion was 20 μm. In addition, the average crystal grain size of the grain growth region was 500 nm, and the average crystal grain size of the central portion of the cover portion 19 was 200 nm.

As a comparative example, a sample was produced that had the same size and basic structure as the multilayer ceramic capacitor sample according to the embodiment, but did not have a grain growth region.

A drop test was conducted using 1,000 samples each from the above examples and comparative examples, and the occurrence rate of cracks at the boundary was calculated. The drop test was conducted by dropping the samples one by one from a height of 0.5 m. The occurrence of cracks was confirmed visually.

As a result, in the example samples, cracks occurred in 0 out of 1000 samples, whereas in the comparative example samples, cracks occurred in 3 out of 1000 samples. This confirmed that by forming a grain growth region at the boundary between the cover portion and the side margin portion, the mechanical strength of the multilayer ceramic capacitor is increased, improving its reliability.

Second Embodiment
In the above first embodiment, the configuration in which the side margin portion 20 covers the cover portion 19 and the capacitance forming portion 16 from the Y-axis direction has been described, but the present invention is not limited to this configuration. In the following description, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted.

Figures 11 and 12 are diagrams showing a multilayer ceramic capacitor 30 according to a second embodiment. Figure 11 is a cross-sectional view taken at the same position as in Figure 3. Figure 12 is an enlarged view of region XII in Figure 11, and is an enlarged cross-sectional view taken at the same position as in Figure 4.

The multilayer ceramic capacitor 30 has a capacitance forming portion 16 and a peripheral portion 37 having a cover portion 39 and a side margin portion 40, and the cover portion 39 covers the capacitance forming portion 16 and the side margin portion 40 from the Z-axis direction.

In the example shown in FIG. 12, the grain growth region R formed at the boundary between the cover portion 39 and the side margin portion 40 extends from the end portion 16d along a straight line Lb that forms an acute angle β of 45 degrees or less with a straight line Ly parallel to the Y-axis direction. The straight line Lb may be a straight line that extends closer to the side margin portion 40 than the straight line Ly, or a straight line that extends closer to the cover portion 39 than the straight line Ly. The cross-sectional shape of the grain growth region R may take on various shapes as described in the first embodiment.

FIG. 13 is a diagram showing a manufacturing process of a multilayer ceramic capacitor 30, and is a perspective view showing a laminated structure of an unfired ceramic body 31.
As shown in the figure, ceramic sheets 301, 302 on which internal electrodes 12, 13 are patterned so as to have side margins M at both ends in the Y-axis direction are laminated, and ceramic sheets 303 forming cover portions 39 are laminated on the top and bottom surfaces in the Z-axis direction of this laminate 304. In this way, an unsintered ceramic body 31 is produced. In this case, too, a laminate sheet configured as a large sheet is actually formed, and the laminate is separated into individual laminates corresponding to each ceramic body 31.

In this embodiment, for example, a titanium oxide-containing paste is applied to the side margin portion M of the outermost ceramic sheets 301, 302 in the laminate 304 of the ceramic sheets 301, 302. As a result, in the firing process, grain growth of the ceramic crystal grains in the boundary portion between the side margin portion 40 and the cover portion 39 is promoted, and a grain growth region R is formed, as in the first embodiment.

Although the above describes various embodiments of the present invention, the present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the spirit of the present invention.

For example, in the above embodiment, the multilayer ceramic capacitor 10 is described as an example of a multilayer ceramic electronic component, but the present invention is applicable to multilayer ceramic electronic components in general. Examples of such multilayer ceramic electronic components include chip varistors, chip thermistors, and multilayer inductors.

10, 30...Multilayer ceramic capacitor (multilayer ceramic electronic component)
REFERENCE SIGNS LIST 11, 31: ceramic body 12, 13: internal electrodes 16: capacitance forming portion 17, 37: peripheral portion 18: ceramic layer 19, 39: cover portion 20, 40: side margin portion R: grain growth region

Claims (3)

providing a first ceramic sheet, a second ceramic sheet and a third ceramic sheet;
forming an internal electrode pattern on the first ceramic sheet and the second ceramic sheet;
laminating the first ceramic sheet and the second ceramic sheet on which the internal electrode pattern is formed;
laminating the third ceramic sheet on top and bottom surfaces of the first ceramic sheet and the second ceramic sheet to obtain a laminate;
singulating the laminate;
applying ceramic paste to a side surface of the third ceramic sheet of the laminate, while leaving the side surfaces of the first ceramic sheet and the second ceramic sheet unapplied ;
forming a side margin on a side surface of the laminate;
sintering the laminate to obtain an element body;
and forming external electrodes on the element body. 2. The method for producing a multilayer ceramic electronic component according to claim 1, wherein the ceramic paste applied to the side surface of the third ceramic sheet contains titanium oxide. The method for manufacturing a multilayer ceramic electronic component according to claim 1, wherein the step of forming the external electrodes comprises forming unfired external electrodes on the laminate and then firing the laminate to obtain the element body, and then firing the external electrodes simultaneously with the laminate.

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