JP7510860B2 - Semiconductor device, information processing device, and method for manufacturing the semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device, an information processing device, and a method for manufacturing a semiconductor device.

Graphene ribbons with a width of about a few nanometers are called GNRs (graphene nanoribbons). Graphene itself does not have a band gap, but GNRs are known to behave as semiconductors because of the quantum confinement effect caused by their narrow width. Because GNRs have high carrier mobility, using GNRs in transistor channels can produce transistors capable of high-speed operation.

It is technically difficult to process sheet-like graphene using lithography or other methods to form GNRs with widths on the order of nanometers. Therefore, a method has been reported in which GNRs are formed by polymerizing precursor molecules on the surface of a catalytic metal. This method does not require processing graphene using lithography, making it technically easy to form GNRs. It has been reported that when GNRs formed using this method are used to make field effect transistors (FETs), their characteristics are improved over silicon metal oxide semiconductor FETs (MOSFETs).

However, there is still room for improvement in transistors using GNRs in terms of increasing the drain current.

JP 2015-101499 A JP 2020-47646 A

“Atomically precise bottom-up fabrication of graphene nanoribbons”, Cai et al., Nature, volume 466, pages 470-473, 2010 “Graphene Nanoribbon Tunnel Transistors”, Zhang et al., Electron Device Letters, IEEE, volume 29, pages 1344-1346, 2009 “States Modulation in Graphene Nanoribbons through Metal Contacts”, Archambault et al, ACS Nano, volume 7, number 6, pages 5414-5420, 2013 “Quasiparticle energies and band gaps in graphene nanoribbons”, Li Yang et al., Physical Review Letters, volume 99, number 18, pages 186801, 2007

According to one aspect, the aim is to increase the drain current.

According to one aspect, a semiconductor device is provided, comprising: a channel layer in which a first graphene nanoribbon layer which is an intrinsic semiconductor containing no impurities and which has a plurality of first graphene nanoribbons; and a second graphene nanoribbon layer which is an intrinsic semiconductor containing no impurities and which has a plurality of second graphene nanoribbons having a band gap narrower than that of the first graphene nanoribbons; a source electrode connected to the channel layer; a drain electrode connected to the channel layer; and a gate electrode provided between the source electrode and the drain electrode and facing the channel layer, wherein at least one of the source electrode and the drain electrode is connected to the second graphene nanoribbon layer.

According to one aspect, the drain current can be increased.

FIG. 1 is a schematic plan view of a GNR. FIG. 2 shows a curve showing the distribution of the length of GNRs. FIG. 3(a) is a plan view of the transistor investigated by the inventors, and FIG. 3(b) is a cross-sectional view of a GNR layer. 4(a) to (d) show the density of states (DOS) of the GNR layer calculated by the density functional theory. FIG. 5 is a band diagram for explaining the problems caused by Fermi surface pinning. 6A to 6C are cross-sectional views (part 1) of the semiconductor device according to the first embodiment during its manufacture. 7A to 7C are cross-sectional views (part 2) of the semiconductor device according to the first embodiment during its manufacture. 8A to 8C are cross-sectional views (part 3) of the semiconductor device according to the first embodiment during its manufacture. 9A and 9B are cross-sectional views (part 4) of the semiconductor device according to the first embodiment during its manufacture. 10A to 10C are cross-sectional views (part 5) of the semiconductor device according to the first embodiment during its manufacture. 11A and 11B are cross-sectional views (part 6) of the semiconductor device according to the first embodiment during its manufacture. FIG. 12 is a cross-sectional view (part 7) of the semiconductor device according to the first embodiment during manufacturing. 13A and 13B are plan views (part 1) of the semiconductor device according to the first embodiment during its manufacture. 14A and 14B are plan views (part 2) of the semiconductor device according to the first embodiment during its manufacture. FIG. 15(a) is an enlarged plan view of a first GNR included in a first GNR layer according to the first embodiment, and FIG. 15(b) is an enlarged plan view of a second GNR included in a second GNR layer according to the first embodiment. FIG. 16A is a graph showing the relationship between the width of a GNR in the short direction and the band gap of the GNR, and FIG. 16B is an enlarged cross-sectional view of the channel layer according to the first embodiment. FIG. 17A is a graph showing the results of investigating the characteristics of the semiconductor device according to the comparative example, and FIG. 17B is a graph showing the results of investigating the characteristics of the semiconductor device according to the first embodiment. FIG. 18( a ) is a cross-sectional view of a calculation model used in the investigation of the first embodiment, and FIG. 18 ( b ) is a diagram obtained by calculating the DOS of the channel layer according to the first embodiment using this calculation model by the density functional method. FIG. 19( a ) is a cross-sectional view of another calculation model used in the investigation of the first embodiment, and FIG. 19 ( b ) is a diagram obtained by calculating the DOS of the channel layer according to the first embodiment using this calculation model by the density functional method. 20A to 20D are cross-sectional views (part 1) of the semiconductor device according to the second embodiment during its manufacture. 21A to 21D are cross-sectional views (part 2) of the semiconductor device according to the second embodiment during its manufacture. 22A to 22D are cross-sectional views (part 3) of the semiconductor device according to the second embodiment during its manufacture. 23A and 23B are cross-sectional views (part 4) of the semiconductor device according to the second embodiment during its manufacture. 24A and 24B are cross-sectional views (part 5) of the semiconductor device according to the second embodiment during its manufacture. FIG. 25 is a schematic diagram of an information processing apparatus according to the third embodiment. FIG. 26 is a schematic diagram of a case where a quantum circuit element is controlled by a semiconductor device having a MOSFET formed on a silicon substrate.

Before explaining this embodiment, we will explain the basics.

FIG. 1 is a schematic plan view of a GNR.
As shown in Figure 1, GNR1 has a ribbon-like planar shape with a length D longer than its width W, and has a structure in which six-membered rings of carbon atoms C are arranged in a plane. Although graphene itself is gapless, when the width W of GNR1 is made on the order of nanometers, a band gap of about several eV is formed due to the quantum confinement effect.

One method for forming such GNR1 is to polymerize precursor molecules on the surface of a catalytic metal, as mentioned above.

Figure 2 shows a curve showing the distribution of the length D of GNR1 formed by this method.

As shown in Figure 2, the most common length D of GNR1 is only about 20 nm. A length of about 20 nm is too short to connect the source and drain electrodes of a transistor, and GNR1 cannot be used as a transistor channel.

To solve this problem, consider the transistor shown in Figure 3(a).

FIG. 3A is a plan view of a transistor examined by the present inventors.
This transistor 5 has a GNR layer 6 including a number of GNRs 1, and a source electrode 7 and a drain electrode 8 spaced apart on the GNR layer 6. Note that a gate electrode between the source electrode 7 and the drain electrode 8 is not shown in the figure.

Of these, GNR1 is formed by polymerizing precursor molecules on the surface of a catalytic metal. Each GNR1 is in the same plane, and the GNR layer6 is only one atomic layer thick.

With this structure, multiple GNRs 1 do not overlap vertically, and adjacent GNRs 1 are in contact with each other when viewed from above, making the GNR layer 6 electrically conductive.

FIG. 3( b ) is a cross-sectional view of a GNR layer 6 .
The molecular orbital of a six-membered carbon ring has a π orbital 9. Due to the symmetry of the six-membered ring, the π orbital 9 extends in the thickness direction z of the GNR 1. Therefore, the π orbitals 9 of two GNRs 1 aligned in the direction x perpendicular to the thickness direction z do not overlap, and electrons cannot flow between the two GNRs 1 via the overlapped π orbitals 9.

As a result, electrons are conducted through two GNRs 1 by hopping conduction, so the electrical conductivity of the GNR layer 6 becomes extremely poor, and the drain current of the transistor 5 becomes extremely small.

Furthermore, the GNR layer 6 has the following problems.
4(a) to (d) are diagrams obtained by calculating the DOS (Density of States) of the GNR layer 6 using the density functional method.

Figure 4(a) shows the DOS of the GNR layer 6 when the source electrode 7 and drain electrode 8 are not formed. In this case, the Fermi surface F exists at a position almost equal to the LUMO (Lowest Unoccupied Molecular Orbital) and the HOMO (Highest Occupied Molecular Orbital), so there is no particular problem.

On the other hand, Figures 4(b) to (d) show the DOS of the GNR layer 6 when the source electrode 7 and drain electrode 8 are formed. Figure 4(b) shows the DOS when gold is used as the material for each of the source electrode 7 and drain electrode 8, and Figure 4(c) shows the DOS when palladium is used as the material for each of the source electrode 7 and drain electrode 8. And Figure 4(d) shows the DOS when titanium is used as the material for each of the source electrode 7 and drain electrode 8.

In Figures 4(b) to (d), the materials of the source electrode 7 and drain electrode 8 react with the GNR 1, forming an in-gap state called MIGS (Metal-Induced Gap State). As a result, the Fermi surface is pinned to the MIGS, and the Fermi surface F is positioned toward either the HOMO or the LUMO.

Figure 5 is a band diagram to explain the problems caused by Fermi surface pinning.

As shown in Figure 5, the HOMO and LUMO bands of the GNR layer 6 are bent by pinning, forming a Schottky barrier V between the source electrode 7 and the GNR layer 6. In order to inject holes from the source electrode 7 into the GNR layer 6 in this state, a strong electric field must be applied between the source and drain to flatten the bent bands, which increases the driving voltage of the transistor.

Below, we explain some embodiments that can solve these problems.

First Embodiment
In this embodiment, a semiconductor device using GNRs in a channel layer is manufactured as follows.

Figures 6 to 12 are cross-sectional views of the semiconductor device according to this embodiment during manufacturing.

First, as shown in FIG. 6(a), a mica substrate with a thickness of about 500 μm to 600 μm is prepared as the first support substrate 10. Then, a gold layer is formed on the first support substrate 10 as the first catalytic metal layer 11 by vapor deposition to a thickness of about 200 nm.

The surface orientation of the first catalytic metal layer 11 is not particularly limited, but in this embodiment, the (111) gold surface is made to appear on the surface 11a of the first catalytic metal layer 11. Note that instead of the (111) surface, a high-index gold surface such as the (110) surface or the (778) surface may be made to appear on the surface 11a. The surface 11a is then cleaned in a vacuum.

Next, as shown in FIG. 6(b), the first catalytic metal layer 11 is heated to about 200°C in a vacuum. Then, in this state, a monomer of the first precursor molecule is vapor-deposited onto the surface 11a, thereby forming a first molecular layer 12 on the first catalytic metal layer 11 to a thickness of about one molecular layer.

In this embodiment, the first precursor molecule is an aromatic compound containing bromine as a halogen group, such as 3',6'-dibromo-1,1':2',1"-terphenyl or 1,2-bis-(2-anthracenyl)-3,6-dibromobenzene.

When these aromatic compounds are used, halogens are eliminated from the aromatic compounds in the first molecular layer 12, causing the Ullmann reaction to occur, forming a polymer of the aromatic compounds.

Next, as shown in FIG. 6(c), the temperature of the first catalytic metal layer 11 is heated to about 350°C to 450°C, and hydrogen is desorbed from the aromatic compounds contained in the first molecular layer 12. As a result, the first molecular layer 12 is aromaticized by the catalytic action of the first catalytic metal layer 11, and multiple first GNRs 13 are formed on the first catalytic metal layer 11. The first GNRs 13 are intrinsic semiconductors that do not contain impurities.

In addition, when the catalytic action of the first catalytic metal layer 11 is utilized in this manner, among the multiple polymers contained in the first molecular layer 12, only the polymer in contact with the first catalytic metal layer 11 becomes the first GNR 13 through aromatization. Therefore, the thickness of the first GNR 13 is the thickness of one molecular layer.

By carrying out the steps up to this point, a first GNR (graphene nanoribbon) layer 14 having a plurality of first GNRs 13 has been formed.

FIG. 13( a ) is a plan view of the first GNR layer 14 .
As shown in FIG. 13A, each of the multiple first GNRs 13 included in the first GNR layer 14 extends in a random direction in a plan view.

Then, the second GNR layer to be laminated with the first GNR layer 14 is formed as follows.

First, as shown in FIG. 7(a), a mica substrate with a thickness of about 500 μm to 600 μm is prepared as the second support substrate 20, and a gold layer is formed on top of it by vapor deposition to a thickness of about 200 nm as the second catalytic metal layer 21.

The plane orientation of the second catalytic metal layer 21 is not particularly limited. In this embodiment, similar to the first catalytic metal layer 11, the (111) plane of gold is made to appear on the surface 21a of the second catalytic metal layer 21. Note that instead of the (111) plane, a high-index plane of gold, such as the (110) plane or the (778) plane, may be made to appear on the surface 21a. Thereafter, the surface 21a is cleaned in a vacuum.

Next, as shown in FIG. 7(b), the second catalytic metal layer 21 is heated to about 200°C in a vacuum. Then, in this state, a monomer of the second precursor molecule is vapor-deposited onto the surface 21a, thereby forming a second molecular layer 22 on the second catalytic metal layer 21 to a thickness of about one molecular layer.

Similar to the first precursor molecule that forms the first molecular layer 12, in this embodiment, an aromatic compound containing bromine as a halogen group is used as the second precursor molecule. Examples of such aromatic compounds include the aforementioned 3',6'-dibromo-1,1':2',1"-terphenyl and 1,2-bis-(2-anthracenyl)-3,6-dibromobenzene.

When these aromatic compounds are used, halogens are eliminated from the aromatic compounds in the second molecular layer 22, causing the Ullmann reaction to occur, forming a polymer of the aromatic compounds.

Next, as shown in FIG. 7(c), the temperature of the second catalytic metal layer 21 is heated to approximately 350°C to 450°C, and hydrogen is desorbed from the aromatic compounds contained in the second molecular layer 22. This causes the second molecular layer 22 to be aromaticized by the catalytic action of the second catalytic metal layer 21, and multiple second GNRs 23 are formed on the second catalytic metal layer 21 to a thickness of one molecular layer. Like the first GNRs 13, the second GNRs 23 are also true semiconductors that do not contain impurities.

By carrying out the steps up to this point, a second GNR (graphene nanoribbon) layer 24 having a plurality of second GNRs 23 has been formed.

FIG. 13( b ) is a top view of second GNR layer 24 .
As shown in FIG. 13B, each of the second GNRs 23 included in the second GNR layer 24 extends in a random direction in a plan view.

Next, as shown in FIG. 8(a), a resist is applied onto the second GNR layer 24 by spin coating and then cured to form a support layer 25. In this embodiment, PMMA (polymethyl methacrylate) is used as the material for the resist.

Next, as shown in FIG. 8(b), the second support substrate 20 is dissolved and removed using an acid such as hydrochloric acid or hydrofluoric acid.

Then, as shown in FIG. 8(c), the second catalytic metal layer 21 is dissolved and removed using an aqueous solution of iodine and potassium iodide.

As a result of the above, a structure is obtained in which the second GNR layer 24 is supported by the support layer 25. After this, the process moves to laminating the first GNR layer 14 and the second GNR layer 24.

First, as shown in FIG. 9(a), a container 30 containing water 31 is prepared, and the first GNR layer 14 is immersed in the water 31 together with the first support substrate 10. Then, the support layer 25 is floated in the water 31 with the second GNR layer 24 facing down. At this time, in this embodiment, since the second GNR layer 24 is supported by the support layer 25, the second GNR layer 24 is easy to handle and can be easily floated in the water 31.

Next, as shown in FIG. 9(b), the first support substrate 10 is lifted out of the water 31, and the first GNR layer 14 scoops up the second GNR layer 24 from the water 31 into the air. This allows the first GNR layer 14 and the second GNR layer 24 to adhere to each other via the small amount of water remaining between them, and a channel layer 33 can be obtained in which these GNR layers 14 and 24 are stacked.

As mentioned above, each GNR 13, 23 is an intrinsic semiconductor, so the channel layer 33 formed from these GNRs 13, 23 is also an intrinsic semiconductor that does not contain impurities.

Then, each of the GNR layers 14, 24 is heated to a temperature of about 80°C in the atmosphere to dry any water remaining between them, and the GNR layers 14, 24 are securely attached to each other by van der Waals forces.

FIG. 14A is a plan view of the channel layer 33.
As shown in FIG. 14( a ), in the channel layer 33 , the first GNR 13 and the second GNR 23 intersect in a plan view.

Next, as shown in FIG. 10(a), the first support substrate 10 is dissolved and removed using an acid such as hydrochloric acid or hydrofluoric acid.

Furthermore, as shown in FIG. 10(b), the first catalytic metal layer 11 is dissolved and removed using an aqueous solution of iodine and potassium iodide.

Next, as shown in FIG. 10(c), a substrate 35 is prepared in which a silicon oxide layer 35b is formed on a silicon substrate 35a, and a channel layer 33 is placed on a surface 35c of the substrate 35. As a result, the channel layer 33 is attached to the substrate 35 by the van der Waals force between the surface 35c and the channel layer 33.

Next, as shown in FIG. 11(a), the support layer 25 is dissolved and removed with acetone.

11(b), a gold layer is formed on the entire upper surface of the channel layer 33 by vapor deposition, and the gold layer is patterned by lift-off to form a source electrode 36 and a drain electrode 37 on the channel layer 33. Note that the source electrode 36 and the drain electrode 37 may be formed of a palladium layer instead of a gold layer.

Figure 14(b) is a plan view of the channel layer 33 at the end of this process.

As described above, the first GNR 13 and the second GNR 23 intersect in a planar view in the channel layer 33. Therefore, even if the length of each GNR 13, 23 is shorter than the distance L between the source electrode 36 and the drain electrode 37, the source electrode 36 and the drain electrode 37 can be connected via each GNR 13, 23.

Next, as shown in FIG. 12, a hafnium oxide layer is formed as a gate insulating layer 38 on the channel layer 33 between the source electrode 36 and the drain electrode 37 by the ALD (Atomic Layer Deposition) method. Note that the gate insulating layer 38 is not limited to a hafnium oxide layer. For example, a single crystal layer of a hexagonal boron nitride layer may be attached to the channel layer 33 as the gate insulating layer 38.

After that, a gold layer is formed as a gate electrode 39 on the gate insulating layer 38 by vapor deposition, so that the gate electrode 39 faces the channel layer 33. Note that instead of the gold layer, a platinum layer or an aluminum layer may be formed as the gate electrode 39.

With the above steps, the basic structure of the semiconductor device 40 according to this embodiment is completed.
This semiconductor device 40 is a FET and has a channel layer 33 in which a first GNR layer 14 and a second GNR layer 24 are laminated.

Figure 15(a) is an enlarged plan view of the first GNR 13 included in the first GNR layer 14.

As shown in FIG. 15(a), the first GNR 13 has multiple six-membered rings of carbon atoms C in a first plane P1 parallel to the surface 35c of the substrate 35.

The number _N1 of carbon atoms C along the short-side direction Y1 of the first GNR 13 can be controlled by the first precursor molecule used to deposit the first GNR 13. Note that when counting the number _N1 , adjacent carbon atoms C along the short-side direction Y1 are counted as shown by line M1.

For example, when the first GNR 13 is formed from 3',6'-dibromo-1,1':2',1"-terphenyl, the number _N1 is 9. A GNR in which the number _N1 of carbon atoms C along the short side is 9 is also called an "N9" GNR.

Furthermore, when the first GNRs 13 are formed from 1,2-bis-(2-anthracenyl)-3,6-dibromobenzene, the number _N1 becomes 17, and it is possible to obtain the first GNRs 13 with “N17”.

Figure 15(b) is an enlarged plan view of the second GNR 23 included in the second GNR layer 24.

Similar to the first GNR 13, the second GNR 23 has multiple hexagonal rings of carbon atoms C in a second plane P2 that is parallel to both the surface 35c of the substrate 35 and the first plane P1.

Similar to the first GNR 13, the number _N2 of carbon atoms C along the short axis Y2 of the second GNR 23 can be controlled by the second precursor molecule used to deposit the second GNR 23. For example, the use of 3',6'-dibromo-1,1':2',1"-terphenyl results in the second GNR 23 of "N9", and the use of 1,2-bis-(2-anthracenyl)-3,6-dibromobenzene results in the second GNR 23 of "N17".

When counting the number _N2 , the carbon atoms C adjacent to each other along the short direction Y2, as shown by the line M2, are counted.

Figure 16(a) is a graph showing the relationship between the width of the GNR in the short direction and the band gap of the GNR.

Figure 16(a) also shows graphs of each series in which the number N of carbon atoms C along the short side of the GNR is expressed as 3p, 3p+1, and 3p+2, respectively, using an integer p.

For example, the 3p graph shows the band gap when N is 3, 6, 9, .... The 3p+1 graph shows the band gap when N is 1, 4, 7, .... The 3p+2 graph shows the band gap when N is 2, 5, 7, ....

As shown in FIG. 16(a), in the 3p, 3p+1, and 3p+2 series, the narrower the width, the larger the band gap. However, when viewed at the same width, the band gap increases in the order of 3p, 3p+2, and 3p+1.

Thus, the band gap of the first GNR 13 can be controlled by selecting the value of the number _N1 that determines the width and the series (3p, 3p+1, and 3p+2) to which the number _N1 belongs. These can be controlled by the type of first precursor molecule used to form the first GNR 13. For example, when 3',6'-dibromo-1,1':2',1"-terphenyl is used as the first precursor molecule, _N1 = 9, and the series to which _N1 belongs is "3p". When 1,2-bis-(2-anthracenyl)-3,6-dibromobenzene is used as the first precursor molecule, _N1 = 17, and the series to which the number _N1 belongs is "3p+2".

Similarly, the bandgap of the second GNR 23 can be controlled by selecting the value of the number _N2 that defines its _width and the series (3p, 3p+1, and 3p+2) to which it belongs.

By controlling the band gap in this manner, in this embodiment, the band gap of the second GNR 23 is made smaller than the band gap of the first GNR 13. This reduces the barrier when injecting holes from the source electrode 36 connected to the second GNR 23 into the channel layer 33, allowing holes to be injected into the channel layer 33 efficiently.

In the example of FIG. 12, the drain electrode 37 is not connected to the second GNR layer 24, but at least one of the source electrode 36 and the drain electrode 37 may be connected to the second GNR layer 24. This allows carriers to be efficiently injected into the channel layer 33 from the electrode connected to the second GNR layer 24, out of the source electrode 36 and the drain electrode 37.

Furthermore, according to FIG. 16(a), by adopting any one of the following conditions (1) to (3), the band gap of the second GNR 23 can be made approximately smaller than the band gap of the first GNR 13.

(1) When _N1 = 3p+1, the number _N2 is a natural number that belongs to the 3p+1 series, _N2 > _N1 . Or, the number _N2 is a natural number that belongs to either the 3p or 3p+1 series.

(2) When _N1 = 3p, the number _N2 is a natural number that belongs to the 3p series, _N2 > _N1 . Or, the number _N2 is a natural number that belongs to the 3p + 2 series.

(3) When _N1 = 3p+2, the number _N2 is a natural number that belongs to the 3p+2 series, _N2 > _N1 .

Next, the conductivity of the channel layer 33 will be described.
FIG. 16B is an enlarged cross-sectional view of the channel layer 33.
16(b), the π orbital 13p of the first GNR 13 extends in a direction Z1 perpendicular to the plane P1 in which the carbon hexagon is located, due to the spatial symmetry of the carbon hexagon. For the same reason, the π orbital 23p of the second GNR 23 also extends in a direction Z2 perpendicular to the plane P2.

As a result, in this embodiment, the π orbitals 13p and 23p overlap each other, making it easier for electrons to move between adjacent GNRs 13 and 23. Therefore, the overall electrical conductivity of the channel layer 33 can be improved compared to when electrons are hopping-conducted inside the single first GNR layer 14 or inside the single second GNR layer 24.

The inventors of the present application investigated the characteristics of the semiconductor device 40 to confirm this. In the investigation, as a comparative example, a case was also investigated in which only a single first GNR layer 14 was used as the channel layer 33.

Figure 17(a) is a graph showing the results of an investigation into the characteristics of the semiconductor device 40 according to the comparative example. The horizontal axis of this graph is the drain voltage, defined as the voltage between the source electrode 36 and the drain electrode 37. The vertical axis of the graph is the drain current flowing between the source electrode 36 and the drain electrode 37. The distance L between the source electrode 36 and the drain electrode 37 (see Figure 14(b)) was set to 0.5 μm. The inventors of the present application obtained multiple graphs by changing the gate electrode in various ways.

As shown in FIG. 17(a), in this comparative example, the magnitude of the drain current is only about 40 pA at most. The reason why only such a small drain current is obtained is thought to be that in the comparative example, electrons are conducted by hopping through each of the multiple first GNRs 13 contained in the single-layer first GNR layer 14.

On the other hand, FIG. 17(b) is a graph obtained by carrying out the same investigation as in FIG. 17(a) on the semiconductor device 40 according to this embodiment. The meanings of the vertical and horizontal axes of the graph are the same as those in FIG. 17(a), so the explanation is omitted. Also, as in the comparative example, the distance L between the source electrode 36 and the drain electrode 37 was set to 0.5 μm.

As shown in FIG. 17(b), in this embodiment, the magnitude of the drain current is a maximum of 3 nA, which is a two-digit increase compared to the comparative example.

In this embodiment, the GNR layers 14 and 24 are stacked to form the channel layer 33, so the thickness of the channel layer 33 is only about twice as thick as in the comparative example. Despite this, the drain current is two orders of magnitude higher than in the comparative example. This is thought to be because in this embodiment, the π orbitals 13p and 23p of the GNRs 13 and 23 overlap as shown in FIG. 16(b), enhancing the electrical conductivity of the channel layer 33.

The inventors of the present application also investigated the extent to which Fermi surface pinning occurs in the channel layer 33 according to this embodiment as follows.

FIG. 18(a) is a cross-sectional view of the computational model used in the study.
In this example, palladium atoms are assumed as the metal atoms 43 forming the source electrode 36 and the drain electrode 37. The number _N1 of carbon atoms in the first GNR layer 14 along the short side direction Y1 (see FIG. 15(a)) is set to 9, and the number _N2 of carbon atoms in the second GNR layer 24 along the short side direction Y2 (see FIG. 15(b)) is set to 11.

Figure 18(b) shows the DOS of the channel layer 33 in this case, calculated using the density functional theory.

As shown in FIG. 18(b), the band gap of the second GNR layer 24 disappears due to the reaction with the metal atoms 43, and the second GNR layer 24 enters a metallic electronic state.

On the other hand, in the first GNR layer 14, the reaction with the metal atoms 43 is suppressed, and the Fermi surface F is located approximately in the center between the HOMO and LUMO.

FIG. 19(a) is a cross-sectional view of another computational model used in the study.
As in the example of Fig. 18(a), this example also assumes palladium atoms as metal atoms 43. However, in this example, the number _N1 of carbon atoms in the first GNR layer 14 along the short-side direction Y1 (see Fig. 15(a)) is set to 11, and the number _N2 of carbon atoms in the second GNR layer 24 along the short-side direction Y2 (see Fig. 15(b)) is also set to 11.

Figure 19(b) shows the DOS of the channel layer 33 in this case, calculated using the density functional theory.

As shown in FIG. 19(b), in this example, the second GNR layer 24 is also in a metallic electronic state due to reaction with the metal atoms 43.

On the other hand, in the first GNR layer 14, the reaction with the metal atoms 43 is suppressed, and the Fermi surface F is located approximately in the center between the HOMO and LUMO.

In this way, in both Figures 18(b) and 19(b), the Fermi surface F of the first GNR layer 14 is located approximately in the center between the HOMO and LUMO, and pinning of the Fermi surface F is suppressed. This suppresses the band bending shown in Figure 5, and prevents the formation of a Schottky barrier between the source electrode 36 and the first GNR layer 14. As a result, holes can be injected from the source electrode 36 to the channel layer 33 even with a small drain voltage, making it possible to reduce the driving voltage of the transistor.

Second Embodiment
20 to 24 are cross-sectional views of the semiconductor device according to this embodiment during its manufacture.

First, by carrying out the steps shown in Figs. 6(a) to (c) described in the first embodiment, a structure is produced in which a first catalytic metal layer 11 and a first GNR layer 14 are laminated in this order on a first support substrate 10, as shown in Fig. 20(a).

Next, as shown in FIG. 20(b), the first support substrate 10 is dissolved and removed using an acid such as hydrochloric acid or hydrofluoric acid.

Next, as shown in FIG. 20(c), a substrate 35 is prepared in which a silicon oxide layer 35b is formed on a silicon substrate 35a. Then, a first catalyst metal layer 11 is placed on a surface 35c of the substrate 35 with the first GNR layer 14 facing downward. This causes the first GNR layer 14 to be attached to the substrate 35 by the van der Waals forces between the surface 35c and the first GNR layer 14.

Next, as shown in FIG. 20(d), the first catalytic metal layer 11 is dissolved and removed using an aqueous solution of iodine and potassium iodide.

The process up to this point completes the structure in which the first GNR layer 14 is attached to the substrate 35. After this, the second GNR layer 24 to be laminated with the first GNR layer 14 is formed as follows.

First, by carrying out the steps shown in Figs. 7(a) to (c) described in the first embodiment, a structure is produced in which a second catalytic metal layer 21 and a second GNR layer 24 are stacked in this order on a second support substrate 20, as shown in Fig. 21(a).

Next, as shown in FIG. 21(b), the second support substrate 20 is dissolved and removed using an acid such as hydrochloric acid or hydrofluoric acid.

Next, as shown in FIG. 21(c), a silicon dioxide substrate is prepared as a third support substrate 51. Then, the second catalyst metal layer 21 is placed on the third support substrate 51 with the second GNR layer 24 facing downward, and the third support substrate 51 and the second GNR layer 24 are mutually attracted by van der Waals forces.

Then, as shown in FIG. 21(d), the second catalytic metal layer 21 is dissolved and removed using an aqueous solution of iodine and potassium iodide.

Next, as shown in FIG. 22(a), a gold layer is formed on the entire upper surface of the second GNR layer 24 by vapor deposition, and the gold layer is patterned by lift-off to form a source electrode 36 and a drain electrode 37.

22(b), the second GNR layer 24 is removed by dry etching in the portions not covered by the source electrode 36 and the drain electrode 37 while using the source electrode 36 and the drain electrode 37 as masks. This dry etching is performed by, for example, reactive ion etching (RIE) using oxygen plasma.

22(c), a resist layer is applied by spin coating onto each of the source electrode 36, the drain electrode 37, and the third support substrate 51, and then cured to form the support layer 53. The material of the support layer 53 is, for example, PMMA.

Next, as shown in FIG. 22(d), the third support substrate 51 is dissolved and removed using a hydrofluoric acid solution.

By carrying out the steps up to this point, a structure is completed in which the second GNR layer 24 is supported by the support layer 53. After this, we move on to the process of laminating the first GNR layer 14 and the second GNR layer 24.

First, as shown in FIG. 23(a), a container 30 containing water 31 is prepared, and the first GNR layer 14 is immersed in the water 31 together with the substrate 35. In this embodiment, the first GNR layer 14 is supported by the substrate 35, making it easy to handle the first GNR layer 14, and the first GNR layer 14 can be easily immersed in the water 31.

Then, the support layer 53 is floated on the water 31 with the second GNR layer 24 facing down. The second GNR layer 24 supported by the support layer 53 is easy to handle and can be easily floated on the water 31.

23(b), the substrate 35 is lifted from the water 31, and the first GNR layer 14 scoops up the second GNR layer 24 from the water 31 into the air. As a result, as in the first embodiment, the first GNR layer 14 and the second GNR layer 24 are adhered to each other via the small amount of water remaining between them, and a channel layer 33 can be obtained in which these GNR layers 14 and 24 are stacked.

As in the first embodiment, the channel layer 33 is a true semiconductor that does not contain impurities.

Then, each of the GNR layers 14, 24 is heated to a temperature of about 80°C in the atmosphere to dry any water remaining between them, and the GNR layers 14, 24 are securely attached to each other by van der Waals forces.

Next, as shown in FIG. 24(a), the support layer 53 is dissolved and removed with acetone.

Next, as shown in FIG. 24(b), a hafnium oxide layer is formed by the ALD method as the gate insulating layer 38 on the channel layer 33 between the source electrode 36 and the drain electrode 37. Note that a single crystal layer of hexagonal boron nitride may be attached to the channel layer 33 as the gate insulating layer 38.

After that, a gold layer is formed as a gate electrode 39 on the gate insulating layer 38 by deposition, so that the gate electrode 39 faces the first GNR layer 14 included in the channel layer 33. In addition to gold, the gate electrode 39 can also be made of platinum or aluminum.

This completes the basic structure of the semiconductor device 60 according to this embodiment.

In this semiconductor device 60, the channel layer 33 beneath each of the source electrode 36 and the drain electrode 37 has a structure in which the first GNR layer 14 and the second GNR layer 24 are stacked. Therefore, as in the first embodiment, the electrical conductivity of the channel layer 33 is increased, and the drain current of the semiconductor device 60 can be increased.

In addition, as described in the first embodiment, the pinning of the Fermi surface of the first GNR layer 14 can be suppressed, so that the formation of a Schottky barrier between the source electrode 36 and the channel layer 33 can be suppressed. As a result, holes can be injected from the source electrode 36 to the channel layer 33 with a small drain voltage, and the driving voltage of the transistor can be reduced.

As in the first embodiment, in this embodiment, the band gap of the second GNR 23 contained in the second GNR layer 24 is made smaller than that of the first GNR 13 contained in the first GNR layer 14. This reduces the barrier when injecting carriers from the source electrode 36 or drain electrode 37 into the channel layer 33, allowing carriers to be injected into the channel layer 33 efficiently.

Third Embodiment
In this embodiment, an information processing device including a semiconductor device 40 according to the first embodiment will be described.

FIG. 25 is a schematic diagram of an information processing device 70 according to the present embodiment.
This information processing device 70 is a quantum computer, and includes a dilution refrigerator 71 and a quantum circuit element 72 housed therein.

Of these, the dilution refrigerator 71 is a refrigerator that utilizes the heat of dilution generated when liquid ^4He is diluted with liquid ^3He , and cools the quantum circuit element 72 to an extremely low temperature of about 10 mK.

The quantum circuit element 72 is a circuit element equipped with multiple quantum bits. The semiconductor device 40 according to the first embodiment is attached to the quantum circuit element 72 as a control chip that controls the on/off of the quantum bits. Note that instead of the semiconductor device 40, the semiconductor device 60 according to the second embodiment may be attached to the quantum circuit element 72.

In this type of information processing device 70, the quantum circuit element 72 and the semiconductor device 40 are both housed in the dilution refrigerator 71. This eliminates the path for heat to flow from the outside into the dilution refrigerator 71, allowing the dilution refrigerator 71 to efficiently cool the quantum circuit element 72.

In addition, since each GNR layer 14, 24 (see FIG. 12) is a true semiconductor that does not contain impurities, carriers are not generated from the impurities in each GNR layer 14, 24, but are injected into each GNR layer 14, 24 from the source electrode 36 or the drain electrode 37. Therefore, the problem of the activation rate of carriers generated from impurities decreasing at low temperatures does not occur, and it is possible to maintain the carrier concentration in each GNR layer 14, 24 even at low temperatures.

Unlike this embodiment, FIG. 26 is a schematic diagram of a case where a quantum circuit element 72 is controlled by a semiconductor device 81 having a MOSFET formed on a silicon substrate. In the MOSFET, carriers are generated from p-type impurities and n-type impurities implanted in the silicon substrate. Therefore, the carrier activation rate decreases at low temperatures, and the carrier concentration in the MOSFET decreases. To avoid this, in the example of FIG. 26, the semiconductor device 81 is placed outside the dilution refrigerator 71 and maintained at room temperature. The semiconductor device 81 and the quantum circuit element 72 are then connected by a cable 82.

In this case, heat flows from the outside to the inside of the dilution refrigerator 71 via the cable 82, making it difficult for the dilution refrigerator 71 to cool the quantum circuit element 72.

The following supplementary notes are further provided with respect to each of the embodiments described above.
(Supplementary Note 1) A channel layer in which a first graphene nanoribbon layer including a plurality of first graphene nanoribbons and a second graphene nanoribbon layer including a plurality of second graphene nanoribbons having a band gap narrower than that of the first graphene nanoribbons are stacked;
a source electrode connected to the channel layer;
a drain electrode connected to the channel layer;
a gate electrode provided at a position facing the channel layer between the source electrode and the drain electrode;
The semiconductor device, wherein at least one of the source electrode and the drain electrode is connected to the second graphene nanoribbon layer.
(Supplementary Note 2) The first graphene nanoribbon has a six-membered ring of carbon atoms included in a first plane,
The semiconductor device described in Appendix 1, characterized in that the second graphene nanoribbon has a six-membered ring of carbon atoms included in a second plane parallel to the first plane.
(Supplementary Note 3) A step of forming a first graphene nanoribbon layer having a plurality of first graphene nanoribbons on a first catalytic metal layer;
forming a second graphene nanoribbon layer on the second catalytic metal layer, the second graphene nanoribbon layer including a plurality of second graphene nanoribbons having a band gap smaller than that of the first graphene nanoribbon;
forming a channel layer by stacking the first graphene nanoribbon layer and the second graphene nanoribbon layer;
forming a source electrode and a drain electrode on the channel layer, thereby connecting at least one of the source electrode and the drain electrode to the second graphene nanoribbon layer;
forming a gate electrode at a position facing the channel layer between the source electrode and the drain electrode;
1. A method for manufacturing a semiconductor device comprising the steps of:
(Additional Note 4) The step of forming the channel layer includes:
floating the second graphene nanoribbon layer on water;
The method for manufacturing a semiconductor device described in Appendix 3, further comprising the step of stacking the first graphene nanoribbon layer and the second graphene nanoribbon layer by scooping up the second graphene nanoribbon layer from the water with the first graphene nanoribbon layer.
(Supplementary Note 5) The method further comprises forming a support layer on the second graphene nanoribbon layer,
The method for manufacturing a semiconductor device described in Appendix 4, characterized in that the step of floating the second graphene nanoribbon layer on the water is performed by floating the support layer on the water with the second graphene nanoribbon layer facing down.
(Supplementary Note 6) The method further comprises attaching the first graphene nanoribbon layer to a substrate,
The method for manufacturing a semiconductor device described in Appendix 4, characterized in that the step of stacking the first graphene nanoribbon layer and the second graphene nanoribbon layer is performed by immersing the substrate and the first graphene nanoribbon layer in the water, pulling the substrate out of the water, and scooping up the second graphene nanoribbon layer from the water with the first graphene nanoribbon layer.
(Supplementary Note 7) A quantum circuit element having a quantum bit;
A semiconductor device for controlling the quantum bit,
The semiconductor device includes:
a channel layer in which a first graphene nanoribbon layer including a plurality of first graphene nanoribbons and a second graphene nanoribbon layer including a plurality of second graphene nanoribbons having a band gap narrower than that of the first graphene nanoribbons are stacked;
a source electrode connected to the channel layer;
a drain electrode connected to the channel layer;
a gate electrode provided at a position facing the channel layer between the source electrode and the drain electrode;
The data processing device, characterized in that at least one of the source electrode and the drain electrode is connected to the second graphene nanoribbon layer.

5...transistor, 6...GNR layer, 7...source electrode, 8...drain electrode, 9...π orbital, 10...first support substrate, 11...first catalytic metal layer, 11a...surface, 12...first molecular layer, 13...first GNR, 13p...π orbital, 14...first GNR layer, 20...second support substrate, 21...second catalytic metal layer, 21a...surface, 22...second molecular layer, 23...second GNR, 23p...π orbital, 24...second GNR layer, 25...support layer, 30...container, 31...water, 33...channel layer, 35...substrate, 35a...silicon substrate, 35b...silicon oxide layer, 35c...surface, 36...source electrode, 37...drain electrode, 38...gate insulating layer, 39...gate electrode, 40...semiconductor device, 43...metal atoms, 51...third support substrate, 53...support layer, 60...semiconductor device, 70...information processing device, 71...dilution refrigerator, 72...quantum circuit element, 81...semiconductor device, 82...cable.

Claims (5)

a channel layer including a first graphene nanoribbon layer which is an intrinsic semiconductor containing no impurities and which includes a plurality of first graphene nanoribbons, and a second graphene nanoribbon layer which is an intrinsic semiconductor containing no impurities and which includes a plurality of second graphene nanoribbons having a band gap narrower than that of the first graphene nanoribbons;
a source electrode connected to the channel layer;
a drain electrode connected to the channel layer;
a gate electrode provided at a position facing the channel layer between the source electrode and the drain electrode;
The semiconductor device, wherein at least one of the source electrode and the drain electrode is connected to the second graphene nanoribbon layer. the first graphene nanoribbon has a six-membered ring of carbon atoms included in a first plane;
The semiconductor device according to claim 1 , wherein the second graphene nanoribbon has a six-membered ring of carbon atoms included in a second plane parallel to the first plane. forming a first graphene nanoribbon layer that is an intrinsic semiconductor free of impurities and includes a plurality of first graphene nanoribbons on the first catalytic metal layer;
forming a second graphene nanoribbon layer, which is an intrinsic semiconductor containing no impurities, on the second catalytic metal layer and includes a plurality of second graphene nanoribbons having a band gap smaller than that of the first graphene nanoribbon;
forming a channel layer by stacking the first graphene nanoribbon layer and the second graphene nanoribbon layer;
forming a source electrode and a drain electrode on the channel layer, thereby connecting at least one of the source electrode and the drain electrode to the second graphene nanoribbon layer;
forming a gate electrode at a position facing the channel layer between the source electrode and the drain electrode;
1. A method for manufacturing a semiconductor device comprising the steps of: The step of forming the channel layer includes:
floating the second graphene nanoribbon layer on water;
4. The method for manufacturing a semiconductor device according to claim 3, further comprising the step of stacking the first graphene nanoribbon layer and the second graphene nanoribbon layer by scooping up the second graphene nanoribbon layer from the water with the first graphene nanoribbon layer. A quantum circuit element having a quantum bit;
A semiconductor device for controlling the quantum bit,
The semiconductor device includes:
a channel layer including a first graphene nanoribbon layer which is an intrinsic semiconductor containing no impurities and which includes a plurality of first graphene nanoribbons, and a second graphene nanoribbon layer which is an intrinsic semiconductor containing no impurities and which includes a plurality of second graphene nanoribbons having a band gap narrower than that of the first graphene nanoribbons;
a source electrode connected to the channel layer;
a drain electrode connected to the channel layer;
a gate electrode provided at a position facing the channel layer between the source electrode and the drain electrode;
The data processing device, characterized in that at least one of the source electrode and the drain electrode is connected to the second graphene nanoribbon layer.

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