JP7510642B2 - Semiconductor elements and devices - Google Patents

Description

The technical field of this specification relates to semiconductor devices and devices.

Group III nitride semiconductors, such as GaN, have a high dielectric breakdown field and a high melting point. For this reason, Group III nitride semiconductors are expected to be a material for high-output, high-frequency, high-temperature semiconductor devices, replacing GaAs-based semiconductors. For this reason, HEMT elements that use Group III nitride semiconductors are being researched and developed.

For example, Patent Document 1 discloses a technique for simultaneously generating electrons and holes by polarization junction (see FIG. 4 of Patent Document 1, etc.). Patent Document 2 discloses a technique for forming a GaN layer, an AlGaN layer, a GaN layer, and a p-type GaN layer in that order (paragraph [0034] of Patent Document 2). This raises the energy Ev at the top of the valence band of the p-type GaN layer to the Fermi level Ef, thereby generating a two-dimensional hole gas.

JP 2007-134607 A WO2011/162243

Semiconductor elements are generally required to have excellent electrical characteristics. Examples of such electrical characteristics include high voltage resistance, low on-resistance, short response time, ability to handle large currents, and suppression of leakage current.

The problem that the technology of this specification aims to solve is to provide a semiconductor element and device that can suppress the formation of a strong electric field around wiring electrodes.

The semiconductor element in the first aspect has a first semiconductor layer, a second semiconductor layer above the first semiconductor layer, a third semiconductor layer above the second semiconductor layer, a fourth semiconductor layer above the third semiconductor layer, a source electrode and a drain electrode above the second semiconductor layer or the third semiconductor layer, and a gate electrode above the fourth semiconductor layer. The first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are group III nitride semiconductor layers. The band gap of the second semiconductor layer is larger than the band gaps of the first semiconductor layer and the third semiconductor layer. The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are undoped semiconductor layers. The fourth semiconductor layer is a p-type semiconductor layer. At least one of the gate electrode, the source electrode, and the drain electrode has a contact electrode, a wiring electrode, and a pad electrode. The wiring electrode connects the contact electrode and the pad electrode. The wiring electrode has a curved portion curved in an arc shape. A region where the second semiconductor layer or the third semiconductor layer contacts the source electrode is defined as a source electrode contact region, and a region where the fourth semiconductor layer contacts the gate electrode is defined as a gate electrode contact region.The source electrode contact regions exist at intervals from each other, and the gate electrode contact region is a ring-shaped pattern surrounding each source electrode contact region.

In this semiconductor element, the wiring electrodes have curved portions that are curved in an arc shape. This prevents a strong electric field from forming at or around the curved portions even when a high voltage is applied. In addition, the internal stress in the insulating layer is also alleviated.

This specification provides semiconductor elements and devices that have at least one excellent electrical characteristic.

1 is a top view of a semiconductor element according to a first embodiment; 1 is a diagram showing a stacked structure of a semiconductor element according to a first embodiment; 3A and 3B are diagrams illustrating electrode contact areas in a device functional region of the semiconductor device according to the first embodiment. 2 is an enlarged view of the periphery of a source contact electrode and a drain contact electrode of the semiconductor element of the first embodiment. FIG. 1 is a diagram (part 1) showing a cross-sectional structure around a source electrode exposed region of a semiconductor element according to a first embodiment; 2 is a diagram showing a cross-sectional structure around a drain electrode exposed region of the semiconductor element according to the first embodiment; 2 is a diagram showing a cross-sectional structure around a gate electrode exposed region of the semiconductor element according to the first embodiment; FIG. 2 is a diagram (part 2) showing a cross-sectional structure around a source electrode exposed region of the semiconductor element according to the first embodiment. 3A and 3B are diagrams illustrating the positional relationship between a source electrode contact region and a drain electrode contact region of the semiconductor element of the first embodiment and an insulating layer. 2 is a diagram showing wiring of a gate electrode of the semiconductor element according to the first embodiment; FIG. 3 is a diagram showing wiring of a source electrode of the semiconductor element according to the first embodiment; FIG. 2A and 2B are diagrams illustrating a stacked structure of a source electrode and a drain electrode of the semiconductor element according to the first embodiment. 1 is a diagram showing a stacked structure of a gate electrode of a semiconductor element according to a first embodiment; 1A and 1B are diagrams illustrating two-dimensional electron gas and two-dimensional hole gas in a semiconductor device according to a first embodiment. FIG. 2 is a diagram showing a band structure of the semiconductor element according to the first embodiment. 4 is a schematic diagram conceptually showing an electric field when a reverse bias is applied to a gate electrode of the semiconductor element of the first embodiment; FIG. 1A to 1C are diagrams for explaining the manufacturing method of the semiconductor element according to the first embodiment; 1A to 1C are diagrams (part 2) for explaining the method for manufacturing the semiconductor element according to the first embodiment; 13A to 13C are views for explaining the method for manufacturing the semiconductor element according to the first embodiment (part 3). FIG. 13 is a top view of a semiconductor element according to a second embodiment. 13A and 13B are diagrams illustrating a stacked structure of a semiconductor element according to a third embodiment. 13 is a diagram showing the periphery of a gate pad electrode of a semiconductor element according to a fourth embodiment; 13 is a diagram showing a cross-sectional structure around a drain electrode exposed region of a semiconductor element according to a fourth embodiment; FIG. FIG. 13 is a top view of a semiconductor element according to a modified example of the fourth embodiment. FIG. 13 is an enlarged view of the periphery of a gate pad electrode in a semiconductor element according to a modified example of the fourth embodiment. 13A and 13B are diagrams illustrating a stacked structure of a semiconductor element according to an eighth embodiment. 13A and 13B are diagrams illustrating electrode formation regions of a semiconductor element according to an eighth embodiment. 13 is a diagram showing an electrode formation region of a semiconductor element in a modified example of the eighth embodiment. FIG. FIG. 23 is a diagram (part 1) showing a stacked structure of a semiconductor element in a modified example of the eighth embodiment; FIG. 23 is a diagram (part 2) showing a stacked structure of a semiconductor element in a modified example of the eighth embodiment; FIG. 23 is a diagram (part 3) showing a stacked structure of a semiconductor element in a modified example of the eighth embodiment; FIG. 13 shows a FET in which a gate electrode contact region GC1 surrounds a source electrode contact region SC1. FIG. 1 shows a FET where a gate electrode contact region GC1 is between a source electrode contact region SC1 and a drain electrode contact region DC1. 1 is a graph showing the relationship between gate voltage and drain current when 0.1 V is applied to the drain electrode of a FET. 1 is a graph showing the relationship between gate voltage and drain current of a FET. 1 is a graph showing the relationship between drain voltage and drain current of a FET. 1 is a graph showing the relationship between drain voltage and drain current in a FET when it is off. 1 is a graph showing the relationship between drain voltage and gate current in a FET when it is off. FIG. 1 is a circuit diagram used for evaluating a FET. 1 is a graph showing output values in an evaluation of a FET. FIG. 2 is a diagram illustrating the definitions of the rise time tr and fall time tf of a FET. 1 is a table showing characteristics of FETs. 13 is a graph showing the relationship between the junction area between a second undoped GaN layer (third semiconductor layer) and an Mg-doped pGaN layer (fourth semiconductor layer) in a FET and the breakdown voltage of a semiconductor element. 1 is a graph showing the relationship between gate length and response time of a FET. 11 is a graph showing the relationship between the junction area between the third semiconductor layer and the fourth semiconductor layer excluding the polarization super junction region PSJ1 in a FET and the response time. 1 is a graph showing the relationship between dislocation density and junction area in a FET. 47 is a table summarizing the data in FIG. 46. 1 is a graph showing the relationship between dislocation density and source-drain distance in a FET. 49 is a table summarizing the data in FIG. 48. 1 is a graph showing the relationship between dislocation density and response time in a FET. 51 is a table summarizing the data in FIG. 50. 1 is a graph showing the relationship between the polarization superjunction length Lpsj and the normalized on-resistance in a FET. 1 is a graph showing the relationship between the source-drain distance and the normalized on-resistance in a FET. 1 is a table showing the relationship between dislocation density in a FET and the characteristics of a semiconductor device. 1 is a table showing the relationship between the chip size of a FET and the current value when the drain voltage Vd is 2 V. 1 is a graph showing the relationship between the active region area of a FET and the current value when the drain voltage Vd is 2 V. 13 is a table showing the breakdown voltage of a FET when the polarization super junction length Lpsj and the distance Lsd between the source contact electrode S1c and the drain contact electrode D1c in the FET are changed. 13 is a table showing the breakdown voltage of a FET when the polarization super junction length Lpsj and the distance Lsd between the source contact electrode S1c and the drain contact electrode D1c in the FET are not changed. 1 is a graph showing the relationship between the polarization superjunction length Lpsj in a FET and the breakdown voltage of the FET. 1 is a graph showing the relationship between the distance between the drain electrode contact region DC1 and the polarization superjunction surface in a FET and the breakdown voltage. 1 is a graph showing the relationship between the polarization superjunction length Lpsj in a FET and the breakdown voltage of a semiconductor element. 1 is a graph showing the relationship between drain voltage and drain current of a FET. 1 is a graph showing the relationship between gate voltage and drain current when the drain voltage of a FET is 0.1 V. 1 is a graph showing the relationship between drain voltage and drain current when a FET is off. 1 is a graph showing the relationship between drain voltage and gate current when a FET is off. 1 is a graph showing the reverse recovery time characteristics of a Schottky barrier diode having a polarization super junction length Lpsj of 20 μm. 1 is a graph showing forward characteristics of a Schottky barrier diode. 1 is a graph showing reverse characteristics of a Schottky barrier diode. 13 is a table showing the breakdown voltage of a Schottky barrier diode when the polarization super junction length Lpsj and the distance Lac between the anode electrode contact region AC1 and the cathode electrode contact region CC1 are changed.

Specific embodiments will be described below using a semiconductor element and its manufacturing method and apparatus as examples. However, the technology of this specification is not limited to these embodiments. In this specification, an undoped semiconductor layer means a semiconductor layer that is not intentionally doped with impurities. The thickness ratios of the layers in the drawings do not necessarily reflect the actual thickness ratios.

First Embodiment
1. Structure of the semiconductor element 1-1. Regions of the semiconductor element Fig. 1 is a top view of a semiconductor element 100 according to a first embodiment. The semiconductor element 100 is a field effect transistor (FET). As shown in Fig. 1, the semiconductor element 100 has an element function region FR1, a source electrode exposed region SR1, a drain electrode exposed region DR1, and gate electrode exposed regions GR1 and GR2.

The element functional region FR1 is a region that functions as an element. As described below, the element functional region FR1 is a region where current actually flows through the semiconductor. The element functional region FR1 is covered with an insulator such as polyimide. Therefore, the semiconductor or metal is not exposed in the element functional region FR1.

The source electrode exposed region SR1 is a region where the source electrode is exposed. The source electrode exposed region SR1 is a region where a pad electrode for electrical connection to an external electrode is exposed. The source electrode exposed region SR1 has an end SR1a, an end SR1b, and a central portion SR1c. The end SR1a and the end SR1b extend in a direction away from the central portion SR1c on the side of the element function region FR1. The source electrode exposed region SR1 widens as it approaches the element function region FR1 and the drain electrode exposed region DR1.

The drain electrode exposed region DR1 is the region where the drain electrode is exposed. The drain electrode exposed region DR1 is the region where the pad electrode for electrical connection to an external electrode is exposed.

The gate electrode exposed regions GR1 and GR2 are regions where the gate electrode is exposed. The gate electrode exposed regions GR1 and GR2 are regions where the pad electrode for electrical connection to the external electrode is exposed.

The source electrode exposed region SR1, the drain electrode exposed region DR1, and the gate electrode exposed regions GR1 and GR2 are formed on the semiconductor via an insulating layer. Therefore, in the source electrode exposed region SR1, the drain electrode exposed region DR1, and the gate electrode exposed regions GR1 and GR2, the source electrode, the drain electrode, and the gate electrode are not in contact with the semiconductor.

The source electrode exposed region SR1 is disposed opposite the drain electrode exposed region DR1 with the element function region FR1 sandwiched therebetween. The combined region of the source electrode exposed region SR1 and the gate electrode exposed regions GR1 and GR2 is disposed in a strip shape. The drain electrode exposed region DR1 is disposed in a strip shape.

The gate electrode exposed regions GR1 and GR2 are formed on the side of the source electrode exposed region SR1. The gate electrode exposed regions GR1 and GR2 are arranged opposite the drain electrode exposed region DR1 with the element function region FR1 sandwiched therebetween. The source electrode exposed region SR1 is arranged between the gate electrode exposed region GR1 and the gate electrode exposed region GR2. The gate electrode exposed region GR1 faces the end SR1a and the center SR1c of the source electrode exposed region SR1. The gate electrode exposed region GR2 faces the end SR1b and the center SR1c of the source electrode exposed region SR1.

The end SR1a of the source electrode exposed region SR1 is located between the gate electrode exposed region GR1 and the element functional region FR1. The end SR1b of the source electrode exposed region SR1 is located between the gate electrode exposed region GR2 and the element functional region FR1. At the position facing the element functional region FR1, the width of the source electrode exposed region SR1 and the width of the drain electrode exposed region DR1 are approximately equal.

1-2. Element functional region 1-2-1. Cross-sectional structure Fig. 2 is a diagram showing a laminated structure of the semiconductor element 100 of the first embodiment. Fig. 2 is a diagram showing a cross section taken along line II-II of Fig. 1. As shown in Fig. 2, the semiconductor element 100 has a sapphire substrate Sub1, a buffer layer Bf1, a first semiconductor layer 110, a second semiconductor layer 120, a third semiconductor layer 130, a fourth semiconductor layer 140, a source electrode S1, a drain electrode D1, a gate electrode G1, and a polyimide layer PI1.

The sapphire substrate Sub1 is a support substrate that supports the semiconductor layer. The sapphire substrate Sub1 may be, for example, a growth substrate on which the semiconductor layer is grown from the +c plane. The thickness of the sapphire substrate Sub1 is, for example, 50 μm or more and 500 μm or less.

The buffer layer Bf1 is formed on the sapphire substrate Sub1. The buffer layer Bf1 is a low-temperature GaN buffer layer. The buffer layer Bf1 may be, for example, a low-temperature AlN buffer layer. The thickness of the buffer layer Bf1 is, for example, 20 nm or more and 50 nm or less.

The first semiconductor layer 110 is formed above the buffer layer Bf1. The first semiconductor layer 110 is, for example, a GaN layer. The first semiconductor layer 110 is not intentionally doped with impurities. The film thickness of the first semiconductor layer 110 is, for example, 300 nm or more and 5000 nm or less.

The second semiconductor layer 120 is formed above the first semiconductor layer 110. The second semiconductor layer 120 is in direct contact with the first semiconductor layer 110. The second semiconductor layer 120 is, for example, an AlGaN layer. The Al composition of the second semiconductor layer 120 is, for example, 0.1 to 0.5. The band gap of the second semiconductor layer 120 is larger than the band gaps of the first semiconductor layer 110 and the third semiconductor layer 130. The second semiconductor layer 120 is not intentionally doped with impurities. The film thickness of the second semiconductor layer 120 is, for example, 20 nm to 150 nm.

The third semiconductor layer 130 is formed above the second semiconductor layer 120. The third semiconductor layer 130 is in direct contact with the second semiconductor layer 120. The third semiconductor layer 130 is, for example, a GaN layer. The third semiconductor layer 130 is not intentionally doped with impurities. The third semiconductor layer 130 is partitioned by being sandwiched between the recesses X1 and X2. The third semiconductor layer 130 also surrounds the recess X1, which is the formation region of the source electrode S1. The film thickness of the third semiconductor layer 130 is, for example, 20 nm or more and 150 nm or less.

The fourth semiconductor layer 140 is formed above the third semiconductor layer 130. The fourth semiconductor layer 140 is in direct contact with the third semiconductor layer 130. The fourth semiconductor layer 140 is, for example, a p-type GaN layer. The fourth semiconductor layer 140 is doped with a p-type impurity. The p-type impurity is, for example, Mg. The impurity concentration of the fourth semiconductor layer 140 is, for example, 1×10 ¹⁷ cm ⁻³ or more and 3×10 ²⁰ cm ⁻³ or less. The closer to the gate electrode G1, the higher the impurity concentration of the fourth semiconductor layer 140. The film thickness of the fourth semiconductor layer 140 is, for example, 20 nm or more and 150 nm or less.

The source electrode S1 is formed on the second semiconductor layer 120. The source electrode S1 is in direct contact with the second semiconductor layer 120. A recess X1 is formed where the source electrode S1 is formed. The recess X1 reaches from the fourth semiconductor layer 140 to partway through the second semiconductor layer 120. The second semiconductor layer 120 is exposed at the bottom of the recess X1. The source electrode S1 is formed on the recess X1.

The drain electrode D1 is formed on the second semiconductor layer 120. The drain electrode D1 is in direct contact with the second semiconductor layer 120. A recess X2 is formed where the drain electrode D1 is formed. The recess X2 reaches from the fourth semiconductor layer 140 to partway through the second semiconductor layer 120. The second semiconductor layer 120 is exposed at the bottom of the recess X2. The drain electrode D1 is formed on the recess X2.

The gate electrode G1 is formed on the fourth semiconductor layer 140. The gate electrode G1 is in direct contact with the fourth semiconductor layer 140.

The polyimide layer PI1 covers the surface of the semiconductor layer. The polyimide layer PI1 also covers each electrode in the element functional region FR1.

In this way, the first semiconductor layer 110, the second semiconductor layer 120, the third semiconductor layer 130, and the fourth semiconductor layer 140 are Group III nitride semiconductor layers. The first semiconductor layer 110, the second semiconductor layer 120, and the third semiconductor layer 130 are undoped semiconductor layers. The fourth semiconductor layer 140 is a p-type semiconductor layer.

The third semiconductor layer 130 has a recess X3 and a region in contact with the fourth semiconductor layer 140. The recess X3 reaches from the fourth semiconductor layer 140 to partway through the third semiconductor layer 130. The film thickness of the third semiconductor layer 130 in the recess X3 is thinner than the film thickness of the third semiconductor layer 130 in contact with the fourth semiconductor layer 140.

The recesses X1 and X2 are not connected. As described below, the recesses X1 are rod-shaped, and the recesses X2 are comb-shaped. The third semiconductor layer 130 is disposed between the recesses X1 and X2.

1-2-2. Planar structure Fig. 3 is a diagram showing electrode contact regions in the element functional region FR1 of the semiconductor element 100 of the first embodiment. Fig. 3 shows the electrode contact regions in the element functional region FR1 projected onto the second semiconductor layer 120. The semiconductor element 100 has a source electrode contact region SC1, a drain electrode contact region DC1, and a gate electrode contact region GC1.

The source electrode contact region SC1 is the region where the source electrode S1 and the second semiconductor layer 120 are in contact. The drain electrode contact region DC1 is the region where the drain electrode D1 and the second semiconductor layer 120 are in contact. The gate electrode contact region GC1 is the region where the gate electrode G1 and the fourth semiconductor layer 140 are in contact.

The source electrode contact region SC1 is, for example, a first electrode contact region. The drain electrode contact region DC1 is, for example, a second electrode contact region. The gate electrode contact region GC1 is, for example, a third electrode contact region.

The source electrode contact region SC1, the drain electrode contact region DC1, and the gate electrode contact region GC1 do not overlap with each other when projected onto the sapphire substrate Sub1, the first semiconductor layer 110, or the second semiconductor layer 120.

The source electrode contact region SC1 has a rod-like shape. The gate electrode contact region GC1 surrounds the source electrode contact region SC1 without contacting it. Strictly speaking, the gate electrode contact region GC1 is on the fourth semiconductor layer 140, and the source electrode contact region SC1 is on the second semiconductor layer 120.

The region obtained by projecting the gate electrode contact region GC1, where the gate electrode G1 and the fourth semiconductor layer 140 are in contact, onto the second semiconductor layer 120 surrounds, in a non-contact manner, the periphery of the source electrode contact region SC1, where the source electrode S1 and the second semiconductor layer 120 are in contact. When the gate electrode contact region GC1 and the source electrode contact region SC1 are projected onto the sapphire substrate Sub1 or the first semiconductor layer 110, the gate electrode contact region GC1 surrounds, in a non-contact manner, the periphery of the source electrode contact region SC1.

The drain electrode contact region DC1 has a comb-tooth shape. The source electrode contact region SC1 and the gate electrode contact region GC1 are arranged in a sandwiched state between the comb teeth of the drain electrode contact region DC1. In other words, the rod-like shape of the source electrode contact region SC1 is arranged between the comb teeth of the drain electrode contact region DC.

The shape of the contact surface where the first semiconductor layer 110 and the second semiconductor layer 120 are in contact is rectangular. The longitudinal direction of the region obtained by projecting the rod-like shape of the source electrode contact region SC1 onto the contact surface is arranged in a direction parallel to the short side of the rectangle. As shown in Figures 2 and 3, in a cross section perpendicular to the longitudinal direction of the rod-like shape of the source electrode contact region SC1, the source electrode contact region SC1 and the drain electrode contact region DC1 are arranged alternately.

As shown in FIG. 3, the source contact electrode S1c has an arc-shaped portion S1c1 at the tip and a rod-shaped portion S1c2 at the other end. The rod-shaped portion S1c2 of the source contact electrode S1c is sandwiched between the arc-shaped portion S1c1 and the arc-shaped portion S1c1.

The drain contact electrode D1c has an arc-shaped portion D1c1 at the tip and a rod-shaped portion D1c2 other than the tip. The rod-shaped portion D1c2 of the drain contact electrode D1c is not sandwiched between the arc-shaped portions D1c1 and D1c1.

The gate contact electrode G1c has an arc-shaped portion G1c1 at the tip and a strip-shaped portion G1c2 other than the tip. The arc-shaped portion G1c1 of the gate contact electrode G1c is located between the strip-shaped portions G1c2. The arc-shaped portion G1c1 and the strip-shaped portion G1c2 of the gate contact electrode G1c are annular in shape.

As shown in FIG. 1, the number of rod-shaped portions of the source electrode contact region SC1 is one more than the number of comb-tooth shaped rod-shaped portions of the drain electrode contact region DC1. Thus, the electrode contact region located on the outermost side of the semiconductor element 100 is the source electrode contact region SC1, not the drain electrode contact region DC1.

Figure 4 is an enlarged view of the periphery of the source contact electrode S1c and the drain contact electrode D1c of the semiconductor element 100 of the first embodiment.

2, the semiconductor device 100 has a polarization super junction region PSJ1. The polarization super junction region PSJ1 is a region that has the first semiconductor layer 110, the second semiconductor layer 120, and the third semiconductor layer 130, but does not have the fourth semiconductor layer 140. In other words, the polarization super junction region PSJ1 is a region in which the third semiconductor layer 130 is formed but the fourth semiconductor layer 140 is not formed, and is located between the gate electrode contact region GC1 and the drain electrode contact region DC1.

In this way, the polarization super junction region PSJ1 does not have a p-type semiconductor layer. The polarization super junction region PSJ1 is located in the region sandwiched between the gate electrode contact region GC1 and the drain electrode contact region DC1. The polarization super junction length Lpsj is the length of the polarization super junction region PSJ1 in the direction connecting the shortest distance from the source electrode contact region SC1 to the drain electrode contact region DC1.

1-3. Source electrode exposed region FIG. 5 is a diagram (part 1) showing a cross-sectional structure around the source electrode exposed region SR1 of the semiconductor element 100 of the first embodiment. FIG. 5 is a diagram showing the V-V cross section of FIG. 1. As shown in FIG. 5, an insulating layer IL1 is formed on the first semiconductor layer 110. Then, a source electrode S1 is formed on the insulating layer IL1. In addition, a polyimide layer PI1 is formed between the gate wiring electrode G1w of the gate electrode G1 and the source wiring electrode S1w of the source electrode S1. The polyimide layer PI1 insulates the gate electrode G1 from the source electrode S1. In the source electrode exposed region SR1, the source electrode S1 and the semiconductor are not electrically connected.

A groove U1 is formed in the first semiconductor layer 110 along at least a portion of the source electrode exposed region SR1. Due to the presence of the groove U1, the distance between the first semiconductor layer 110 and the source electrode S1 can be increased. In other words, the insulation between the first semiconductor layer 110 and the source electrode S1 is improved.

The source electrode S1 has a source contact electrode S1c, a source wiring electrode S1w, and a source pad electrode S1p. The source contact electrode S1c is in direct contact with the second semiconductor layer 120. The source wiring electrode S1w connects the source contact electrode S1c and the source pad electrode S1p. The source pad electrode S1p is an electrode for electrically connecting to an external power supply.

1-4. Drain electrode exposed region Fig. 6 is a diagram showing a cross-sectional structure around the drain electrode exposed region DR1 of the semiconductor element 100 of the first embodiment. Fig. 6 is a diagram showing a VI-VI cross section of Fig. 1. As shown in Fig. 6, an insulating layer IL1 is formed on the first semiconductor layer 110. Then, a drain electrode D1 is formed on the insulating layer IL1. In addition, a polyimide layer PI1 fills the gap between the drain electrode D1 and the insulating layer IL1. In the drain electrode exposed region DR1, the drain electrode D1 and the semiconductor are not electrically connected.

A groove U2 is formed in the first semiconductor layer 110 along at least a portion of the drain electrode exposed region DR1. Due to the presence of the groove U2, the distance between the first semiconductor layer 110 and the drain electrode D1 can be increased. In other words, the insulation between the first semiconductor layer 110 and the drain electrode D1 is improved.

The drain electrode D1 has a drain contact electrode D1c, a drain wiring electrode D1w, and a drain pad electrode D1p. The drain contact electrode D1c is in direct contact with the second semiconductor layer 120. The drain wiring electrode D1w connects the drain contact electrode D1c and the drain pad electrode D1p. The drain pad electrode D1p is an electrode for electrically connecting to an external power source.

1-5. Gate electrode exposed region Fig. 7 is a diagram showing a cross-sectional structure around the gate electrode exposed region GR1 of the semiconductor element 100 of the first embodiment. Fig. 7 is a diagram showing a cross section taken along line VII-VII in Fig. 1. As shown in Fig. 7, an insulating layer IL1 is formed on the first semiconductor layer 110. Then, a gate electrode G1 is formed on the insulating layer IL1. In the gate electrode exposed region GR1, the gate electrode G1 and the semiconductor are not electrically connected.

The gate electrode G1 has a gate contact electrode G1c, a gate wiring electrode G1w, and a gate pad electrode G1p. The gate contact electrode G1c is in direct contact with the fourth semiconductor layer 140. The gate wiring electrode G1w connects the gate contact electrode G1c and the gate pad electrode G1p. The gate pad electrode G1p is an electrode for electrically connecting to an external power supply.

1-6. Formation region of insulating film FIG. 8 is a diagram (part 2) showing a cross-sectional structure around the source electrode exposed region SR1 of the semiconductor element 100 of the first embodiment. FIG. 8 is a diagram showing a VIII-VIII cross section of FIG. 1. As shown in FIG. 8, the drain contact electrode D1c of the drain electrode D1 extends to the source pad electrode S1p side. On the extension of the drain contact electrode D1c of the drain electrode D1 extending to the source pad electrode S1p side, the insulating layer IL1 does not contact the first semiconductor layer 110 and the second semiconductor layer 120. However, the insulating layer IL1 is formed on the first semiconductor layer 110 and contacts the first semiconductor layer 110 at the bottom of the groove U1.

Figure 9 is a diagram showing the positional relationship between the source electrode contact region SC1 and the drain electrode contact region DC1 of the semiconductor element 100 of the first embodiment and the insulating layer IL1. Figure 9 is a plan view showing the insulating layer IL1 and the source electrode contact region SC1 and the drain electrode contact region DC1.

As shown in FIG. 9, the insulating layer IL1 has a protrusion IL1a that protrudes toward the source electrode contact region SC1 and the gate electrode contact region GC1. As shown in FIG. 9, the protrusion IL1a is located between the gate wiring electrode G1w and the first semiconductor layer 110, and is disposed on a longitudinal extension of the source electrode contact region SC1.

As shown in Figures 5 and 9, the insulating layer IL1 is in contact with the second semiconductor layer 120 at the position of the protrusion IL1a. As shown in Figures 8 and 9, the insulating layer IL1 is not in contact with the second semiconductor layer 120 at any position other than the protrusion IL1a. As shown in Figure 5, the protrusion IL1a of the insulating layer IL1 is in contact with the second semiconductor layer 120, the third semiconductor layer 130, the fourth semiconductor layer 140, the gate contact electrode G1c, and the gate wiring electrode G1w.

1-7. Electrode Wiring Structure Fig. 10 is a diagram showing wiring of the gate electrode G1 of the semiconductor element 100 of the first embodiment. The gate electrode G1 in the gate electrode contact region GC1 is connected to the gate wiring electrode GW2. The gate wiring electrode GW2 is formed in a direction parallel to the longitudinal direction of the source electrode contact region SC1. The gate wiring electrode GW1 is electrically connected to a plurality of gate contact electrodes G1c via the gate wiring electrode GW2. The gate wiring electrode GW1 and the gate wiring electrode GW2 are part of the gate wiring electrode G1w.

Figure 11 is a diagram showing the wiring of the source electrode S1 of the semiconductor element 100 of the first embodiment. The source contact electrode S1c is connected to the source wiring electrode SW2. The source wiring electrode SW2 is formed in a direction parallel to the longitudinal direction of the source electrode contact region SC1. The source wiring electrode SW1 is electrically connected to a plurality of source contact electrodes S1c via the source wiring electrode SW2. The source wiring electrode SW1 and the source wiring electrode SW2 are part of the source wiring electrode S1w.

As shown in FIG. 11, the area where the source wiring electrode S1w of the source electrode S1 is projected onto the second semiconductor layer 120 does not overlap with the area where the drain wiring electrode D1w of the drain electrode D1 is projected onto the second semiconductor layer 120.

As shown in Figures 10 and 11, the area where the source wiring electrode SW2 is projected onto the second semiconductor layer 120 overlaps with the area where the gate wiring electrode GW2 is projected onto the second semiconductor layer 120.

The area where the source wiring electrode S1w of the source electrode S1 is projected onto the second semiconductor layer 120 partially overlaps with the area where the gate wiring electrode G1w of the gate electrode G1 is projected onto the second semiconductor layer 120. The area where the drain wiring electrode D1w of the drain electrode D1 is projected onto the second semiconductor layer 120 does not overlap with the area where the gate wiring electrode G1w of the gate electrode G1 is projected onto the second semiconductor layer 120.

1-8. Electrode stacking structure 1-8-1. Source electrode and drain electrode As described above, the source electrode S1 and the drain electrode D1 are formed on the second semiconductor layer 120. When the second semiconductor layer 120 is an AlGaN layer, the source electrode S1 and the drain electrode D1 are in contact with the AlGaN layer.

Figure 12 is a diagram showing the layered structure of the source electrode S1 and drain electrode D1 of the semiconductor element 100 of the first embodiment. The source electrode S1 has a first metal layer S1a1, a second metal layer S1a2, a third metal layer S1a3, a fourth metal layer S1a4, a fifth metal layer S1a5, and a sixth metal layer S1a6, which are formed in this order from the second semiconductor layer 120 side. Other metal layers may be present between the third metal layer S1a3 and the fourth metal layer S1a4.

The first metal layer S1a1 is, for example, V. The second metal layer S1a2 is, for example, Al. The third metal layer S1a3 is, for example, Ti. The fourth metal layer S1a4 is, for example, Ti. The fifth metal layer S1a5 is, for example, Au. The sixth metal layer S1a6 is, for example, Au. The above are examples, and metals or alloys other than those listed above may also be used.

The film thickness of the first metal layer S1a1 is, for example, 5 nm or more and 60 nm or less. The film thickness of the second metal layer S1a2 is, for example, 20 nm or more and 400 nm or less. The film thickness of the third metal layer S1a3 is, for example, 5 nm or more and 60 nm or less. The film thickness of the fourth metal layer S1a4 is, for example, 5 nm or more and 60 nm or less. The film thickness of the fifth metal layer S1a5 is, for example, 50 nm or more and 400 nm or less. The film thickness of the sixth metal layer S1a6 is, for example, 1000 nm or more and 15000 nm or less. The above are examples, and values other than the above may be used.

The metal layers from the first metal layer S1a1 to the fifth metal layer S1a5 correspond to, for example, the source contact electrode S1c. The sixth metal layer S1a6 corresponds to, for example, the source wiring electrode S1w.

The drain electrode D1 has a first metal layer D1a1, a second metal layer D1a2, a third metal layer D1a3, a fourth metal layer D1a4, a fifth metal layer D1a5, and a sixth metal layer D1a6, which are formed in this order from the second semiconductor layer 120 side. The types of metal and film thicknesses of these metal layers are the same as those of the source electrode S1. Of course, the types of metal and film thicknesses of these metal layers may be different from those of the source electrode S1.

13 is a diagram showing a laminated structure of the gate electrode G1 of the semiconductor element 100 of the first embodiment. The gate electrode G1 has a first metal layer G1a1, a second metal layer G1a2, a third metal layer G1a3, and a fourth metal layer G1a4 formed in this order from the fourth semiconductor layer 140 side.

The first metal layer G1a1 is, for example, Ni. The second metal layer G1a2 is, for example, Au. The third metal layer G1a3 is, for example, Ni. The fourth metal layer G1a4 is, for example, Au. The above are examples, and metals or alloys other than those listed above may also be used.

The film thickness of the first metal layer G1a1 is, for example, 5 nm or more and 100 nm or less. The film thickness of the second metal layer G1a2 is, for example, 5 nm or more and 300 nm or less. The film thickness of the third metal layer G1a3 is, for example, 5 nm or more and 100 nm or less. The film thickness of the fourth metal layer G1a4 is, for example, 50 nm or more and 400 nm or less. The above are examples, and values other than the above may be used.

The metal layers from the first metal layer G1a1 to the third metal layer G1a3 correspond to, for example, the gate contact electrode G1c. The fourth metal layer G1a4 corresponds to, for example, the gate wiring electrode G1w. In addition, the metal layers from the first metal layer G1a1 to the fourth metal layer G1a4 correspond to the gate contact electrode G1c, and the gate wiring electrode G1w may be present on top of it.

2. Operation Principle of Semiconductor Device 2-1. Two-dimensional electron gas and two-dimensional hole gas Fig. 14 is a diagram showing the two-dimensional electron gas and two-dimensional hole gas of the semiconductor device 100 of the first embodiment. Fig. 15 is a diagram showing the band structure of the semiconductor device 100 of the first embodiment.

As shown in FIG. 14, the first semiconductor layer 110 and the second semiconductor layer 120 are heterojunctioned. This causes piezoelectric polarization and spontaneous polarization, and a positive fixed charge is induced in the second semiconductor layer 120 on the first semiconductor layer 110 side. In addition, the second semiconductor layer 120 and the third semiconductor layer 130 are heterojunctioned. This causes piezoelectric polarization and spontaneous polarization, and a negative fixed charge is induced in the second semiconductor layer 120 on the third semiconductor layer 130 side.

As a result, as shown in Figures 14 and 15, two-dimensional electron gas (2DEG) is generated inside the first semiconductor layer 110 on the second semiconductor layer 120 side, and two-dimensional hole gas (2DHG) is generated inside the third semiconductor layer 130 on the second semiconductor layer 120 side.

In addition, the p-type fourth semiconductor layer 140 is in contact with the third semiconductor layer 130. This raises the energy of the upper end of the valence band on the second semiconductor layer 120 side of the third semiconductor layer 130. This promotes the generation of two-dimensional hole gas (2DHG).

In this way, two-dimensional electron gas (2DEG) and two-dimensional hole gas (2DHG) are generated at the heterointerface, as shown in Figures 14 and 15.

2-2. Threshold voltage When the gate voltage applied to the gate electrode G1 is equal to or higher than the threshold voltage Vth, piezoelectric polarization and spontaneous polarization occur as described above. Then, two-dimensional electron gas (2DEG) and two-dimensional hole gas (2DHG) are generated. In this state, a current flows between the source electrode S1 and the drain electrode D1. The threshold voltage Vth is, for example, about -5V.

When the gate voltage applied to the gate electrode G1 is less than the threshold voltage Vth, no piezoelectric polarization or spontaneous polarization occurs. Therefore, almost no current flows between the source electrode S1 and the drain electrode D1. In reality, a small leakage current flows between the source electrode S1 and the drain electrode D1.

When the gate voltage is set to less than the threshold voltage Vth, holes are extracted from the fourth semiconductor layer 140. As a result, no positive charge is supplied from the gate electrode G1 to the third semiconductor layer 130, and the two-dimensional electron gas (2DEG) and the two-dimensional hole gas (2DHG) disappear almost simultaneously.

The drain current flows through the drain electrode D1, the second semiconductor layer 120, the two-dimensional electron gas (2DEG) of the first semiconductor layer 110, the second semiconductor layer 120, and the source electrode S1. The two-dimensional hole gas (2DHG) is only generated together with the two-dimensional electron gas (2DEG) when the semiconductor element 100 is turned on and off, and is not directly used to pass a current through the semiconductor element 100.

3. Electrical Characteristics of the Semiconductor Element Here, the relationship between the structure of the semiconductor element 100 and the electrical characteristics of the semiconductor element 100 will be described.

16 is a schematic diagram conceptually showing the electric field when a reverse bias is applied to the gate electrode G1 of the semiconductor element 100 of the first embodiment. The horizontal axis of FIG. 16 indicates the position of the semiconductor element 100. The vertical axis of FIG. 16 is the electric field. When a reverse bias is applied, holes in the semiconductor element 100 are extracted. As a result, the two-dimensional electron gas (2DEG) and the two-dimensional hole gas (2DHG) disappear. Then, the first semiconductor layer 110, the second semiconductor layer 120, and the third semiconductor layer 130 are depleted. As a result, the strength of the electric field becomes uniform across the width of the polarization super junction region PSJ1 in FIG. 16. Here, the area of the electric field shown in FIG. 16 corresponds to the voltage.

Even if a high voltage is applied between the source electrode S1 and the drain electrode D1 of the semiconductor element 100, the electric field can be distributed widely in space as shown in FIG. 16 by applying a reverse bias to the gate electrode. In other words, this semiconductor element 100 can prevent a strong electric field from being formed locally. Therefore, the semiconductor element 100 has high voltage resistance.

In this specification, the breakdown voltage of a FET refers to the value of the drain voltage Vd at which the drain current Id reaches 1×10 ⁻⁴ A when the drain voltage Vd is applied in the off state with the gate voltage Vg applied being −10 V. In this embodiment, the rated current of the semiconductor element 100 at room temperature is about several A to several tens of A. The above-mentioned drain current Id is a value about five orders of magnitude lower than this rated current.

3-1. Polarization super junction region The presence of the polarization super junction region PSJ1 allows the polarization super junction region PSJ1 to be depleted. Even if a large reverse bias is applied to the gate electrode G1, a uniform electric field distribution is formed over the polarization super junction region PSJ1. On the other hand, in conventional FETs, a strong electric field is often formed near the gate. Therefore, the electric field strength formed near the gate electrode G1 is sufficiently smaller than that of conventional FETs under similar conditions. In this way, in the semiconductor element 100, the electric field concentration near the gate is alleviated. Therefore, the longer the polarization super junction length Lpsj, which is the length of the polarization super junction region PSJ1, the higher the voltage resistance of the semiconductor element 100 tends to be.

On the other hand, when the polarization superjunction length Lpsj is short, the distance between the source electrode S1 and the drain electrode D1 is short. Therefore, the shorter the polarization superjunction length Lpsj, the lower the on-resistance of the semiconductor element 100 tends to be.

3-2. Gate Length The gate length Lg is the length of the fourth semiconductor layer 140 in a direction that connects the shortest distance from the source electrode contact region SC1 to the drain electrode contact region DC1. The shorter the gate length Lg, the shorter the response time tends to be. When the gate length Lg is short, the depletion layer region in the gate length Lg direction is short. Since the depletion layer region is narrow, the gate charge capacity can be small. In other words, when the semiconductor element 100 is caused to perform a switching operation, the gate electrode G1 needs to supply or discharge a small amount of charge to or from the depletion layer region. This improves the switching speed of the semiconductor element 100.

3-3. Gate width The gate width is the length of the fourth semiconductor layer 140 in a direction perpendicular to the direction connecting the shortest distance from the source electrode contact region SC1 to the drain electrode contact region DC1. In other words, the gate width is the length of the gate electrode contact region GC1 surrounding the periphery of the source electrode contact region SC1. Since the multiple source electrode contact regions SC1 are discretely arranged, the gate width is actually the sum of the lengths of the multiple gate electrode contact regions GC1 surrounding the periphery of the multiple source electrode contact regions SC1.

The longer the gate width, the larger the area through which current can flow in the semiconductor element 100. Therefore, the longer the gate width, the larger the current value tends to be when the drain voltage Vd is 2 V. In the first embodiment, in order to increase the gate width, the source electrode contact region SC1 is rod-shaped and the drain electrode contact region DC1 is comb-shaped.

In addition, since the drain current flows between the source electrode S1 and the drain electrode D1, it is possible to consider lengthening the source width or the drain width. It is considered that the drain current is limited depending on the shorter of the source width and the drain width. The source width is the perimeter length of the source electrode contact region SC1. The drain width is the perimeter length of the drain electrode contact region DC1. However, the source width or drain width may be calculated by subtracting the length of the region where the source electrode contact region SC1 and the drain electrode contact region DC1 do not face each other.

3-4. Protruding portion of insulating layer As shown in Fig. 5, the second semiconductor layer 120 is in contact with the insulating layer IL1 at the protruding portion IL1a of the insulating layer IL1. As shown in Fig. 8, the second semiconductor layer 120 is in contact with the polyimide layer PI1 at a location other than the protruding portion IL1a of the insulating layer IL1. The polyimide layer PI1 is suitable for forming a thicker film than the insulating layer IL1. Therefore, the polyimide layer PI1 insulates a larger area around the semiconductor layer.

As shown in FIG. 5, in the region directly below the gate wiring electrode G1w, the insulating layer IL1 insulates the semiconductor layer from the surrounding materials. As shown in FIG. 8, in the region other than directly below the gate wiring electrode G1w, the polyimide layer PI1 insulates the semiconductor layer from the surrounding materials.

Here, it is assumed that the insulating layer IL1 insulates the semiconductor layer from the surrounding material in regions other than directly below the gate wiring electrode G1w. A high potential is applied to the drain electrode contact region DC1. For this reason, there is a risk of leakage current occurring through the surface of the insulating layer IL1 from the drain electrode contact region DC1 to the source electrode contact region SC1 or the gate electrode contact region GC1. In this embodiment, the polyimide layer PI1 insulates the semiconductor layer from the surrounding material in regions other than directly below the gate wiring electrode G1w, so that leakage current through the surface of the insulating layer IL1 is suppressed.

As shown in FIG. 5, at the protrusion IL1a, the first semiconductor layer 110, the second semiconductor layer 120, the third semiconductor layer 130, the fourth semiconductor layer 140, the insulating layer IL1, and the gate wiring electrode G1w are stacked in this order from the sapphire substrate Sub side. If the insulating layer IL1 is an oxide, this stacked structure becomes a MOS structure. The gate voltage for depleting the polarization super junction region PSJ1 is different between the protrusion IL1a and the location where the gate contact electrode G1c and the fourth semiconductor layer 140 are in direct contact.

In the semiconductor element 100 of the first embodiment, the contact point between the second semiconductor layer 120 and the insulating layer IL1 is limited to the protrusion IL1a. Furthermore, the area obtained by projecting the gate electrode contact area GC1 onto the second semiconductor layer 120 surrounds the source electrode contact area SC1. This suppresses leakage current.

17, a buffer layer Bf1, a first semiconductor layer 110, a second semiconductor layer 120, a third semiconductor layer 130, and a fourth semiconductor layer 140 are grown in this order on a sapphire substrate Sub1. For this purpose, for example, an MOCVD method may be used. Alternatively, other vapor phase growth methods, liquid phase growth methods, etc. may be used.

4-2. Recess formation process As shown in FIG. 18, recesses X1, X2, and X3 are formed. For this purpose, dry etching such as ICP may be used. The etching gas may be, for example, a chlorine-based gas such as _Cl2 , _BCl3 , or _SiCF4 . Photoresist or the like may be used during the dry etching. Recess X1 is a region where the source electrode S1 is formed. Recess X2 is a region where the drain electrode D1 is formed. Recess X3 is a region that becomes the polarization super junction region PSJ1.

The second semiconductor layer 120 is exposed at the bottom of the recesses X1 and X2. The third semiconductor layer 130 is exposed at the bottom of the recesses X3. Therefore, after first exposing the third semiconductor layer 130, only the regions forming the recesses X1 and X2 are etched again to expose the second semiconductor layer 120. Alternatively, two separate processes may be performed. Here, the recesses X1 and X2 have approximately the same depth, but are not connected. The recesses X1 are rod-shaped, and the recesses X2 are comb-shaped.

In addition, in the region outside the element function region FR1, grooves U1 and U2 are formed to expose the first semiconductor layer 110. As a result, no current path is formed in any region other than the region in which the source electrode contact region SC1, the drain electrode contact region DC1, the gate electrode contact region GC1, and the polarization super junction region PSJ1 exist. In other words, the active region of the semiconductor element 100 is limited.

4-3. Insulating Layer Forming Step The insulating layer IL1 is formed on the grooves U1 and U2 of the first semiconductor layer 110. For this purpose, for example, a CVD method may be used.

4-4. Electrode Formation Step As shown in FIG. 19, the source electrode S1, the drain electrode D1, and the gate electrode G1 are formed. The source electrode S1 and the drain electrode D1 have the same electrode layer structure, so they may be formed in the same step. The layer structure of the gate electrode G1 is different from that of the source electrode S1 and the drain electrode D1, so it is formed in a different step. To form these electrodes, a film formation technique such as sputtering, ALD, or EB deposition may be used. By this step, the insulating layer IL1 is disposed between the source electrode S1, the drain electrode D1, the gate electrode G1, and the first semiconductor layer 110.

4-5. Protective layer formation process Next, the exposed surface of the semiconductor layer is covered with polyimide. Polyamic acid, which is a precursor of polyimide, is applied to the exposed part of the semiconductor. The wafer is then heated at 250° C. to 500° C. to form a polyimide layer PI1.

4-6. Element Isolation Step Then, the semiconductor elements 100 are cut out from the wafer to manufacture individual independent semiconductor elements 100 .

4-7. Other Steps Other steps may be appropriately performed, such as a step of forming wiring electrodes or pad electrodes, a heat treatment step, etc. Through the above steps, the semiconductor element 100 is obtained.

5. Effects of the First Embodiment 5-1. Source Electrode Contact Region and Drain Electrode Contact Region The source electrode contact region SC1 has a rod-like shape. The drain electrode contact region DC1 has a comb-tooth shape. The rod-like shape of the source electrode contact region SC1 is disposed between the comb-tooth shapes of the drain electrode contact region DC1. The path formed by the outer periphery of the source electrode contact region SC1 and the outer periphery of the drain electrode contact region DC1 is long. Current flows in the semiconductor layer in the region sandwiched between the source electrode contact region SC1 and the drain electrode contact region DC1. Therefore, this semiconductor element 100 can pass a large current.

5-2. Gate electrode contact region In the semiconductor element 100, the region obtained by projecting onto the second semiconductor layer 120 the gate electrode contact region GC1 where the gate electrode G1 and the fourth semiconductor layer 140 are in contact with each other surrounds, in a non-contact manner, the periphery of the region obtained by projecting onto the second semiconductor layer 120 the source electrode contact region SC1 where the source electrode S1 and the second semiconductor layer 120 are in contact with each other. Therefore, the gate electrode contact region GC1 is always present between the drain electrode contact region DC1 where the drain electrode D1 and the second semiconductor layer 120 are in contact with each other, and the source electrode contact region SC1. Therefore, the semiconductor element 100 can suppress leakage current when turned off.

5-3. Polarization Super Junction Region The semiconductor device 100 has a polarization super junction region PSJ1. The presence of the polarization super junction region PSJ1 makes it possible to widen the depletion region. This provides the semiconductor device 100 with high voltage resistance.

5-4. Gate Length The semiconductor element 100 has a relatively long gate length Lg. Because the gate length Lg is relatively long, the depletion region can be made wide.

6. Modifications 6-1. Device The technique of the first embodiment can be applied to a device having the semiconductor element 100. Examples of such devices include a package, a module, a transmitter, a communication device, and a power transmitter.

6-2. Semiconductor Layer In the first embodiment, the second semiconductor layer 120 is AlGaN. The second semiconductor layer 120 may be _{AlXInYGa (1-XY)} N (X>0). The first semiconductor layer ₁₁₀ and the third semiconductor layer 130 may be _{AlXInYGa (1-XY)} N (X≧0). However, the band gaps of the first _{semiconductor} layer 110 and the third semiconductor layer 130 are smaller than the band gap of the second semiconductor layer 120. In addition, the compositions of the first semiconductor layer 110 and the third semiconductor layer 130 do not have to be the same.

6-3. Source Electrode Contact Region and Drain Electrode Contact Region In the first embodiment, the source electrode contact region SC1 has a bar shape, and the drain electrode contact region DC1 has a comb shape. Alternatively, the source electrode contact region SC1 may have a comb shape, and the drain electrode contact region DC1 may have a bar shape.

Therefore, one of the source electrode contact region SC1 and the drain electrode contact region DC1 has a rod-like shape. The other of the source electrode contact region SC1 and the drain electrode contact region DC1 has a comb-tooth shape. The rod-like shape of one of the source electrode contact region SC1 and the drain electrode contact region DC1 is disposed between the comb-tooth shape of the other of the source electrode contact region SC1 and the drain electrode contact region DC1.

6-4. Shape of the electrode contact region The tip portion of the rod-like shape of the source electrode contact region SC1 is arc-shaped. However, the tip portion is not limited to an arc. The tip portion of the rod-like shape is an arc-shaped portion. The portion other than the tip portion of the rod-like shape is a straight rod-like portion.

6-5. Source Contact Electrode and Drain Contact Electrode The source contact electrode S1c and the drain contact electrode D1c are in direct contact with the second semiconductor layer 120. This is because the recesses X1 and X2 reach halfway through the second semiconductor layer 120. However, if the bottoms of the recesses X1 and X2 are sufficiently close to the second semiconductor layer 120, the source contact electrode S1c and the drain contact electrode D1c do not need to be in direct contact with the second semiconductor layer 120. In this case, the recesses X1 and X2 reach halfway through the third semiconductor layer 130. The source contact electrode S1c and the drain contact electrode D1c are in contact with the very thin third semiconductor layer 130. The thickness of the very thin portion of the third semiconductor layer 130 is, for example, 10 nm or less. At this time, the third semiconductor layer 130 is thin at the recesses X1 and X2, and thicker than the recesses X1 and X2 at the other portions than the recesses X1 and X2. Even in this case, the semiconductor element can allow a sufficient amount of current to flow between the source and drain.

Therefore, the source electrode S1 and the drain electrode D1 are formed on the second semiconductor layer 120 or the third semiconductor layer 130. The source electrode contact region SC1 is the region where the source electrode S1 contacts the second semiconductor layer 120 or the third semiconductor layer 130. The drain electrode contact region DC1 is the region where the drain electrode D1 contacts the second semiconductor layer 120 or the third semiconductor layer 130.

6-6. Gate electrode contact region The gate electrode contact region GC1 may surround the drain electrode contact region DC1. In this case as well, the leakage current during off-state is suppressed. In this case, the region in which the gate electrode contact region GC1 is projected onto the second semiconductor layer 120 surrounds the periphery of the region in which the source electrode contact region SC1 or the drain electrode contact region DC1 is projected onto the second semiconductor layer 120.

6-7. Wiring Electrode The positional relationship between the source electrode S1 and the drain electrode D1 may be interchanged. In this case, one of the two regions, the region where the source wiring electrode S1w is projected onto the second semiconductor layer 120 and the region where the drain wiring electrode D1w is projected onto the second semiconductor layer 120, partially overlaps with the region where the gate wiring electrode G1w is projected onto the second semiconductor layer 120, and the other of the two regions, the region where the source wiring electrode S1w is projected onto the second semiconductor layer 120 and the region where the drain wiring electrode D1w is projected onto the second semiconductor layer 120, does not overlap with the region where the gate wiring electrode G1w is projected onto the second semiconductor layer 120.

In addition, in a location where one of the two regions, the region where the source wiring electrode S1w is projected onto the second semiconductor layer 120 and the region where the drain wiring electrode D1w is projected onto the second semiconductor layer 120, partially overlaps with the region where the gate wiring electrode G1w is projected onto the second semiconductor layer 120, the distance between the source wiring electrode S1w or the drain wiring electrode D1w and the first semiconductor layer 110 is greater than the distance between the gate wiring electrode G1w and the first semiconductor layer 110.

6-8. Protective film The protective film that protects the semiconductor layer may be an insulating layer other than polyimide. The insulating layer may have at least one of an inorganic dielectric film and an organic dielectric film. For example, the insulating layer may have one or more of _SiO2 , _SiXNy , _SiON , _Al2O3 , AlN, AlON, _ZrO2 , ZrN, _ZrON , _Ta2O3 , TaN, _TaON , _HfO2 , _HfN2 , HfON, _TiO2 , TiN, TiON, and polyimide.

6-9. Combinations The above modifications may be freely combined.

Second Embodiment
A second embodiment will be described.

1. Semiconductor element Fig. 20 is a top view of a semiconductor element 200 according to a second embodiment. A source electrode contact region SC1 where the source electrode S1 and the second semiconductor layer 120 contact each other has a rod-like shape. A drain electrode contact region DC1 where the drain electrode D1 and the second semiconductor layer 120 contact each other has a comb-like shape. The rod-like shape of the source electrode contact region SC1 is disposed between the comb-like shapes of the drain electrode contact region DC1.

In the semiconductor element 200, the distance Lpsj2 is equal to or greater than the distance Lpsj1. The distance Lpsj1 is the polarization superjunction length in the rod-shaped portion other than the tip portion of the source electrode contact region SC1. The distance Lpsj2 is the polarization superjunction length in the tip portion of the source electrode contact region SC1.

In this way, the length of the polarization super junction region PSJ2 in the direction of the shortest distance from the source electrode contact region SC1 to the drain electrode contact region DC1 at the tip of the rod-like shape is greater than or equal to the length of the polarization super junction region PSJ1 in the direction of the shortest distance from the source electrode contact region SC1 to the drain electrode contact region DC1 at the part other than the tip of the rod-like shape.

The length of the polarization super junction region PSJ2 in the direction connecting the shortest distance from the source electrode contact region SC1 to the drain electrode contact region DC1 at the tip of the rod-shaped shape relative to the length of the polarization super junction region PSJ1 in the direction connecting the shortest distance from the source electrode contact region SC1 to the drain electrode contact region DC1 at the part other than the tip of the rod-shaped shape is preferably 1.05 to 3.

In the semiconductor element 200, the distance Lsd2 is equal to or greater than the distance Lsd1. The distance Lsd1 is the distance between the source electrode contact region SC1 and the drain electrode contact region DC1 in the rod-shaped portion other than the tip portion of the source electrode contact region SC1. The distance Lsd2 is the distance between the source electrode contact region SC1 and the drain electrode contact region DC1 in the tip portion of the source electrode contact region SC1.

That is, the distance between the source electrode contact region SC1 and the drain electrode contact region DC1 at the tip of the rod shape is equal to or greater than the distance between the source electrode contact region SC1 and the drain electrode contact region DC1 at the other part of the rod shape.

The tip of the rod shape is an arc-shaped portion. The rest of the rod shape is a straight rod-shaped portion.

2. Effects of the Second Embodiment The tip portion of the source electrode contact region SC1 of the source electrode S1 is more likely to have a strong electric field than the other rod-shaped portions. In the semiconductor element 200 of the second embodiment, the polarization super junction length Lpsj2 of the polarization super junction region PSJ is longer at the tip portion. For the same reason, the distance Lsd2 is also increased. As a result, the semiconductor element 200 has higher voltage resistance.

3. Modification 3-1. Source electrode contact region and drain electrode contact region The source electrode contact region SC1 may have a comb-tooth shape, and the drain electrode contact region DC1 may have a rod-like shape. Even in this case, the distance between the source electrode contact region SC1 and the drain electrode contact region DC1 at the tip of the rod-like shape is equal to or greater than the distance between the source electrode contact region SC1 and the drain electrode contact region DC1 at the portion other than the tip of the rod-like shape.

3-2. Arc-Shaped Portion The arc-shaped portion is, for example, a circular arc shape. However, the arc-shaped portion may be an arc shape other than a circular arc.

3-3. Combinations The above modifications may be freely combined.

Third Embodiment
A third embodiment will now be described.

21 is a diagram showing a laminated structure of a semiconductor element 300 according to the third embodiment. A source electrode S1 is formed on a recess X1. A drain electrode D1 is formed on a recess X2.

Here, the distance Ld between the drain electrode contact region DC1 and the third semiconductor layer 130 is greater than the distance Ls between the source electrode contact region SC1 and the third semiconductor layer 130. The distance Ld between the drain electrode contact region DC1 and the third semiconductor layer 130 is, for example, 1 μm or more and 10 μm or less.

In addition, when the source electrode contact region SC1, the drain electrode contact region DC1, and the gate electrode contact region GC1 are projected onto the second semiconductor layer 120, the distance Ldg between the region onto which the drain electrode contact region DC1 is projected and the region onto which the gate electrode contact region GC1 is projected is greater than the distance Lsg between the region onto which the source electrode contact region SC1 is projected and the region onto which the gate electrode contact region GC1 is projected.

2. Effects of the Third Embodiment During operation of the semiconductor element 300, the potential difference (voltage) between the drain electrode D1 and the gate electrode G1 may be sufficiently larger than the potential difference (voltage) between the source electrode S1 and the gate electrode G1. For this reason, in the third embodiment, the distance Ldg between the drain electrode contact region DC1 and the gate electrode contact region GC1 is set sufficiently larger than the distance Lsg between the source electrode contact region SC1 and the gate electrode contact region GC1. Since a high potential is applied to the drain electrode D1, the electric field strength between the drain and gate is stronger than the electric field strength between the source and gate. For this reason, the distance Ldg is set sufficiently larger than the distance Lsg.

Fourth Embodiment
A fourth embodiment will now be described.

Figure 22 is a diagram showing the periphery of the gate pad electrode of the semiconductor element 400 of the fourth embodiment.

The source electrode S2 has a source contact electrode S2c, a source wiring electrode S2w, and a source pad electrode S2p. The source contact electrode S2c is in direct contact with the second semiconductor layer 120. The source wiring electrode S2w connects the source contact electrode S2c and the source pad electrode S2p. The source pad electrode S2p is an electrode for electrically connecting to an external power supply.

The gate electrode G2 has a gate contact electrode G2c, a gate wiring electrode G2w, and a gate pad electrode G2p. The gate contact electrode G2c is in direct contact with the fourth semiconductor layer 140. The gate wiring electrode G2w connects the gate contact electrode G2c and the gate pad electrode G2p. The gate pad electrode G2p is an electrode for electrically connecting to an external power supply.

The source wiring electrode S2w has a curved portion S2r that curves in an arc shape at the connection point with the source pad electrode S2p. The gate wiring electrode G2w has a curved portion G2r that curves in an arc shape at the connection point with the gate pad electrode G2p.

2. Insulating Layer Fig. 23 is a diagram showing a cross-sectional structure of the periphery of the drain electrode exposed region of the semiconductor element 400 of the fourth embodiment. As shown in Fig. 23, the semiconductor element 400 has insulating layers IL2, IL3, and IL4 in addition to the insulating layer IL1. The insulating layer IL2 is located on the insulating layer IL1. The insulating layer IL3 is located on the insulating layer IL2. The insulating layer IL4 is located on the insulating layer IL3.

The insulating layer IL1 and the insulating layer IL2 are made of an inorganic dielectric film. The inorganic dielectric film is, for example, _SiO2 . The insulating layer IL3 and the insulating layer IL4 are made of an organic dielectric film. The organic dielectric film is, for example, polyimide. It is preferable to form the organic dielectric film on a hard film such as _SiO2 .

The insulating layer IL2 and the insulating layer IL3 fill the gap between the insulating layer IL1 and the second semiconductor layer 120. The insulating layer IL2 fills the side and surface of the semiconductor layer. The insulating layer IL2 also fills the contact electrodes of the source electrode S1, the drain electrode D1, and the gate electrode G1. The insulating layer IL4 is the top layer.

2. Effects of the Fourth Embodiment The semiconductor element 400 has high voltage resistance. Therefore, a high voltage may be applied to the semiconductor element 400 during use. Even when such a high voltage is applied, the formation of a strong electric field around the curved portion S2r and the curved portion G2r is suppressed. It is also believed that the internal stress in the insulating layer is also alleviated.

3. Modification 3-1. Drain Electrode In the drain electrode as well, the drain wiring electrode may have a curved portion curved in an arc shape at the connection portion with the drain pad electrode.

3-2. Number of pad electrodes Fig. 24 is a top view of a semiconductor element in a modified example of the fourth embodiment. As shown in Fig. 24, the semiconductor element may have a plurality of source pad electrodes S2p. That is, at least one of the gate electrode G2, the source electrode S2, and the drain electrode D2 may have a plurality of pad electrodes. As shown in Fig. 24, the gate pad electrode G2p is disposed in a state of being sandwiched between the source pad electrodes S2p and the source pad electrodes S2p.

Figure 25 is an enlarged view of the periphery of the gate pad electrode in a semiconductor element in a modified example of the fourth embodiment. As shown in Figure 25, a curved shape S2i1 is also formed in the connection portion S2i that connects the source pad electrodes S2p and S2p.

3-3. Shape of Pad Electrode At least one corner of the source pad electrode S2p, the gate pad electrode G2p, and the drain pad electrode may be curved.

The insulating layer may include at least one of an inorganic dielectric film and an organic dielectric film. For example, the insulating layer may include one or more of _SiO2 , _SiXNY , SiON, _Al2O3 , AlN, AlON, _ZrO2 , _ZrN , _ZrON , _Ta2O3 , TaN, TaON, _HfO2 , _HfN2 , _{HfON, TiO2 ,} TiN, TiON, and polyimide.

3-5. Combinations The above modifications may be freely combined.

Fifth Embodiment
A fifth embodiment will be described.

1. Semiconductor Element The basic structure of the semiconductor element is the same as that of the first embodiment.

The dislocation density in the second semiconductor layer 120 is, for example, not less than 1×10 ⁶ cm ⁻² and not more than 1×10 ¹⁰ cm ⁻² . The dislocation density is preferably not more than 5×10 ⁹ cm ⁻² . The dislocation density in the first semiconductor layer 110 is, for example, not less than 1×10 ⁶ cm ⁻² and not more than 1×10 ¹⁰ cm ⁻² . The dislocation density is preferably not more than 5×10 ⁹ cm ⁻² .

The contact area between the second semiconductor layer 120 and the third semiconductor layer 130 is not less than 10 μm ² and not more than 200 μm ² per 1 μm in the gate width direction.

The gate length Lg is 0.1 μm or more and 6 μm or less. The gate length Lg may also be 0.3 μm or more and 5 μm or less. The gate length Lg may also be 1 μm or more and 4 μm or less.

The contact area between the second semiconductor layer 120 and the third semiconductor layer 130 and the breakdown voltage are expressed by the following formula (1):
101x-810≦y≦235x+585 ………(1)
x: contact area between the second semiconductor layer and the third semiconductor layer per 1 μm in the gate width direction; y: satisfying the breakdown voltage.

2. Electrical Characteristics of the Semiconductor Element In the semiconductor element of the fifth embodiment, the rise time (tr) and fall time (tf) at 300 V switching are both 3 ns or more and 30 ns or less.

The breakdown voltage of the semiconductor element of the fifth embodiment is 1500 V or more and 20000 V or less. The breakdown voltage of the semiconductor element may also be 3000 V or more and 10000 V or less.

3. Dislocation Density In order to reduce the dislocation density of the semiconductor layer, a method of forming an AlN buffer layer by sputtering, a method of forming an uneven shape on a substrate, a method of forming a thick film of several tens of μm or more by VPE, or the like may be used.

Sixth Embodiment
A sixth embodiment will now be described.

1. Semiconductor Element The basic structure of the semiconductor element is the same as that of the first embodiment.

The polarization superjunction length Lpsj is 1 μm or more and 50 μm or less. The polarization superjunction length Lpsj may be 2 μm or more and 40 μm or less. The polarization superjunction length Lpsj may be 3 μm or more and 30 μm or less.

The gate length Lg is 0.1 μm or more and 6 μm or less. The gate length Lg may also be 0.3 μm or more and 5 μm or less. The gate length Lg may also be 1 μm or more and 4 μm or less.

2. Electrical characteristics of the semiconductor element In the semiconductor element of the sixth embodiment, the rise time (tr) and fall time (tf) at 300V switching are both 3ns or more and 30ns or less. The rise time (tr) and fall time (tf) may be 4ns or more and 20ns or less. The rise time (tr) and fall time (tf) may be 5ns or more and 10ns or less.

The normalized on-resistance in the semiconductor element of the sixth embodiment is 1 mΩ·cm ² or more and 20 mΩ·cm ² or less. The normalized on-resistance may be 2 mΩ·cm ² or more and 17 mΩ·cm ² or less. The normalized on-resistance may be 3 mΩ·cm ² or more and 15 mΩ·cm ² or less.

Seventh Embodiment
A seventh embodiment will now be described.

1. Semiconductor Element The basic structure of the semiconductor element is the same as that of the first embodiment.

The active area is 2.2 mm ² or more and 100 mm ² or less. The active area may be 2.5 mm ² or more and 90 mm ² or less. The active area may be 3 mm ² or more and 80 mm ² or less.

The active region area is the area through which current substantially flows in the first semiconductor layer 110. The active region area is the area of the second semiconductor layer 120 on the third semiconductor layer 130 side minus the areas of the source electrode contact region SC1 and the drain electrode contact region DC1, and the area of the region sandwiched between the outermost source electrode contact region SC1 and the outer periphery of the second semiconductor layer 120.

The gate length Lg is 0.1 μm or more and 6 μm or less. The gate length Lg may also be 0.3 μm or more and 5 μm or less. The gate length Lg may also be 1 μm or more and 4 μm or less.

The gate width is 300 mm or more and 12,000 mm or less. The gate width may be 350 mm or more and 11,000 mm or less. The gate width may be 400 mm or more and 10,000 mm or less.

The peripheral length of the semiconductor element is 13 mm or more and 520 mm or less. The peripheral length of the semiconductor element may be 15 mm or more and 500 mm or less. The peripheral length of the semiconductor element may be 20 mm or more and 480 mm or less. The peripheral length is the sum of the lengths of the four sides of the sapphire substrate Sub1 of the semiconductor element.

2. Electrical Characteristics of the Semiconductor Element In the semiconductor element of the seventh embodiment, the rise time (tr) and fall time (tf) at 300 V switching are both 3 ns or more and 30 ns or less.

In the semiconductor element of the seventh embodiment, the current value when the drain voltage Vd is 2 V is 30 A or more and 1200 A or less. The current value when the drain voltage Vd is 2 V is a current value in a region that is not a current saturation region in the on state.

Eighth embodiment
26 is a diagram showing a stacked structure of a semiconductor element 500 according to an eighth embodiment. The semiconductor element 500 is a Schottky barrier diode. The semiconductor element 500 includes a sapphire substrate Sub2, a buffer layer Bf2, a first semiconductor layer 510, a second semiconductor layer 520, a third semiconductor layer 530, a fourth semiconductor layer 540, a cathode electrode C1, and an anode electrode A1.

The buffer layer Bf2 is formed on the sapphire substrate Sub2. The first semiconductor layer 510 is formed on the buffer layer Bf2. The second semiconductor layer 520 is formed on the first semiconductor layer 510. The third semiconductor layer 530 is formed on the second semiconductor layer 520. The fourth semiconductor layer 540 is formed on the third semiconductor layer 530.

The first semiconductor layer 510, the second semiconductor layer 520, the third semiconductor layer 530, and the fourth semiconductor layer 540 are Group III nitride semiconductor layers. The band gap of the second semiconductor layer 520 is larger than the band gaps of the first semiconductor layer 510 and the third semiconductor layer 530. The first semiconductor layer 510, the second semiconductor layer 520, and the third semiconductor layer 530 are undoped semiconductor layers. The fourth semiconductor layer 540 is a p-type semiconductor layer.

The cathode electrode C1 is formed on the second semiconductor layer 520. The recess Y1 reaches from the fourth semiconductor layer 540 to halfway into the second semiconductor layer 520. The cathode electrode C1 is formed on the recess Y1.

The anode electrode A1 is formed on the fourth semiconductor layer 540. The recess Y2 reaches from the fourth semiconductor layer 540 to halfway into the first semiconductor layer 510. The anode electrode A1 is formed from the bottom surface of the recess Y2 to the fourth semiconductor layer 540. Therefore, the anode electrode A1 is in contact with the first semiconductor layer 510, the second semiconductor layer 520, the third semiconductor layer 530, and the fourth semiconductor layer 540. The anode electrode A1 is in contact with the bottom surface and side surfaces of the first semiconductor layer 510, the side surfaces of the second semiconductor layer 520 and the third semiconductor layer 530, and the side surfaces and top surface of the fourth semiconductor layer 540.

Figure 27 is a diagram showing the electrode formation regions of a semiconductor element 500 of the eighth embodiment. As shown in Figure 27, the semiconductor element 500 has a cathode electrode contact region CC1 where the cathode electrode C1 and the second semiconductor layer 520 contact each other, and an anode electrode contact region AC1 where the anode electrode A1 and the fourth semiconductor layer 540 contact each other.

The cathode electrode contact region CC1 where the cathode electrode C1 and the second semiconductor layer 520 contact each other has a comb-tooth shape. The anode electrode contact region AC1 where the anode electrode A1 and the first semiconductor layer 510 and the fourth semiconductor layer 540 contact each other has a rod-like shape. The rod-like shape of the region where the anode electrode contact region AC1 is projected onto the first semiconductor layer 510 is located between the comb-tooth shapes of the region where the cathode electrode contact region CC1 is projected onto the first semiconductor layer 510.

The polarization superjunction region is an area where the third semiconductor layer 530 is formed but the fourth semiconductor layer 540 is not formed, and is located between the anode electrode contact region AC1 and the cathode electrode contact region CC1.

2. Withstand Voltage In this specification, the withstand voltage of a Schottky barrier diode refers to the value of anode voltage Va at which anode current Ia reaches 1×10 ⁻⁴ A when a reverse voltage Va is applied between anode electrode A1 and cathode electrode C1.

3. Modification 3-1. Shape of the electrode contact area The cathode electrode contact area CC1 may have a rod-like shape, and the anode electrode contact area AC1 may have a comb-tooth shape. That is, one of the cathode electrode contact area CC1 and the anode electrode contact area AC1 may have a comb-tooth shape, and the other of the cathode electrode contact area CC1 and the anode electrode contact area AC1 may have a rod-like shape.

Figure 28 is a diagram showing electrode formation regions of a semiconductor element in a modified example of the eighth embodiment. The cathode electrode contact region CC1 where the cathode electrode C1 contacts the second semiconductor layer 520 has a comb-tooth shape. The anode electrode contact region AC1 where the anode electrode A1 contacts the first semiconductor layer 510 and the fourth semiconductor layer 540 has a comb-tooth shape. The comb-tooth shape of the region where the cathode electrode contact region CC1 is projected onto the first semiconductor layer 510 is arranged alternately with the comb-tooth shape of the region where the anode electrode contact region AC1 is projected onto the first semiconductor layer 510.

It is sufficient that the rod-shaped portion (including the rod-shaped portion at the tip of the comb-tooth shape) of one of the cathode electrode contact area CC1 and the anode electrode contact area AC1 is positioned between the comb-tooth shape of the other of the cathode electrode contact area CC1 and the anode electrode contact area AC1.

3-2. Anode Electrode Contact Region FIG. 29 is a diagram (part 1) showing a stacked structure of a semiconductor element 600 in a modified example of the eighth embodiment. The semiconductor element 600 has a sapphire substrate Sub2, a buffer layer Bf2, a first semiconductor layer 510, a second semiconductor layer 520, a third semiconductor layer 530, a fourth semiconductor layer 540, a cathode electrode C1, and an anode electrode A1. The anode electrode A1 is formed on a recess Y3. The recess Y3 reaches from the fourth semiconductor layer 540 to partway through the second semiconductor layer 520. In the semiconductor element 600, the anode electrode A1 is not in contact with the first semiconductor layer 510.

Figure 30 is a diagram (part 2) showing the layered structure of a semiconductor element 700 in a modified example of the eighth embodiment. The semiconductor element 700 has a sapphire substrate Sub2, a buffer layer Bf2, a first semiconductor layer 510, a second semiconductor layer 520, a third semiconductor layer 530, a fourth semiconductor layer 540, a cathode electrode C1, an anode electrode A1, and an insulating layer 750.

The insulating layer 750 covers a part of the second semiconductor layer 520, a side surface of the third semiconductor layer 530, and a part of the fourth semiconductor layer 540. The insulating layer 750 is located between the side surface of the third semiconductor layer 530, the side surface of the fourth semiconductor layer 540, and the anode electrode A1. The anode electrode A1 is in contact with the second semiconductor layer 520 and the fourth semiconductor layer 540, but is not in contact with the third semiconductor layer 530.

In this way, the anode electrode A1 only needs to be in contact with the first semiconductor layer 510 or the second semiconductor layer 520.

3-3. Cathode Electrode Contact Region Fig. 31 is a diagram (part 3) showing a stacked structure of a semiconductor element 800 in a modified example of the eighth embodiment. As shown in Fig. 31, the cathode electrode C2 is in contact with the bottom surface and side surface of the first semiconductor layer 510 and the side surface of the second semiconductor layer 520.

3-4. Polarization super junction region The length of the polarization super junction region in the direction of the shortest distance from the cathode electrode contact region CC1 to the anode electrode contact region AC1 at the tip of the rod-like shape is equal to or longer than the length of the polarization super junction region in the direction of the shortest distance from the cathode electrode contact region CC1 to the anode electrode contact region AC1 at the portion other than the tip of the rod-like shape.

3-5. Distance Between Cathode Electrode and Third Semiconductor Layer The distance between the cathode electrode contact region CC1 and the third semiconductor layer 530 is not less than 1 μm and not more than 10 μm.

3-6. Combinations The above modifications may be freely combined.

(Combination of embodiments)
The first to eighth embodiments may be freely combined, including modified examples, in some cases.

(Evaluation test)
1. Experiment 1
1-1. Fabrication of FET A FET with a simple structure was fabricated as shown in Fig. 32 and Fig. 33. Fig. 32 is a diagram showing a FET in which the gate electrode contact region GC1 surrounds the source electrode contact region SC1. Fig. 33 is a diagram showing a FET in which the gate electrode contact region GC1 is between the source electrode contact region SC1 and the drain electrode contact region DC1. In Fig. 33, the gate electrode contact region GC1 does not surround the source electrode contact region SC1.

In this way, we manufactured a FET in which the gate electrode contact region GC1 surrounds the source electrode contact region SC1, and a FET in which the gate electrode contact region GC1 does not surround the source electrode contact region SC1. We then compared the leakage currents of these FETs.

1-2. Experimental results (leakage current)
Fig. 34 is a graph showing the relationship between the gate voltage and the drain current when 0.1 V is applied to the drain electrode of an FET. The horizontal axis of Fig. 34 is the gate voltage. The vertical axis of Fig. 34 is the drain current.

Fig. 35 is a graph showing the relationship between the gate voltage and drain current of a FET. The horizontal axis of Fig. 35 is the gate voltage. The vertical axis of Fig. 35 is the drain current. As shown in Fig. 35, when the gate electrode G1 surrounds the source electrode S1, the FET operates at a gate voltage of -5V or higher. Even if the gate voltage is less than -5V, an off-leak current flows. The off-leak current is about 1 x ^10-9 A/mm.

35, when the gate electrode G1 does not surround the source electrode S1, the FET operates at a gate voltage of -4.5 V or higher. When the gate voltage is less than -4.5 V, an off-leak current of about 1.0 x 10 ^-6 A/mm flows. In this way, by having the gate electrode G1 surround the periphery of the source electrode S1, the off-leak current is reduced by about two orders of magnitude.

Figure 36 is a graph showing the relationship between the drain voltage and drain current of a FET. The horizontal axis of Figure 36 is the drain voltage. The vertical axis of Figure 36 is the drain current. Figure 36 shows the drain current of a FET in which the gate electrode G1 surrounds the source electrode S1. Figure 36 shows the drain current when the gate voltage is changed. As shown in Figure 36, the higher the gate voltage, the larger the drain current.

Fig. 37 is a graph showing the relationship between drain voltage and drain current in an FET when it is off. The horizontal axis of Fig. 37 is drain voltage. The vertical axis of Fig. 37 is drain current. The gate voltage at this time is -10 V. Fig. 37 shows the drain current of an FET in which a gate electrode G1 surrounds a source electrode S1. As shown in Fig. 37, a leakage current of about 1 x ^10-9 A/mm flows when it is off. Also, the higher the drain voltage, the larger the drain current becomes.

Fig. 38 is a graph showing the relationship between drain voltage and gate current in an FET when it is off. The horizontal axis of Fig. 38 is drain voltage. The vertical axis of Fig. 38 is gate current. The gate voltage at this time is -10 V. Fig. 38 shows the gate current of an FET in which a gate electrode G1 surrounds a source electrode S1. As shown in Fig. 38, a leakage current of about 1 x ^10-9 A/mm flows when it is off. Also, the higher the drain voltage, the larger the gate current becomes.

As described above, the leakage current is suppressed in the FET that was actually manufactured. Note that the current values in Figures 35 to 38 are normalized by the gate width.

2. Experiment 2
2-1. Fabrication of FET An FET similar to the semiconductor device 100 of the first embodiment was fabricated. A low-temperature GaN buffer layer, a first undoped GaN layer, an AlGaN layer, a second undoped GaN layer, and an Mg-doped pGaN layer were laminated in this order on a c-plane sapphire substrate by MOCVD. The thicknesses of the low-temperature GaN buffer layer, the first undoped GaN layer, the AlGaN layer, the second undoped GaN layer, and the Mg-doped pGaN layer were 30 nm, 1.0 μm, 47 nm, 80 nm, and 53 nm, respectively. The deposition temperature of the low-temperature GaN buffer layer was 530° C. The deposition temperature of the first undoped GaN layer, the AlGaN layer, and the second undoped GaN layer was 1100° C. The Mg concentration in the Mg-doped pGaN layer was increased from 5.0×10 ¹⁹ cm ⁻³ to 2.0×10 ²⁰ cm ⁻³ to increase the Mg concentration near the surface of the Mg-doped GaN layer.

For the gate electrode, Ni and Au were laminated in this order from the semiconductor layer side. For the source electrode and drain electrode, Ti, Al, Ni and Au were laminated in this order from the semiconductor layer side.

Three types of dislocation density were used for the semiconductor layer. The dislocation density of the first element was 5.0×10 ⁸ cm ⁻² , the dislocation density of the second element was 2.3×10 ⁹ cm ⁻² , and the dislocation density of the third element was 9.0×10 ⁹ cm ⁻² .

2-2. Evaluation method Fig. 39 is a circuit diagram used in the evaluation of the FET. Fig. 40 is a graph showing the output value in the evaluation of the FET. The drain voltage Vd was 300V.

Figure 41 shows the definitions of the rise time tr and fall time tf of a FET. The rise time tr is the time it takes for the drain voltage Vd to fall from 90% to 10% of its maximum value. The fall time tf is the time it takes for the drain voltage Vd to rise from 10% to 90% of its maximum value. As shown in Figure 40, the drain current Id increases as the drain voltage Vd falls. As shown in Figure 40, the drain current Id fluctuates slightly, so the drain voltage Vd is used as the basis for the rise time tr and fall time tf instead of the drain current Id.

2-3. Experimental results (response time)
42 is a table showing the characteristics of the FET. In Examples 1-6, the rise time was 20 ns or less. In Comparative Example 1, the rise time was 42 ns. In Examples 1-6, the gate length was 4 μm, whereas in Comparative Example 1, the gate length was 8 μm.

Figure 43 is a graph showing the relationship between the junction area between the second undoped GaN layer (third semiconductor layer) and the Mg-doped pGaN layer (fourth semiconductor layer) in a FET and the breakdown voltage of the semiconductor element. The horizontal axis of Figure 43 is the area of the second undoped GaN layer (third semiconductor layer) per μm in the gate width direction. The vertical axis of Figure 43 is the breakdown voltage of the semiconductor element.

As shown in FIG. 43, in the region where the above-mentioned formula (1) is satisfied, the breakdown voltage is 1500 V or more.
101x-810≦y≦235x+585 ………(1)
x: contact area between the second semiconductor layer and the third semiconductor layer per 1 μm in the gate width direction y: breakdown voltage

Figure 44 is a graph showing the relationship between the gate length and response time of a FET. The horizontal axis of Figure 44 is gate length. The horizontal axis of Figure 44 is response time. As shown in Figure 44, the shorter the gate length, the shorter the response time tends to be. When the gate length is 6 μm or less, the rise time tr and fall time tf are 30 ns or less. When the gate length is 4 μm or less, the rise time tr and fall time tf are 20 ns or less.

Figure 45 is a graph showing the relationship between the junction area between the third semiconductor layer 130 and the fourth semiconductor layer 140 excluding the polarization super junction region PSJ1 in a FET and the response time. The horizontal axis of Figure 45 is the junction area between the third semiconductor layer 130 and the fourth semiconductor layer 140. The vertical axis of Figure 45 is the response time. As shown in Figure 45, the smaller the junction area between the third semiconductor layer 130 and the fourth semiconductor layer 140, the shorter the response time tends to be.

Figure 46 is a graph showing the relationship between dislocation density and junction area in a FET. The horizontal axis of Figure 46 is dislocation density. The vertical axis of Figure 46 is the junction area between the third semiconductor layer 130 and the fourth semiconductor layer 140. As shown in Figure 46, in order to provide high pressure resistance, it is necessary to increase the junction area between the third semiconductor layer 130 and the fourth semiconductor layer 140. Furthermore, the higher the dislocation density, the larger the junction area must be.

Figure 47 is a table summarizing the data in Figure 46.

Figure 48 is a graph showing the relationship between dislocation density and source-drain distance in a FET. The horizontal axis of Figure 48 is dislocation density. The vertical axis of Figure 48 is source-drain distance. As shown in Figure 48, in order to have high voltage resistance, it is necessary to increase the source-drain distance. Furthermore, the higher the dislocation density, the greater the source-drain distance needs to be.

Figure 49 is a table summarizing the data in Figure 48.

Figure 50 is a graph showing the relationship between dislocation density and response time in a FET. The horizontal axis of Figure 50 is dislocation density. The vertical axis of Figure 50 is response time. As shown in Figure 50, the lower the dislocation density, the shorter both the rise time tr and the fall time tf tend to be. In particular, the rise time tr is significantly improved by reducing the dislocation density.

Fig. 51 is a table summarizing the data in Fig. 50. As shown in Fig. 50 and Fig. 51, when the dislocation density is 5 x 10 ⁸ cm ^-2 or less, the rise time tr is 16 ns or less. When the dislocation density is 5 x 10 ⁸ cm ^-2 or less, the fall time tf is 10 ns or less.

2-4. Experimental results (on-resistance)
Fig. 52 is a graph showing the relationship between the polarization super junction length Lpsj and the normalized on-resistance in a FET. The horizontal axis of Fig. 52 is the polarization super junction length. The vertical axis of Fig. 52 is the normalized on-resistance. As shown in Fig. 52, the normalized on-resistance increases as the polarization super junction length Lpsj increases. Furthermore, when the polarization super junction length Lpsj is 50 μm or less, the normalized on-resistance is 20 mΩ·cm ² or less. When the polarization super junction length Lpsj is 2 μm, the normalized on-resistance is about 1 mΩ·cm ² .

Fig. 53 is a graph showing the relationship between the source-drain distance and the normalized on-resistance in a FET. The horizontal axis of Fig. 53 is the source-drain distance. The vertical axis of Fig. 53 is the normalized on-resistance. As shown in Fig. 53, the normalized on-resistance increases as the source-drain distance increases. Furthermore, when the source-drain distance is 60 μm or less, the normalized on-resistance is 20 mΩ· ^cm2 or less. When the source-drain distance is 11 μm, the normalized on-resistance is about 1 mΩ· ^cm2 .

2-5. Experimental results (dislocation density)
FIG. 54 is a table showing the relationship between the dislocation density in a FET and the characteristics of a semiconductor element. As shown in FIG. 54, the lower the dislocation density, the smaller the value of the half-width of the X-ray rocking curve. Also, the lower the dislocation density, the smaller the sheet resistance. And, the lower the dislocation density, the higher the mobility of the two-dimensional hole gas. The sheet resistance is affected by the mobility of the two-dimensional electron gas. Therefore, it is considered that the mobility of the two-dimensional electron gas increases as the dislocation density decreases and the crystallinity improves. On the other hand, the concentration of the two-dimensional hole gas is almost independent of the dislocation density.

2-6. Experimental results (active area)
Fig. 55 is a table showing the relationship between the chip size of a FET and the current value when the drain voltage Vd is 2V. As shown in Fig. 55, the larger the chip size, the larger the chip perimeter, chip area, and active region area. The active region area is the area of the semiconductor through which current actually flows in the on state. The active region area is the area obtained by subtracting from the area of the element function region FR1 the area of the region where the source electrode and drain electrode are in contact with the semiconductor layer, and the area of the region sandwiched between the outermost source electrode contact region and the periphery of the second semiconductor layer.

The larger the chip size, the larger the gate width. The gate width is the total length of the line that surrounds the gate electrode G1 and the source electrode S1.

Fig. 56 is a graph showing the relationship between the active area area of a FET and the current value when the drain voltage Vd is 2V. The horizontal axis of Fig. 56 is the active area area. The vertical axis of Fig. 56 is the current value when the drain voltage Vd is 2V. As shown in Fig. 56, when the active area area is 2.2 ^{mm2 or} more, the current value when the drain voltage Vd is 2V is 30A or more. When the active area area is 5.0 mm2 or more, the current value when the drain voltage Vd is 2V is 100A or more.

3. Experiment 3
3-1. Fabrication of FET An FET similar to the semiconductor device 200 of the second embodiment was fabricated. The other points were the same as those in Experiment 2 except for the polarization super junction length Lpsj.

3-2. Experimental results (polarization superjunction length)
57 is a table showing the breakdown voltage of an FET when the polarization super junction length Lpsj and the distance Lsd between the source contact electrode S1c and the drain contact electrode D1c in the FET are changed. In FIG. 57, the minimum value of the polarization super junction length Lpsj at the tip portion and the minimum value of the polarization super junction length Lpsj at the portion other than the tip portion are changed.

Figure 58 is a table showing the voltage resistance of a FET when the polarization superjunction length Lpsj in the FET and the distance Lsd between the source contact electrode S1c and the drain contact electrode D1c are not changed. In Figure 58, the polarization superjunction length Lpsj at the tip portion is the same as the polarization superjunction length Lpsj at the portion other than the tip portion.

Figure 59 is a graph showing the relationship between the polarization superjunction length Lpsj in a FET and the voltage resistance of the FET. The horizontal axis of Figure 59 is the polarization superjunction length Lpsj. The vertical axis of Figure 59 is the voltage resistance of the FET. As shown in Figure 59, the voltage resistance of the FET is approximately proportional to the polarization superjunction length Lpsj.

Thus, the breakdown voltage of the FET depends on the minimum value of the polarization superjunction length Lpsj.

4. Experiment 4
4-1. Fabrication of a FET A FET similar to the semiconductor device 300 of the third embodiment was fabricated. The other points were the same as those in Experiment 2, except for the distance between the electrodes and the semiconductor layer.

4-2. Experimental results (distance between electrode and semiconductor layer)
Fig. 60 is a graph showing the relationship between the distance between the drain electrode contact region DC1 and the polarization super junction surface in a FET and the breakdown voltage. The horizontal axis of Fig. 60 is the distance between the drain electrode contact region DC1 and the polarization super junction surface. The vertical axis of Fig. 60 is the breakdown voltage. As shown in Fig. 60, even when the distance between the drain electrode contact region DC1 and the third semiconductor layer 130 is as short as 10 μm or less, the breakdown voltage of the semiconductor element is sufficiently high.

Figure 61 is a graph showing the relationship between the polarization superjunction length Lpsj in a FET and the breakdown voltage of a semiconductor element. The horizontal axis of Figure 61 is the polarization superjunction length Lpsj. The vertical axis of Figure 61 is the breakdown voltage of the semiconductor element. As shown in Figure 61, the longer the polarization superjunction length Lpsj, the higher the breakdown voltage of the semiconductor element. The breakdown voltage of the semiconductor element is somewhat proportional to the polarization superjunction length Lpsj.

5. Experiment 5
5-1. Fabrication of a FET A FET similar to the semiconductor element 400 of the fourth embodiment was fabricated. Everything except the pad electrodes was the same as in Experiment 2.

5-2. Experimental results (pad electrodes)
Fig. 62 is a graph showing the relationship between the drain voltage and drain current of a FET. The horizontal axis of Fig. 62 is the drain voltage. The vertical axis of Fig. 62 is the drain current. As shown in Fig. 62, when the gate voltage is increased, the drain current tends to increase. The drain current saturates when the drain voltage is about 15 V or more.

Figure 63 is a graph showing the relationship between gate voltage and drain current when the drain voltage of a FET is 0.1 V. The horizontal axis of Figure 63 is gate voltage. The vertical axis of Figure 63 is drain current.

Figure 64 is a graph showing the relationship between drain voltage and drain current when the FET is off. The horizontal axis of Figure 64 is drain voltage. The vertical axis of Figure 64 is drain current. The gate voltage is -10V.

Figure 65 is a graph showing the relationship between drain voltage and gate current when the FET is off. The horizontal axis of Figure 65 is drain voltage. The vertical axis of Figure 65 is gate current. The gate voltage is -10V.

The current values in Figures 62 to 65 are normalized by the gate width.

6. Experiment 6
6-1. Manufacture of Schottky Barrier Diodes Schottky barrier diodes similar to those in the eighth embodiment were manufactured. The stacked structure of the semiconductor layers and the manufacturing conditions were the same as those in Experiment 1. Elements with different polarization superjunction lengths Lpsj were manufactured.

6-2. Experimental results (reverse recovery current)
Fig. 66 is a graph showing the reverse recovery time characteristics of a Schottky barrier diode with a polarization superjunction length Lpsj of 20 μm. The horizontal axis of Fig. 66 is time. The vertical axis of Fig. 66 is the anode current. The reverse recovery time was 21.8 ns. The peak value of the reverse recovery current was 5.0 A.

6-3. Experimental results (forward characteristics)
Fig. 67 is a graph showing forward characteristics of a Schottky barrier diode. The horizontal axis of Fig. 67 is the anode voltage. The vertical axis of Fig. 67 is the anode current. As shown in Fig. 67, the shorter the polarization super junction length Lpsj, the larger the anode current tends to be. In other words, the shorter the polarization super junction length Lpsj, the smaller the normalized on-resistance tends to be.

6-4. Experimental results (reverse characteristics)
Fig. 68 is a graph showing the reverse characteristics of a Schottky barrier diode. The horizontal axis of Fig. 68 is the cathode voltage. The vertical axis of Fig. 68 is the anode current. As shown in Fig. 68, the shorter the polarization super junction length Lpsj, the lower the breakdown voltage. When the polarization super junction length Lpsj was 15 μm, 20 μm, 25 μm, 30 μm, and 40 μm, the breakdown voltage was approximately 2000 V, 2600 V, 3000 V, over 3000 V, and over 3000 V, respectively.

6-5. Experimental results (polarization superjunction length)
69 is a table showing the breakdown voltage of the Schottky barrier diode when the polarization super junction length Lpsj and the distance Lac between the anode electrode contact area AC1 and the cathode electrode contact area CC1 are changed. In FIG. 69, the minimum value of the polarization super junction length Lpsj at the tip portion and the minimum value of the polarization super junction length Lpsj at the portion other than the tip portion are changed.

By making the polarization superjunction length Lpsj and distance Lac of the tip portion greater than or equal to the polarization superjunction length Lpsj and distance Lac of the portion other than the tip portion, the breakdown voltage of the Schottky barrier diode is improved.

(Additional Note)
1. No. 1
The semiconductor device in the first aspect has a first semiconductor layer, a second semiconductor layer above the first semiconductor layer, a third semiconductor layer above the second semiconductor layer, a fourth semiconductor layer above the third semiconductor layer, a source electrode and a drain electrode above the second semiconductor layer or the third semiconductor layer, a gate electrode above the fourth semiconductor layer, a gate electrode contact region where the gate electrode and the fourth semiconductor layer are in contact, a source electrode contact region where the source electrode and the second semiconductor layer or the third semiconductor layer are in contact, and a drain electrode contact region where the drain electrode and the second semiconductor layer or the third semiconductor layer are in contact. The first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are Group III nitride semiconductor layers. The band gap of the second semiconductor layer is larger than the band gaps of the first semiconductor layer and the third semiconductor layer. The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are undoped semiconductor layers. The fourth semiconductor layer is a p-type semiconductor layer. The region in which the gate electrode contact region is projected onto the second semiconductor layer surrounds the periphery of the region in which the source electrode contact region or the drain electrode contact region is projected onto the second semiconductor layer.

In the semiconductor element of the second aspect, one of the source electrode contact region and the drain electrode contact region has a rod-like shape. The other of the source electrode contact region and the drain electrode contact region has a comb-tooth shape. The rod-like shape of one of the source electrode contact region and the drain electrode contact region is disposed between the comb-tooth shape of the other of the source electrode contact region and the drain electrode contact region.

In the semiconductor element of the third aspect, the source electrode has a source wiring electrode. The drain electrode has a drain wiring electrode. The area where the source wiring electrode is projected onto the second semiconductor layer does not overlap with the area where the drain wiring electrode is projected onto the second semiconductor layer.

In the semiconductor element of the fourth aspect, the source electrode has a source wiring electrode. The drain electrode has a drain wiring electrode. The gate electrode has a gate wiring electrode. One of the two regions, the region where the source wiring electrode is projected onto the second semiconductor layer and the region where the drain wiring electrode is projected onto the second semiconductor layer, partially overlaps with the region where the gate wiring electrode is projected onto the second semiconductor layer. The other of the two regions, the region where the source wiring electrode is projected onto the second semiconductor layer and the region where the drain wiring electrode is projected onto the second semiconductor layer, does not overlap with the region where the gate wiring electrode is projected onto the second semiconductor layer.

In the semiconductor element of the fifth aspect, in a location where one of the two regions, the region where the source wiring electrode is projected onto the second semiconductor layer and the region where the drain wiring electrode is projected onto the second semiconductor layer, partially overlaps with the region where the gate wiring electrode is projected onto the second semiconductor layer, the distance between the source wiring electrode or the drain wiring electrode and the first semiconductor layer is greater than the distance between the gate wiring electrode and the first semiconductor layer.

In the semiconductor element of the sixth aspect, the first semiconductor layer and the second semiconductor layer are in direct contact with each other. The shape of the contact surface where the first semiconductor layer and the second semiconductor layer are in contact is rectangular. The longitudinal direction of the rod-like shape is arranged in a direction parallel to the short side of the rectangle.

The device in the seventh aspect has the semiconductor element described above.

2. No. 2
The semiconductor element in the first aspect has a first semiconductor layer, a second semiconductor layer above the first semiconductor layer, a third semiconductor layer above the second semiconductor layer, a fourth semiconductor layer above the third semiconductor layer, a source electrode and a drain electrode above the second semiconductor layer or the third semiconductor layer, a gate electrode above the fourth semiconductor layer, a gate electrode contact region where the gate electrode and the fourth semiconductor layer are in contact, a source electrode contact region where the source electrode and the second semiconductor layer or the third semiconductor layer are in contact, and a drain electrode contact region where the drain electrode and the second semiconductor layer or the third semiconductor layer are in contact. The first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are Group III nitride semiconductor layers. The band gap of the second semiconductor layer is larger than the band gaps of the first semiconductor layer and the third semiconductor layer. The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are undoped semiconductor layers. The fourth semiconductor layer is a p-type semiconductor layer. One of the source electrode contact region and the drain electrode contact region has a rod-like shape. The other of the source electrode contact region and the drain electrode contact region has a comb-teeth shape, and the bar-shaped portion of one of the source electrode contact region and the drain electrode contact region is disposed between the comb-teeth-shaped portion of the other of the source electrode contact region and the drain electrode contact region.

In the semiconductor element of the second aspect, the region in which the gate electrode contact region is projected onto the second semiconductor layer surrounds the region in which the source electrode contact region or the drain electrode contact region is projected onto the second semiconductor layer.

In the semiconductor element of the third aspect, the source electrode has a source wiring electrode. The drain electrode has a drain wiring electrode. The area where the source wiring electrode is projected onto the second semiconductor layer does not overlap with the area where the drain wiring electrode is projected onto the second semiconductor layer.

In the semiconductor element of the fourth aspect, the source electrode has a source wiring electrode. The drain electrode has a drain wiring electrode. The gate electrode has a gate wiring electrode. One of the two regions, the region where the source wiring electrode is projected onto the second semiconductor layer and the region where the drain wiring electrode is projected onto the second semiconductor layer, partially overlaps with the region where the gate wiring electrode is projected onto the second semiconductor layer. The other of the two regions, the region where the source wiring electrode is projected onto the second semiconductor layer and the region where the drain wiring electrode is projected onto the second semiconductor layer, does not overlap with the region where the gate wiring electrode is projected onto the second semiconductor layer.

In the semiconductor element of the fifth aspect, in a location where one of the two regions, the region where the source wiring electrode is projected onto the second semiconductor layer and the region where the drain wiring electrode is projected onto the second semiconductor layer, partially overlaps with the region where the gate wiring electrode is projected onto the second semiconductor layer, the distance between the source wiring electrode or the drain wiring electrode and the first semiconductor layer is greater than the distance between the gate wiring electrode and the first semiconductor layer.

In the semiconductor element of the sixth aspect, the first semiconductor layer and the second semiconductor layer are in direct contact with each other. The shape of the contact surface where the first semiconductor layer and the second semiconductor layer are in contact is rectangular. The longitudinal direction of the rod-like shape is arranged in a direction parallel to the short side of the rectangle.

The device in the seventh aspect has the semiconductor element described above.

3. Third
The semiconductor element in the first aspect has a first semiconductor layer, a second semiconductor layer above the first semiconductor layer, a third semiconductor layer above the second semiconductor layer, a fourth semiconductor layer above the third semiconductor layer, a source electrode and a drain electrode above the second semiconductor layer or the third semiconductor layer, a gate electrode above the fourth semiconductor layer, a gate electrode contact region where the gate electrode and the fourth semiconductor layer are in contact, a source electrode contact region where the source electrode and the second semiconductor layer or the third semiconductor layer are in contact, and a drain electrode contact region where the drain electrode and the second semiconductor layer or the third semiconductor layer are in contact. The first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are Group III nitride semiconductor layers. The band gap of the second semiconductor layer is larger than the band gaps of the first semiconductor layer and the third semiconductor layer. The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are undoped semiconductor layers. The fourth semiconductor layer is a p-type semiconductor layer. One of the source electrode contact region and the drain electrode contact region has a rod-like shape. The other of the source electrode contact region and the drain electrode contact region has a comb-tooth shape. The rod-shaped one of the source electrode contact region and the drain electrode contact region is disposed between the comb-tooth shape of the other of the source electrode contact region and the drain electrode contact region. This semiconductor element has a polarization super-junction region located between the gate electrode contact region and the drain electrode contact region in a region where the third semiconductor layer is formed and the fourth semiconductor layer is not formed. The length of the polarization super-junction region in a direction connecting the shortest distance from the source electrode contact region to the drain electrode contact region at the tip of the rod-shaped shape is equal to or longer than the length of the polarization super-junction region in a direction connecting the shortest distance from the source electrode contact region to the drain electrode contact region at the portion other than the tip of the rod-shaped shape.

In the semiconductor element of the second embodiment, the tip portion of the rod shape is an arc-shaped portion. The portion other than the tip portion of the rod shape is a straight rod-shaped portion.

In the semiconductor element of the third aspect, the length of the polarization superjunction region in the direction of the shortest distance from the source electrode contact region to the drain electrode contact region at the tip of the rod-shaped shape is 1.05 or more relative to the length of the polarization superjunction region in the direction of the shortest distance from the source electrode contact region to the drain electrode contact region at the part other than the tip of the rod-shaped shape.

In the semiconductor element of the fourth aspect, the distance between the source electrode contact region and the drain electrode contact region at the tip of the rod shape is equal to or greater than the distance between the source electrode contact region and the drain electrode contact region at the portion other than the tip of the rod shape.

The semiconductor element in the fifth aspect has a first semiconductor layer, a second semiconductor layer above the first semiconductor layer, a third semiconductor layer above the second semiconductor layer, a fourth semiconductor layer above the third semiconductor layer, a cathode electrode above the second semiconductor layer, an anode electrode above the fourth semiconductor layer, a cathode electrode contact region where the cathode electrode and the second semiconductor layer are in contact, and an anode electrode contact region where the anode electrode and the fourth semiconductor layer are in contact. The first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are Group III nitride semiconductor layers. The band gap of the second semiconductor layer is larger than the band gaps of the first semiconductor layer and the third semiconductor layer. The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are undoped semiconductor layers. The fourth semiconductor layer is a p-type semiconductor layer. The anode electrode is in contact with the second semiconductor layer or the first semiconductor layer. One of the cathode electrode contact region and the anode electrode contact region has a rod-like shape. The other of the cathode electrode contact region and the anode electrode contact region has a comb-tooth shape. The rod-shaped shape of one of the cathode electrode contact region and the anode electrode contact region is disposed between the comb-tooth shape of the other of the cathode electrode contact region and the anode electrode contact region. This semiconductor element has a polarization super-junction region located between the cathode electrode contact region and the anode electrode contact region in a region where the third semiconductor layer is formed and the fourth semiconductor layer is not formed. The length of the polarization super-junction region in the direction of the shortest distance from the cathode electrode contact region to the anode electrode contact region at the tip of the rod-shaped shape is equal to or longer than the length of the polarization super-junction region in the direction of the shortest distance from the cathode electrode contact region to the anode electrode contact region at the part other than the tip of the rod-shaped shape.

In a sixth aspect, the semiconductor element has a first recess that extends from the fourth semiconductor layer to the second semiconductor layer. The cathode electrode is formed at least on the first recess.

In the seventh aspect of the semiconductor element, the cathode electrode is in contact with a side surface of the first semiconductor layer and a side surface of the second semiconductor layer.

The semiconductor element in the eighth aspect has an anode electrode contact region where the anode electrode and the fourth semiconductor layer are in contact, and a second recess that extends from the fourth semiconductor layer to the first semiconductor layer. The anode electrode is formed on the second recess and is in contact with the first semiconductor layer or the second semiconductor layer.

In the ninth aspect, the semiconductor element has an insulating layer between the third and fourth semiconductor layers and the anode electrode.

The device in the tenth aspect has the semiconductor element described above.

4. Fourth
The semiconductor element in the first aspect has a first semiconductor layer, a second semiconductor layer above the first semiconductor layer, a third semiconductor layer above the second semiconductor layer, a fourth semiconductor layer above the third semiconductor layer, a source electrode and a drain electrode above the second semiconductor layer or the third semiconductor layer, a gate electrode above the fourth semiconductor layer, a gate electrode contact region where the gate electrode and the fourth semiconductor layer are in contact, a source electrode contact region where the source electrode and the second semiconductor layer or the third semiconductor layer are in contact, a drain electrode contact region where the drain electrode and the second semiconductor layer or the third semiconductor layer are in contact, and a first recess and a second recess that reach from the fourth semiconductor layer to the second semiconductor layer. The first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are Group III nitride semiconductor layers. The band gap of the second semiconductor layer is larger than the band gaps of the first semiconductor layer and the third semiconductor layer. The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are undoped semiconductor layers. The fourth semiconductor layer is a p-type semiconductor layer. A source electrode is formed on the first recess. A drain electrode is formed on the second recess. A distance between the drain electrode contact region and the third semiconductor layer is greater than a distance between the source electrode contact region and the third semiconductor layer.

In the semiconductor element of the second aspect, the distance between the drain electrode contact region and the third semiconductor layer is 10 μm or less.

In the semiconductor element of the third aspect, when the source electrode contact region, the drain electrode contact region, and the gate electrode contact region are projected onto the second semiconductor layer, the distance between the region onto which the drain electrode contact region is projected and the region onto which the gate electrode contact region is projected is greater than the distance between the region onto which the source electrode contact region is projected and the region onto which the gate electrode contact region is projected.

The semiconductor element in the fourth aspect has a first semiconductor layer, a second semiconductor layer above the first semiconductor layer, a third semiconductor layer above the second semiconductor layer, a fourth semiconductor layer above the third semiconductor layer, a cathode electrode above the second semiconductor layer, an anode electrode above the fourth semiconductor layer, and a cathode electrode contact region where the cathode electrode and the second semiconductor layer are in contact. The first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are Group III nitride semiconductor layers. The band gap of the second semiconductor layer is larger than the band gaps of the first semiconductor layer and the third semiconductor layer. The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are undoped semiconductor layers. The fourth semiconductor layer is a p-type semiconductor layer. The distance between the cathode electrode contact region and the third semiconductor layer is 10 μm or less.

In a fifth aspect, the semiconductor element has a first recess that extends from the fourth semiconductor layer to the second semiconductor layer. The cathode electrode is formed at least on the first recess.

In the semiconductor element of the sixth aspect, the cathode electrode is in contact with a side surface of the first semiconductor layer and a side surface of the second semiconductor layer.

The semiconductor element in the seventh aspect has an anode electrode contact region where the anode electrode and the fourth semiconductor layer are in contact, and a second recess that extends from the fourth semiconductor layer to the first semiconductor layer. The anode electrode is formed on the second recess and is in contact with the first semiconductor layer or the second semiconductor layer.

In the eighth aspect, the semiconductor element has an insulating layer between the third and fourth semiconductor layers and the anode electrode.

The device in the ninth aspect has the semiconductor element described above.

5. Fifth
The semiconductor element in the first aspect has a first semiconductor layer, a second semiconductor layer above the first semiconductor layer, a third semiconductor layer above the second semiconductor layer, a fourth semiconductor layer above the third semiconductor layer, a source electrode and a drain electrode above the second semiconductor layer or the third semiconductor layer, and a gate electrode above the fourth semiconductor layer. The first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are group III nitride semiconductor layers. The band gap of the second semiconductor layer is larger than the band gaps of the first semiconductor layer and the third semiconductor layer. The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are undoped semiconductor layers. The fourth semiconductor layer is a p-type semiconductor layer. At least one of the gate electrode, the source electrode, and the drain electrode has a contact electrode, a wiring electrode, and a pad electrode. The wiring electrode connects the contact electrode and the pad electrode. The wiring electrode has a curved portion curved in an arc shape.

In the second aspect of the semiconductor element, at least one of the gate electrode, source electrode, and drain electrode has multiple pad electrodes.

In the semiconductor element of the third aspect, the gate electrode, source electrode, and drain electrode have contact electrodes, wiring electrodes, and pad electrodes. This semiconductor element has an insulating layer between the wiring electrode of the gate electrode and the wiring electrode of the source electrode. The insulating layer has a first insulating layer and a second insulating layer on the first insulating layer.

In the semiconductor element of the fourth aspect, the insulating layer has at least one of an inorganic dielectric film and an organic dielectric film.

In the semiconductor element of the fifth aspect, the first semiconductor layer and the second semiconductor layer are in direct contact with each other. The shape of the contact surface where the first semiconductor layer and the second semiconductor layer are in contact with each other is rectangular.

The device in the sixth aspect has the semiconductor element described above.

6. No. 6
The semiconductor device according to the first aspect has a first semiconductor layer, a second semiconductor layer above the first semiconductor layer, a third semiconductor layer above the second semiconductor layer, a fourth semiconductor layer above the third semiconductor layer, a source electrode and a drain electrode above the second semiconductor layer or the third semiconductor layer, and a gate electrode above the fourth semiconductor layer. The first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are Group III nitride semiconductor layers. The band gap of the second semiconductor layer is larger than the band gaps of the first semiconductor layer and the third semiconductor layer. The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are undoped semiconductor layers. The fourth semiconductor layer is a p-type semiconductor layer. The dislocation density is 1×10 ⁶ cm ⁻² or more and 1×10 ¹⁰ cm ⁻² or less. The contact area between the second semiconductor layer and the third semiconductor layer is 10 μm ² or more and 200 μm ² or less per μm in the gate width direction.

In the semiconductor device according to the second aspect, the dislocation density is 5×10 ⁹ cm ⁻² or less.

In the semiconductor element according to the third aspect, the contact area between the second semiconductor layer and the third semiconductor layer and the breakdown voltage are expressed by the following formula: 101x-810≦y≦235x+585
x: contact area between the second semiconductor layer and the third semiconductor layer per 1 μm in the gate width direction; y: satisfying the breakdown voltage.

In the semiconductor element of the fourth aspect, the gate length, which is the length of the fourth semiconductor layer in the direction connecting the shortest distance from the source electrode contact region to the drain electrode contact region, is 6 μm or less. Both the rise time and fall time at 300 V switching are 30 ns or less.

The semiconductor element in the fifth aspect has the above-mentioned semiconductor element.

7. Seventh
The semiconductor device in the first aspect has a first semiconductor layer, a second semiconductor layer above the first semiconductor layer, a third semiconductor layer above the second semiconductor layer, a fourth semiconductor layer above the third semiconductor layer, a source electrode and a drain electrode above the second semiconductor layer or the third semiconductor layer, a gate electrode above the fourth semiconductor layer, a source electrode contact region where the source electrode and the second semiconductor layer or the third semiconductor layer are in contact, and a drain electrode contact region where the drain electrode and the second semiconductor layer or the third semiconductor layer are in contact. The first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are Group III nitride semiconductor layers. The band gap of the second semiconductor layer is larger than the band gaps of the first semiconductor layer and the third semiconductor layer. The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are undoped semiconductor layers. The fourth semiconductor layer is a p-type semiconductor layer. The semiconductor element has a polarization super-junction region located between the gate electrode contact region and the drain electrode contact region in a region where the third semiconductor layer is formed and where the fourth semiconductor layer is not formed. The polarization super-junction length, which is the length of the polarization super-junction region in a direction along the shortest distance from the source electrode contact region to the drain electrode contact region, is 50 μm or less. The gate length, which is the length of the fourth semiconductor layer in a direction along the shortest distance from the source electrode contact region to the drain electrode contact region, is 6 μm or less.

In the semiconductor element according to the second aspect, the normalized on-resistance is 20 mΩ·cm ² or less.

In the semiconductor element of the third aspect, both the rise time and fall time at 300V switching are 30ns or less.

The device in the fourth aspect has the semiconductor element described above.

8. No. 8
The semiconductor device in the first aspect has a first semiconductor layer, a second semiconductor layer above the first semiconductor layer, a third semiconductor layer above the second semiconductor layer, a fourth semiconductor layer above the third semiconductor layer, a source electrode and a drain electrode above the second semiconductor layer or the third semiconductor layer, a gate electrode above the fourth semiconductor layer, a source electrode contact region where the source electrode and the second semiconductor layer or the third semiconductor layer are in contact, and a drain electrode contact region where the drain electrode and the second semiconductor layer or the third semiconductor layer are in contact. The first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are Group III nitride semiconductor layers. The band gap of the second semiconductor layer is larger than the band gaps of the first semiconductor layer and the third semiconductor layer. The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are undoped semiconductor layers. The fourth semiconductor layer is a p-type semiconductor layer. The active region area, obtained by subtracting the areas of the source electrode contact region and the drain electrode contact region and the area of the region sandwiched between the outermost source electrode contact region and the outer periphery of the second semiconductor layer from the area of the second semiconductor layer on the third semiconductor layer side, is ^2.2 mm2 or more.

In the semiconductor element of the second aspect, the gate length, which is the length of the fourth semiconductor layer in the direction connecting the shortest distance from the source electrode contact region to the drain electrode contact region, is 6 μm or less.

In the third aspect of the semiconductor element, the gate width is 300 mm or more.

In the fourth aspect, the semiconductor element has a peripheral length of 13 mm or more.

In the semiconductor element of the fifth aspect, both the rise time and fall time are 30 ns or less.

In the semiconductor element of the sixth aspect, the source electrode has a source pad electrode exposed to the outside of the element. The drain electrode has a drain pad electrode exposed to the outside of the element. The area where the source pad electrode and the drain pad electrode are projected onto the second semiconductor layer does not overlap with the formation area of the second semiconductor layer.

The semiconductor element in the seventh aspect has the above-mentioned semiconductor element.

100...semiconductor element Sub1...sapphire substrate Bf1...buffer layer 110...first semiconductor layer 120...second semiconductor layer 130...third semiconductor layer 140...fourth semiconductor layer S1...source electrode SC1...source electrode contact region D1...drain electrode DC1...drain electrode contact region G1...gate electrode GC1...gate electrode contact region

Claims (6)

A first semiconductor layer;
A second semiconductor layer above the first semiconductor layer;
a third semiconductor layer above the second semiconductor layer;
a fourth semiconductor layer above the third semiconductor layer;
a source electrode and a drain electrode on the second semiconductor layer or the third semiconductor layer;
a gate electrode on the fourth semiconductor layer;
having
The first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are
a Group III nitride semiconductor layer;
The band gap of the second semiconductor layer is
a band gap larger than the band gap of the first semiconductor layer and the third semiconductor layer;
The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are
It is an undoped semiconductor layer,
The fourth semiconductor layer is
A p-type semiconductor layer,
At least one of the gate electrode, the source electrode, and the drain electrode is
The semiconductor device has a contact electrode, a wiring electrode, and a pad electrode,
The wiring electrode is
The contact electrode and the pad electrode are connected to each other.
The wiring electrode is
A curved portion that is curved in an arc shape ,
a region where the second semiconductor layer or the third semiconductor layer contacts the source electrode is defined as a source electrode contact region, and a region where the fourth semiconductor layer contacts the gate electrode is defined as a gate electrode contact region,
The source electrode contact region is present in a plurality of regions spaced apart from each other,
the gate electrode contact regions are in an annular pattern surrounding each of the source electrode contact regions . 2. The semiconductor device according to claim 1 ,
At least one of the gate electrode, the source electrode, and the drain electrode is
A semiconductor device having a plurality of pad electrodes. 3. The semiconductor device according to claim 1,
The gate electrode, the source electrode, and the drain electrode are
The semiconductor device has a contact electrode, a wiring electrode, and a pad electrode,
an insulating layer on the wiring electrode of the gate electrode;
The insulating layer is
A first insulating layer;
a second insulating layer on the first insulating layer;
A semiconductor device comprising: 4. The semiconductor device according to claim 3,
the first insulating layer is an inorganic dielectric film,
The second insulating layer is an organic dielectric film.
A semiconductor element comprising: The semiconductor device according to any one of claims 1 to 4,
the first semiconductor layer and the second semiconductor layer are in direct contact with each other;
The shape of a contact surface where the first semiconductor layer and the second semiconductor layer are in contact with each other is
A semiconductor element that is rectangular. A device having a semiconductor element according to any one of claims 1 to 5.

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