JP7509148B2 - DATA PROCESSING APPARATUS, DATA PROCESSING METHOD, AND PROGRAM - Google Patents

Description

The present disclosure relates to a data processing device, a data processing method, and a program, and in particular to a data processing device, a data processing method, and a program that enable secure transmission of biometric authentication results.

Traditionally, many biometric authentication technologies have been proposed to identify individuals using biometric information such as human fingerprints, faces, iris patterns, and vein patterns.

For example, Patent Document 1 discloses a communication system in which a communication terminal device encrypts a message indicating that biometric authentication has been successful and notifies a server, and the server begins providing a service when it receives the message.

JP 2009-140231 A

On the other hand, in recent years, there are devices such as smartphones and wearable devices that operate by performing biometric authentication.

However, in the past, when transmitting the biometric authentication results from an authentication chip in such devices to a separate control chip, there was a significant risk of data tampering or replay attacks.

This disclosure has been made in light of these circumstances and makes it possible to securely transmit biometric authentication results between chips.

The data processing device disclosed herein includes a first chip that performs encryption and decryption using a first common key and holds a first counter value, and a second chip that performs encryption and decryption using the first common key and holds a second counter value, the first chip encrypts a command and the first counter value and transmits them to the second chip, the second chip encrypts the execution result of the decrypted command and the second counter value and transmits them to the first chip, and the first chip and the second chip are data processing devices that synchronize the first counter value and the second counter value each time data is transmitted to and received from the other chip.

The data processing method disclosed herein is a data processing device comprising a first chip that performs encryption and decryption using a first common key and holds a first counter value, and a second chip that performs encryption and decryption using the first common key and holds a second counter value, the first chip encrypts a command and the first counter value and transmits them to the second chip, the second chip encrypts the execution result of the decrypted command and the second counter value and transmits them to the first chip, and the first chip and the second chip synchronize the first counter value and the second counter value each time data is transmitted to and received from each other.

The program disclosed herein is a program for causing a computer to function as a first chip that performs encryption and decryption using a first common key and holds a first counter value, and a second chip that performs encryption and decryption using the first common key and holds a second counter value, in which the first chip encrypts a command and the first counter value and transmits them to the second chip, the second chip encrypts the execution result of the decrypted command and the second counter value and transmits them to the first chip, and the first chip and the second chip synchronize the first counter value and the second counter value each time data is transmitted to and received from each other.

In the present disclosure, a command and a first counter value are encrypted and transmitted to a second chip, the execution result of the decrypted command and the second counter value are encrypted and transmitted to a first chip, and the first counter value and the second counter value are synchronized between the first chip and the second chip each time data is transmitted to and received from the other chip.

1 is a block diagram showing a configuration example of a data processing device according to the present disclosure. 1 is a diagram illustrating a configuration example of a fingerprint authentication device according to an embodiment of the present disclosure. 1A and 1B are diagrams illustrating states of the fingerprint authentication device. FIG. 1 is a diagram illustrating a flow of sharing and storing a key. 1A and 1B are diagrams illustrating states of the fingerprint authentication device. FIG. 11 is a diagram illustrating a flow of key sharing when the power is turned on. 1A and 1B are diagrams illustrating states of the fingerprint authentication device. FIG. 11 is a diagram illustrating a flow of generating and encrypting an authentication template. 1A and 1B are diagrams illustrating states of the fingerprint authentication device. FIG. 11 is a diagram illustrating a flow of encryption and transmission of authentication results. FIG. 13 is a diagram illustrating a modified example. FIG. 13 is a diagram illustrating a modified example. FIG. 13 is a diagram illustrating a modified example. FIG. 13 is a diagram illustrating a modified example. FIG. 13 is a diagram illustrating a modified example. FIG. 13 is a diagram illustrating a modified example.

The following describes the form for implementing the present disclosure (hereinafter, referred to as the embodiment). The description will be given in the following order:

1. Example of the configuration of a data processing device 2. Example of the configuration of a fingerprint authentication device 3. States and operations of the fingerprint authentication device 3-1. Initial state of the fingerprint authentication device 3-2. Sharing and saving keys 3-3. Sharing keys at power-on 3-4. Generating and encrypting authentication templates 3-5. Encrypting and transmitting authentication results 4. Modifications 4-1. First modification 4-2. Second modification 4-3. Third modification 4-4. Fourth modification 4-5. Fifth modification 4-6. Sixth modification

1. Example of the configuration of a data processing device
FIG. 1 is a block diagram showing an example of the configuration of a data processing device according to the present disclosure.

The data processing device 10 shown in FIG. 1 constitutes part of a device that operates by performing biometric authentication, such as a smartphone, a wearable terminal, a personal computer, AR (Augmented Reality) glasses, or VR (Virtual Reality) glasses. Biometric authentication includes fingerprint authentication, face authentication, iris authentication, vein authentication, and even gait authentication. For example, in the case of a smartphone, the user is authenticated when he or she uses the smartphone, and in the case of a wearable terminal, the user is authenticated when he or she puts on the wearable terminal.

The data processing device 10 has a first chip 11, a second chip 12, and a sensor 13.

The first chip 11 is a control chip that controls the second chip 12 and the like, and is composed of, for example, a CPU (Central Processing Unit) or a SOC (System-on-a-Chip) including a CPU. The first chip 11 may also be composed of a SE (Secure Element) or a CPU including a SE.

The second chip 12 is an authentication chip that performs biometric authentication based on characteristic information from the sensor 13, and is composed of, for example, an FPGA (Field-Programmable Gate Array) or a CPU.

The sensor 13 is a sensor that acquires sensor data including bioinformation, and is composed of, for example, an image sensor with a microlens array arranged on an imaging surface. The bioinformation may include, for example, acceleration, angular velocity, orientation, altitude, illuminance, temperature, air pressure, pulse, sweat, brainwaves, touch, smell, taste, other bioinformation, emotions, and location information detected by a sensor included in another system that cooperates with an external service, and information generated by posting to the external service. The sensor 13 may also be composed of a microphone or the like, and may acquire voice as sensor data. Furthermore, the sensor 13 may include a position detection means for detecting an indoor or outdoor position. The position detection means may specifically include a GNSS (Global Navigation Satellite System) receiver, for example a GPS (Global Positioning System) receiver, a GLONASS (Global Navigation Satellite System) receiver, a BDS (BeiDou Navigation Satellite System) receiver, and/or a communication device. The communication device detects its location using technologies such as Wi-fi (registered trademark), MIMO (Multi-Input Multi-Output), cellular communication (e.g., location detection using a mobile base station, femtocell), or short-range wireless communication (e.g., Bluetooth (registered trademark), BLE (Bluetooth Low Energy)).

The first chip 11 and the second chip 12 transmit and receive data to each other while encrypting and decrypting data using an authenticated encryption method that uses the same common key. The common key is built in beforehand at the factory, etc.

In addition, the first chip 11 holds a first counter value (CTR1), and the second chip 12 holds a second counter value (CTR2). The first chip 11 and the second chip 12 synchronize the counter values CTR1 and CTR2 each time data is transmitted or received with the other chip.

Specifically, after receiving data from the other, the first chip 11 and the second chip 12 check whether the decrypted counter value CTR1 and the counter value CTR2 match. After checking whether they match and after transmitting data to the other, the first chip 11 and the second chip 12 update the counter value CTR1 or the counter value CTR2 that they each hold.

For example, the first chip 11 uses a common key to encrypt the counter value CTR1 and a command to be executed by the second chip 12, and transmits them to the second chip 12. After that, the first chip 11 increments the counter value CTR1 by 1.

The second chip 12 uses the common key to verify and decrypt the counter value CTR1 and command from the first chip 11, and determines whether the decrypted counter value CTR1 matches the counter value CTR2 it holds. If the counter values CTR1 and CTR2 match, the second chip 12 increments the counter value CTR2 by 1 and executes the decrypted command. Specifically, the second chip 12 performs biometric authentication based on the decrypted command. If the counter values CTR1 and CTR2 do not match, the second chip 12 ends the process.

The second chip 12 uses the common key to encrypt the incremented counter value CTR2 and the command execution result (biometric authentication result) and transmits them to the first chip 11. The second chip 12 then further increments the counter value CTR2 by 1.

The first chip 11 uses the common key to verify and decrypt the counter value CTR2 and the biometric authentication result from the second chip 12, and determines whether the decrypted counter value CTR2 matches the counter value CTR1 it holds. If the counter value CTR1 and the counter value CTR2 match, the first chip 11 increments the counter value CTR1 by 1. If the counter value CTR1 and the counter value CTR2 do not match, the first chip 11 ends the process.

In this way, the counter values CTR1 and CTR2 are synchronized so that they are incremented by 2 between the transmission of a command by the first chip 11 and the transmission of the authentication result by the second chip 12.

The results of the biometric authentication are supplied to an SE (not shown) and used, for example, for payment processing via NFC (Near Field Communication).

According to the above configuration, when the authentication result of the biometric authentication in the second chip 12 is transmitted to the first chip 11 within the data processing device 10, data tampering can be prevented and resistance to replay attacks can be increased. In other words, it is possible to transmit the authentication result of the biometric authentication securely between chips. At this time, only the authentication result of the biometric authentication is transmitted at high speed with a small amount of communication while maintaining security.

Below, we describe an embodiment in which the technology disclosed herein is applied to a fingerprint authentication device.

2. Example of the fingerprint authentication device configuration
FIG. 2 is a diagram illustrating an example of a configuration of a fingerprint authentication device according to an embodiment of the present disclosure.

The fingerprint authentication device 100 shown in Figure 2 forms part of a device that operates by performing biometric authentication, such as a watch-type wearable terminal.

The fingerprint authentication device 100 includes a CPU 110, an FPGA 120, a sensor module 130, a RAM (Random Access Memory) 140, a non-volatile memory 150, and a setting ROM (Read Only Memory) 160. The CPU 110 is also connected to an SE 170 and an RF communication unit 180.

1 and is configured as a control chip that controls the FPGA 120 and the like. The CPU 110 exchanges control signals with the FPGA 120, the SE 170, and the RF communication unit 180. The CPU 110 holds a counter value CTR1.

1 and is configured as an authentication chip that performs biometric authentication based on video data from the sensor module 130. The FPGA 120 exchanges control signals with the sensor module 130. The FPGA 120 holds a counter value CTR2.

The FPGA 120 has a calculation unit 121, an extraction unit 122, and a matching unit 123.

The calculation unit 121 is a calculation IP (Intellectual Property) core provided by the setting ROM 160 and includes a fingerprint authentication algorithm and FPGA control code.

Based on the fingerprint authentication algorithm of the calculation unit 121, the extraction unit 122 extracts feature amount data of the fingerprint of the finger to be authenticated from the image data supplied from the image sensor 131. The image data from the image sensor 131 and the extracted feature amount data are temporarily stored in the RAM 140 as image data 141 and feature amount data 142.

Based on the fingerprint authentication algorithm of the calculation unit 121, the matching unit 123 matches the feature data extracted by the extraction unit 122 with the authentication template 151 stored in the non-volatile memory 150. The result of the matching is supplied to the SE 170 via the CPU 110 as the authentication result of the fingerprint authentication.

The sensor module 130 is composed of an image sensor 131 and an LED light 132. The image sensor 131 captures an image of the fingerprint of the finger to be authenticated and supplies the obtained image data to the FPGA 120. The LED light 132 irradiates light onto the fingerprint of the finger to be authenticated based on the LED current from the FPGA 120.

The RAM 140 temporarily stores the video data 141 and feature data 142 from the extraction unit 122.

The non-volatile memory 150 stores a pre-generated authentication template 151. The authentication template 151 is read out to the matching unit 123 of the FPGA 120 and used to match the feature data extracted by the extraction unit 122.

The setting ROM 160 stores the above-mentioned calculation IP core and provides it to the calculation unit 121. A debug controller 161 is connected to the setting ROM 160 as necessary.

Based on the authentication result supplied from FPGA 120 via CPU 110, SE 170 performs payment processing by NFC via RF communication unit 180. Note that SE 170 may be built into CPU 110.

With the above-described configuration, the fingerprint authentication device 100 can perform payment processing using fingerprint authentication.

<3. Status and operation of fingerprint authentication device>
The states and operations of the above-mentioned fingerprint authentication device 100 will be described below.

(3-1. Initial state of the fingerprint authentication device)
FIG. 3 is a diagram showing the initial state of the fingerprint authentication device 100 in the factory.

In the fingerprint authentication device 100 described in Figure 3 and subsequent figures, only the CPU 110, FPGA 120, image sensor 131, RAM 140, non-volatile memory 150, and setting ROM 160 are shown.

In the fingerprint authentication device 100 of FIG. 3, the CPU 110 holds unique identification information ID _C.

On the other hand, the FPGA 120 holds unique identification information ID _F as hardware information. Furthermore, the FPGA 120 holds a common key K _common provided by the setting ROM 160 as setting information.

(3-2. Sharing and storing keys)
Next, a flow of sharing and storing a key between the CPU 110 and the FPGA 120 in a factory will be described with reference to FIG.

In step S11, the CPU 110 generates a common key _K1 using a pseudo-random number generator (PRNG).

In step S12, the CPU 110 transmits the generated key K ₁ to the FPGA 120 together with the identification information ID _C that it holds.

Thereafter, in step S13, the CPU 110 stores the generated key _K1 .

On the other hand, the FPGA 120 receives the identification information ID _C and the key K ₁ sent from the CPU 110 in step S 21 .

Thereafter, in step S22, the FPGA 120 stores the received identification information ID _C and key K ₁ in an internal non-volatile area.

FIG. 5 is a diagram showing the state of the fingerprint authentication device 100 after the key K ₁ has been shared and stored.

In the fingerprint authentication device 100 in FIG. 5, the CPU 110 holds a key _K1 in addition to the state in FIG.

3, the FPGA 120 stores the identification information ID _C and the key K ₁ of the CPU 110 in an internal non-volatile area. When the power supply of the fingerprint authentication device 100 is OFF, the FPGA 120 stores only the identification information ID _C and the key K ₁ .

Note that the key K ₁ may be generated by an external device and supplied to the CPU 110 and FPGA 120 instead of by the CPU 110 .

(3-3. Key sharing at power-on)
Next, a flow of key sharing between the CPU 110 and the FPGA 120 that is performed when the power is turned on will be described with reference to FIG.

In step S31, the FPGA 120 reads the key _K1 from the internal non-volatile area.

On the other hand, the CPU 110 also reads out the key _K1 in step S41.

In steps S32 and S42, the FPGA 120 and the CPU 110 execute key sharing based on the key _K1 . For example, the key sharing is executed using a key sharing protocol (ISO/IEC 11770-2) using the key _K1 as a common key. At this time, mutual authentication based on ISO/IEC 9798-2 is also performed between the FPGA 120 and the CPU 110. Note that the key sharing protocol is not limited to the one described above.

As a result of steps S32 and S42, the key K ₂ is shared between the FPGA 120 and the CPU 110.

In step S33, the FPGA 120 stores the shared key _K2 in an internal RAM area.

Then, in step S34, FPGA 120 sets (resets) the counter value CTR2 stored internally to 0.

On the other hand, in step S43, the CPU 110 stores the shared key _K2 .

Then, in step S44, the CPU 110 sets (resets) the counter value CTR1 stored internally to 0.

Figure 7 shows the state of the fingerprint authentication device 100 after key sharing is performed when the power is turned on.

In the fingerprint authentication device 100 in FIG. 7, the CPU 110 holds a key _K2 and a counter value CTR1 set to 0 in addition to the state in FIG.

On the other hand, in addition to the state shown in FIG. 5, the FPGA 120 holds a key _K2 and a counter value CTR2 set to 0 in the internal RAM area.

In this manner, in the fingerprint authentication device 100, a new key _K2 is generated every time the power is turned on.

(3-4. Generating and Encrypting an Authentication Template)
Next, a flow of generating and encrypting an authentication template in the FPGA 120 when the power is turned on will be described with reference to Fig. 8. The process in Fig. 8 starts when the image sensor 131 captures an image of the user's fingerprint and supplies the obtained image data to the FPGA 120.

In step S51, the FPGA 120 generates an authentication template T by extracting fingerprint feature data from the image data from the image sensor 131 based on a predetermined algorithm.

In step S52, the FPGA 120 generates a storage key K _STO =AES_CMAC(K ₁ , ID _F ∥ID _C ) based on the Advanced Encryption Standard (AES)-Cipher-based Message Authentication Code (CMAC) algorithm. In generating the storage key K _STO , the key K ₁ and data ID _F ∥ID _C obtained by concatenating the identification information ID _F of the FPGA 120 and the identification information ID _C of the CPU 110 are used. Note that here, in addition to AES, common key block encryption methods such as DES (Data Encryption Standard), Triple DES, the Fast Data Encipherment Algorithm (FEAL), and IDEA (International Data Encryption Algorithm) may be used. In addition to CMAC, MAC algorithms such as CBC-MAC (Cipher Block Chaining MAC) and HMAC (Hash-based MAC) may be used.

In step S53, the FPGA 120 encrypts the authentication template T using the storage key K _STO .

Then, in step S54, the FPGA 120 stores the encrypted authentication template C ₂ =AES_Enc(K _STO , T) in the non-volatile memory 150.

Figure 9 shows the state of the fingerprint authentication device 100 after the authentication template has been generated and encrypted.

In the fingerprint authentication device 100 of FIG. 9, the encrypted authentication template C ₂ is stored in the non-volatile memory 150 .

(3-5. Encryption and transmission of authentication results)
Next, a flow of encryption and transmission of authentication results in the CPU 110 and the FPGA 120 will be described with reference to Fig. 10. The process in Fig. 10 is started, for example, when the fingerprint authentication device 100 configured as a watch-type wearable terminal is worn and it is detected that the user's finger is placed over the sensor module 130.

In step S61, the CPU 110 generates a command for causing the FPGA 120 to execute biometric authentication (fingerprint authentication) and encrypts the command by authenticated encryption with associated data (AEAD) and AES using a common key _K2 . At this time, the counter value CTR1 is also encrypted together with the command.

In step S62, the CPU 110 transmits encrypted data COM, in which the command command and the counter value CTR1 are encrypted, to the FPGA 120.

Then, in step S63, the CPU 110 increments the counter value CTR1 by 1.

On the other hand, the FPGA 120 receives the encrypted data COM from the CPU 110 in step S71, and in step S72 verifies the encrypted data COM (verifies that it has not been tampered with) and decrypts it using the key _K2 , which is a common key.

In step S73, FPGA 120 determines whether the decoded counter value CTR1 matches the held counter value CTR2.

If it is determined that counter value CTR1 and counter value CTR2 do not match, processing proceeds to step S74 and terminates abnormally.

On the other hand, if it is determined that the counter value CTR1 and the counter value CTR2 match, the process proceeds to step S75, and the FPGA 120 increments the counter value CTR2 by 1.

Thereafter, in step S76, the FPGA 120 performs fingerprint authentication of the finger to be authenticated by executing the decrypted command using the authentication template _C2 stored in the non-volatile memory 150. Specifically, the FPGA 120 performs fingerprint authentication of the finger to be authenticated based on the image data acquired by the image sensor 131 and the authentication template _C2 .

In step S77, the FPGA 120 generates an authentication result “result” regardless of whether the fingerprint authentication is successful or unsuccessful, and encrypts it by the AEAD and AES using the common key _K2 . At this time, the incremented counter value CTR2 is also encrypted together with the authentication result “result”.

In step S78, FPGA 120 transmits encrypted data RESP, in which the authentication result result and counter value CTR2 are encrypted, to CPU 110.

Then, in step S79, FPGA120 increments counter value CTR2 by 1.

On the other hand, the CPU 110 receives the encrypted data RESP from the FPGA 120 in step S64, and verifies and decrypts the encrypted data RESP using the key _K2 , which is a common key, in step S65.

In step S66, the CPU 110 determines whether the decoded counter value CTR2 matches the held counter value CTR1.

If it is determined that counter value CTR2 and counter value CTR1 do not match, processing proceeds to step S67 and terminates abnormally.

On the other hand, if it is determined that counter value CTR2 and counter value CTR1 match, processing proceeds to step S68, in which CPU 110 increments counter value CTR1 by 1.

The results of the fingerprint authentication are supplied to SE170 and used, for example, for payment processing via NFC via the RF communication unit 180.

According to the above process, when the authentication result of fingerprint authentication in FPGA 120 in fingerprint authentication device 100 is transmitted to CPU 110, encryption and decryption are performed using an authenticated encryption method, and counter values are synchronized. This prevents data tampering and increases resistance to replay attacks. In other words, it becomes possible to transmit the authentication result of fingerprint authentication safely between chips. At this time, only the authentication result of fingerprint authentication is transmitted at high speed and with a small amount of communication while maintaining security.

4. Modifications
In the following, a modification of the above-described embodiment will be described.

(4-1. First Modified Example)
FIG. 11 shows an example of the configuration of a fingerprint authentication device 100 in which only the SE 170 knows the authentication result of fingerprint authentication.

In the configuration of Figure 11, since the CPU 110 does not need to know the authentication result, the authentication result is transmitted directly from the FPGA 120 to the SE 170 with the CPU 110 serving simply as a communication path.

In this case, the key _K1 is shared between the SE 170 and the FPGA 120 in the same manner as in the process of Fig. 4. After that, processes similar to those in Figs.

With this configuration, payment processing can be performed, for example, by NFC via the RF communication unit 180, with fewer steps.

(4-2. Second Modified Example)
FIG. 12 shows an example of the configuration of a fingerprint authentication device 100 in which the CPU 110 and the SE 170 each know the result of fingerprint authentication.

In the configuration of Figure 12, the authentication result is transmitted from FPGA 120 to each of CPU 110 and SE 170.

In this case, the key _K1 is shared between the CPU 110 and the FPGA 120 according to the process of Fig. 4. Thereafter, the processes of Figs.

4, a key K ₁ ' different from the key K ₁ is shared between the SE 170 and the FPGA 120. After that, processing similar to that in FIGS.

With this configuration, it is possible to securely transmit the fingerprint authentication results to both the CPU 110 and the SE 170.

(4-3. Third Modified Example)
FIG. 13 shows another example of the configuration of the fingerprint authentication device 100 in which the CPU 110 and the SE 170 each know the result of fingerprint authentication.

In the configuration of FIG. 13, the authentication result is transmitted from FPGA 120 to CPU 110. Then, the authentication result decrypted by CPU 110 is transmitted from CPU 110 to SE 170.

In this case, the key _K1 is shared between the CPU 110 and the FPGA 120 according to the process of Fig. 4. Thereafter, the processes of Figs.

4, a key K ₁ ' different from key K ₁ is shared between SE 170 and CPU 110. Thereafter, processing similar to that in FIGS.

With this configuration, it is possible to securely transmit the fingerprint authentication results to both the CPU 110 and the SE 170.

(4-4. Fourth Modified Example)
The above has described a configuration assuming that authentication of the user is performed when the wearable terminal is worn, for example.

Without being limited to this, for example, as shown in FIG. 14, when an authentication result is required in SE170, SE170 may inquire about the authentication result from FPGA120, and FPGA120 may respond to SE170 with the authentication result that it holds.

This configuration can be used in cases where the wearable device is touched once to a POS terminal at the time of payment to authenticate the user, and then touched to the POS terminal again to authenticate the user if the payment amount is higher than a certain amount. This configuration can further increase the security of authentication.

(4-5. Fifth Modification)
The above describes a configuration in which encryption and decryption are performed within the same device while ensuring a minimum level of security, but the technology disclosed herein can also be applied to a configuration in which encryption and decryption are performed over a network rather than within the same device.

Figure 15 shows an example system configuration in which the technology disclosed herein is applied to a server and a device connected via a network.

In the system shown in FIG. 15, a server 210 and a device 220 having a CPU 110, an FPGA 120, and an image sensor 131 are connected via a network NW.

In the configuration of FIG. 15, the authentication result is transmitted from the device 220 to the server 210. The server 210 executes processing using the authentication result from the device 220.

In this case, the key _K1 is shared between the server 210 and the device 220 (FPGA 120) in the same manner as in the process of Fig. 4. After that, processes similar to those in Figs. 6, 8, and 10 are performed between the server 210 and the device 220.

(4-6. Sixth Modification)
The technology according to the present disclosure is not limited to a configuration in which authentication is performed only once, such as fingerprint authentication, but can also be applied to a configuration in which authentication is performed continuously multiple times, such as gait authentication. Specifically, in the FPGA 120, authentication is performed once every few seconds based on sensor data obtained from an acceleration sensor, and the authentication result is transmitted to the CPU 110.

Figure 16 is a diagram explaining the process of encrypting and transmitting authentication results in a configuration in which multiple authentications are performed continuously.

Note that before steps S81 and S91 in Figure 16, processing similar to the processing of steps S71 to S75 and S61 to S63 in Figure 10 is executed. Also, the processing of steps S81 to S84 and S91 to S95 in Figure 16 is similar to the processing of steps S76 to S79 and S64 to S68 in Figure 10.

In the process of FIG. 16, in step S85, FPGA 120 determines whether the authentication result has been transmitted the required number of times. Until the authentication result has been transmitted the required number of times, FPGA 120 repeats steps S81 to S84, and CPU 110 repeats steps S91 to S95.

That is, the FPGA 120 performs biometric authentication multiple times based on the decrypted command. Then, the FPGA 120 encrypts the authentication result of the biometric authentication each time and transmits it to the CPU 110 multiple times.

At this time, FPGA 120 may transmit the authentication result to CPU 110 for the number of transmissions included in the command from CPU 110, or may transmit the authentication result to CPU 110 until a transmission end command is received from CPU 110. FPGA 120 may also stop transmitting the authentication result by transmitting a transmission end message to CPU 110.

The above processing makes it possible to prevent data tampering even within the device performing gait authentication and to increase resistance to replay attacks, making it possible to safely transmit gait authentication results between chips.

The above-mentioned series of processes can be executed by hardware or by software. When the series of processes are executed by software, the programs that make up the software are installed on a computer. Here, computers include computers that are built into dedicated hardware, and general-purpose personal computers, for example, that can execute various functions by installing various programs.

In a computer including the above-mentioned fingerprint authentication device 100, the CPU 110 and FPGA 120 load and execute programs stored in a storage unit or non-volatile memory 150 (not shown), thereby performing the above-mentioned series of processes.

The program executed by the computer (CPU 110 and FPGA 120) can be provided, for example, by recording it on a removable medium such as a package medium. The program can also be provided via a wired or wireless transmission medium such as a local area network, the Internet, or digital satellite broadcasting.

In a computer, a program can be installed in the storage unit or non-volatile memory 150 by inserting a removable medium into a drive. The program can also be installed in the storage unit or non-volatile memory 150 via a wired or wireless transmission medium. Alternatively, the program can be pre-installed in the setting ROM 160.

The program executed by the computer may be a program in which processing is performed chronologically in the order described in this specification, or a program in which processing is performed in parallel or at the required timing, such as when called.

In this specification, the steps of describing a program to be recorded on a recording medium include not only processes that are performed chronologically in the order described, but also processes that are not necessarily performed chronologically but are executed in parallel or individually.

The embodiments of the technology disclosed herein are not limited to the embodiments described above, and various modifications are possible without departing from the gist of the technology disclosed herein.

Furthermore, the effects described in this specification are merely examples and are not limiting, and other effects may also exist.

Furthermore, the technology according to the present disclosure can have the following configuration.
(1)
a first chip that performs encryption and decryption using a first common key and stores a first counter value;
a second chip that performs encryption and decryption using the first common key and stores a second counter value;
the first chip encrypts a command and the first counter value and transmits them to the second chip;
the second chip encrypts the execution result of the decrypted command and the second counter value and transmits them to the first chip;
A data processing device, wherein the first chip and the second chip synchronize the first counter value and the second counter value each time data is transmitted to and received from the other chip.
(2)
The first chip and the second chip
After receiving the data from the other party, a match determination is performed between the decrypted first counter value and the decrypted second counter value;
The data processing device according to any one of claims 1 to 5, wherein after the match determination and after the data is transmitted to the other party, the first counter value or the second counter value held by each of the devices is updated.
(3)
The data processing device according to claim 2, wherein the first chip and the second chip continue processing if the first counter value and the second counter value match as a result of the match determination, and terminate processing if they do not match.
(4)
The second chip includes:
performing biometric authentication based on the decrypted command;
The data processing device according to any one of (1) to (3), further comprising: a data processing device that encrypts a result of the biometric authentication and transmits the encrypted result to the first chip.
(5)
The data processing device according to any one of claims 1 to 4, wherein the first chip and the second chip perform encryption and decryption using an authenticated encryption method.
(6)
The data processing device according to claim 4, wherein the first chip and the second chip share the first common key based on a second common key held by each of them when the data processing device is powered on, and reset the first counter value and the second counter value held by each of them.
(7)
The data processing device according to (6), wherein the first chip and the second chip share the first common key by using a predetermined key sharing protocol.
(8)
The data processing device according to (6) or (7), wherein the second chip performs the biometric authentication using an authentication template encrypted based on the second common key.
(9)
Further comprising a sensor for acquiring sensor data including biological information;
The data processing device according to (8), wherein the second chip performs the biometric authentication on the living body based on the sensor data acquired by the sensor and the authentication template.
(10)
The data processing device according to any one of (6) to (9), wherein the second common key is generated by the first chip using a pseudorandom number generator, and transmitted to the second chip, so that the second common key is stored in the first chip and the second chip.
(11)
The data processing device according to any one of (4) to (10), wherein the first chip is configured by a CPU (Central Processing Unit).
(12)
The data processing device according to any one of (4) to (10), wherein the first chip is configured by a SE (Secure Element).
(13)
a third chip that performs encryption and decryption using a third common key;
The data processing device according to any one of (4) to (10), wherein the first chip encrypts the decrypted authentication result by using the third common key and transmits the encrypted result to the third chip.
(14)
The first chip is configured with a CPU (Central Processing Unit),
The data processing device according to (13), wherein the third chip is configured by a SE (Secure Element).
(15)
The second chip includes:
performing the biometric authentication a plurality of times based on the decrypted command;
The data processing device according to claim 4, further comprising: encrypting a result of the biometric authentication each time and transmitting the encrypted result to the first chip a plurality of times.
(16)
The data processing device according to any one of claims 1 to 15, wherein the second chip transmits the authentication result to the first chip a number of times included in the command.
(17)
The data processing device according to any one of claims 1 to 15, wherein the second chip transmits the authentication result to the first chip until a transmission end command is received from the first chip.
(18)
The data processing device according to any one of claims 1 to 15, wherein the second chip stops transmitting the authentication result by transmitting a transmission end message to the first chip.
(19)
The data processing device comprises:
a first chip that performs encryption and decryption using a first common key and stores a first counter value;
a second chip that performs encryption and decryption using the first common key and stores a second counter value;
the first chip encrypts a command and the first counter value and transmits them to the second chip;
the second chip encrypts the execution result of the decrypted command and the second counter value and transmits them to the first chip;
A data processing method, wherein the first chip and the second chip synchronize the first counter value and the second counter value each time the first chip transmits or receives data to or from the other chip.
(20)
Computer,
a first chip that performs encryption and decryption using a first common key and stores a first counter value;
a program for causing a second chip to function as a second chip that performs encryption and decryption using the first common key and holds a second counter value,
the first chip encrypts a command and the first counter value and transmits them to the second chip;
the second chip encrypts the execution result of the decrypted command and the second counter value and transmits them to the first chip;
A program for causing the first chip and the second chip to synchronize the first counter value with the second counter value every time data is transmitted to and received from the other chip.

10 Data processing device, 11 First chip, 12 Server, 13 Sensor, 100 Fingerprint authentication device, 110 CPU, 120 FPGA, 131 Image sensor, 140 RAM, 150 Non-volatile memory, 170 SE, 180 RF communication unit

Claims (20)

a first chip that performs encryption and decryption using a first common key and stores a first counter value;
a second chip that performs encryption and decryption using the first common key and stores a second counter value;
the first chip encrypts a command and the first counter value and transmits them to the second chip;
the second chip encrypts the execution result of the decrypted command and the second counter value and transmits them to the first chip;
A data processing device, wherein the first chip and the second chip synchronize the first counter value and the second counter value each time data is transmitted to and received from the other chip. The first chip and the second chip
After receiving the data from the other party, a match determination is performed between the decrypted first counter value and the decrypted second counter value;
The data processing device according to claim 1 , wherein after the match determination and after the data is transmitted to the other party, the first counter value or the second counter value held by each of the devices is updated. 3. The data processing device according to claim 2, wherein the first chip and the second chip continue processing when the first counter value and the second counter value match as a result of the match determination, and terminate processing when they do not match. The second chip includes:
performing biometric authentication based on the decrypted command;
The data processing device according to claim 1 , wherein the biometric authentication result is encrypted and transmitted to the first chip. The data processing device according to claim 4 , wherein the first chip and the second chip perform encryption and decryption using an authenticated encryption method. The data processing device according to claim 4 , wherein the first chip and the second chip share the first common key based on a second common key held by each of them when the data processing device is powered on, and reset the first counter value and the second counter value held by each of them. The data processing device according to claim 6 , wherein the first chip and the second chip share the first common key by using a predetermined key sharing protocol. The data processing device according to claim 6 , wherein the second chip performs the biometric authentication using an authentication template encrypted based on the second common key. Further comprising a sensor for acquiring sensor data including biological information;
The data processing device according to claim 8 , wherein the second chip performs the biometric authentication for the living body based on the sensor data acquired by the sensor and the authentication template. The data processing device according to claim 6 , wherein the second common key is generated by the first chip using a pseudorandom number generator and transmitted to the second chip, and is held in the first chip and the second chip. The data processing device according to claim 4 , wherein the first chip is configured by a CPU (Central Processing Unit). The data processing device according to claim 4 , wherein the first chip is configured by a SE (Secure Element). a third chip that performs encryption and decryption using a third common key;
The data processing device according to claim 4 , wherein the first chip encrypts the decrypted authentication result by using the third common key and transmits the encrypted result to the third chip. The first chip is configured with a CPU (Central Processing Unit),
The data processing device according to claim 13 , wherein the third chip is configured by a SE (Secure Element). The second chip includes:
performing the biometric authentication a plurality of times based on the decrypted command;
The data processing device according to claim 4 , wherein the authentication result of the biometric authentication is encrypted each time and transmitted to the first chip a plurality of times. The data processing device according to claim 15 , wherein the second chip transmits the authentication result to the first chip a number of times included in the command. The data processing device according to claim 15 , wherein the second chip transmits the authentication result to the first chip until a transmission end command is received from the first chip. The data processing device according to claim 15 , wherein the second chip stops transmitting the authentication result by transmitting a transmission end message to the first chip. The data processing device comprises:
a first chip that performs encryption and decryption using a first common key and stores a first counter value;
a second chip that performs encryption and decryption using the first common key and stores a second counter value;
the first chip encrypts a command and the first counter value and transmits them to the second chip;
the second chip encrypts the execution result of the decrypted command and the second counter value and transmits them to the first chip;
A data processing method, wherein the first chip and the second chip synchronize the first counter value and the second counter value each time the first chip transmits or receives data to or from the other chip. Computer,
a first chip that performs encryption and decryption using a first common key and stores a first counter value;
a program for causing a second chip to function as a second chip that performs encryption and decryption using the first common key and holds a second counter value,
the first chip encrypts a command and the first counter value and transmits them to the second chip;
the second chip encrypts the execution result of the decrypted command and the second counter value and transmits them to the first chip;
A program for causing the first chip and the second chip to synchronize the first counter value with the second counter value every time data is transmitted to and received from the other chip.

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