JP7494957B2 - Pattern calculation apparatus, pattern calculation method, mask, exposure apparatus, device manufacturing method, computer program, and recording medium - Google Patents

Description

The present invention relates to the technical fields of pattern calculation devices and pattern calculation methods for calculating mask patterns formed on masks used in exposure devices, and further to the technical fields of masks, exposure devices and exposure methods, device manufacturing methods, computer programs, and recording media.

Exposure apparatuses are used that expose a substrate (such as a glass substrate coated with resist) with an image of a mask pattern formed on a mask. Exposure apparatuses are used, for example, to manufacture flat panel displays such as liquid crystal displays and organic EL (Electro Luminescence) displays. In such exposure apparatuses, it is required to appropriately calculate (i.e., determine) the mask pattern in order to manufacture the mask.

US Patent Application Publication No. 2010/0266961

According to a first aspect, there is provided a pattern calculation device that calculates a mask pattern to be formed on a mask for forming a device pattern, in which a plurality of unit device pattern parts are arranged, on a substrate using exposure light, and that calculates a unit mask pattern part for forming one of the unit device pattern parts of the mask pattern on the substrate, and calculates the mask pattern by arranging a plurality of the calculated unit mask pattern parts, and that calculates the unit mask pattern part under the assumption that a specific mask pattern part corresponding to at least a portion of the unit mask pattern part is adjacent to the unit mask pattern part when calculating the unit mask pattern part.

According to a second aspect, there is provided a pattern calculation device that calculates a mask pattern to be formed on a mask for forming a device pattern on a substrate with exposure light, the mask including a first mask region to which the exposure light is irradiated at least twice to form at least a part of the device pattern, and a second mask region to which the exposure light is irradiated once to form at least another part of the device pattern, and the pattern calculation device corrects at least a part of the mask pattern calculated based on the device pattern based on the correspondence between the first and second mask regions and the mask pattern.

According to a third aspect, there is provided a pattern calculation device that calculates a mask pattern to be formed on a mask for forming a device pattern on a substrate with exposure light, the mask including a first mask region to which the exposure light is irradiated at least twice to form at least a portion of the device pattern, and the pattern calculation device corrects at least a portion of the mask pattern calculated based on the device pattern based on variations on the substrate in exposure characteristics due to the exposure light passing through the first mask region.

According to a fourth aspect, there is provided a pattern calculation device that calculates a mask pattern to be formed on a mask for forming a device pattern on a substrate with exposure light, the mask including a third mask region to which the exposure light for exposing the substrate is irradiated via a first projection optical system, and a fourth mask region to which the exposure light for exposing the substrate is irradiated via a second projection optical system, and the pattern calculation device corrects at least a portion of the mask pattern calculated based on the device pattern based on the correspondence between the third and fourth mask regions and the mask pattern.

According to a fifth aspect, there is provided a pattern calculation device that calculates a mask pattern to be formed on a mask for forming a device pattern on a substrate with exposure light, the mask including a fifth mask region to which the exposure light for exposing the substrate is irradiated via a desired projection optical system, and the pattern calculation device corrects at least a portion of the mask pattern calculated based on the device pattern based on the variation on the substrate of the exposure characteristics due to the exposure light passing through the fifth mask region.

According to a sixth aspect, there is provided a pattern calculation method for calculating a mask pattern to be formed on a mask for forming a device pattern, in which a plurality of unit device pattern portions are arranged, on a substrate using exposure light, the method calculating a unit mask pattern portion for forming one of the unit device pattern portions on the substrate from the mask pattern, and calculating the mask pattern by arranging a plurality of the calculated unit mask pattern portions, and, when calculating the unit mask pattern portion, calculating the unit mask pattern portion under the assumption that a specific mask pattern portion corresponding to at least a portion of the unit mask pattern portion is adjacent to the unit mask pattern portion.

According to a seventh aspect, there is provided a pattern calculation method for calculating a mask pattern to be formed on a mask for forming a device pattern on a substrate with exposure light, the mask including a first mask region to which the exposure light is irradiated at least twice to form at least a part of the device pattern, and a second mask region to which the exposure light is irradiated once to form at least another part of the device pattern, and the pattern calculation method corrects at least a part of the mask pattern calculated based on the device pattern based on a correspondence relationship between the first and second mask regions and the mask pattern.

According to an eighth aspect, there is provided a pattern calculation method for calculating a mask pattern to be formed on a mask for forming a device pattern on a substrate with exposure light, the mask including a first mask region to which the exposure light is irradiated at least twice to form at least a portion of the device pattern, and the pattern calculation method corrects at least a portion of the mask pattern calculated based on the device pattern based on variations on the substrate in exposure characteristics due to the exposure light passing through the first mask region.

According to a ninth aspect, there is provided a pattern calculation method for calculating a mask pattern to be formed on a mask for forming a device pattern on a substrate with exposure light, the mask including a third mask region to which the exposure light for exposing the substrate is irradiated via a first projection optical system, and a fourth mask region to which the exposure light for exposing the substrate is irradiated via a second projection optical system, and the pattern calculation method corrects at least a portion of the mask pattern calculated based on the device pattern based on a correspondence relationship between the third and fourth mask regions and the mask pattern.

According to a tenth aspect, there is provided a pattern calculation method for calculating a mask pattern to be formed on a mask for forming a device pattern on a substrate with exposure light, the mask including a fifth mask region to which the exposure light for exposing the substrate is irradiated via a desired projection optical system, and the pattern calculation method corrects at least a portion of the mask pattern calculated based on the device pattern based on the variation on the substrate of the exposure characteristics due to the exposure light passing through the fifth mask region.

According to an eleventh aspect, a mask is provided that is manufactured using any one of the sixth to tenth aspects of the pattern calculation method described above.

According to the twelfth aspect, a mask is provided on which a mask pattern calculated by any one of the sixth to tenth aspects of the pattern calculation method described above is formed.

According to the thirteenth aspect, there is provided an exposure apparatus that forms the device pattern on the substrate by irradiating the substrate with the exposure light through the mask of the eleventh or twelfth aspect described above.

According to the 14th aspect, a device manufacturing method is provided in which the substrate coated with a photosensitive agent is exposed using the exposure apparatus of the 13th aspect described above, the device pattern is formed on the substrate, the exposed photosensitive agent is developed to form an exposure pattern layer corresponding to the device pattern, and the substrate is processed via the exposure pattern layer.

According to a fifteenth aspect, a computer program is provided that causes a computer to execute any one of the sixth to tenth aspects of the pattern calculation method described above.

According to a sixteenth aspect, a recording medium is provided on which the fifteenth aspect of the computer program described above is recorded.

According to the seventeenth aspect, a mask is provided that is illuminated by an illumination area having a first area in which the amount of illumination from an illumination system varies along the second direction intersecting the first direction depending on the position in the first direction, and a second area different from the first area, the mask comprising a first circuit pattern provided in a region of the illumination area corresponding to the first area, and a second circuit pattern provided in a region corresponding to the second area and formed based on the first circuit pattern.

According to the 18th aspect, a mask having a predetermined pattern exposed on an object by a plurality of projection optical systems having different optical characteristics is provided, the mask comprising a first circuit pattern formed based on the optical characteristics of a first optical system among the plurality of projection optical systems, and a second circuit pattern formed based on the optical characteristics of a second optical system different from the first optical system.

The operation and other advantages of the present invention will become apparent from the following detailed description of the embodiment.

FIG. 1 is a perspective view showing an example of the overall structure of an exposure apparatus according to the present embodiment. FIG. 2(a) is a plan view showing a projection area set on a substrate, FIG. 2(b) is a plan view showing an illumination area set on a mask, and FIG. 2(c) is a plan view showing multiple unit mask pattern portions repeatedly formed on the mask. FIG. 3A is a plan view showing a specific example of a mask used for manufacturing a display panel, and FIG. 3B is a plan view showing a part of the mask shown in FIG. 3A. FIG. 4 is a block diagram showing the structure of a mask pattern calculation apparatus. FIG. 5 is a flowchart showing the flow of the mask pattern calculation operation performed by the mask pattern calculation apparatus. FIG. 6 is a flowchart showing the process flow of calculating a mask pattern by utilizing the fact that a plurality of unit mask pattern portions are included in the mask in step S3 of FIG. FIG. 7 is a plan view showing a specific example of a pattern layout of one unit mask pattern portion. Each of FIGS. 8(a) to 8(d) is a plan view showing the positional relationship between two adjacent unit mask pattern portions. FIG. 9 is a plan view showing a situation in which it is assumed that a part of a unit mask pattern portion is adjacent to the unit mask pattern portion. FIG. 10 is a plan view showing a situation in which it is assumed that a part of a unit mask pattern portion is adjacent to the unit mask pattern portion. FIG. 11 is a plan view showing a mask pattern obtained by arranging a plurality of unit mask pattern portions. FIG. 12 is a plan view showing a mask pattern group obtained by arranging a plurality of mask patterns. FIG. 13 is a plan view showing a group of multiple types of unit mask patterns that can be distinguished based on differences in the pattern layouts of adjacent regions. FIG. 14 is a plan view showing a composite mask pattern portion including a unit mask pattern portion and at least a part of a peripheral mask pattern portion adjacent to the unit mask pattern portion. FIG. 15 is a flowchart showing the flow of a process for calculating a mask pattern in the second modified example. FIG. 16 is a plan view showing a situation in which it is assumed that a part of a mask pattern is adjacent to the mask pattern. FIG. 17 is a plan view showing a mask pattern group obtained by arranging a plurality of mask patterns. FIG. 18 is a flowchart showing the flow of a process for calculating a mask pattern in the third modified example. FIG. 19(a) is a plan view showing an example of a device pattern formed on a substrate, and each of FIGS. 19(b) to 19(d) is a plan view showing an example of a mask pattern for forming the device pattern shown in FIG. 19(a). FIG. 20 is a flowchart showing the flow of a process for calculating a mask pattern in the fourth modified example. FIG. 21 is a plan view showing the positional relationship between the seamless exposure area and two projection areas that perform double exposure on the seamless exposure area. FIG. 22 is a plan view showing an example of a mask pattern for forming the device pattern shown in FIG. FIG. 23 is a flowchart showing the flow of a process for calculating a mask pattern in the fifth modified example. 24A to 24C are plan views showing the relationship between the image plane and projection area of the projection optical system and distortion. FIG. 25A is a plan view showing a projection area set on a substrate when there is a projection optical system in which distortion aberration occurs and a projection optical system in which distortion aberration does not occur, and FIG. 25B is a plan view showing an example of the correction content of a mask pattern when the distortion aberration shown in FIG. 25A occurs; FIG. 26(a) is a plan view showing the relationship between the projection area and exposure amount of a projection optical system in which no curvature of field occurs, and FIG. 26(b) is a plan view showing the relationship between the projection area and exposure amount of a projection optical system in which curvature of field occurs. FIG. 27A is a plan view showing a projection area set on a substrate when there are a projection optical system in which curvature of field occurs and a projection optical system in which curvature of field does not occur, and FIG. 27B is a plan view showing an example of the correction content of a mask pattern in the case in which the curvature of field shown in FIG. 27A occurs; FIG. 28 is a flowchart showing the flow of a device manufacturing method for manufacturing a display panel using an exposure apparatus.

Below, the pattern calculation apparatus, the pattern calculation method, the mask, the exposure apparatus, the device manufacturing method, the computer program, and the recording medium will be described with reference to the drawings. However, the present invention is not limited to the embodiments described below.

In the following explanation, the positional relationship between the components that make up the mask and exposure apparatus will be explained using an XYZ Cartesian coordinate system defined by mutually orthogonal X-axis, Y-axis, and Z-axis. For the sake of convenience, the X-axis and Y-axis directions are each considered to be horizontal (i.e., a specific direction within a horizontal plane), and the Z-axis direction is considered to be vertical (i.e., a direction perpendicular to the horizontal plane, essentially an up-down direction). The +Z-axis side is considered to be upward (upper side), and the -Z-axis side is considered to be downward (lower side). The directions of rotation around the X-axis, Y-axis, and Z-axis (in other words, the tilt directions) are referred to as the θX direction, θY direction, and θZ direction, respectively.

(1) Exposure Apparatus 1 of the Present Embodiment
An exposure apparatus 1 of this embodiment will be described with reference to Figures 1 and 2. The exposure apparatus 1 of this embodiment exposes a substrate 151, which is a flat glass plate coated with a photoresist (i.e., a photosensitive agent), with an image of a mask pattern formed on a mask 131. The substrate 151 exposed by the exposure apparatus 1 is used, for example, to manufacture a display panel of a display device (e.g., a liquid crystal display, an organic EL display, etc.).

(1-1) Structure of exposure apparatus 1 of this embodiment First, the structure of exposure apparatus 1 of this embodiment will be described with reference to Fig. 1. Fig. 1 is a perspective view showing an example of the overall structure of exposure apparatus 1 of this embodiment.

As shown in FIG. 1, the exposure apparatus 1 includes a light source unit 11, multiple illumination optical systems 12, a mask stage 13, multiple projection optical systems 14, a substrate stage 15, and a control device 16.

The light source unit 11 emits exposure light EL. The exposure light EL is, for example, light in at least one wavelength band of g-line, h-line, and i-line. In particular, the light source unit 11 branches the exposure light EL into multiple exposure light EL that can respectively illuminate multiple illumination areas IR set on the effective area 131p of the mask 131 (see FIG. 2 described later). In the example shown in FIG. 1, the light source unit 11 branches the exposure light EL into seven exposure light EL that can respectively illuminate seven illumination areas IR (i.e., illumination area IRa, illumination area IRb, illumination area IRc, illumination area IRd, illumination area IRe, illumination area IRf, and illumination area IRg). The multiple exposure light EL are incident on the multiple illumination optical systems 12, respectively.

The multiple illumination optical systems 12 constitute a multi-lens type illumination optical system. In the example shown in FIG. 1, the exposure apparatus 1 has seven illumination optical systems 12 (i.e., illumination optical system 12a, illumination optical system 12b, illumination optical system 12c, illumination optical system 12d, illumination optical system 12e, illumination optical system 12f, and illumination optical system 12g). The illumination optical systems 12a, illumination optical system 12c, illumination optical system 12e, and illumination optical system 12g are arranged so as to be aligned at equal intervals along the Y-axis direction. The illumination optical systems 12b, illumination optical system 12d, and illumination optical system 12f are arranged so as to be aligned at equal intervals along the Y-axis direction. The illumination optical systems 12a, illumination optical system 12c, illumination optical system 12e, and illumination optical system 12g are arranged at positions spaced apart by a predetermined amount along the X-axis direction from the illumination optical systems 12b, illumination optical system 12d, and illumination optical system 12f. The illumination optical system 12a, the illumination optical system 12c, the illumination optical system 12e, and the illumination optical system 12g, and the illumination optical system 12b, the illumination optical system 12d, and the illumination optical system 12f are arranged in a staggered pattern.

Each illumination optical system 12 is disposed below the light source unit 11. Each illumination optical system 12 irradiates the illumination region IR corresponding to each illumination optical system 12 with exposure light EL. Specifically, illumination optical systems 12a to 12g irradiate the exposure light EL to illumination regions IRa to IRg, respectively. Therefore, the number of illumination regions IR set on the mask 131 is the same as the number of illumination optical systems 12 provided in the exposure apparatus 1.

The mask stage 13 is disposed below the multiple illumination optical systems 12. The mask stage 13 can hold a mask 131. The mask stage 13 can release the held mask 131. The mask 131 is, for example, made of a rectangular glass plate with one side or diagonal of 500 mm or more. A mask pattern corresponding to a device pattern to be transferred to a substrate 151 is formed on the mask 131. More specifically, a mask pattern capable of forming an image (for example, an aerial image or an exposure pattern) for exposing the substrate 151 so as to form a device pattern on the substrate 151 is formed on the mask 131.

The mask stage 13, while holding the mask 131, is capable of moving along a plane (e.g., the XY plane) that includes multiple illumination regions IR. The mask stage 13 is capable of moving along the X-axis direction. For example, the mask stage 13 is capable of moving along the X-axis direction by the operation of a mask stage drive system that includes an arbitrary motor. In addition to being capable of moving along the X-axis direction, the mask stage 13 may also be capable of moving along at least one of the Y-axis direction, Z-axis direction, θX direction, θY direction, and θZ direction.

The multiple projection optical systems 14 constitute a multi-lens type projection optical system. In the example shown in FIG. 1, the exposure apparatus 1 includes seven projection optical systems 14 (i.e., projection optical system 14a, projection optical system 14b, projection optical system 14c, projection optical system 14d, projection optical system 14e, projection optical system 14f, and projection optical system 14g). The number of projection optical systems 14 included in the exposure apparatus 1 is the same as the number of illumination optical systems 12 included in the exposure apparatus 1. The projection optical systems 14a, projection optical system 14c, projection optical system 14e, and projection optical system 14g are arranged so as to be aligned at approximately equal intervals along the Y-axis direction. The projection optical systems 14b, projection optical system 14d, and projection optical system 14f are arranged so as to be aligned at approximately equal intervals along the Y-axis direction. The projection optical systems 14a, projection optical system 14c, projection optical system 14e, and projection optical system 14g are arranged at positions spaced apart by a predetermined amount along the X-axis direction from the projection optical systems 14b, projection optical system 14d, and projection optical system 14f. The projection optical system 14a, the projection optical system 14c, the projection optical system 14e, and the projection optical system 14g, and the projection optical system 14b, the projection optical system 14d, and the projection optical system 14f are arranged in a staggered pattern.

Each projection optical system 14 is disposed below the mask stage 13. Each projection optical system 14 projects the exposure light EL irradiated to the illumination area IR corresponding to each projection optical system 14 (i.e., the image of the mask pattern formed in the effective area 131p of the mask 131 in which the illumination area IR is set) onto a projection area PR set on the substrate 151 corresponding to each projection optical system 14. Specifically, the projection optical system 14a projects the exposure light EL irradiated to the illumination area IRa (i.e., the image of the mask pattern formed in the effective area 131p of the mask 131 in which the illumination area IRa is set) onto a projection area PRa set on the substrate 151. The same applies to the projection optical systems 14b to 14g.

Each projection optical system 14 is equipped with a field stop 144. The field stop 144 sets a projection area PR on the substrate 151. The field stop 144 has a trapezoidal opening with an upper side and a lower side parallel to the Y-axis direction. As a result, a trapezoidal projection area PR with an upper side and a lower side parallel to the Y-axis direction is set on the substrate 151.

The substrate stage 15 is disposed below the multiple projection optical systems 14. The substrate stage 15 is capable of holding a substrate 151. The substrate stage 15 is capable of holding the substrate 151 so that the top surface of the substrate 151 is parallel to the XY plane. The substrate stage 15 is capable of releasing the substrate 151 that it holds. The substrate 151 is, for example, a glass substrate of several meters square.

The substrate stage 15 is capable of moving along a plane (e.g., the XY plane) that includes the projection region PR while holding the substrate 151. The substrate stage 15 is capable of moving along the X-axis direction. For example, the substrate stage 15 may be capable of moving along the X-axis direction by the operation of a substrate stage drive system that includes an arbitrary motor. In addition to being capable of moving along the X-axis direction, the substrate stage 15 may also be capable of moving along at least one of the Y-axis direction, Z-axis direction, θX direction, θY direction, and θZ direction.

The control device 16 can control the operation of the exposure device 1. The control device 16 includes, for example, a CPU (Central Processing Unit), a ROM (Read Only Memory), and a RAM (Random Access Memory).

The control device 16 controls the mask stage drive system so that the mask stage 13 moves in the desired first movement mode (as a result, the mask 131 moves in the desired first movement mode). The control device 16 controls the substrate stage drive system so that the substrate stage 15 moves in the desired second movement mode (as a result, the substrate 151 moves in the desired second movement mode). For example, the control device 16 controls the mask stage drive system and the substrate stage drive system so that exposure is performed by the step-and-scan method. In other words, the control device 16 controls the mask stage drive system and the substrate stage drive system so that the mask stage 13 holding the mask 131 and the substrate stage 15 holding the substrate 151 move synchronously along a predetermined scanning direction while the exposure light EL is irradiated onto the illumination region IR on the mask 131. As a result, the mask pattern formed on the mask 131 is transferred to the substrate 151. In the following description, the scanning direction in which the mask stage 13 and the substrate stage 15 move synchronously is the X-axis direction, and the Y-axis direction perpendicular to the X-axis direction is appropriately referred to as the "non-scanning direction".

The structure of the exposure apparatus 1 described using Figures 1 and 2 is an example. Therefore, at least a part of the structure of the exposure apparatus 1 may be modified as appropriate. For example, the exposure apparatus 1 may be equipped with six or less or eight or more illumination optical systems 12. For example, the exposure apparatus 1 may be equipped with six or less or eight or more projection optical systems 14.

Alternatively, the exposure apparatus 1 may have a single illumination optical system 12. The exposure apparatus 1 may have a single projection optical system 14. However, if the exposure apparatus 1 has a single projection optical system 14, the joint pattern area 131a and the non-joint pattern area 131b described below do not have to be set on the mask 131, and the joint exposure area 151a and the non-joint exposure area 151b described below do not have to be set on the substrate 151.

(1-2) Arrangement of illumination region IR and projection region PR Next, the illumination region IR set on the mask 131 and the projection region RP set on the substrate 151 will be described with reference to Fig. 2(a) to Fig. 2(c). Fig. 2(a) is a plan view showing the projection region PR set on the substrate 151. Fig. 2(b) is a plan view showing the illumination region IR set on the mask 131. Fig. 2(c) is a plan view showing unit mask pattern portions MPp repeatedly formed on the mask 131.

2A, the same number of projection areas PR as the number of projection optical systems 14 equipped in the exposure apparatus 1 are set on the substrate 151. In this embodiment, since the exposure apparatus 1 is equipped with seven projection optical systems 14, seven projection areas PR (i.e., projection area PRa, projection area PRb, projection area PRc, projection area PRd, projection area PRe, projection area PRf, and projection area PRg) are set on the substrate 151. The projection optical system 14a sets the projection area PRa onto which the exposure light EL irradiated to the illumination area IRa is projected by the projection optical system 14a. The projection optical system 14b sets the projection area PRb onto which the exposure light EL irradiated to the illumination area IRb is projected by the projection optical system 14b. The projection optical system 14c sets the projection area PRc onto which the exposure light EL irradiated to the illumination area IRc is projected by the projection optical system 14c. The projection optical system 14d sets a projection area PRd onto which the exposure light EL irradiated to the illumination area IRd is projected by the projection optical system 14d. The projection optical system 14e sets a projection area PRe onto which the exposure light EL irradiated to the illumination area IRe is projected by the projection optical system 14e. The projection optical system 14f sets a projection area PRf onto which the exposure light EL irradiated to the illumination area IRf is projected by the projection optical system 14f. The projection optical system 14g sets a projection area PRg onto which the exposure light EL irradiated to the illumination area IRg is projected by the projection optical system 14g.

Projection area PRa, projection area PRc, projection area PRe, and projection area PRg are trapezoidal areas with the side on the +X side as the base. Projection area PRb, projection area PRd, and projection area PRf are trapezoidal areas with the side on the -X side as the base. Projection area PRa, projection area PRc, projection area PRe, and projection area PRg are set at a position a first predetermined amount away from projection area PRb, projection area PRd, and projection area PRf along the X-axis direction. Projection area PRa, projection area PRc, projection area PRe, and projection area PRg, and projection area PRb, projection area PRd, and projection area PRf are set in a staggered pattern.

Each projection region PR includes two ends (hereinafter referred to as "inclined portions") defined by sides inclined with respect to the X-axis direction. However, the -Y side of projection region PRa and the +Y side of projection region PRg are not inclined with respect to the X-axis direction due to the exposure light EL being blocked by the light-shielding band 131s (see FIG. 2(b)) surrounding the effective region 131p of the mask 131. Therefore, each of projection region PRa and projection region PRg includes a single inclined portion.

The inclined portion on the +Y side of the projection region PRa overlaps with the inclined portion on the -Y side of the projection region PRb along the X-axis direction (in other words, adjacent, the same applies below). The inclined portion on the +Y side of the projection region PRb overlaps with the inclined portion on the -Y side of the projection region PRc along the X-axis direction. The inclined portion on the +Y side of the projection region PRc overlaps with the inclined portion on the -Y side of the projection region PRd along the X-axis direction. The inclined portion on the +Y side of the projection region PRd overlaps with the inclined portion on the -Y side of the projection region PRe along the X-axis direction. The inclined portion on the +Y side of the projection region PRe overlaps with the inclined portion on the -Y side of the projection region PRf along the X-axis direction. The inclined portion on the +Y side of the projection region PRf overlaps with the inclined portion on the -Y side of the projection region PRg along the X-axis direction.

The two inclined portions overlapping along the X-axis direction define a joint exposure area 151a on the substrate 151, onto which the exposure light EL is projected twice by the two inclined portions during one scanning exposure operation. In other words, the two inclined portions overlapping along the X-axis direction define a joint exposure area 151a on the substrate 151, onto which the exposure light EL is doubly exposed by the two inclined portions during one scanning exposure operation. On the other hand, the non-joint exposure area 151b on the surface of the substrate 151 other than the joint exposure area 151a is an area onto which the exposure light EL is projected once during one scanning exposure operation. The inclined portions of each projection area PR are set so that the sum of the widths along the X-axis direction of the two inclined portions overlapping along the X-axis direction is the same as the width along the X-axis direction of each projection area PR (i.e., the width along the X-axis direction of the area portion other than the inclined portions). As a result, the exposure amount of the joint exposure area 151a that is doubly exposed is substantially the same as the exposure amount of the non-joint exposure area 151b that is not doubly exposed. Therefore, the images of the mask pattern projected onto multiple projection regions PR are connected with relatively high accuracy.

The continuous exposure area 151a is a rectangular area. The continuous exposure area 151a is an area whose longitudinal direction is the X-axis direction (i.e., the scanning direction) and whose transverse direction is the Y-axis direction (i.e., the non-scanning direction). The continuous exposure area 151a is an area extending along the X-axis direction. On the substrate 151, a plurality of continuous exposure areas 151a (six continuous exposure areas 151a in the example shown in FIG. 2(a)) are set at equal intervals along the Y-axis direction.

The non-seamless exposure region 151b is a rectangular region. The non-seamless exposure region 151b is a region in which the X-axis direction is the long side and the Y-axis direction is the short side. The non-seamless exposure region 151b is a region that extends along the X-axis direction. On the substrate 151, multiple non-seamless exposure regions 151b (seven non-seamless exposure regions 151b in the example shown in FIG. 2(a)) are set at equal intervals along the Y-axis direction.

On the other hand, as shown in FIG. 2B, the same number of illumination regions IR as the number of illumination optical systems 12 included in the exposure apparatus 1 are set on the mask 131. In this embodiment, since the exposure apparatus 1 has seven illumination optical systems 14, seven illumination regions IR (i.e., illumination region IRa, illumination region IRb, illumination region IRc, illumination region IRd, illumination region IRe, illumination region IRf, and illumination region IRg) are set on the mask 131. The illumination optical system 12a irradiates the illumination region IRa with exposure light EL. The illumination optical system 12b irradiates the illumination region IRb with exposure light EL. The illumination optical system 12c irradiates the illumination region IRc with exposure light EL. The illumination optical system 12d irradiates the illumination region IRd with exposure light EL. The illumination optical system 12e irradiates the illumination region IRe with exposure light EL. The illumination optical system 12f irradiates the illumination region IRf with exposure light EL. The illumination optical system 12g irradiates the illumination region IRg with the exposure light EL.

The field of view on the object plane side of each projection optical system 14 is determined by the field stop 144 provided in each projection optical system 14. Therefore, each illumination region IR means a region optically conjugate with the field stop 144.

In this embodiment, each projection optical system 14 projects an erect image of the mask pattern at the same magnification onto the substrate 151. Therefore, the shapes and arrangements of the illumination areas IRa to IRg are the same as those of the projection areas PRa to PRg. Therefore, each illumination area IR includes two ends (hereinafter, appropriately referred to as "inclined portions") defined by sides inclined with respect to the X-axis direction. The two inclined portions overlapping along the X-axis direction define on the mask 131 a continuous pattern area 131a in which the exposure light EL is illuminated twice by the two inclined portions during one scanning exposure operation. In other words, the two inclined portions of the two illumination areas IR overlapping along the X-axis direction define on the mask 131 a continuous pattern area 131a in which the exposure light EL is illuminated twice by the two inclined portions during one scanning exposure operation. On the other hand, the non-seamless pattern area 131b of the effective area 131p other than the seamless pattern area 131a is an area that is illuminated once by the exposure light EL during one scanning exposure operation.

The seamless pattern region 131a is a region corresponding to the seamless exposure region 151a. In other words, the exposure light EL that illuminates the seamless pattern region 131a passes through the seamless pattern region 131a and is irradiated onto the seamless exposure region 151a. On the other hand, the non-seamless pattern region 131b is a region corresponding to the non-seamless exposure region 151b. In other words, the exposure light EL that illuminates the non-seamless pattern region 131b passes through the non-seamless pattern region 131b and is irradiated onto the non-seamless exposure region 151b.

The joint pattern area 131a is a rectangular area. The joint pattern area 131a is an area whose longitudinal direction is the X-axis direction (i.e., the scanning direction) and whose transverse direction is the Y-axis direction (i.e., the non-scanning direction). The joint pattern area 131a is an area extending along the X-axis direction. On the mask 131, multiple joint pattern areas 131a (six joint pattern areas 131a in the example shown in FIG. 3(b)) are set at equal intervals along the Y-axis direction.

The non-seamless pattern region 131b is a rectangular region. The non-seamless pattern region 131b is a region in which the X-axis direction is the longitudinal direction and the Y-axis direction is the lateral direction. The non-seamless pattern region 131b is a region that extends along the X-axis direction. On the mask 131, multiple non-seamless pattern regions 131b (seven non-seamless pattern regions 131b in the example shown in FIG. 3(b)) are set at equal intervals along the Y-axis direction.

The mask pattern formed on the mask 131 includes a plurality of unit mask pattern portions 1311u that are regularly and repeatedly formed along the Y-axis direction, as shown in FIG. 2(c), and each of which is the same mask pattern. The plurality of unit mask pattern portions 1311u are formed in at least a portion of the effective area 131p. In other words, at least a portion of the effective area 131p includes a repeating area in which the plurality of unit mask pattern portions 1311u are regularly and repeatedly formed along at least one of the X-axis direction and the Y-axis direction. In the example shown in FIG. 2(c), the plurality of unit mask pattern portions 1311u are regularly and repeatedly formed along both the X-axis direction and the Y-axis direction.

In this case, the distance D1 between two adjacent joint pattern regions 131a along the Y-axis direction is longer than the distance D2 between two adjacent unit mask pattern portions 1311u along the Y-axis direction. The frequency with which joint pattern regions 131a appear along the Y-axis direction is lower than the frequency with which unit mask pattern portions 1311u appear along the Y-axis direction. The arrangement period of the joint pattern regions 131a along the Y-axis direction is longer than the arrangement period of the unit mask pattern portions 1311u along the Y-axis direction.

By the exposure light EL passing through the unit mask pattern portion 1311u, a unit device pattern portion 1511u corresponding to the unit mask pattern portion 1311u is formed on the substrate 151. Therefore, by the exposure light EL passing through the mask 131 including a plurality of unit mask pattern portions 1311u formed in a regular, repeated pattern (i.e., arranged), a device pattern including a plurality of unit device pattern portions 1511u arranged in a regular, repeated pattern is formed on the substrate 151.

As described above, the substrate 151 exposed by the exposure apparatus 1 is used, for example, to manufacture a display panel. In this case, the unit mask pattern portion 1311u is a mask pattern for forming each pixel (i.e., each display pixel) that constitutes the display panel on the substrate 151. In other words, the unit mask pattern portion 1311u is a mask pattern for forming circuit elements such as TFT (Thin Film Transistor) elements, color filters, black matrices, touch panel circuit elements, etc., formed in each pixel, on the substrate 151. Furthermore, the unit device pattern portion 1511u is a device pattern for each pixel.

A specific example of a mask 131 used to manufacture such a display panel will be described with reference to Figs. 3(a) and 3(b). Fig. 3(a) is a plan view showing a specific example of a mask 131 used to manufacture a display panel. Fig. 3(b) is a plan view showing a part of the mask 131 shown in Fig. 3(a).

3(a), a mask pattern group 1311g including a plurality of identical mask patterns 1311d is formed on the mask 131 (particularly in the effective area 131p surrounded by the light-shielding area 131s). Each mask pattern 1311d is a mask pattern for manufacturing one display panel. In other words, each mask pattern 1311d is a mask pattern corresponding to the device pattern of one display panel. Therefore, the mask 131 shown in FIG. 3(a) is used to manufacture a plurality of identical display panels from one substrate 151. In the example shown in FIG. 3(a), eight mask patterns 1311d are formed on the mask 131. Therefore, the mask 131 shown in FIG. 3(a) is used to manufacture eight identical display panels from one substrate 151.

As shown in FIG. 3(b), each mask pattern 1311d includes a plurality of unit mask pattern portions 1311u for forming a plurality of pixels of one display panel on the substrate 151. Hereinafter, a set of a plurality of unit mask pattern portions 1311u is appropriately referred to as a "pixel mask pattern portion 1311p". Each mask pattern 1311d further includes a peripheral mask pattern portion 1311s for forming a peripheral circuit, etc., arranged around a pixel region in which a plurality of pixels are arranged, on the substrate 151. FIG. 3(b) shows an example in which the peripheral mask pattern portion 1311s includes a mask pattern for forming wiring (for example, wiring connecting a plurality of pixels to a driving circuit) drawn out from a plurality of pixels. In the example shown in FIG. 3(b), the peripheral mask pattern portion 1311s is arranged on the -X side of the pixel mask pattern portion 1311p. However, the peripheral mask pattern portion 1311s may be arranged on at least one of the +X side, -Y side, and +Y side of the pixel mask pattern portion 1311p, in accordance with the arrangement position of the peripheral circuits, etc.

Such a mask 131 is manufactured as follows. First, a mask pattern corresponding to the device pattern (in the example shown in FIG. 3(a) to FIG. 3(b), a mask pattern group 1311g including a plurality of mask patterns 1311d) is calculated by a mask pattern calculation device 2 described later. Note that "calculation of a mask pattern" here means determining the contents of the mask pattern (i.e., a pattern layout), and is essentially equivalent to generating mask pattern data indicating the contents of the mask pattern. Then, the calculated mask pattern is actually formed on a mask blank on which no mask pattern is formed. Specifically, for example, an electron beam exposure device or the like exposes a mask blank on which a photosensitive material is applied based on the calculated mask pattern. Then, the exposed mask blank is developed, and a pattern layer of a photosensitive material corresponding to the mask pattern is formed on the mask blank. Then, the mask blank (particularly, a light-shielding film provided in the mask blank) is processed through the pattern layer of the photosensitive material. As a result, a mask 131 on which a mask pattern corresponding to the device pattern is formed is manufactured.

(2) Mask Pattern Calculation Apparatus 2 of the Present Embodiment
Next, a mask pattern calculation device 2 that calculates a mask pattern to be formed on the mask 131 will be described with reference to FIGS.

(2-1) Structure of Mask Pattern Calculation Apparatus 2 First, the structure of the mask pattern calculation apparatus 2 will be described with reference to Fig. 4. Fig. 4 is a block diagram showing the structure of the mask pattern calculation apparatus 2.

As shown in FIG. 4, the mask pattern calculation device 2 includes a CPU (Central Processing Unit) 21, a memory 22, an input unit 23, an operation device 24, and a display device 25.

The CPU 21 controls the operation of the mask pattern calculation device 2. The CPU 21 calculates a mask pattern and generates mask pattern data. That is, the CPU 21 designs a mask layout. Specifically, the CPU 21 calculates a mask pattern that satisfies a desired calculation condition based on device pattern data indicating the contents of the device pattern (that is, the pattern layout). Specifically, the CPU 21 calculates a mask pattern by solving an optimization problem or a mathematical programming problem for calculating a mask pattern that satisfies the desired calculation condition. A specific example of a desired calculation condition is a condition that optimizes the exposure amount (DOSE amount) and the depth of focus (DOF: Depth Of Focus) (so-called process window optimization). The condition of optimizing the exposure amount and the depth of focus means a condition that sets the exposure amount to a first desired amount and sets the depth of focus to a second desired amount.

The CPU 21 may essentially function as an EDA (Electronic Design Automation) tool. For example, the CPU 21 may function as an EDA tool by executing a computer program for causing the CPU 21 to perform the above-mentioned mask pattern calculation operation.

The memory 22 stores a computer program for causing the CPU 21 to perform a mask pattern calculation operation. However, the computer program for causing the CPU 21 to perform a mask pattern calculation operation may be recorded in an external storage device (e.g., a hard disk or an optical disk). The memory 22 further temporarily stores intermediate data generated while the CPU 21 is performing the mask pattern calculation operation.

The input unit 23 accepts input of various data used by the CPU 21 to perform mask pattern calculation operations. An example of such data is device pattern data indicating the device pattern to be formed on the substrate 151. However, the mask pattern calculation device 2 does not necessarily have to include the input unit 23.

The operation device 24 accepts user operations on the mask pattern calculation device 2. The operation device 24 may include, for example, at least one of a keyboard, a mouse, and a touch panel. The CPU 21 may perform a mask pattern calculation operation based on the user operations accepted by the operation device 24. However, the mask pattern calculation device 2 does not have to be equipped with the operation device 24.

The display device 25 can display desired information. For example, the display device 25 may directly or indirectly display information indicating the state of the mask pattern calculation device 2. For example, the display device 25 may directly or indirectly display the mask pattern being calculated by the mask pattern calculation device 2. For example, the display device 25 may directly or indirectly display any information related to the calculation operation of the mask pattern. However, the mask pattern calculation device 2 does not have to be equipped with a display device 25.

(2-2) Mask Pattern Calculation Operation Next, the mask pattern calculation operation performed by the mask pattern calculation device 2 will be described with reference to Fig. 5. Fig. 5 is a flowchart showing the flow of the mask pattern calculation operation performed by the mask pattern calculation device 2.

As shown in FIG. 5, the CPU 21 of the mask pattern calculation device 2 acquires device pattern data indicating a device pattern (step S1). The device pattern data is data indicating the contents of a device pattern (i.e., a pattern layout) that has been adjusted to satisfy a predetermined design rule, and is acquired as a result of so-called device design (in other words, circuit design). Examples of predetermined design rules include the minimum width of a line or hole, and the minimum space between two lines or two holes.

In parallel with the processing of step 1, the CPU 21 sets a state variable indicating the state of the exposure apparatus 1 when forming a device pattern on the substrate 151 with the exposure light EL through the mask 131 (step S2).

For example, the CPU 21 may set state variables related to the illumination optical system 12. The state variables related to the illumination optical system 12 are adjustable or fixed parameters that define the state of the light source unit 11 (e.g., the light intensity distribution on the pupil plane of the illumination optical system 12, the distribution of the polarization state of light on the pupil plane of the illumination optical system 12, etc.). Specific examples of such state variables related to the illumination optical system 12 include at least one of a state variable related to the shape of the illumination pattern by the illumination optical system 12 (i.e., the shape of the emission pattern of the exposure light EL), a state variable related to the σ value, and a state variable related to the light intensity of the exposure light EL1.

For example, the CPU 21 may set state variables related to the projection optical system 14. The state variables related to the projection optical system 14 are adjustable or fixed parameters that define the state of the projection optical system 14 (e.g., optical characteristics such as aberration and retardation). Specific examples of such state variables related to the projection optical system 14 include at least one of a state variable related to the wavefront shape of the exposure light EL projected by the projection optical system 14, a state variable related to the intensity distribution of the exposure light EL projected by the projection optical system 14, and a state variable related to the phase shift amount (or phase) of the exposure light EL projected by the projection optical system 14.

Then, the CPU 21 calculates a mask pattern capable of forming an image of the device pattern indicated by the device pattern data acquired in step S1 on the substrate 151 (step S3). At this time, the CPU 21 calculates a mask pattern capable of satisfying the above-mentioned calculation conditions under the circumstances in which the exposure apparatus 1 in the state indicated by the state variable set in step S2 irradiates the exposure light EL. For this reason, each time the CPU 21 calculates a mask pattern, it determines whether the calculated mask pattern satisfies the calculation conditions. If the calculated mask pattern does not satisfy the calculation conditions, the CPU 21 repeats the operation of changing the mask pattern (in other words, adjusting the calculated mask pattern) until the calculation conditions are satisfied. However, in addition to or instead of changing the mask pattern, the CPU 21 may change the state variable. In this case, the CPU 21 calculates a mask pattern capable of satisfying the above-mentioned calculation conditions under the circumstances in which the exposure apparatus 1 in the state indicated by the changed state variable irradiates the exposure light EL.

In particular, in this embodiment, when calculating the mask pattern in step S3 of FIG. 5, the CPU 21 calculates the mask pattern relatively efficiently by utilizing the fact that the multiple unit mask pattern parts 1311u are included (i.e., formed) in the mask 131. Hereinafter, with reference to FIG. 6, the process of calculating the mask pattern in step S3 of FIG. 5 by utilizing the fact that the multiple unit mask pattern parts 1311u are included in the mask 131 will be further described. FIG. 6 is a flowchart showing the flow of the process of calculating the mask pattern in step S3 of FIG. 5 by utilizing the fact that the multiple unit mask pattern parts 1311u are included in the mask 131. For convenience of explanation, the explanation using FIG. 6 will proceed using the operation of calculating the mask pattern shown in FIG. 3(a) to FIG. 3(b), but the process shown in FIG. 6 can be applied when calculating any mask pattern.

6, the CPU 21 acquires the pattern layout of the unit device pattern part 1511u based on the device pattern data (step S311). Note that the device pattern includes multiple unit device pattern parts 1511u, but since the pattern layouts of the multiple unit device pattern parts 1511u are the same, the CPU 21 only needs to acquire the pattern layout of one unit device pattern part 1511u.

Then, the CPU 21 calculates the pattern layout of one unit mask pattern part 1311u based on the pattern layout of one unit device pattern part 1511u acquired in step S311 (step S312). That is, instead of collectively calculating the pixel mask pattern part 1311p including multiple unit mask pattern parts 1311u, the CPU 21 first calculates the pattern layout of one unit mask pattern part 1311u.

In this embodiment, when calculating the pattern layout of one unit mask pattern portion 1311u in step S312, the CPU 21 utilizes the fact that the mask 131 contains multiple unit mask pattern portions 1311u. Specifically, as described above, the mask pattern to be calculated by the CPU 21 contains multiple unit mask pattern portions 1311u that are arranged in a repeating and regular pattern. The pattern layouts of the multiple unit mask pattern portions 1311u are the same. In that case, on the mask 131, a certain unit mask pattern portion 1311u should be adjacent to a part of the certain unit mask pattern portion 1311u itself.

For example, FIG. 7 shows a pattern layout of a unit mask pattern portion 1311u for forming a unit device pattern portion 1511u corresponding to one pixel of a display panel. A mask pattern for forming a TFT element included in a pixel, and a mask pattern for forming a signal line (e.g., a gate line, a data line, etc.) included in a pixel and connected to the TFT element are included. However, the scanning exposure operation for forming the TFT element and the scanning exposure operation for forming the signal line are generally performed separately using different masks 131. Therefore, the pattern calculation device 2 actually calculates a mask pattern including a unit mask pattern portion 1311u for forming a TFT element and a mask pattern including a unit mask pattern portion 1311u for forming a signal line separately. However, in this embodiment, for the sake of convenience, in order to clearly illustrate the repeated arrangement of multiple unit mask pattern portions 1311u in FIG. 7 (and further in the following FIGS. 8(a) to 10), the explanation will be given using unit mask pattern portions 1311u that include a mask pattern for forming TFT elements and a mask pattern for forming signal lines.

In the example shown in FIG. 7, the shape of the unit mask pattern portion 1311u on the XY plane is rectangular (e.g., rectangular or square). That is, the shape of the area on the mask 131 that the unit mask pattern portion 1311u occupies on the XY plane is rectangular. On the mask 131, multiple such unit mask pattern portions 1311u are regularly arranged in a repeated manner along both the X-axis direction and the Y-axis direction. That is, on the mask 131, multiple such unit mask pattern portions 1311u are arranged in a matrix.

In this case, as shown in FIG. 8(a), unit mask pattern portion 1311u-2 is adjacent to the +X side of unit mask pattern portion 1311u-1. The pattern layout of unit mask pattern portion 1311u-2 is the same as the pattern layout of unit mask pattern portion 1311u-1. Therefore, essentially, adjacent mask pattern portion 1311n, which is part of unit mask pattern portion 1311u-1 including the -X side outer edge of unit mask pattern portion 1311u-1, is adjacent to the outer edge (or side, the same below) of the +X side of unit mask pattern portion 1311u-1.

Similarly, as shown in FIG. 8(b), unit mask pattern portion 1311u-3 is adjacent to the -X side of unit mask pattern portion 1311u-1. The pattern layout of unit mask pattern portion 1311u-3 is the same as the pattern layout of unit mask pattern portion 1311u-1. Therefore, essentially, adjacent to the outer edge of the -X side of unit mask pattern portion 1311u-1 is adjacent mask pattern portion 1311n, which is part of unit mask pattern portion 1311u-1 and includes the outer edge of unit mask pattern portion 1311u-1 on the +X side.

Similarly, as shown in FIG. 8(c), unit mask pattern portion 1311u-4 is adjacent to the -Y side of unit mask pattern portion 1311u-1. The pattern layout of unit mask pattern portion 1311u-4 is the same as the pattern layout of unit mask pattern portion 1311u-1. Therefore, essentially, adjacent to the outer edge of the -Y side of unit mask pattern portion 1311u-1 is adjacent mask pattern portion 1311n, which is part of unit mask pattern portion 1311u-1 and includes the outer edge of unit mask pattern portion 1311u-1 on the +Y side.

Similarly, as shown in FIG. 8(d), unit mask pattern portion 1311u-5 is adjacent to the +Y side of unit mask pattern portion 1311u-1. The pattern layout of unit mask pattern portion 1311u-5 is the same as the pattern layout of unit mask pattern portion 1311u-1. Therefore, essentially, adjacent to the outer edge of unit mask pattern portion 1311u-1 on the +Y side is adjacent mask pattern portion 1311n, which is part of unit mask pattern portion 1311u-1 and includes the outer edge of unit mask pattern portion 1311u-1 on the -Y side.

Considering that a part of such a unit mask pattern portion 1311u may be an adjacent mask pattern portion 1311n adjacent to the unit mask pattern portion 1311u, the CPU 21 assumes (in other words, considers) that a part of one unit mask pattern portion 1311u to be calculated is adjacent to the one unit mask pattern portion 1311u as an adjacent mask pattern portion 1311n. For example, as shown in FIG. 9, the CPU 21 may assume that the adjacent mask pattern portion 1311n is adjacent to the unit mask pattern portion 1311u along the direction in which each side of the unit mask pattern portion 1311 extends (i.e., at least one of the X-axis direction and the Y-axis direction). Specifically, the CPU 21 may assume that (i) the outer edge on the +X side of the unit mask pattern unit 1311u is adjacent to an adjacent mask pattern unit 1311n-1 including the outer edge on the -X side of the unit mask pattern unit 1311u, (ii) the outer edge on the -X side of the unit mask pattern unit 1311u is adjacent to an adjacent mask pattern unit 1311n-2 including the outer edge on the +X side of the unit mask pattern unit 1311u, (iii) the outer edge on the +Y side of the unit mask pattern unit 1311u is adjacent to an adjacent mask pattern unit 1311n-3 including the outer edge on the -Y side of the unit mask pattern unit 1311u, and (iv) the outer edge on the -Y side of the unit mask pattern unit 1311u is adjacent to an adjacent mask pattern unit 1311n-4 including the outer edge on the +Y side of the unit mask pattern unit 1311u. 10, the CPU 21 may assume that the adjacent mask pattern portion 1311n is adjacent to the unit mask pattern portion 1311u along the diagonal direction of the unit mask pattern portion 1311u (i.e., a direction intersecting both the X-axis direction and the Y-axis direction on the XY plane) in addition to (or instead of) the direction in which each side of the unit mask pattern portion 1311 shown in FIG. 9 extends. Specifically, the CPU 21 assumes that (i) adjacent mask pattern portion 1311n-5 including the outer edges of the -X side and -Y side of the unit mask pattern portion 1311u is adjacent to the outer edges of the -X side and -Y side of the unit mask pattern portion 1311u along the diagonal direction of the unit mask pattern portion 1311u (e.g., vertices, the same applies hereinafter in this text), and (ii) adjacent mask pattern portion 1311n-5 including the outer edges of the -X side and -Y side of the unit mask pattern portion 1311u is adjacent to the outer edges of the -X side and -Y side of the unit mask pattern portion 1311u. It may be assumed that (iii) adjacent to the outer edge of the unit mask pattern unit 1311u on the +X side and -Y side is adjacent to adjacent mask pattern unit 1311n-7 including the outer edge of the -X side and +Y side of the unit mask pattern unit 1311u, and (iv) adjacent to the outer edge of the -X side and -Y side of the unit mask pattern unit 1311u is adjacent to adjacent mask pattern unit 1311n-8 including the outer edge of the +X side and +Y side of the unit mask pattern unit 1311u.

Under such a hypothetical situation, the CPU 21 calculates the pattern layout of one unit mask pattern portion 1311u, taking into account the influence of the adjacent mask pattern portion 1311n. As an example, the CPU 21 first calculates the unit mask pattern portion 1311u corresponding to the unit device pattern portion 1511u based on the unit device pattern portion 1511u so as to satisfy the above-mentioned calculation conditions. That is, the CPU 21 first calculates the unit mask pattern portion 1311u without taking into account the repeated arrangement of the multiple unit mask pattern portions 1311u. At this point, the mask pattern portion 1311u is calculated without taking into account the existence of the adjacent mask pattern portion 1311n (that is, on the assumption that the adjacent mask pattern portion 1311n is not adjacent to the unit mask pattern portion 1311u). However, in reality, the unit mask pattern portion 1311u is adjacent to the adjacent mask pattern portion 1311n (that is, a part of another unit mask pattern portion 1311u). Therefore, the exposure light EL passing through the unit mask pattern portion 1311u may be influenced not only by the unit mask pattern portion 1311u through which the exposure light EL itself has passed, but also by the adjacent mask pattern portion 1311n. For this reason, the exposure light EL passing through the unit mask pattern portion 1311u calculated without considering the existence of the adjacent mask pattern portion 1311n may not be able to form an image capable of forming the unit device pattern portion 1511u on the substrate 151 due to the influence of the adjacent mask pattern portion 1311n. Therefore, the CPU 21 assumes that a part of the calculated unit mask pattern portion 1311u is adjacent to the calculated unit mask pattern portion 1311u as the adjacent mask pattern portion 1311n. After that, the CPU 21 estimates the influence of the existence of the adjacent mask pattern portion 1311n on the formation of the unit device pattern portion 1511u by the exposure light EL passing through the unit mask pattern portion 1311u, and corrects at least a part of the unit mask pattern portion 1311u so as to satisfy the above-mentioned calculation condition while offsetting the influence. That is, even when the adjacent mask pattern portion 1311n exists, the CPU 21 corrects at least a portion of the unit mask pattern portion 1311u so that an image capable of forming an appropriate unit device pattern portion 1511u can be formed in the same manner as when the adjacent mask pattern portion 1311n does not exist. Note that the correction of at least a portion of the unit mask pattern portion 1311u includes adjusting the line width of at least a portion of the unit mask pattern portion 1311u, adjusting the extension direction of at least a portion of the unit mask pattern portion 1311u, removing at least a portion of the unit mask pattern portion 1311u, and adding a new mask pattern to at least a portion of the unit mask pattern portion 1311u.

6 again, after (or before or in parallel with) the calculation of the unit mask pattern portion 1311u, the CPU 21 acquires a pattern layout of the peripheral device pattern portion 1511s corresponding to the device pattern of the peripheral circuit based on the device pattern data (step S313). After that, the CPU 21 calculates a pattern layout of the peripheral mask pattern portion 1311s based on the peripheral device pattern portion 1511s acquired in step S313 (step S314).

Then, the CPU 21 arranges the unit mask pattern parts 1311u calculated in step S312 in a repeated and regular manner (step S315). Specifically, the CPU 21 specifies the arrangement of the unit device pattern parts 1511u included in the device pattern based on the device pattern data acquired in step S1 of FIG. 5. The CPU 21 then arranges the unit mask pattern parts 1311u according to the arrangement of the specified unit device pattern parts 1511u. As a result, the pattern layout of the pixel mask pattern part 1311p (see FIG. 3B) including the unit mask pattern parts 1311u is calculated. The CPU 21 then arranges the peripheral mask pattern part 1311s calculated in step S314 for the calculated pixel mask pattern part 1311p (step S315). As a result, as shown in FIG. 11, the pattern layout of the mask pattern 1311d including the unit mask pattern parts 1311u is calculated (step S315).

Then, the CPU 21 arranges a plurality of mask patterns 1311d calculated in step S315 (step S316). As a result, as shown in FIG. 12, a mask pattern group 1311g (i.e., mask patterns on the mask 131) including a plurality of mask patterns 1311d is calculated.

As described above, in this embodiment, the CPU 21 can calculate the mask pattern by utilizing the fact that the mask 131 contains multiple unit mask pattern parts 1311u. Therefore, the CPU 21 can efficiently calculate the mask pattern.

The process of step S316 in FIG. 6 described above is a process that is performed when calculating a mask pattern of a mask 131 that includes a plurality of mask patterns 1311d that include a plurality of unit mask pattern portions 1311u. However, the pattern calculation device 2 may calculate a mask pattern of a mask 131 that includes only one mask pattern 1311d that includes a plurality of unit mask pattern portions 1311u. In this case, the process of step S316 in FIG. 6 described above does not need to be performed.

(3) Modifications Next, modifications of the above-mentioned mask pattern calculation operation will be described.

(3-1) First Modification In the above description, the CPU 21 calculates one unit mask pattern portion 1311u and arranges a plurality of the calculated unit mask pattern portions 1311u to calculate the mask pattern 1311d. On the other hand, in the first modification, the CPU 21 calculates a plurality of different types of unit mask pattern portions 1311u.

Specifically, as shown in FIG. 13, each of the multiple unit mask pattern parts 1311u included in the mask pattern 1311d can be classified into multiple types of unit mask pattern groups 1311ud that can be distinguished based on the difference in the adjacent positions of other unit mask pattern parts 1311u. In the example shown in FIG. 13, for example, each of the multiple unit mask pattern parts 1311u can be classified into one of nine types of unit mask pattern groups 1311ud-1 to 1311ud-9. The unit mask pattern group 1311ud-1 includes unit mask pattern parts 1311u that are adjacent to other unit mask pattern parts 1311u on the +X side, -X side, +Y side, and -Y side, respectively. The unit mask pattern group 1311ud-2 includes unit mask pattern parts 1311u that are adjacent to other unit mask pattern parts 1311u on the +X side, -X side, and +Y side, respectively, but are not adjacent to other unit mask pattern parts 1311u on the -Y side. The unit mask pattern group 1311ud-3 includes unit mask pattern parts 1311u that are adjacent to other unit mask pattern parts 1311u on the +X side, the -X side, and the -Y side, respectively, but are not adjacent to other unit mask pattern parts 1311u on the +Y side. The unit mask pattern group 1311ud-4 includes unit mask pattern parts 1311u that are adjacent to other unit mask pattern parts 1311u on the -X side, the +Y side, and the -Y side, respectively, but are not adjacent to other unit mask pattern parts 1311u on the +X side. The unit mask pattern group 1311ud-5 includes unit mask pattern parts 1311u that are adjacent to other unit mask pattern parts 1311u on the +X side, the +Y side, and the -Y side, respectively, but are not adjacent to other unit mask pattern parts 1311u on the -X side. The unit mask pattern group 1311ud-6 includes unit mask pattern parts 1311u adjacent to other unit mask pattern parts 1311u on the +X side and +Y side, respectively, but not adjacent to other unit mask pattern parts 1311u on the -X side and -Y side, respectively. The unit mask pattern group 1311ud-7 includes unit mask pattern parts 1311u adjacent to other unit mask pattern parts 1311u on the +X side and -Y side, respectively, but not adjacent to other unit mask pattern parts 1311u on the -X side and +Y side, respectively. The unit mask pattern group 1311ud-8 includes unit mask pattern parts 1311u adjacent to other unit mask pattern parts 1311u on the -X side and +Y side, respectively, but not adjacent to other unit mask pattern parts 1311u on the +X side and -Y side, respectively. The unit mask pattern group 1311ud-9 includes unit mask pattern parts 1311u that are adjacent to other unit mask pattern parts 1311u on the -X side and -Y side, but are not adjacent to other unit mask pattern parts 1311u on the +X side and +Y side.

The CPU 21 calculates multiple types of unit mask pattern parts 1311u belonging to multiple different types of unit mask pattern groups 1311ud. In the example shown in FIG. 13, the CPU 21 calculates one unit mask pattern part 1311u-11 belonging to unit mask pattern group 1311ud-1, one unit mask pattern part 1311u-12 belonging to unit mask pattern group 1311ud-2, one unit mask pattern part 1311u-13 belonging to unit mask pattern group 1311ud-3, one unit mask pattern part 1311u-14 belonging to unit mask pattern group 1311ud-4, one unit mask pattern part 1311u-15 belonging to unit mask pattern group 1311ud-5, and one unit mask pattern part 1311u-6 belonging to unit mask pattern group 1311ud-7. Calculate one unit mask pattern part 1311u-15 belonging to unit mask pattern group 1311ud-6, one unit mask pattern part 1311u-16 belonging to unit mask pattern group 1311ud-7, one unit mask pattern part 1311u-18 belonging to unit mask pattern group 1311ud-8, and one unit mask pattern part 1311u-19 belonging to unit mask pattern group 1311ud-9.

The process of calculating each of the multiple types of unit mask pattern parts 1311u is the same as the process of calculating the unit mask pattern part 1311u described above. Therefore, the CPU 21 calculates each type of unit mask pattern part 1311u on the assumption that at least a part of each type of unit mask pattern part 1311u is adjacent to the outer edge of each of the X side, -X side, +Y side, and -Y side of each type of unit mask pattern part 1311u to which other unit mask pattern parts 1311u are adjacent. For example, the CPU 21 calculates the unit mask pattern part 1311u-11 on the assumption that at least a part of the unit mask pattern part 1311u-11 is adjacent to the outer edge of each of the +X side, -X side, +Y side, and -Y side of the unit mask pattern part 1311u-11. For example, the CPU 21 calculates the unit mask pattern unit 1311u-12 on the assumption that at least a part of the unit mask pattern unit 1311u-12 is adjacent to each of the outer edges on the +X side, -X side, and +Y side of the unit mask pattern unit 1311u-12. For example, the CPU 21 calculates the unit mask pattern unit 1311u-13 on the assumption that at least a part of the unit mask pattern unit 1311u-13 is adjacent to each of the outer edges on the +X side, -X side, and -Y side of the unit mask pattern unit 1311u-13. For example, the CPU 21 calculates the unit mask pattern unit 1311u-14 on the assumption that at least a part of the unit mask pattern unit 1311u-14 is adjacent to each of the outer edges on the -X side, +Y side, and -Y side of the unit mask pattern unit 1311u-14. For example, the CPU 21 calculates the unit mask pattern unit 1311u-15 on the assumption that at least a part of the unit mask pattern unit 1311u-15 is adjacent to each of the outer edges on the +X side, +Y side, and -Y side of the unit mask pattern unit 1311u-15. For example, the CPU 21 calculates the unit mask pattern unit 1311u-16 on the assumption that at least a part of the unit mask pattern unit 1311u-16 is adjacent to each of the outer edges on the +X side and +Y side of the unit mask pattern unit 1311u-16. For example, the CPU 21 calculates the unit mask pattern unit 1311u-17 on the assumption that at least a part of the unit mask pattern unit 1311u-17 is adjacent to each of the outer edges on the +X side and -Y side of the unit mask pattern unit 1311u-17. For example, the CPU 21 calculates the unit mask pattern unit 1311u-18 on the assumption that at least a portion of the unit mask pattern unit 1311u-18 is adjacent to each of the outer edges on the -X side and +Y side of the unit mask pattern unit 1311u-18. For example, the CPU 21 calculates the unit mask pattern unit 1311u-19 on the assumption that at least a portion of the unit mask pattern unit 1311u-19 is adjacent to each of the outer edges on the -X side and -Y side of the unit mask pattern unit 1311u-19.

Then, the CPU 21 calculates a mask pattern by arranging the calculated multiple types of unit mask pattern parts 1311u and peripheral mask pattern parts 1311s.

According to this first modified example, the CPU 21 can calculate the unit mask pattern portion 1311u taking into consideration that the influence from the adjacent mask pattern portion 1311n differs for each unit mask pattern portion 1311u. Therefore, the CPU 21 can relatively efficiently calculate a mask pattern capable of forming a desired device pattern with relatively high accuracy. Furthermore, the exposure apparatus 1 that exposes the substrate 151 using the mask 131 on which the mask pattern calculated according to this first modified example is formed can expose the substrate 151 so as to form the desired device pattern with relatively high accuracy.

When calculating the unit mask pattern portion 1311u adjacent to the peripheral mask pattern portion 1311s, the CPU 21 may calculate the unit mask pattern portion 1311u on the assumption that at least a part of the peripheral mask pattern portion 1311s is adjacent to the unit mask pattern portion 1311u as the adjacent mask pattern portion 1311n. For example, in the example shown in FIG. 13, the CPU 21 may calculate the unit mask pattern portion 1311u-15 on the assumption that at least a part of the peripheral mask pattern portion 1311s is adjacent to the outer edge of the -X side of the unit mask pattern portion 1311u-15. The same applies to the unit mask pattern portions 1311u-16 and 1311ud-17. In this case, the CPU 21 may calculate the peripheral mask pattern portion 1311s before calculating the unit mask pattern portion 1311u. As a result, the CPU 21 can calculate the unit mask pattern portion 1311u while taking into consideration the influence of the peripheral mask pattern portion 1311s on the exposure light EL passing through the unit mask pattern portion 1311u. Therefore, the CPU 21 can relatively efficiently calculate a mask pattern capable of forming a desired device pattern with relatively high accuracy.

For the same reason, when calculating the peripheral mask pattern portion 1311s adjacent to the unit mask pattern portion 1311u, the CPU 21 may calculate the peripheral mask pattern portion 1311s on the assumption that at least a portion of the unit mask pattern portion 1311u is adjacent to the peripheral mask pattern portion 1311s as an adjacent mask pattern portion 1311n.

Alternatively, when calculating the unit mask pattern portion 1311u adjacent to the peripheral mask pattern portion 1311s, the CPU 21 may calculate a composite mask pattern portion 1311c including the unit mask pattern portion 1311u and at least a portion of the peripheral mask pattern portion 1311s adjacent to the unit mask pattern portion 1311u, as shown in FIG. 14. Even when calculating such a composite mask pattern portion 1311c, the CPU 21 can relatively efficiently calculate a mask pattern capable of forming a desired device pattern with relatively high accuracy, just as in the case of calculating the unit mask pattern portion 1311u on the assumption that at least a portion of the peripheral mask pattern portion 1311s is adjacent to the unit mask pattern portion 1311u.

(3-2) Second Modification In the above description, the CPU 21 calculates the mask pattern group 1311g by arranging the multiple mask patterns 1311d. On the other hand, in the second modification, the CPU 21 calculates the mask pattern group 1311g by arranging the multiple mask patterns 1311d and then correcting at least a part of the multiple mask patterns 1311d according to the arrangement of the multiple mask patterns 1311d. Hereinafter, the mask pattern calculation operation in the second modification will be described with reference to FIG. 15. Note that the same processes as those performed in the above embodiment are denoted by the same step numbers and detailed descriptions thereof will be omitted.

As shown in FIG. 15, in the second modified example, the processes from step S311 to step S316 are performed in the same manner as in the above-described embodiment. In the second modified example, after the multiple mask patterns 1311d are arranged in step S316, the CPU 21 corrects at least a portion of the multiple mask patterns 1311d by utilizing the fact that the multiple mask patterns 1311d are included in the mask 131 (i.e., the multiple mask patterns 1311d are arranged) (step S321). Note that the correction of at least a portion of the multiple mask patterns 1311d includes adjusting the line width of at least a portion of the multiple mask patterns 1311d, adjusting the extension direction of at least a portion of the multiple mask patterns 1311d, removing at least a portion of the multiple mask patterns 1311d, and adding a new mask pattern to at least a portion of the multiple mask patterns 1311d.

Specifically, as described above, the pattern layout of the multiple mask patterns 1311d included in the mask pattern group 1311g is the same. In that case, a certain mask pattern 1311d should be adjacent to a part of the certain mask pattern 1311d itself on the mask 131. For this reason, the CPU 21 corrects at least a part of each mask pattern 1311d, assuming that a part of each mask pattern 1311d is adjacent to each mask pattern 1311d, in a manner similar to the operation of calculating the unit mask pattern portion 1311u, assuming that a part of the unit mask pattern portion 1311u is adjacent to the unit mask pattern portion 1311u.

For example, as shown in FIG. 16, the CPU 21 assumes that at least a portion of the mask pattern 1311d-1 including the outer edge on the +X side of the mask pattern 1311d-1 is adjacent to the outer edge on the -X side of the mask pattern 1311d-1, and that at least a portion of the mask pattern 1311d-1 including the outer edge on the -Y side of the mask pattern 1311d-1 is adjacent to the outer edge on the +Y side of the mask pattern 1311d-1. The CPU 21 then estimates the effect that the presence of the mask patterns assumed to be adjacent has on the formation of the device pattern by the exposure light EL via each mask pattern 1311d-1, and corrects at least a portion of the mask pattern 1311d-1 so as to satisfy the above-mentioned calculation condition while offsetting the effect.

Although not shown in order to avoid complicating the drawing, the CPU 21 corrects mask pattern 1311d-2 under the assumption that at least a portion of mask pattern 1311d-2 including the outer edge on the +X side of mask pattern 1311d-2 is adjacent to the outer edge on the -X side of mask pattern 1311d-2, and that at least a portion of mask pattern 1311d-2 including the outer edge on the +Y side of mask pattern 1311d-2 is adjacent to the outer edge on the -Y side of mask pattern 1311d-2. The CPU 21 corrects the mask pattern 1311d-3 on the assumption that at least a part of the mask pattern 1311d-3 including the outer edge of the mask pattern 1311d-3 on the -X side is adjacent to the outer edge of the mask pattern 1311d-3 on the +X side, at least a part of the mask pattern 1311d-3 including the outer edge of the mask pattern 1311d-3 on the +X side is adjacent to the outer edge of the mask pattern 1311d-3 on the -X side, and at least a part of the mask pattern 1311d-3 including the outer edge of the mask pattern 1311d-3 on the -Y side is adjacent to the outer edge of the mask pattern 1311d-3 on the +Y side, and the CPU 21 corrects the mask pattern 1311d-3 on the assumption that at least a part of the mask pattern 1311d-3 including the outer edge of the mask pattern 1311d-3 on the -Y side is adjacent to the outer edge of the mask pattern 1311d-3 on the +Y side. The mask pattern 1311d-5 is the same as the mask pattern 1311d-3. Therefore, the CPU 21 may correct the mask pattern 1311d-5 in the same correction manner as the mask pattern 1311d-3. The CPU 21 corrects the mask pattern 1311d-4 on the assumption that at least a part of the mask pattern 1311d-4 including the outer edge on the -X side of the mask pattern 1311d-4 is adjacent to the outer edge on the +X side of the mask pattern 1311d-4, at least a part of the mask pattern 1311d-4 including the outer edge on the +X side of the mask pattern 1311d-4 is adjacent to the outer edge on the -X side of the mask pattern 1311d-4, and at least a part of the mask pattern 1311d-4 including the outer edge on the +Y side of the mask pattern 1311d-4 is adjacent to the outer edge on the -Y side of the mask pattern 1311d-4. The mask pattern 1311d-6 is similar to the mask pattern 1311d-4. Therefore, the CPU 21 may correct the mask pattern 1311d-6 in the same correction manner as the mask pattern 1311d-4. The CPU 21 corrects the mask pattern 1311d-7 on the assumption that at least a portion of the mask pattern 1311d-7 including the outer edge on the -X side of the mask pattern 1311d-7 is adjacent to the outer edge on the +X side of the mask pattern 1311d-7, and at least a portion of the mask pattern 1311d-7 including the outer edge on the -Y side of the mask pattern 1311d-7 is adjacent to the outer edge on the +Y side of the mask pattern 1311d-7. The CPU 21 corrects the mask pattern 1311d-8 on the assumption that at least a portion of the mask pattern 1311d-8 including the outer edge on the -X side of the mask pattern 1311d-8 is adjacent to the outer edge on the +X side of the mask pattern 1311d-8, and at least a portion of the mask pattern 1311d-8 including the outer edge on the +Y side of the mask pattern 1311d-8 is adjacent to the outer edge on the -Y side of the mask pattern 1311d-8.

According to this second modified example, the CPU 21 can correct the mask pattern 1311d, taking into consideration that the influence of adjacent mask patterns differs for each mask pattern 1311d. Therefore, the CPU 21 can relatively efficiently calculate a mask pattern capable of forming a desired device pattern with relatively high accuracy. Furthermore, the exposure apparatus 1 that exposes the substrate 151 using the mask 131 on which the mask pattern calculated according to this second modified example is formed can expose the substrate 151 so as to form the desired device pattern with relatively high accuracy.

The CPU 21 may arrange the multiple mask patterns 1311d so that two adjacent mask patterns 1311d are adjacent to each other via a peripheral mask pattern portion 1311s, as shown in FIG. 17. In this case, the CPU 21 may recognize that the peripheral mask pattern portions 1311s are adjacent to each other before arranging the multiple mask patterns 1311d. Therefore, in this case, the CPU 21 may calculate the peripheral mask pattern portion 1311s by assuming that a part of the peripheral mask pattern portion 1311s is adjacent to the peripheral mask pattern portion 1311s, in a manner similar to the operation of calculating the unit mask pattern portion 1311u by assuming that a part of the unit mask pattern portion 1311u is adjacent to the unit mask pattern portion 1311u.

(3-3) Third Modification In the third modification, the CPU 21 calculates a mask pattern group 1311g by arranging a plurality of mask patterns 1311d and then correcting at least a portion of the plurality of mask patterns 1311d based on the correspondence between the above-mentioned joint pattern area 131a and non-joint pattern area 131b and the plurality of mask patterns 1311d. The joint pattern area 131a and non-joint pattern area 131b correspond to the joint exposure area 151a and non-joint exposure area 151b on the substrate 151, respectively. Therefore, it can be said that the CPU 21 corrects at least a portion of the plurality of mask patterns 1311d based on the correspondence between the joint exposure area 151a and non-joint exposure area 151b and the plurality of mask patterns 1311d. Hereinafter, the calculation operation of the mask pattern in the third modification will be described with reference to FIG. 18. Note that the same processes as those performed in the above-mentioned embodiment are given the same step numbers and detailed descriptions thereof will be omitted.

As shown in FIG. 18, in the third modified example, the processes from step S311 to step S316 are performed in the same manner as in the above-described embodiment. In the third modified example, after the multiple mask patterns 1311d are arranged in step S316, the CPU 21 corrects at least a portion of the multiple mask patterns 1311d based on the exposure amount in the seamless exposure area 151a by the exposure light EL through the seamless pattern area 131a and the exposure amount in the non-seamless exposure area 151b by the exposure light EL through the non-seamless pattern area 131b (step S331).

Specifically, as described above, the inclined portions of each projection region PR that defines the joint exposure region 151a are set so that the sum of the widths along the X-axis direction of the two inclined portions that overlap along the X-axis direction is the same as the width along the X-axis direction of each projection region PR (i.e., the width along the X-axis direction of the area portion other than the inclined portions). Therefore, theoretically, the exposure amount of the joint exposure region 151a that is doubly exposed is substantially the same as the exposure amount of the non-joint exposure region 151b that is not doubly exposed. However, because there is a difference in that the joint exposure region 151a is doubly exposed while the non-joint exposure region 151b is not doubly exposed, there is a possibility that the exposure amount of the joint exposure region 151a will not be the same as the exposure amount of the non-joint exposure region 151b due to some factor.

Therefore, in the third modified example, the CPU 21 corrects at least a portion of the mask patterns 1311d so that the deviation (i.e., difference) between the exposure amount of the seamless exposure area 151a and the exposure amount of the non-seamless exposure area 151b becomes smaller or becomes zero compared to before correcting at least a portion of the mask patterns 1311d. For example, when the exposure amount of the seamless exposure area 151a is larger than the exposure amount of the non-seamless exposure area 151b, the CPU 21 may correct at least a portion of the mask patterns 1311d so that the exposure amount of the seamless exposure area 151a becomes smaller and/or the exposure amount of the non-seamless exposure area 151b becomes larger. For example, when the exposure amount of the seamless exposure area 151a is smaller than the exposure amount of the non-seamless exposure area 151b, the CPU 21 may correct at least a portion of the mask patterns 1311d so that the exposure amount of the seamless exposure area 151a becomes larger and/or the exposure amount of the non-seamless exposure area 151b becomes smaller.

The CPU 21 may correct at least a part of the continuous mask pattern portion 1311a (for example, the unit mask pattern portion 1311u and the peripheral mask pattern portion 1311s included in the continuous pattern region 131a) formed in the continuous pattern region 131a of the multiple mask patterns 1311d. That is, the CPU 21 may correct at least a part of the continuous mask pattern portion 1311a to which the exposure light EL for exposing the continuous exposure region 151a is irradiated among the multiple mask patterns 1311d. For example, the CPU 21 may correct at least a part of the non-continuous mask pattern portion 1311b (for example, the unit mask pattern portion 1311u and the peripheral mask pattern portion 1311s included in the non-continuous pattern region 131b) included in the multiple mask patterns 1311d. That is, the CPU 21 may correct at least a part of the non-continuous mask pattern portion 1311b to which the exposure light EL for exposing the non-continuous exposure region 151b is irradiated among the multiple mask patterns 1311d.

When the CPU 21 corrects both the stitch mask pattern portion 1311a and the non-stitch mask pattern portion 1311b, the correction content of the stitch mask pattern portion 1311a differs from the correction content of the non-stitch mask pattern portion 1311b. However, the correction content of the stitch mask pattern portion 1311a may be the same as the correction content of the non-stitch mask pattern portion 1311b.

Now, with reference to Figures 19(a) to 19(d), we will explain a specific example of a process for correcting at least a portion of the multiple mask patterns 1311d so as to reduce the difference between the amount of exposure in the seamless exposure area 151a and the amount of exposure in the non-sequential exposure area 151b.

As shown in FIG. 19(a), the following explanation will be given using as an example a case where the device pattern to be formed on the substrate 151 is a device pattern in which the line width (more specifically, the reference line width) is the same between the joint exposure area 151a and the non-joint exposure area 151b.

In this case, if the difference between the exposure amount in the repeat exposure area 151a and the exposure amount in the non-repeat exposure area 151b is not taken into consideration, the CPU 21 calculates a mask pattern so that the line width of the repeat mask pattern portion 1311a included in the repeat pattern area 131a is the same as the line width of the non-repeat mask pattern portion 1311b included in the non-repeat pattern area 131b, as shown in FIG. 19(b). In this case, if the exposure amount of the repeat exposure area 151a and the exposure amount of the non-repeat exposure area 151b are the same under the condition that the line width of the repeat mask pattern portion 1311a and the line width of the non-repeat mask pattern portion 1311b are the same, the CPU 21 does not need to correct at least a portion of the multiple mask patterns 1311d.

However, in some cases, under a situation where the line width of the repeating mask pattern portion 1311a and the line width of the non-repeatable mask pattern portion 1311b are the same, the exposure amount of the repeating exposure area 151a and the exposure amount of the non-repeatable exposure area 151b may not be the same. In this case, the CPU 21 corrects at least a part of the multiple mask patterns 1311d so as to reduce the difference between the exposure amount of the repeating exposure area 151a and the exposure amount of the non-repeatable exposure area 151b. Specifically, the CPU 21 may correct at least a part of the multiple mask patterns 1311d so as to adjust the line width of at least one of the repeating mask pattern portion 1311a and the non-repeatable pattern 1311b. In other words, the CPU 21 may correct at least a part of the repeating mask pattern portion 1311a and the non-repeatable mask pattern portion 1311b so that the line width of the repeating mask pattern portion 1311a and the line width of the non-repeatable pattern 1311b are different. More specifically, for example, when a negative resist is applied to the substrate 151, the CPU 21 may adjust the line width of at least a part of the light-transmitting pattern 1311a-1 of the stitch mask pattern portion 1311a that transmits the exposure light EL and the light-transmitting pattern 1311b-1 of the non-stitch mask pattern portion 1311b that transmits the exposure light EL. For example, when a positive resist is applied to the substrate 151, the CU 21 may adjust the line width of at least a part of the light-shielding pattern 1311a-2 of the stitch mask pattern portion 1311a that shields the exposure light EL and the light-shielding pattern 1311b-2 of the non-stitch mask pattern portion 1311b that shields the exposure light EL. In the following, for convenience of explanation, an example in which a negative resist is applied to the substrate 151 will be used for explanation. In other words, in the following explanation, an example will be used in which the adjustment of at least a portion of mask pattern 1311a and mask pattern 1311b corresponds to the adjustment of at least a portion of the line width of light-transmitting patterns 1311a-1 and 1311b-1.

For example, the amount of exposure in the seamless exposure region 151a may be greater than the amount of exposure in the non-seamless exposure region 151b. In this case, the device pattern formed in the seamless exposure region 151a may be thicker than the device pattern formed in the non-seamless exposure region 151b. Therefore, as described above, the CPU 21 adjusts the line width of at least a portion of the light-transmitting patterns 1311a-1 and 1311b-1 so that the amount of exposure in the seamless exposure region 151a is smaller and/or the amount of exposure in the non-seamless exposure region 151b is larger. Specifically, as shown in FIG. 19(c), the CPU 21 adjusts the line width of at least a portion of the light-transmitting patterns 1311a-1 and 1311b-1 so that the line width of the light-transmitting pattern 1311a-1 is narrower than the line width of the light-transmitting pattern 1311b-1.

Alternatively, for example, under a situation where the line width of the stitch mask pattern portion 1311a and the line width of the non-stitch mask pattern portion 1311b are the same, the exposure amount of the stitch exposure region 151a may be smaller than the exposure amount of the non-stitch exposure region 151b. In this case, the device pattern formed in the stitch exposure region 151a may be thinner than the device pattern formed in the non-stitch exposure region 151b. Therefore, as described above, the CPU 21 adjusts the line width of at least a part of the light-transmitting patterns 1311a-1 and 1311b-1 so that the exposure amount of the stitch exposure region 151a is larger and/or the exposure amount of the non-stitch exposure region 151b is smaller. Specifically, as shown in FIG. 19(d), the CPU 21 adjusts the line width of at least a part of the light-transmitting patterns 1311a-1 and 1311b-1 so that the line width of the light-transmitting pattern 1311a-1 is wider than the line width of the light-transmitting pattern 1311b-1.

As a result of adjusting the line width of at least a portion of the light-transmitting patterns 1311a-1 and 1311b-1 in this way, the difference between the amount of exposure in the seamless exposure region 151a and the amount of exposure in the non-seamless exposure region 151b becomes small or zero. Therefore, the difference between the line width of the device pattern formed in the seamless exposure region 151a and the line width of the device pattern formed in the non-seamless exposure region 151b also becomes small or zero. In other words, according to this third modified example, the CPU 21 can relatively efficiently calculate a mask pattern that can form a desired device pattern with relatively high accuracy. Furthermore, the exposure apparatus 1 that exposes the substrate 151 using the mask 131 on which the mask pattern calculated by this third modified example is formed can expose the substrate 151 so as to form the desired device pattern with relatively high accuracy.

The difference between the exposure amount of the continuous exposure area 151a and the exposure amount of the non-continuous exposure area 151b varies depending on the characteristics of the exposure device 1 and the characteristics of the resist applied to the substrate 151. For this reason, the pattern calculation device 2 may store in advance in the memory 22 first correlation information indicating the correlation between the difference between the exposure amount of the continuous exposure area 151a and the exposure amount of the non-continuous exposure area 151b, the characteristics of the exposure device 1, and the characteristics of the resist applied to the substrate 151. Such first correlation information may be generated based on the measurement results of the substrate 151 actually exposed by the exposure device 1, or may be generated based on the results of a simulation of the operation of the exposure device 1. When the first correlation information is stored in advance in the memory 22, the CPU 21 may specify the difference in the exposure amount between the continuous exposure area 151a and the non-continuous exposure area 151b in the exposure device 1 that actually uses the mask 131 on which the mask pattern calculated by the pattern calculation device 2 is formed, based on the first correlation information. The CPU 21 may then correct at least a portion of the multiple mask patterns 1311d so that the identified deviation is reduced or reduced to zero.

In addition, the correction amount of the exposure dose difference between the seamless exposure region 151a and the non-seamless exposure region 151b depends on at least a part of the correction content (for example, the line width adjustment amount) of the multiple mask patterns 1311d. For this reason, the pattern calculation device 2 may store in advance in the memory 22 second correlation information indicating the correlation between the correction amount of the exposure dose difference between the seamless exposure region 151a and the non-seamless exposure region 151b and at least a part of the correction content of the multiple mask patterns 1311d. Such second correlation information may be generated based on the measurement result of the substrate 151 actually exposed by the exposure device 1, or may be generated based on the result of a simulation of the operation of the exposure device 1. When the second correlation information is stored in advance in the memory 22, the CPU 21 may specify the correction amount required to reduce or eliminate the exposure dose difference between the seamless exposure region 151a and the non-seamless exposure region 151b, and may specify the correction content of at least a part of the multiple mask patterns 1311d required to correct the exposure dose difference by the specified correction amount based on the second correlation information.

In addition to or instead of based on the exposure amount of the seamless exposure area 151a and the exposure amount of the non-seamless exposure area 151b, the CPU 21 may correct at least a portion of the multiple mask patterns 1311d based on any exposure characteristic in the seamless exposure area 151a and any exposure characteristic in the non-seamless exposure area 151b. For example, the CPU 21 may correct at least a portion of the multiple mask patterns 1311d so that the deviation (i.e., the difference) between any exposure characteristic in the seamless exposure area 151a and any exposure characteristic in the non-seamless exposure area 151b becomes small or becomes zero.

In the above description, the continuous exposure area 151a is defined by a plurality of projection areas PR set by the plurality of projection optical systems 14, respectively. However, even if the exposure apparatus 1 has a single projection optical system 14 (i.e., a single projection area PR is set), the continuous exposure area 151a can be defined on the substrate 151. For example, when at least a part of the area onto which the exposure light EL is projected by the N1 (where N1 is an integer of 1 or more) scanning exposure operation for forming at least a part of a certain device pattern overlaps with at least a part of the area onto which the exposure light EL is projected by the N2 (where N2 is an integer of 1 or more different from N1) scanning exposure operation for forming at least a part of the same device pattern, there is an area on the substrate 151 onto which the exposure light EL is exposed two or more times to form the same device pattern (for example, a device pattern of the same layer). This area onto which the exposure light EL is exposed two or more times corresponds to the above-mentioned continuous exposure area 151a. On the other hand, for example, if at least a portion of the area onto which the exposure light EL is projected by the N1th scanning exposure operation does not overlap with the area onto which the exposure light EL is projected by the N2th (where N2 is an integer equal to or greater than 1 and different from N1) scanning exposure operation, there is an area on the substrate 151 onto which the exposure light EL is exposed only once to form the same device pattern. This area onto which the exposure light EL is exposed only once corresponds to the non-seamless exposure area 151b described above. Therefore, the pattern calculation device 2 can also calculate the mask pattern of the mask 131 used by the exposure device 1 that has a single projection optical system 14 (i.e., a single projection area PR is set) using the calculation method of the third modified example.

In addition, in the third modified example, the CPU 21 does not have to calculate a mask pattern by calculating the unit mask pattern portion 1311u and then arranging a plurality of the calculated unit mask pattern portions 1311u. In this case, the CPU 21 may calculate a mask pattern corresponding to the device pattern by any method, and then correct the calculated mask pattern according to the correspondence between the repeat pattern area 131a and the non-repeat pattern area 131b and the plurality of mask patterns 1311d. Even in this case, the CPU 21 can still calculate a mask pattern capable of forming a desired device pattern with relatively high accuracy.

(3-4) Fourth Modification In the above-mentioned third modification, the CPU 21 calculates the mask pattern group 1311g by correcting at least a part of the mask patterns 1311d so that the difference between the exposure amount in the intermittent exposure region 151a and the exposure amount in the non-intermittent exposure region 151b becomes small or zero. On the other hand, in the fourth modification, the CPU 21 calculates the mask pattern group 1311g by arranging the mask patterns 1311d and then correcting at least a part of the mask patterns 1311d so that the variation in the exposure amount in the intermittent exposure region 151a becomes small or zero. Hereinafter, the calculation operation of the mask pattern in the fourth modification will be described with reference to FIG. 20. Note that the same processes as those performed in the above-mentioned embodiment are assigned the same step numbers and detailed descriptions thereof will be omitted. In addition, the processing contents not particularly described in the following description may be the same as the processing contents in the third modification.

As shown in FIG. 20, in the fourth modified example, the processes from step S311 to step S316 are performed in the same manner as in the above-described embodiment. In the fourth modified example, after the multiple mask patterns 1311d are arranged in step S316, the CPU 21 corrects at least a portion of the multiple mask patterns 1311d based on the exposure amount in the continuous exposure area 151a by the exposure light EL through the continuous pattern area 131a (step S341).

Specifically, as described above, the sum of the widths along the X-axis direction of the inclined parts of the two projection areas PR that overlap along the X-axis direction to define the joint exposure area 151a is set to a constant value (specifically, the width along the X-axis direction of the area other than the inclined parts). Therefore, theoretically, there is no variation in the amount of exposure in the joint exposure area 151a that is doubly exposed by the two projection areas PR. However, in a certain joint exposure area 151a, the ratio R of the amount of exposure by one of the two projection areas PR to the amount of exposure by the other of the two projection areas PR may change. Specifically, as shown in FIG. 21, in the area 151ar-1 that extends along the X-axis direction through the center of the joint exposure area 151a along the Y-axis direction, the ratio R of the amount of exposure by one projection area PR (projection area PRa in the example shown in FIG. 21) to the amount of exposure by the other projection area PR (projection area PRb in the example shown in FIG. 21) is approximately 50:50. On the other hand, in the region 151ar-2 extending along the X-axis direction through a position shifted a predetermined amount to the -Y side from the center of the continuous exposure region 151a along the Y-axis direction, the ratio R of the exposure amount by one projection region PRa to the exposure amount by the other projection region PRb is approximately R1 (where R1>50):R2 (where R2<50). In the region 151ar-3 extending along the X-axis direction through a position shifted a predetermined amount to the +Y side from the center of the continuous exposure region 151a along the Y-axis direction, the ratio R of the exposure amount by one projection region PRa to the exposure amount by the other projection region PRb is approximately R3 (where R3<50):R4 (where R4>50). Such a change in the ratio R within the continuous exposure region 151a may cause variations in the exposure amount within the continuous exposure region 151a.

Therefore, in the fourth modified example, the CPU 21 corrects at least a portion of the mask patterns 1311d (e.g., the intermittent mask pattern portion 1311a, the light-transmitting pattern 1311a-1, and the light-shielding pattern 1311a-2) so that the variation in the amount of exposure in the intermittent exposure region 151a is reduced compared to before correcting at least a portion of the mask patterns 1311d. Alternatively, the CPU 21 corrects at least a portion of the mask patterns 1311d so that the variation in the amount of exposure in the intermittent exposure region 151a is reduced to zero (i.e., the amount of exposure is uniform) compared to before correcting at least a portion of the mask patterns 1311d. For example, when the amount of exposure of a first region in the intermittent exposure region 151a is greater than the amount of exposure of a second region in the intermittent exposure region 151a, the CPU 21 may correct at least a portion of the mask patterns 1311d so that the amount of exposure of the first region is reduced and/or the amount of exposure of the second region is increased. For example, if the exposure amount of a first region in the continuous exposure region 151a is smaller than the exposure amount of a second region in the continuous exposure region 151a, the CPU 21 may correct at least a portion of the multiple mask patterns 1311d so that the exposure amount of the first region is increased and/or the exposure amount of the second region is decreased.

As an example, the closer the ratio R in a certain region in the continuous exposure region 151a is to 50:50 (=1), the greater the amount of exposure in that certain region may be. More specifically, in the example shown in FIG. 21, as shown in the graph on the right side of FIG. 21, in the continuous exposure region 151a, the amount of exposure in region 151ar-1 may be maximum, and the more distant the region is from the exposure region 151ar-1 along the Y axis direction, the smaller the amount of exposure may be. In other words, in the continuous exposure region 151a, the amount of exposure in the center of the continuous exposure region 151a along the Y axis direction may be maximum, and the more distant the region is from the center along the Y axis direction, the smaller the amount of exposure may be. In this case, the CPU 21 may correct at least a portion of the multiple mask patterns 1311d so that the more distant the region is along the Y axis direction from the center of the continuous exposure region 151a along the Y axis direction, the greater the amount of exposure is increased by correcting at least a portion of the multiple mask patterns 1311d. Alternatively, the CPU 21 may correct at least a portion of the mask patterns 1311d so that the exposure dose is less likely to be reduced by correcting at least a portion of the mask patterns 1311d in a region that is farther away from the center of the continuous exposure region 151a along the Y axis direction. More specifically, as shown in FIG. 22, the CPU 21 may adjust at least a portion of the continuous mask pattern portion 1311a so that the line width of the continuous mask pattern portion 1311a becomes wider in a region that is farther away from the center of the continuous exposure region 151a along the Y axis direction in the continuous pattern region 131a. The mask pattern shown in FIG. 22 is a mask pattern for forming a device pattern (i.e., the device pattern shown in FIG. 19(a)) in which the line width is the same between the continuous exposure region 151a and the non-continuous exposure region 151b.

As a result of correcting at least a portion of the multiple mask patterns 1311d in this way, the variation in the amount of exposure in the intermittent exposure area 151a is reduced or eliminated. Therefore, the variation in the line width of the device pattern formed in the intermittent exposure area 151a is also reduced or eliminated. In other words, according to this fourth modified example, the CPU 21 can relatively efficiently calculate a mask pattern capable of forming a desired device pattern with relatively high accuracy. Furthermore, the exposure apparatus 1 that exposes the substrate 151 using the mask 131 on which the mask pattern calculated by this fourth modified example is formed can expose the substrate 151 so as to form the desired device pattern with relatively high accuracy.

The variation in the exposure amount in the continuous exposure region 151a varies depending on the characteristics of the exposure device 1 and the characteristics of the resist applied to the substrate 151. For this reason, the pattern calculation device 2 may store in advance in the memory 22 third correlation information indicating the correlation between the variation in the exposure amount in the continuous exposure region 151a and the characteristics of the exposure device 1 and the characteristics of the resist applied to the substrate 151. Such third correlation information may be generated based on the measurement results of the substrate 151 actually exposed by the exposure device 1, or may be generated based on the results of a simulation of the operation of the exposure device 1. When the third correlation information is stored in advance in the memory 22, the CPU 21 may specify the variation in the exposure amount in the continuous exposure region 151a in the exposure device 1 that actually uses the mask 131 on which the mask pattern calculated by the pattern calculation device 2 is formed, based on the third correlation information. After that, the CPU 21 may correct at least a part of the multiple mask patterns 1311d so that the specified variation becomes small or zero.

The amount of correction of the exposure amount variation in the continuous exposure region 151a depends on at least a part of the correction content (e.g., the line width adjustment amount) of the multiple mask patterns 1311d. For this reason, the pattern calculation device 2 may store in advance in the memory 22 fourth correlation information indicating the correlation between the amount of correction of the exposure amount variation in the continuous exposure region 151a and at least a part of the correction content of the multiple mask patterns 1311d. Such fourth correlation information may be generated based on the measurement result of the substrate 151 actually exposed by the exposure device 1, or may be generated based on the result of a simulation of the operation of the exposure device 1. When the fourth correlation information is stored in advance in the memory 22, the CPU 21 may specify the correction amount required to reduce or eliminate the exposure amount variation in the continuous exposure region 151a, and may specify the correction content of at least a part of the multiple mask patterns 1311d required to correct the exposure amount variation by the specified correction amount based on the fourth correlation information.

The CPU 21 may also correct at least a portion of the multiple mask patterns 1311d based on the variation in the amount of exposure in the continuous exposure region 151a, in addition to or instead of based on the variation in the amount of exposure in the continuous exposure region 151a. For example, the CPU 21 may correct at least a portion of the multiple mask patterns 1311d so that the variation in the exposure characteristic in the continuous exposure region 151a is reduced or reduced to zero.

In addition, in the fourth modified example, the CPU 21 does not have to calculate a mask pattern by calculating the unit mask pattern portion 1311u and then arranging a plurality of the calculated unit mask pattern portions 1311u. In this case, the CPU 21 may calculate a mask pattern corresponding to the device pattern by any method, and then correct the calculated mask pattern so that the variation in the exposure amount in the continuous exposure area 151a is small or zero. Even in this case, the CPU 21 can still calculate a mask pattern capable of forming a desired device pattern with relatively high accuracy.

(3-5) Fifth Modification In the fifth modification, the CPU 21 calculates a mask pattern group 1311g by arranging a plurality of mask patterns 1311d and then correcting at least a part of the plurality of mask patterns 1311d according to the corresponding relationship between the plurality of projection optical systems 14 and the plurality of mask patterns 1311d. The plurality of projection optical systems 14 correspond to a plurality of illumination regions IR (or a plurality of projection regions PR), respectively. Therefore, it can be said that the CPU 21 corrects at least a part of the plurality of mask patterns 1311d according to the corresponding relationship between the plurality of illumination regions IR (or a plurality of projection regions PR) and the plurality of mask patterns 1311d. Hereinafter, the calculation operation of the mask pattern in the fifth modification will be described with reference to FIG. 23. Note that the same processes as those performed in the above-mentioned embodiment are given the same step numbers and their detailed description will be omitted.

As shown in FIG. 23, in the fifth modified example, the processes from step S311 to step S316 are performed in the same manner as in the above-described embodiment. In the fifth modified example, after the multiple mask patterns 1311d are arranged in step S316, the CPU 21 corrects at least a portion of the multiple mask patterns 1311d based on the variation in the exposure amount due to the multiple exposure light EL projected from the multiple projection optical systems 14, respectively (step S351).

Specifically, the multiple projection optical systems 14 are manufactured so that the optical characteristics (e.g., aberration, etc.) are the same among the multiple projection optical systems 14. In this case, the exposure amounts by the multiple exposure light EL from the multiple projection optical systems 14 should all be the same. However, in reality, there is a possibility that the optical characteristics vary among the multiple projection optical systems 14 due to manufacturing errors, etc. For example, the optical characteristics of one projection optical system 14 may not be the same as the optical characteristics of the other projection optical systems 14. In this case, the exposure amount by one exposure light EL projected from one projection optical system 14 may not be the same as the exposure amount by the other exposure light EL projected from the other projection optical system 14. As a result, on the substrate 151, the exposure amount in one exposure area exposed by one exposure light EL projected from one projection optical system 14 may not be the same as the exposure amount in the other exposure area exposed by the other exposure light EL projected from the other projection optical system 14. More specifically, the amount of exposure in one exposure area on the substrate 151 where one projection area PR corresponding to one projection optical system 14 is set may not be the same as the amount of exposure in another exposure area on the substrate 151 where another projection area PR corresponding to another projection optical system 14 is set.

Therefore, in the fifth modified example, the CPU 21 corrects at least a portion of the mask patterns 1311d so that the variation in the exposure amount due to the multiple exposure light EL projected from the multiple projection optical systems 14 is reduced compared to before correcting at least a portion of the mask patterns 1311d. Alternatively, the CPU 21 corrects at least a portion of the mask patterns 1311d so that the variation in the exposure amount due to the multiple exposure light EL from the multiple projection optical systems 14 becomes zero (i.e., the exposure amounts due to the multiple exposure light EL become the same) compared to before correcting at least a portion of the mask patterns 1311d. In other words, the CPU 21 corrects at least a portion of the mask patterns 1311d so that the variation in the exposure amount in the multiple exposure regions on the substrate 151 that are respectively exposed by the multiple exposure light EL projected from the multiple projection optical systems 14 becomes small or zero compared to before correcting at least a portion of the mask patterns 1311d. For example, when the exposure amount of one exposure area exposed by one exposure light EL projected from one projection optical system 14 is greater than the exposure amount of other exposure areas exposed by other exposure light EL projected from other projection optical systems 14, the CPU 21 may correct at least a portion of the mask patterns 1311d so that the exposure amount of one exposure area is smaller and/or the exposure amount of other exposure areas is larger. For example, when the exposure amount of one exposure area exposed by one exposure light EL projected from one projection optical system 14 is smaller than the exposure amount of other exposure areas exposed by other exposure light EL projected from other projection optical systems 14, the CPU 21 may correct at least a portion of the mask patterns 1311d so that the exposure amount of one exposure area is larger and/or the exposure amount of other exposure areas is smaller.

An exposure area on the substrate 151 exposed by an exposure light EL projected from a projection optical system 14 is an area on the substrate 151 where a projection area PR corresponding to the projection optical system 14 is set (more specifically, an area through which the projection area PR passes as the substrate 151 moves). The exposure light EL exposing an area on the substrate 151 where a certain projection area PR is set is the exposure light EL projected onto the substrate 151 through an area on the mask 131 where an illumination area IR corresponding to the certain projection area PR is set (more specifically, an area through which the illumination area IR passes as the mask 131 moves). For this reason, in order to adjust the exposure amount of an exposure area exposed by an exposure light EL projected from a projection optical system 14, the CPU 21 may correct a mask pattern included in an area on the mask 131 through which an illumination area IR corresponding to the certain projection optical system 14 (i.e., an illumination area IR irradiated with the exposure light EL projected by the projection optical system 14) passes. For example, the CPU 21 may correct a mask pattern (e.g., unit mask pattern portion 1311u and peripheral mask pattern portion 1311s included in the area on the mask 131 where the illumination area IRa is set) included in order to adjust the amount of exposure of the exposure area exposed by the exposure light EL projected from the projection optical system 14a. For example, the CPU 21 may correct a mask pattern (e.g., unit mask pattern portion 1311u and peripheral mask pattern portion 1311s included in the area on the mask 131 where the illumination area IRb is set) included in order to adjust the amount of exposure of the exposure area exposed by the exposure light EL projected from the projection optical system 14b. The same applies to the projection optical systems 14c to 14g (illumination areas IRa to IRg).

The CPU 21 corrects at least a part of the mask patterns 1311d so that the correction content of one mask pattern included in the area on the mask 131 where one illumination area IR is set is different from the correction content of the other mask patterns included in the area on the mask 131 where the other illumination area IR is set. This is because one of the causes of the variation in the amount of exposure is the variation in the optical characteristics between the multiple projection optical systems 14, and therefore if the correction content of one mask pattern is made different from the correction content of the other mask patterns, the variation in the optical characteristics between the multiple projection optical systems 14 can be corrected by the mask pattern (as a result, the variation in the amount of exposure can also be corrected). However, the CPU 21 may correct at least a part of the mask patterns 1311d so that the correction content of the mask pattern included in the area on the mask 131 where one illumination area IR is set is the same as the correction content of the mask pattern included in the area on the mask 131 where the other illumination area IR is set.

Next, with reference to Figures 24(a) to 24(c) and Figures 25(a) to 25(b), a specific example of a process for correcting at least a portion of the multiple mask patterns 1311d so as to reduce the variation in the exposure amount due to the multiple exposure light beams EL projected from the multiple projection optical systems 14, respectively, will be described.

As described above, one of the causes of variation in the amount of exposure light EL projected from each of the projection optical systems 14 is variation in the optical characteristics between the projection optical systems 14. One example of such an optical characteristic is aberration (particularly, distortion). Distortion is a phenomenon in which the image formed on the image plane by the projection optical system 14 is distorted.

For example, FIG. 24(a) shows the image plane 141 of the projection optical system 14 where no distortion occurs and the projection area PR set within the image plane 141. The dotted lines within the image plane 141 are auxiliary lines for expressing the distortion of the image plane 141. Furthermore, FIG. 24(a) shows the exposure amount at a certain position on the substrate 151 that is scanned and exposed with the exposure light EL projected onto the projection area PR of the projection optical system 14 where no distortion occurs. In particular, FIG. 24(a) shows the exposure amount at three positions A, B, and C that are aligned along the Y-axis direction on the substrate 151. Position A is sequentially scanned and exposed with a portion of the exposure light EL (in FIG. 24(a), for convenience, it is written as "exposure light ELa(1), exposure light ELa(2), ..., exposure light ELa(n)") projected onto an area a extending along the X-axis on the -Y side of the center in the Y-axis direction of the projection area PR. Position B is sequentially scanned and exposed by a portion of the exposure light EL projected onto an area b extending along the X-axis at the center of the Y-axis direction of the projection area PR (in FIG. 24A, for convenience, these are referred to as "exposure light ELb(1), exposure light ELb(2), ..., exposure light ELb(n)"). Position C is sequentially scanned and exposed by a portion of the exposure light EL projected onto an area c extending along the X-axis at the +Y side of the center of the Y-axis direction of the projection area PR (in FIG. 24A, for convenience, these are referred to as "exposure light ELc(1), exposure light ELc(2), ..., exposure light ELc(n)"). As shown in FIG. 24A, when no distortion aberration occurs, the exposure amount (particularly, its distribution pattern) from position A to position C is the same. As a result, when the exposure light EL is projected from position A to position C through a mask pattern of the same line width, a device pattern of the same line width is formed from position A to position C.

On the other hand, FIG. 24(b) shows the image plane 141 of the projection optical system 14 where distortion aberration (particularly, barrel-shaped distortion in which a distortion that bulges from the center of the image plane toward the outside) occurs, and the projection area PR set within the image plane 141. Furthermore, FIG. 24(b) also shows the exposure amount at a certain position on the substrate 151 that is scanned and exposed with the exposure light EL projected onto the projection area PR of the projection optical system 14 where barrel-shaped distortion aberration occurs. FIG. 24(c) shows the image plane 141 of the projection optical system 14 where distortion aberration (particularly, pincushion-shaped distortion in which a distortion that bulges from the outside of the image plane toward the center occurs) occurs, and the projection area PR set within the image plane 141. Furthermore, FIG. 24(c) also shows the exposure amount at a certain position on the substrate 151 that is scanned and exposed with the exposure light EL projected onto the projection area PR of the projection optical system 14 where pincushion-shaped distortion aberration occurs. As can be seen from FIG. 24(b) to FIG. 24(c), when distortion occurs, the area a onto which the exposure light ELa(1), the exposure light ELa(2), ..., the exposure light ELa(n) is projected and the area c onto which the exposure light ELc(1), the exposure light ELc(2), ..., the exposure light ELc(n) is projected are also curved in accordance with the distortion of the image surface 141 caused by the distortion. Therefore, the exposure amount (particularly, its distribution pattern) at positions A and C is different from the exposure amount (particularly, its distribution pattern) at position B. Specifically, the peak value of the exposure amount at positions A and C is smaller than the peak value of the exposure amount at position B, and the decreasing gradient of the exposure amount at positions A and C is smaller than the decreasing gradient of the exposure amount at position B. As a result, even if the exposure light EL is projected from position A to position C through a mask pattern with the same line width, the line width of the device pattern formed at positions A and C may be thicker than the line width of the device pattern formed at position B.

Although there is a possibility that no distortion occurs in all of the multiple projection optical systems 14 or that the same distortion occurs, in reality, there is a high possibility that different distortions occur in each of the multiple projection optical systems 14 or that distortion occurs only in some of the multiple projection optical systems 14. For this reason, it is not easy to eliminate such distortions by adjusting the multiple projection optical systems 14. Therefore, since it is not easy to eliminate distortions, the exposure amount varies due to the multiple exposure lights EL projected from the multiple projection optical systems 14 due to such distortions. For example, FIG. 25A shows projection areas PRa to PRc set on the substrate 151 when barrel distortion occurs in the projection optical system 14a, pincushion distortion occurs in the projection optical system 14b, and no distortion occurs in the projection optical system 14c. As shown in FIG. 25A, the projection area PRa is set across the non-seamless exposure area 151b-a and the stitching exposure area 151a-ab. The projection area PRc is set across the seamless exposure area 151a-ab, the non-seamless exposure area 151b-b, and the seamless exposure area 151a-bc. The projection area PRc is set in the seamless exposure area 151a-bc and the non-seamless exposure area 151b-c. For this reason, as shown on the right side of FIG. 25(a), the exposure amount varies between the seamless exposure area 151a-ab to 151a-bc and the non-seamless exposure area 151b-a to 151b-c. As a result, the line width of the device pattern formed also varies between the seamless exposure area 151a-ab to 151a-bc and the non-seamless exposure area 151b-a to 151b-c. Furthermore, the exposure amount varies within each of the seamless exposure area 151a-ab to 151a-bc and the non-seamless exposure area 151b-a to 151b-b. As a result, there is variation in the line width of the device pattern formed even within the seamless exposure regions 151a-ab to 151a-bc and the non-sequential exposure regions 151b-a to 151b-b.

25(b), the CPU 21 corrects at least a part of the mask pattern included in at least one of the joint pattern area 131a-ab corresponding to the joint exposure area 151a-ab, the joint pattern area 131a-bc corresponding to the joint exposure area 151a-bc, the non-joint pattern area 131b-a corresponding to the non-joint exposure area 151b-a, the non-joint pattern area 131b-b corresponding to the non-joint exposure area 151b-b, and the non-joint pattern area 131b-c corresponding to the non-joint exposure area 151b-c, so as to reduce the variation in the amount of exposure (particularly, to reduce the variation in the line width of the device pattern to be formed). For example, the CPU 21 may correct the mask pattern so as to adjust the line width of at least a part of the mask pattern, as in the third and fourth modified examples. Furthermore, the CPU 21 may correct the mask pattern so that the correction content of the mask pattern (for example, the amount of adjustment of the line width) corresponds to the amount of exposure before the mask pattern is corrected. As a result, as shown on the right side of FIG. 25(b), the corrected mask pattern reduces the variation in the amount of exposure between the seamless exposure regions 151a-ab to 151a-bc and the non-seamless exposure regions 151b-a to 151b-c (zero in the example shown in FIG. 25(b)). Therefore, the variation in the line width of the device pattern formed between the seamless exposure regions 151a-ab to 151a-bc and the non-seamless exposure regions 151b-a to 151b-c is reduced (zero in the example shown in FIG. 25(b)). Furthermore, in the example shown in FIG. 25(b), the variation in the amount of exposure within each of the seamless exposure regions 151a-ab to 151a-bc and the non-seamless exposure regions 151b-a to 151b-b is also reduced. As a result, the variation in line width of the formed device pattern is reduced even within the seamless exposure regions 151a-ab to 151a-bc and the non-seamless exposure regions 151b-a to 151b-b.

Furthermore, with reference to Figures 26(a) to 26(b) and Figures 27(a) to 27(b), another specific example of a process for correcting at least a portion of the multiple mask patterns 1311d so as to reduce the variation in the exposure amount due to the multiple exposure light beams EL projected from the multiple projection optical systems 14, respectively, will be described.

As described above, one of the causes of variation in the amount of exposure light EL due to multiple exposure light beams is variation in the optical characteristics between multiple projection optical systems 14. One example of such an optical characteristic is aberration (particularly, field curvature). Field curvature is a phenomenon in which the image surface 141 of the projection optical system 14 is curved to be concave or convex with respect to the projection optical system 14. Because the image surface 141 is curved, the exposure light EL projected from the projection optical system 14 in which field curvature occurs is essentially in a defocused state on the substrate 151.

For example, FIG. 26(a) shows the image plane 141 of the projection optical system 14 where no curvature of field occurs and the projection area PR set within the image plane 141. Furthermore, FIG. 26(a) shows the exposure amount at a certain position (position A to position C described above) on the substrate 151 scanned and exposed with the exposure light EL projected onto the projection area PR of the projection optical system 14 where no curvature of field occurs. As shown in FIG. 24(a), when no curvature of field occurs, the exposure amount (particularly, its distribution pattern) from position A to position C is the same. As a result, when the exposure light EL is projected from position A to position C via a mask pattern of the same line width, a device pattern of the same line width is formed from position A to position C.

On the other hand, FIG. 26(b) shows the image plane 141 of the projection optical system 14 where curvature of field occurs and the projection area PR set within the image plane 141. Furthermore, FIG. 26(b) shows the exposure amount at a certain position (position A to position C) on the substrate 151 scanned and exposed with the exposure light EL projected onto the projection area PR of the projection optical system 14 where curvature of field occurs. In the example shown in FIG. 26(b), it is assumed that the image plane 141 coincides with the surface of the substrate 151 (i.e., in focus) at position B. In this case, the exposure light EL is appropriately focused at position B, but the exposure light EL is in a defocused state at positions A and C. For this reason, the exposure amount (particularly, its distribution pattern) at positions A and C is different from the exposure amount (particularly, its distribution pattern) at position B. Specifically, the peak value of the exposure amount at positions A and C is smaller than the peak value of the exposure amount at position B, and the decrease gradient of the exposure amount at positions A and C is smaller than the decrease gradient of the exposure amount at position B. As a result, even if the exposure light EL is projected from position A to position C through a mask pattern of the same line width, the line width of the device pattern formed at positions A and C may be thicker than the line width of the device pattern formed at position B.

Although there is a possibility that no curvature of field occurs in all of the projection optical systems 14 or that the same curvature of field occurs, in reality, there is a high possibility that different curvatures of field occur in each of the projection optical systems 14 or that curvature of field occurs only in some of the projection optical systems 14. For this reason, it is not easy to eliminate such curvature of field by adjusting the projection optical systems 14. Therefore, since it is not easy to eliminate the curvature of field, the exposure amount of the multiple exposure lights EL projected from the multiple projection optical systems 14 varies due to such curvature of field. For example, FIG. 27(a) shows projection areas PRa to PRc set on the substrate 151 when a curvature of field occurs in the projection optical system 14a such that the image surface 141 is curved to be concave, a curvature of field occurs in the projection optical system 14b such that the image surface 141 is curved to be convex, and no curvature of field occurs in the projection optical system 14c. As shown in FIG. 26(a), the amount of exposure varies between the seamless exposure regions 151a-ab to 151a-bc and the non-seamless exposure regions 151b-a to 151b-c. As a result, the line width of the device pattern formed also varies between the seamless exposure regions 151a-ab to 151a-bc and the non-seamless exposure regions 151b-a to 151b-c. Furthermore, the amount of exposure also varies within each of the seamless exposure regions 151a-ab to 151a-bc and the non-seamless exposure regions 151b-a to 151b-b. As a result, the line width of the device pattern formed also varies within the seamless exposure regions 151a-ab to 151a-bc and the non-seamless exposure regions 151b-a to 151b-b.

Therefore, as shown in Figure 27(b), the CPU 21 corrects at least a portion of the mask pattern included in at least one of the seamless pattern region 131a-ab, the seamless pattern region 131a-bc, the non-seamless pattern region 131b-a, the non-seamless pattern region 131b-b, and the non-seamless pattern region 131b-c so as to reduce such variations in the amount of exposure (particularly, to reduce variations in the line width of the device pattern to be formed). As a result, as shown on the right side of Figure 27(b), the corrected mask pattern reduces the variation in the amount of exposure between the seamless exposure regions 151a-ab to 151a-bc and the non-seamless exposure regions 151b-a to 151b-c (to zero in the example shown in Figure 27(b)). Therefore, the variation in line width of the device pattern formed between the seamless exposure regions 151a-ab to 151a-bc and the non-seamless exposure regions 151b-a to 151b-c is reduced (zero in the example shown in FIG. 27(b)). Furthermore, in the example shown in FIG. 27(b), the variation in the amount of exposure within each of the seamless exposure regions 151a-ab to 151a-bc and the non-seamless exposure regions 151b-a to 151b-b is also reduced. As a result, the variation in line width of the device pattern formed is also reduced within the seamless exposure regions 151a-ab to 151a-bc and the non-seamless exposure regions 151b-a to 151b-b.

In this way, according to the fifth modified example, the variation in the amount of exposure light EL projected from the multiple projection optical systems 14 is reduced or eliminated. Therefore, the variation in the line width of the device pattern formed in different regions on the substrate 151 onto which the different exposure light EL projected from the different projection optical systems 14 is projected is also reduced or eliminated. In other words, according to the fifth modified example, the CPU 21 can relatively efficiently calculate a mask pattern capable of forming the desired device pattern with relatively high accuracy. Furthermore, the exposure apparatus 1 that exposes the substrate 151 using the mask 131 on which the mask pattern calculated according to the fifth modified example is formed can expose the substrate 151 so as to form the desired device pattern with relatively high accuracy.

The variation in the amount of exposure light EL projected from each of the projection optical systems 14 varies depending on the characteristics of the exposure apparatus 1 and the characteristics of the resist applied to the substrate 151. For this reason, the pattern calculation device 2 may store in advance in the memory 22 fifth correlation information indicating the correlation between the variation in the amount of exposure light EL projected from each of the projection optical systems 14 and the characteristics of the exposure apparatus 1 and the characteristics of the resist applied to the substrate 151. Such fifth correlation information may be generated based on the measurement results of the substrate 151 actually exposed by the exposure apparatus 1, or may be generated based on the results of a simulation of the operation of the exposure apparatus 1. When the fifth correlation information is stored in advance in the memory 22, the CPU 21 may specify the variation in the amount of exposure light EL in the exposure device 1 that actually uses the mask 131 on which the mask pattern calculated by the pattern calculation device 2 is formed, based on the fifth correlation information. After that, the CPU 21 may correct at least a part of the mask patterns 1311d so that the specified variation becomes small or zero.

The amount of correction of the variation in the amount of exposure light EL depends on at least a part of the correction content (e.g., the amount of adjustment of the line width) of the mask patterns 1311d. For this reason, the pattern calculation device 2 may store in advance in the memory 22 sixth correlation information indicating the correlation between the amount of correction of the variation in the amount of exposure light EL and at least a part of the correction content of the mask patterns 1311d. Such sixth correlation information may be generated based on the measurement result of the substrate 151 actually exposed by the exposure device 1, or may be generated based on the result of a simulation of the operation of the exposure device 1. When the sixth correlation information is stored in advance in the memory 22, the CPU 21 may specify the correction amount required to reduce or eliminate the variation in the amount of exposure light EL, and may specify the correction content of at least a part of the mask patterns 1311d required to correct the variation in the amount of exposure by the specified correction amount based on the sixth correlation information.

The CPU 21 may also correct at least a portion of the multiple mask patterns 1311d based on the variation in any exposure characteristic due to the multiple exposure light beams EL, in addition to or instead of based on the variation in the amount of exposure due to the multiple exposure light beams EL projected from the multiple projection optical systems 14. For example, the CPU 21 may correct at least a portion of the multiple mask patterns 1311d so that the variation in any exposure characteristic due to the multiple exposure light beams EL is reduced or reduced to zero.

In addition, in the fifth modified example, the CPU 21 does not have to calculate the mask pattern by calculating the unit mask pattern portion 1311u and then arranging a plurality of the calculated unit mask pattern portions 1311u. In this case, the CPU 21 may calculate a mask pattern corresponding to the device pattern by any method, and then correct the calculated mask pattern so that the variation in the exposure amount due to the multiple exposure light beams EL projected respectively from the multiple projection optical systems 14 is reduced or zero. Even in this case, the CPU 21 can still calculate a mask pattern capable of forming a desired device pattern with relatively high accuracy.

In the fifth modified example, the CPU 21 corrects at least a part of the mask patterns 1311d based on the variation in the exposure characteristics due to the exposure light EL projected from each of the projection optical systems 14. However, in addition to or instead of this, the CPU 21 may correct at least a part of the mask patterns 1311d based on the variation in the exposure characteristics due to the exposure light EL projected from a certain projection optical system 14 (i.e., the variation in the exposure characteristics within one projection region PR corresponding to one projection optical system 14). In other words, the CPU 21 corrects at least a part of the mask patterns 1311d without considering the variation in the exposure characteristics due to the exposure light EL projected from each of the projection optical systems 14. Specifically, as shown in FIG. 24B and FIG. 24C, in the projection region PR of the projection optical system 14 in which distortion aberration occurs, the exposure characteristics vary (i.e., the exposure characteristics vary so that the exposure amount at positions A and C is different from the exposure amount at position B). The same applies when image plane curvature occurs. Furthermore, depending on the optical characteristics of the projection optical system 14, there is a possibility that variations in the exposure characteristics may occur even within the projection region PR of the projection optical system 14 where no distortion aberration or image plane curvature occurs. For this reason, the CPU 21 may correct at least a portion of the multiple mask patterns 1311d so as to reduce or eliminate the variations in the exposure characteristics due to the exposure light EL projected from such a single projection optical system 14 (i.e., the variations in the exposure characteristics within a single projection region PR corresponding to a single projection optical system 14).

(4) Device Manufacturing Method Next, a method for manufacturing a display panel using the above-described exposure apparatus 1 will be described with reference to Fig. 28. Fig. 28 is a flow chart showing the flow of a device manufacturing method for manufacturing a display panel using the above-described exposure apparatus 1. Note that, for ease of explanation, the device manufacturing method for manufacturing a liquid crystal display panel, which is an example of a display panel, will be described below. However, other display panels can also be manufactured using a device manufacturing method that is at least partially modified from the device manufacturing method shown in Fig. 28.

28, first, the mask 131 is manufactured. That is, the mask pattern is calculated by the mask pattern calculation device 2, and the mask 131 on which the calculated mask pattern is formed is manufactured. Then, in step S201 (pattern formation process), a coating process of coating a resist on the substrate 151 to be exposed, an exposure process of transferring a mask pattern for a display panel to the substrate 151 using the exposure device 1 described above, and a development process of developing the substrate 151 are performed. A resist pattern corresponding to the mask pattern (or device pattern) is formed on the substrate 151 by the lithography process including the coating process, exposure process, and development process. Following the lithography process, an etching process using the resist pattern as a mask and a stripping process of removing the resist pattern are performed. As a result, a device pattern is formed on the substrate 151. Such lithography processes are performed multiple times according to the number of layers formed on the substrate 151.

In step S202 (color filter formation process), a color filter is formed. In step S203 (cell assembly process), liquid crystal is injected between the substrate 151 on which the device pattern is formed in step S201 and the color filter formed in step S202. As a result, a liquid crystal cell is manufactured.

In the subsequent step S204 (module assembly process), components (e.g., electrical circuits and backlights) are attached to the liquid crystal cell manufactured in step S203 to enable the desired display operation. As a result, the liquid crystal display panel is completed.

At least some of the constituent elements of each of the above-mentioned embodiments can be appropriately combined with at least some of the other constituent elements of each of the above-mentioned embodiments. Some of the constituent elements of each of the above-mentioned embodiments may not be used. In addition, to the extent permitted by law, all publications and U.S. patents relating to exposure apparatuses and the like cited in each of the above-mentioned embodiments are incorporated by reference into the present text.

The present invention is not limited to the above-described embodiments, but may be modified as appropriate within the scope of the claims and the entire specification without violating the spirit or concept of the invention. Pattern calculation devices, pattern calculation methods, masks, exposure devices, device manufacturing methods, computer programs, and recording media that incorporate such modifications are also included within the technical scope of the present invention.

1 exposure device 131 mask 131a joint pattern area 131b non-joint pattern area 1311u unit mask pattern portion 1311p pixel mask pattern portion 1311s peripheral mask pattern portion 1311d mask pattern 1311g mask pattern group 14 projection optical system 15 substrate stage 151 substrate 151a joint area 151b non-joint area 1511u unit device pattern portion EL exposure light IR illumination area PR projection area

Claims (7)

a mask for forming a device pattern on a substrate, the mask being used in an exposure apparatus that performs scanning exposure by irradiating an area extending in a scanning direction on the substrate with light transmitted through the first projection optical system and then with light transmitted through the second projection optical system while moving a first projection optical system and a second projection optical system, at least a portion of which are aligned in the scanning direction relative to the substrate, in the scanning direction, the mask comprising:
disposed on an area extending in the scanning direction,
a wiring pattern extending in a non-scanning direction intersecting the scanning direction;
a difference between a line width of a portion of the wiring pattern corresponding to a region extending in the scanning direction and the line width of the wiring pattern at the central portion increases as the line width approaches an end of the portion in the non-scanning direction from a central portion of the portion;
Mask. the line width of the portion corresponding to a region extending in the scanning direction in the wiring pattern becomes thicker from the center of the portion toward the end of the portion in the non-scanning direction;
The mask of claim 1 . A mask for forming a device pattern on a substrate with exposure light, comprising:
the mask includes a first wiring pattern for forming a first wiring extending in a first direction on the substrate, a second wiring pattern for forming a second wiring extending in the first direction on the substrate, and a third wiring pattern for forming a third wiring extending in the first direction on the substrate;
the third wiring pattern is located between the first wiring pattern and the second wiring pattern,
a line width of the third wiring pattern is different from a line width of the first wiring pattern and is different from a line width of the second wiring pattern;
Mask. the mask is a mask for forming the device pattern on the substrate, and is used in an exposure apparatus that performs scanning exposure by irradiating an area extending in a scanning direction on the substrate with light via the first projection optical system and then with light via the second projection optical system while moving a first projection optical system and a second projection optical system, at least a portion of which are aligned in the scanning direction, relative to the substrate in the scanning direction, the mask comprising:
disposed on an area extending in the scanning direction,
The third wiring pattern is a wiring pattern extending in the first direction, which is the scanning direction, and is projected onto a region extending in the scanning direction.
The mask of claim 3. 4. The mask according to claim 3, wherein the first wiring pattern, the second wiring pattern, and the third wiring pattern are data lines. 4. The mask according to claim 3, wherein the first wiring pattern, the second wiring pattern, and the third wiring pattern are each a gate line. the device pattern has a plurality of arranged unit device pattern portions,
The mask according to any one of claims 1 to 6, wherein the mask pattern is calculated by calculating a unit mask pattern portion for forming one of the unit device pattern portions on the substrate among the mask patterns of the mask, correcting the unit mask pattern portion based on an influence that a specific mask pattern portion adjacent to the unit mask pattern portion and corresponding to at least a part of the unit mask pattern portion has on the formation of the unit device pattern portion by exposure light passing through the unit mask pattern portion, and arranging a plurality of the corrected unit mask pattern portions.