JP7494609B2 - Semiconductor Module - Google Patents

Description

The present invention relates to a semiconductor module, and in particular to a semiconductor module (power module) used in power conversion devices such as motor drive inverter devices and DC-DC converter devices.

Power conversion devices use semiconductor modules that integrate multiple power semiconductor elements for power conversion into a single package. Known semiconductor modules include IPMs (Intelligent Power Modules) that are equipped with drivers for driving the power semiconductor elements and control ICs (Integrated Circuits) that have the function of detecting and protecting against operational anomalies.

Figure 9 is a circuit diagram showing an example of a conventional semiconductor module that constitutes an inverter device that drives a three-phase AC motor, and Figure 10 is a circuit diagram showing the connection relationship of an overcurrent detection circuit in a control IC for the lower arm of a conventional semiconductor module.

As shown in FIG. 9, the conventional semiconductor module 100 has three half-bridge circuits and constitutes a three-phase inverter circuit. This semiconductor module 100 uses an IGBT (Insulated Gate Bipolar Transistor) as a power semiconductor element and an FWD (Free Wheeling Diode) connected in inverse parallel to the IGBT.

In the semiconductor module 100, the first half-bridge circuit is configured by connecting in series the U-phase IGBT 101 and FWD 102 in the upper arm and the X-phase IGBT 103 and FWD 104 in the lower arm. The second half-bridge circuit is configured by connecting in series the V-phase IGBT 105 and FWD 106 in the upper arm and the Y-phase IGBT 107 and FWD 108 in the lower arm. The third half-bridge circuit is configured by connecting in series the W-phase IGBT 109 and FWD 110 in the upper arm and the Z-phase IGBT 111 and FWD 112 in the lower arm.

The collector terminals of the U-phase, V-phase, and W-phase IGBTs 101, 105, and 109 are connected to a positive power supply terminal P (hereinafter referred to as the P terminal), and the emitter terminals of the X-phase, Y-phase, and Z-phase IGBTs 103, 107, and 111 are connected to a negative power supply terminal N (hereinafter referred to as the N terminal). The P terminal is connected to the positive terminal of the power supply 150, and the N terminal is connected to the negative terminal of the power supply 140. The connection between the emitter terminal of the U-phase IGBT 101 and the collector terminal of the X-phase IGBT 103 is connected to the U-phase input terminal of the motor 150. The connection between the emitter terminal of the V-phase IGBT 105 and the collector terminal of the Y-phase IGBT 107 is connected to the V-phase input terminal of the motor 150. The connection between the emitter terminal of the W-phase IGBT 109 and the collector terminal of the Z-phase IGBT 111 is connected to the W-phase input terminal of the motor 150.

IGBTs 101, 103, 105, 107, 109, and 111 each have a sense IGBT that can output a current proportional to the collector current, and have a sense emitter terminal in addition to the emitter terminal. The gate terminals, sense emitter terminals, and auxiliary emitter terminals of IGBTs 101, 103, 105, 107, 109, and 111 are connected to the OUT terminals, OC terminals, and GND terminals of control ICs 113, 114, 115, 116, 117, and 118, respectively. The control ICs 113, 115, and 117 of the U-phase, V-phase, and W-phase of the upper arm each have a Vcc terminal and a GND terminal, and the Vcc terminal and the GND terminal are connected to the positive terminal and the negative terminal of the power supplies 119, 120, and 121, respectively. The control ICs 114, 116, 118 of the X-phase, Y-phase, and Z-phase of the lower arm have Vcc and GND terminals, which are connected to the positive and negative terminals of a common power supply 122, respectively.

The Vin terminals of the control ICs 113, 114, 115, 116, 117, and 118 are input terminals for input signals that drive the corresponding IGBTs 101, 103, 105, 107, 109, and 111, and are each connected to an input terminal (not shown) of the semiconductor module 100. The input terminal (not shown) of the semiconductor module 100 is connected to a higher-level control device.

The coil seen on the N-terminal line (hereinafter referred to as the N-line) represents the parasitic inductances Lxp, Lyp, and Lzp in the current path of the printed circuit board on which the X-phase, Y-phase, and Z-phase IGBTs 103, 107, and 111 are mounted.

Each of the control ICs 113, 114, 115, 116, 117, and 118 has an overcurrent detection circuit. Each overcurrent detection circuit receives a sense current from the sense emitter terminal of the corresponding IGBT 101, 103, 105, 107, 109, or 111 to its OC terminal, and determines whether the main current (collector current) has reached a preset value. When the overcurrent detection circuit detects an overcurrent state of the main current, the control ICs 113, 114, 115, 116, 117, and 118 transition to a protective operation such as stopping the corresponding IGBT 101, 103, 105, 107, 109, or 111.

Here, the control ICs 114, 116, and 118 in the lower arm, which have a common reference potential of the ground line to which the negative terminal of the power supply 122 is connected, have overcurrent detection circuits 114a, 116a, and 118a, respectively, as shown in FIG. 10. In addition, in the semiconductor module 100, the X-phase IGBT 103, the Y-phase IGBT 107, and the Z-phase IGBT 111 are arranged in this order in a direction away from the N terminal.

The X-phase overcurrent detection circuit 114a has a current sense resistor 123, a reference voltage source 124, and a comparator 125. The OC terminal of the control IC 114 is connected to one terminal of the current sense resistor 123 and the inverting input terminal of the comparator 125, and the other terminal of the current sense resistor 123 is connected to the GND terminal. The positive terminal of the reference voltage source 124 is connected to the non-inverting input terminal of the comparator 125, and the negative terminal of the reference voltage source 124 is connected to the GND terminal. The output terminal of the comparator 125 is connected to a protection circuit (not shown) of the control IC 114.

The Y-phase overcurrent detection circuit 116a has a current sense resistor 126, a reference voltage source 127, and a comparator 128. The OC terminal of the control IC 116 is connected to one terminal of the current sense resistor 126 and the inverting input terminal of the comparator 128, and the other terminal of the current sense resistor 126 is connected to the GND terminal. The positive terminal of the reference voltage source 127 is connected to the non-inverting input terminal of the comparator 128, and the negative terminal of the reference voltage source 127 is connected to the GND terminal. The output terminal of the comparator 128 is connected to a protection circuit (not shown) of the control IC 116.

The Z-phase overcurrent detection circuit 118a has a current sense resistor 129, a reference voltage source 130, and a comparator 131. The OC terminal of the control IC 118 is connected to one terminal of the current sense resistor 129 and the inverting input terminal of the comparator 131, and the other terminal of the current sense resistor 129 is connected to the GND terminal. The positive terminal of the reference voltage source 130 is connected to the non-inverting input terminal of the comparator 131, and the negative terminal of the reference voltage source 130 is connected to the GND terminal. The output terminal of the comparator 131 is connected to a protection circuit (not shown) of the control IC 118.

In the above overcurrent detection circuits 114a, 116a, and 118a, when the IGBTs 103, 107, and 111 are turned on, the collector current flows from each emitter terminal E to the N terminal via the N line. At this time, a sense current proportional to the collector current is supplied to the OC terminal from the sense emitter terminals of the IGBTs 103, 107, and 111. This sense current is converted into a voltage by flowing through the current sense resistors 123, 126, and 129, and becomes the current detection signal Vsense. This current detection signal Vsense is compared with the reference voltages of the reference voltage sources 124, 127, and 130 by the comparators 125, 128, and 131. In normal operation when the current detection signal Vsense has not reached the reference voltages of the reference voltage sources 124, 127, and 130, the comparators 125, 128, and 131 output a high (H) level protection operation signal. In the event of an abnormality in which the current detection signal Vsense rises above the reference voltage of the reference voltage sources 124, 127, and 130, the comparators 125, 128, and 131 output a low (L) level protection operation signal.

When the X-phase IGBT 103 is turned on, the collector current flows from its emitter terminal E through the N line to the N terminal. At this time, the potential of the emitter terminal E as seen from the N terminal rises due to the action of the parasitic inductance Lxp of the N line. Also, when the Y-phase IGBT 107 is turned on, the collector current flows from its emitter terminal E through the N line to the N terminal, so the potential of the emitter terminal E as seen from the N terminal rises due to the action of the parasitic inductances Lyp and Lxp of the N line. Similarly, when the Z-phase IGBT 111 is turned on, the collector current flows from its emitter terminal E through the N line to the N terminal, so the potential of the emitter terminal E as seen from the N terminal rises due to the action of the parasitic inductances Lzp, Lyp, and Lxp of the N line. These increases in potential are transmitted to the GND terminals of the control ICs 114, 116, and 118 via the auxiliary emitter terminal EE, so the ground potential of the control ICs 114, 116, and 118 increases. When this ground potential increases, the current detection signal Vsense changes. The change in this current detection signal Vsense is small for the X-phase overcurrent detection circuit 114a, which is close to the N terminal, and large for the Z-phase overcurrent detection circuit 118a, which is far from the N terminal.

As such, the value of the detected current detection signal Vsense varies depending on the positions of the IGBTs 103, 107, and 111 arranged within the semiconductor module 100. In particular, in a semiconductor module 100 that constitutes a three-phase inverter circuit, it is desirable for all phases to have the same characteristics.

A technique has been proposed for correcting the overcurrent determination so that the overcurrent determination is uniform in response to the variations present in the overcurrent detection circuits 114a, 116a, and 118a (see, for example, Patent Document 1). According to the technique described in Patent Document 1, the reference voltage compared to the current detection signal is variable, and the reference voltage is set to the voltage of the current detection signal when the collector current reaches an overcurrent state.

JP 2001-197723 A

However, a configuration that varies the reference voltage of the overcurrent detection circuit is not practical for semiconductor modules that incorporate multiple power semiconductor elements and control ICs in a single package, because each control IC requires pre-processing such as trimming.

The present invention has been made in consideration of these points, and aims to provide a semiconductor module that suppresses the detection variation of the overcurrent detection circuit caused by differences in the installation distance from the power supply terminal of the power semiconductor element.

In order to solve the above problems, one idea of the present invention provides a semiconductor module, which includes a first negative power supply terminal and a second negative power supply terminal provided on both sides of a package and selectively connected to a power supply, a plurality of power semiconductor elements arranged along a line internally connecting the first negative power supply terminal and the second negative power supply terminal and having main electrodes connected to the line, a plurality of control ICs for driving the power semiconductor elements, and a power supply connection terminal provided on the same side of the package as the first negative power supply terminal and to which a power supply voltage is applied. The control IC also includes a power supply connection terminal voltage detection circuit that detects whether a power supply voltage is applied to the power supply connection terminal, a phase identification circuit that identifies an arrangement position along a line corresponding to the distance from the first negative power supply terminal or the second negative power supply terminal of the power semiconductor element to be driven, a selection signal generation circuit that generates a selection signal from the detection result of the power supply connection terminal voltage detection circuit and the identification result of the phase identification circuit, a current sense resistor that receives a sense current proportional to the main current of the power semiconductor element and converts it into a voltage to output a current detection signal, a variable reference voltage source that has a plurality of voltage sources, one of the voltage sources is selected by the selection signal upon receiving the selection signal and outputs it as a reference voltage, and a comparator that compares the current detection signal with the selected reference voltage.

The semiconductor module of the above configuration varies the sense current or overcurrent detection threshold of the overcurrent detection circuit depending on the distance from the negative power supply terminal of the power semiconductor element, making it possible to detect an overcurrent state under the same conditions regardless of the distance from the negative power supply terminal of the power semiconductor element.

1 is a circuit diagram showing a configuration example of a semiconductor module according to an embodiment of the present invention; 2 is a circuit diagram illustrating an example of an overcurrent detection circuit of a control IC included in the semiconductor module according to the first embodiment; 13 is a circuit diagram illustrating an example of an overcurrent detection circuit of a control IC included in a semiconductor module according to a second embodiment. FIG. 11 is a circuit diagram showing another configuration example of a semiconductor module according to an embodiment of the present invention. FIG. 13 is a circuit diagram illustrating an example of an overcurrent detection circuit of a control IC included in a semiconductor module according to a third embodiment. FIG. 13 is a circuit diagram illustrating an example of an overcurrent detection circuit of a control IC included in a semiconductor module according to a fourth embodiment. FIG. 13 is a circuit diagram illustrating an example of an overcurrent detection circuit of a control IC included in a semiconductor module according to a fifth embodiment. FIG. 13 is a circuit diagram illustrating an example of an overcurrent detection circuit of a control IC included in a semiconductor module according to a sixth embodiment. FIG. 1 is a circuit diagram showing an example of a conventional semiconductor module that constitutes an inverter device for driving a three-phase AC motor. 1 is a circuit diagram showing the connections of an overcurrent detection circuit in a control IC for a lower arm of a conventional semiconductor module.

The following describes in detail an embodiment of the present invention with reference to the drawings, taking as an example a case where the present invention is applied to a semiconductor module for a three-phase AC motor in which power terminals are provided on both sides of a package. In the drawings, parts indicated with the same reference numerals indicate the same components, and the same reference numerals may be used for terminal names and the voltages and signals at those terminals.

FIG. 1 is a circuit diagram showing an example of the configuration of a semiconductor module according to an embodiment of the present invention.
The semiconductor module 10 of the present invention shown in Fig. 1 has basically the same configuration as the conventional one shown in Fig. 9. That is, the semiconductor module 10 has a first half-bridge circuit in which a U-phase IGBT 11 and FWD 12 and an X-phase IGBT 13 and FWD 14 are connected in series. The second half-bridge circuit is configured by connecting a V-phase IGBT 15 and FWD 16 and a Y-phase IGBT 17 and FWD 18 in series. The third half-bridge circuit is configured by connecting a W-phase IGBT 19 and FWD 20 and a Z-phase IGBT 21 and FWD 22 in series.

IGBTs 11, 13, 15, 17, 19, and 21 are connected to be driven by control ICs 23, 24, 25, 26, 27, and 28, respectively. The control ICs 23, 25, and 27 of the U-phase, V-phase, and W-phase of the upper arm are powered by power supplies 29, 30, and 31, respectively, and the control ICs 24, 26, and 28 of the X-phase, Y-phase, and Z-phase of the lower arm are powered by a common power supply 32.

The output of the first half-bridge circuit is connected to the U-phase input terminal of motor 1, the output of the second half-bridge circuit is connected to the V-phase input terminal of motor 1, and the output of the third half-bridge circuit is connected to the W-phase input terminal of motor 1.

IGBTs 11, 13, 15, 17, 19, and 21 also incorporate sense IGBTs, and their sense emitter terminals are connected to the OC terminals of the overcurrent detection circuits of control ICs 23, 24, 25, 26, 27, and 28, respectively.

This semiconductor module 10 further has a P terminal and an N terminal for connecting an external power supply 2. Inside the semiconductor module 10, the P terminal is connected to the collector terminals of the IGBTs 11, 15, and 19 of the upper arm via a positive power supply line, and the N terminal is connected to the emitter terminals of the IGBTs 13, 17, and 21 of the lower arm via a negative N line. In the illustrated example, the IGBTs 13, 17, and 21 of the X-phase, Y-phase, and Z-phase are arranged in this order from the N terminal along the N line. For this reason, on the N line, there is a parasitic inductance Lxp of the wiring of the printed circuit board between the N terminal and the emitter terminal of the IGBT 13 of the X phase. On the N line between the N terminal and the emitter terminal of the IGBT 17 of the Y phase, there are parasitic inductances Lxp and Lyp, and on the N line between the N terminal and the emitter terminal of the IGBT 21 of the Z phase, there are parasitic inductances Lxp, Lyp, and Lzp.

The control ICs 24, 26, and 28 of the lower arm also each have a Ph1 terminal and a Ph2 terminal, and identify whether they are X-phase, Y-phase, or Z-phase depending on how the Ph1 and Ph2 terminals are connected to the ground line. In the example shown, control IC 24 identifies it as X-phase because neither the Ph1 nor Ph2 terminals are connected to the ground line. Control IC 26 identifies it as Y-phase because the Ph1 terminal is connected to the ground line, and control IC 28 identifies it as Z-phase because the Ph2 terminal is connected to the ground line.

Next, we will explain the reference voltage and current sense resistor correction operations performed by the overcurrent detection circuit based on the identification result of whether the lower arm control ICs 24, 26, and 28 are X-phase, Y-phase, or Z-phase.

Figure 2 is a circuit diagram showing an example of an overcurrent detection circuit of a control IC included in a semiconductor module according to the first embodiment. Note that the overcurrent detection circuits of the lower arm control ICs 24, 26, and 28 have the same circuit configuration, so in Figure 2, the X-phase control IC 24 will be described as a representative.

The overcurrent detection circuit of the control IC 24 of the semiconductor module according to the first embodiment has a current sense resistor Rs that receives a sense current supplied from the sense emitter terminal of the IGBT 13 at its OC terminal and converts it into a current detection signal Vsense. The overcurrent detection circuit also has a comparator 40 for detecting overcurrent, and a phase identification circuit 50 and a variable reference voltage circuit 60 for generating a reference voltage for the comparator 40.

The phase identification circuit 50 has resistors R1 and R2, inverter circuits 51 and 52, and AND circuits 53, 54, and 55. One terminal of the resistors R1 and R2 is connected to the Vdd power supply line, the other terminal of the resistor R1 is connected to the Ph1 terminal of the control IC 24, and the other terminal of the resistor R2 is connected to the Ph2 terminal of the control IC 24. The Ph1 terminal is also connected to the input terminal of the inverter circuit 52 and one input terminal of the AND circuits 53 and 55. The Ph2 terminal is also connected to the input terminal of the inverter circuit 51, one input terminal of the AND circuit 54, and the other input terminal of the AND circuit 55. The output terminal of the inverter circuit 51 is connected to the other input terminal of the AND circuit 53, and the output terminal of the inverter circuit 52 is connected to the other input terminal of the AND circuit 54. The output terminal of AND circuit 53 outputs the identification signal Siz, the output terminal of AND circuit 54 outputs the identification signal Siy, and the output terminal of AND circuit 55 outputs the identification signal Six.

The variable reference voltage circuit 60 has resistors R11, R12, R13, and R14, and transmission gates 61, 62, and 63. One terminal of the resistor R11 is connected to the Vdd power supply line, and the other terminal of the resistor R11 is connected to one terminal of the resistor R12 and the input terminal of the transmission gate 63. The other terminal of the resistor R12 is connected to one terminal of the resistor R13 and the input terminal of the transmission gate 62. The other terminal of the resistor R13 is connected to one terminal of the resistor R14 and the input terminal of the transmission gate 61, and the other terminal of the resistor R14 is connected to the ground line. The output terminals of the transmission gates 61, 62, and 63 are connected to the non-inverting input terminal of the comparator 40. The identification signals Six, Siy, and Siz output by the phase identification circuit 50 are input to the control input terminals of the transmission gates 61, 62, and 63.

Here, as shown in FIG. 1, the Ph1 and Ph2 terminals of the phase identification circuit 50 are both H level because neither of them is connected to the ground line for the X-phase control IC 24. Therefore, only the AND circuit 55, which receives the H level of the Ph1 and Ph2 terminals at both input terminals, outputs the H level identification signal Six.

In the Y-phase control IC 26, only the Ph1 terminal is connected to the ground line, so the Ph1 terminal is at L level and the Ph2 terminal is at H level. At this time, only the AND circuit 54 has both input terminals input with H level, so the AND circuit 54 outputs an H level identification signal Siy. In the Z-phase control IC 28, only the Ph2 terminal is connected to the ground line, so the Ph1 terminal is at H level and the Ph2 terminal is at L level. At this time, only the AND circuit 53 has both input terminals input with H level, so the AND circuit 53 outputs an H level identification signal Siz.

In the control IC 24 for the X phase, the phase identification circuit 50 outputs an identification signal Six at an H level, so in the variable reference voltage circuit 60, the transmission gate 61 that receives the identification signal Six is controlled to be conductive. At this time, the other identification signals Siy and Siz are at an L level, so the transmission gates 72 and 71 that receive the identification signals Siy and Siz are controlled to be non-conductive. As a result, in the variable reference voltage circuit 60, the voltage Vref1 obtained by dividing the voltage Vdd by resistors R11-R13 and resistor R14 is provided to the non-inverting input terminal of the comparator 40 as a reference voltage.

In the Y-phase control IC 26, the phase identification circuit 50 outputs the identification signal Siy, so that the transmission gate 62 in the variable reference voltage circuit 60 is controlled to be conductive. Therefore, in the variable reference voltage circuit 60, the voltage Vref2 obtained by dividing the voltage Vdd by resistors R11, R12 and resistors R13, R14 is provided to the non-inverting input terminal of the comparator 40 as a reference voltage.

Similarly, in the Z-phase control IC 28, the phase identification circuit 50 outputs the identification signal Siz, so that the transmission gate 63 in the variable reference voltage circuit 60 is controlled to be conductive. Therefore, in the variable reference voltage circuit 60, the voltage Vref3 obtained by dividing the voltage Vdd by resistor R11 and resistors R12-R14 is provided to the non-inverting input terminal of the comparator 40 as a reference voltage.

As described above, in the X-phase overcurrent detection circuit, the rise in emitter potential when the IGBT 13 closest to the N terminal is turned on is the smallest, so the reference voltage of the comparator 40 is set to the smallest voltage, Vref1. Similarly, in the Y-phase and Z-phase overcurrent detection circuits, the reference voltage of the comparator 40 is set to successively larger voltages, Vref2 and Vref3, in response to the successively larger rises in the emitter potential of the IGBTs 17 and 21. For this reason, the X-phase, Y-phase and Z-phase overcurrent detection circuits detect an overcurrent state at the same current value.

Figure 3 is a circuit diagram showing an example of an overcurrent detection circuit of a control IC included in a semiconductor module according to the second embodiment. The overcurrent detection circuit of the second embodiment changes the current detection signal Vsense applied to the comparator 40 for each phase, whereas the overcurrent detection circuit of the first embodiment changes the reference voltage applied to the comparator 40 for each phase. Note that Figure 3 shows the X-phase control IC 24a of the second embodiment, and the Y-phase and Z-phase control ICs will be described with reference to this X-phase control IC 24a.

The overcurrent detection circuit of the second embodiment has a comparator 40 for detecting overcurrent and a reference voltage source 41 that outputs the voltage of the overcurrent detection threshold. The overcurrent detection circuit also has a variable resistance circuit 70 that converts the sense current supplied to the OC terminal from the sense emitter terminal of the IGBT 13 into a current detection signal Vsense, and a phase identification circuit 50. Note that the phase identification circuit 50 is the same as that shown in FIG. 2, so a detailed description thereof will be omitted here.

The variable resistance circuit 70 has current sense resistors Rs1, Rs2, and Rs3 and transmission gates 71, 72, and 73. One terminal of the current sense resistor Rs1 is connected to the OC terminal and the input terminal of the transmission gate 71. The other terminal of the current sense resistor Rs1 is connected to one terminal of the current sense resistor Rs2 and the input terminal of the transmission gate 72. The other terminal of the current sense resistor Rs2 is connected to one terminal of the current sense resistor Rs3 and the input terminal of the transmission gate 73, and the other terminal of the current sense resistor Rs3 is connected to the ground line. The output terminals of the transmission gates 71, 72, and 73 are connected to the inverting input terminal of the comparator 40.

In the control IC 24a for the X phase, the phase identification circuit 50 outputs an identification signal Six at H level, so that the transmission gate 71 in the variable resistance circuit 70 is controlled to be conductive. At this time, the other identification signals Siy and Siz are at L level, so that the transmission gates 72 and 73 are non-conductive.

Therefore, the current detection signal Vsense converted to a voltage by the current sense resistors Rs1, Rs2, and Rs3 is supplied to the inverting input terminal of the comparator 40 without being attenuated because the voltage division ratio is zero.

At this time, in the overcurrent detection circuit of the Y-phase control IC 26, the phase identification circuit 50 outputs the identification signal Siy, so in the variable resistance circuit 70, the transmission gate 72 is controlled to be conductive. As a result, in the variable resistance circuit 70, the voltage converted by the current sense resistors Rs1-Rs3 is divided by the voltage division ratio of the current sense resistor Rs1 to the current sense resistors Rs2 and Rs3, and the resulting voltage is output as the current detection signal Vsense, which is supplied to the inverting input terminal of the comparator 40.

In the overcurrent detection circuit of the Z-phase control IC 28, the phase identification circuit 50 outputs an H-level identification signal Siz, so that the transmission gate 73 in the variable resistance circuit 70 is controlled to be conductive. As a result, in the variable resistance circuit 70, the voltage converted by the current sense resistors Rs1-Rs3 is divided by the voltage division ratio of the current sense resistors Rs1, Rs2 and the current sense resistor Rs3, and the resulting voltage is output as the current detection signal Vsense, which is supplied to the inverting input terminal of the comparator 40.

In this way, when IGBTs 13, 17, and 21 are turned on, the potentials of the emitter terminals rise differently, but by compensating for this rise with variable resistance circuit 70, each overcurrent detection circuit detects an overcurrent state at the same current value.

The above semiconductor module 10 has a P terminal and an N terminal for connecting an external power supply 2 on one side of the package, but next we will explain the application to a semiconductor module that has power supply terminals for connecting an external power supply 2 on opposing sides of the package. In this case, the distance from the power supply terminal to which the power supply 2 is connected to the X-phase, Y-phase, and Z-phase IGBTs 13, 17, and 21 will change depending on whether the external power supply 2 is connected to the power supply terminal on one side or the other side.

FIG. 4 is a circuit diagram showing another example of the configuration of a semiconductor module according to an embodiment of the present invention.
4 has a positive power supply terminal P1 (hereinafter referred to as the P1 terminal) and a negative power supply terminal N1 (hereinafter referred to as the N1 terminal) on one side of the package (the left side of the figure), and a positive power supply terminal P2 (hereinafter referred to as the P2 terminal) and a negative power supply terminal N2 (hereinafter referred to as the N2 terminal) on the right side of the package.

Inside the semiconductor module 10a, the P1 terminal and the P2 terminal are connected by a line, and the N1 terminal and the N2 terminal are connected by an N line. Between the N1 terminal and the N2 terminal, the X-phase, Y-phase, and Z-phase IGBTs 13, 17, and 21 are arranged in this order along the N line from the N1 terminal. Therefore, on the N line, a parasitic inductance Lxp of the wiring of the printed circuit board exists between the N1 terminal and the emitter terminal of the X-phase IGBT 13. On the N line between the N1 terminal and the emitter terminal of the Y-phase IGBT 17, parasitic inductances Lxp and Lyp exist, and on the N line between the N1 terminal and the emitter terminal of the Z-phase IGBT 21, parasitic inductances Lxp, Lyp, and Lzp exist.

The semiconductor module 10a also has a P3 terminal (power supply connection terminal) on the side where the P1 terminal is located. This P3 terminal is the terminal to which the positive terminal of the power supply 2 is connected when the power supply 2 is connected to the P1 terminal and the N1 terminal. Therefore, when the power supply 2 is connected to the P2 terminal and the N2 terminal on the opposite side, nothing is connected to this P3 terminal.

The P3 terminal is connected to one terminal of resistor R21, the other terminal of resistor R21 is connected to one terminal of resistor R22, and the other terminal of resistor R22 is connected to the N line to which the N1 terminal is connected. The common connection point of resistors R21 and R22 is connected to the Vp3 terminals of the lower arm control ICs 33, 34, and 35. As a result, when the control ICs 33, 34, and 35 receive voltage Vp3, which is the divided voltage of power supply 2, from the voltage divider circuit of resistors R21 and R22, they determine that power supply 2 is connected to the P1 terminal and the N1 terminal.

The lower arm control ICs 33, 34, and 35 have Ph1 and Ph2 terminals that identify whether they are X-phase, Y-phase, or Z-phase. In the example shown, control IC 33 identifies itself as X-phase because neither Ph1 nor Ph2 terminals are connected to the ground line. Control IC 34 identifies itself as Y-phase because the Ph1 terminal is connected to the ground line, and control IC 35 identifies itself as Z-phase because the Ph2 terminal is connected to the ground line.

Next, we will explain the operation of the overcurrent detection circuit based on the condition of whether the power supply 2 is connected to the P1 and N1 terminals or the P2 and N2 terminals, and the condition of whether the lower arm control ICs 33, 34, and 35 are X-phase, Y-phase, or Z-phase.

Figure 5 is a circuit diagram showing an example of an overcurrent detection circuit of a control IC in a semiconductor module according to a third embodiment. In this Figure 5, components that are the same as or equivalent to those shown in Figure 2 are given the same reference numerals and detailed description thereof is omitted. In addition, the overcurrent detection circuits of the lower arm control ICs 33, 34, and 35 have the same circuit configuration, so in Figure 5, the X-phase control IC 33 will be described as a representative. In the semiconductor module according to the third embodiment, the Y-phase IGBT 17 is disposed closer to the X-phase IGBT 13, and therefore, there is a detection variation in the overcurrent detection circuit even when the power source 2 is connected to the P1 terminal and when it is connected to the P2 terminal.

The overcurrent detection circuit of the control IC 33 of the semiconductor module according to the third embodiment has a current sense resistor Rs that receives a sense current supplied from the sense emitter terminal of the IGBT 13 at the OC terminal and converts it into a current detection signal Vsense, and a comparator 40 for overcurrent detection. The overcurrent detection circuit also has a phase identification circuit 50, a variable reference voltage circuit 60a, a power supply connection terminal voltage detection circuit 80, and a selection signal generation circuit 90 to generate a reference voltage for the comparator 40.

The power supply connection terminal voltage detection circuit 80 has resistors R31 and R32 and a comparator 81. One terminal of the resistor R31 is connected to the Vdd power supply line, and the other terminal of the resistor R31 is connected to one terminal of the resistor R32 and the inverting input terminal of the comparator 81. The other terminal of the resistor R32 is connected to the ground line. The non-inverting input terminal of the comparator 81 is connected to the Vp3 terminal of the control IC 33, and the Vp3 terminal is connected to the connection point of the resistors R1 and R2, which divide the voltage of the external power supply 2.

The selection signal generating circuit 90 has an inverter circuit 91, AND circuits 92-97, and OR circuits 98 and 99. The input terminal of the inverter circuit 91 is connected to the output terminal of the comparator 81 of the power supply connection terminal voltage detection circuit 80 and one of the input terminals of the AND circuits 92-94, and the output terminal of the inverter circuit 91 is connected to one of the input terminals of the AND circuits 95-97. The other input terminals of the AND circuits 92 and 95 are connected to the output terminal of the AND circuit 53 of the phase identification circuit 50, the other input terminals of the AND circuits 93 and 96 are connected to the output terminal of the AND circuit 54 of the phase identification circuit 50, and the other input terminals of the AND circuits 94 and 97 are connected to the output terminal of the AND circuit 55 of the phase identification circuit 50. One input terminal of the OR circuit 98 is connected to the output terminal of the AND circuit 94, and the other input terminal of the OR circuit 98 is connected to the output terminal of the AND circuit 95. One input terminal of the OR circuit 99 is connected to the output terminal of the AND circuit 92, and the other input terminal of the OR circuit 99 is connected to the output terminal of the AND circuit 97. The output terminal of the OR circuit 99 outputs a selection signal SH, the output terminal of the AND circuit 96 outputs a selection signal SM1, the output terminal of the OR circuit 98 outputs a selection signal SL, and the output terminal of the AND circuit 93 outputs a selection signal SM2.

The variable reference voltage circuit 60a has resistors R11, R12, R13, R14, and R15, and transmission gates 61, 62, 63, and 64. One terminal of the resistor R11 is connected to the Vdd power supply line, and the other terminal of the resistor R11 is connected to one terminal of the resistor R12 and the input terminal of the transmission gate 64. The other terminal of the resistor R12 is connected to one terminal of the resistor R13 and the input terminal of the transmission gate 63. The other terminal of the resistor R13 is connected to one terminal of the resistor R14 and the input terminal of the transmission gate 62. The other terminal of the resistor R14 is connected to one terminal of the resistor R15 and the input terminal of the transmission gate 61, and the other terminal of the resistor R15 is connected to the ground line. The output terminals of the transmission gates 61, 62, 63, and 64 are connected to the non-inverting input terminal of the comparator 40. The selection signals SL, SM2, SM1, and SH output by the selection signal generation circuit 90 are input to the control input terminals of the transmission gates 61, 62, 63, and 64.

As shown in FIG. 4, when the positive terminal of the power supply 2 is connected to the P3 terminal of the semiconductor module 10a, a voltage Vp3 of a predetermined value obtained by dividing the voltage of the power supply 2 is input to the power supply connection terminal voltage detection circuit 80. This voltage Vp3 is set higher than the reference voltage output by resistors R31 and R32, so the comparator 81 outputs an H-level signal. On the other hand, when the positive terminal of the power supply 2 is not connected to the P3 terminal of the semiconductor module 10a, a voltage Vp3 of approximately ground level is input to the power supply connection terminal voltage detection circuit 80. At this time, the comparator 81 outputs an L-level signal.

When the control IC 33 is an X-phase, the phase identification circuit 50 outputs an H-level identification signal Six. When the control IC 34 is a Y-phase, the phase identification circuit 50 outputs an H-level identification signal Siy, and when the control IC 35 is a Z-phase, the phase identification circuit 50 outputs an H-level identification signal Siz.

Here, when the power supply connection terminal voltage detection circuit 80 outputs a high-level signal and the phase identification circuit 50 outputs a high-level identification signal Six, only the AND circuit 94 in the selection signal generation circuit 90 outputs a high-level signal. The high-level signal output by the AND circuit 94 is input to the OR circuit 98, which outputs a high-level selection signal SL and controls the conduction of the transmission gate 61 of the variable reference voltage circuit 60a. At this time, the other identification signals Siy and Siz are low-level, so the AND circuits 92 and 93 output low-level signals, and the AND circuits 95, 96, and 97 also receive a low-level signal from the inverter circuit 91 at one of their input terminals and output low-level signals. Therefore, the AND circuits 93 and 96 and the OR circuit 99 output low-level selection signals SM2, SM1, and SH, so that the transmission gates 62, 63, and 64 that receive the low-level selection signals SM2, SM1, and SH at their control input terminals are controlled to be non-conductive. As a result, the variable reference voltage circuit 60a provides the voltage Vref1, which is the voltage Vdd divided by resistors R11-R14 and resistor R15, to the non-inverting input terminal of the comparator 40 as a reference voltage.

In the control IC 34 for the Y phase, the phase identification circuit 50 outputs an identification signal Siy, and therefore the AND circuit 93 of the selection signal generation circuit 90 outputs an H-level selection signal SM2. As a result, in the variable reference voltage circuit 60a, the voltage Vref2 obtained by dividing the voltage Vdd by the resistors R11-R13 and the resistors R14 and R15 is provided to the non-inverting input terminal of the comparator 40 as a reference voltage. In the control IC 35 for the Z phase, the phase identification circuit 50 outputs an identification signal Siz, and therefore the AND circuit 92 of the selection signal generation circuit 90 outputs an H-level signal, and the OR circuit 99 outputs an H-level selection signal SH. As a result, in the variable reference voltage circuit 60a, the voltage Vref4 obtained by dividing the voltage Vdd by the resistors R11 and the resistors R12-R15 is provided to the non-inverting input terminal of the comparator 40 as a reference voltage.

As described above, in the X-phase overcurrent detection circuit, the reference voltage of the comparator 40 is set to a small voltage Vref1 in response to the small increase in the emitter potential of IGBT 13. Similarly, in the Y-phase and Z-phase overcurrent detection circuits, the reference voltage of the comparator 40 is set to successively larger voltages Vref2 and Vref4 in response to the successively larger increase in the emitter potential of IGBTs 17 and 21. Therefore, the X-phase, Y-phase, and Z-phase overcurrent detection circuits detect an overcurrent state at the same current value.

Next, when the power supply 2 is connected to the P2 and N2 terminals of the semiconductor module 10a and nothing is connected to the P3 terminal, a voltage Vp3 of 0 volts (V) is input to the power supply connection terminal voltage detection circuit 80, and the comparator 81 outputs an L-level signal. At this time, in the selection signal generation circuit 90, the inverter circuit 91 receives the L-level signal and outputs an H-level signal, and the AND circuits 95-97 input an H-level signal to one of their input terminals, so that they output an output signal with a logical level according to the other input terminal.

That is, when the selection signal generating circuit 90 receives an H-level identification signal Six from the phase identification circuit 50, the AND circuit 97 outputs an H-level signal, and the OR circuit 99 outputs an H-level selection signal SH. As a result, in the variable reference voltage circuit 60a, the transmission gate 64 is controlled to be conductive, and the voltage Vref4 is set as the reference voltage. Also, when the selection signal generating circuit 90 receives an H-level identification signal Siy from the phase identification circuit 50, the AND circuit 96 outputs an H-level selection signal SM1. As a result, in the variable reference voltage circuit 60a, the transmission gate 63 is controlled to be conductive, and the voltage Vref3 is set as the reference voltage. When the selection signal generating circuit 90 receives an H-level identification signal Siz from the phase identification circuit 50, the AND circuit 95 outputs an H-level signal, and the OR circuit 98 outputs an H-level selection signal SL. As a result, in the variable reference voltage circuit 60a, the transmission gate 61 is controlled to be conductive, and the voltage Vref1 is set as the reference voltage.

When the power source 2 is connected to the P2 terminal and the N2 terminal of the semiconductor module 10a, the rise in the emitter potential of the Z-phase IGBT 21, which is closest to the N2 terminal, is small, and the rise in the emitter potential of the X-phase IGBT 13, which is the furthest from the N2 terminal, is large. In this case, the variable reference voltage circuit 60 sets the reference voltage to increase in the order of Z-phase, Y-phase, and X-phase, so that the overcurrent detection circuits of the X-phase, Y-phase, and Z-phase detect the overcurrent state at the same current value. Note that, although the description has been given assuming that the Y-phase IGBT 17 is disposed closer to the X-phase IGBT 13, if the Y-phase IGBT 17 is disposed closer to the Z-phase IGBT 21, in the Y-phase control IC 34, the selection signal generation circuit 90 may be changed so that the AND circuit 93 outputs the H-level selection signal SM2.

Figure 6 is a circuit diagram showing an example of an overcurrent detection circuit of a control IC included in a semiconductor module according to the fourth embodiment. The overcurrent detection circuit of the fourth embodiment changes the current detection signal Vsense applied to the comparator 40, whereas the overcurrent detection circuit of the second embodiment changes the reference voltage applied to the comparator 40. In this Figure 6, components that are the same as or equivalent to those shown in Figures 3 and 5 are given the same reference numerals and detailed descriptions thereof are omitted. In this Figure 6, the X-phase control IC 33a of the fourth embodiment is also shown, and the Y-phase and Z-phase control ICs will be described with reference to this X-phase control IC 33a.

The overcurrent detection circuit of the fourth embodiment has a comparator 40 for detecting overcurrent and a reference voltage source 41 that outputs the voltage of the overcurrent detection threshold. The overcurrent detection circuit also has a variable resistance circuit 70a that converts the sense current supplied to the OC terminal from the sense emitter terminal of the IGBT 13 into a current detection signal Vsense.

The variable resistance circuit 70a has current sense resistors Rs1, Rs2, Rs3, and Rs4, and transmission gates 71, 72, 73, and 74. One terminal of the current sense resistor Rs1 is connected to the OC terminal and the input terminal of the transmission gate 71. The other terminal of the current sense resistor Rs1 is connected to one terminal of the current sense resistor Rs2 and the input terminal of the transmission gate 72. The other terminal of the current sense resistor Rs2 is connected to one terminal of the current sense resistor Rs3 and the input terminal of the transmission gate 73. The other terminal of the current sense resistor Rs3 is connected to one terminal of the current sense resistor Rs4 and the input terminal of the transmission gate 74, and the other terminal of the current sense resistor Rs4 is connected to the ground line. The output terminals of the transmission gates 71, 72, 73, and 74 are connected to the inverting input terminal of the comparator 40.

Here, we will explain the case where the positive terminal of the power supply 2 is connected to the P3 terminal of the semiconductor module 10a. In this case, the potential rise is smallest at the emitter terminal of the X-phase IGBT 13, which is closest to the N1 terminal, and the potential rise is largest at the emitter terminal of the Z-phase IGBT 21. When the power supply 2 is connected to the P3 terminal, the comparator 81 of the power supply connection terminal voltage detection circuit 80 outputs an H-level signal.

In the phase identification circuit 50, the Ph1 and Ph2 terminals of the X-phase control IC 33a are at the H level, so the AND circuit 55 outputs an H-level identification signal Six, and the identification signals Siy and Siz are at the L level.

Therefore, in the selection signal generation circuit 90, the AND circuit 94 outputs an H-level signal, and the OR circuit 98 outputs an H-level selection signal SL, controlling the conduction of the transmission gate 71 of the variable resistance circuit 70a. At this time, since the other identification signals Siy and Siz are at L level, the selection signals SM2, SM1, and SH output by the AND circuits 93 and 96 and the OR circuit 99 of the selection signal generation circuit 90 are at L level, and the transmission gates 72, 73, and 74 are non-conductive.

Therefore, the current detection signal Vsense, which is converted to a voltage by the current sense resistors Rs1, Rs2, Rs3, and Rs4, is supplied to the inverting input terminal of the comparator 40 without being attenuated because the voltage division ratio is zero.

At this time, in the overcurrent detection circuit of the Y-phase control IC 34, the phase identification circuit 50 outputs the identification signal Siy, so that in the selection signal generation circuit 90, the AND circuit 93 outputs the H-level selection signal SM2, and in the variable resistance circuit 70a, the transmission gate 72 is controlled to be conductive. As a result, in the variable resistance circuit 70a, the voltage converted by the current sense resistors Rs1-Rs4 is divided by the voltage division ratio of the current sense resistors Rs1 and Rs2-Rs4, and the resulting voltage is output as the current detection signal Vsense, which is supplied to the inverting input terminal of the comparator 40.

In the overcurrent detection circuit of the Z-phase control IC 35, the phase identification circuit 50 outputs an H-level identification signal Siz, so in the selection signal generation circuit 90, the AND circuit 92 outputs an H-level signal and the OR circuit 99 outputs an H-level selection signal SH. As a result, in the variable resistance circuit 70a, the transmission gate 74 is controlled to be conductive, so that the voltage converted by the current sense resistors Rs1-Rs4 is divided by the voltage division ratio of the current sense resistors Rs1-Rs3 and Rs4, and the voltage is output as the current detection signal Vsense and supplied to the inverting input terminal of the comparator 40.

As described above, in the X-phase overcurrent detection circuit, which is closest to the N1 terminal, the voltage division ratio of the current detection signal Vsense supplied to the comparator 40 is set to zero in response to the small increase in the emitter potential of the IGBT 13. In the Y-phase and Z-phase overcurrent detection circuits, which are successively farther away from the N1 terminal, the voltage division ratio of the current detection signal Vsense is set to successively larger values. For this reason, the X-phase, Y-phase, and Z-phase overcurrent detection circuits detect an overcurrent state at the same current value.

Next, a case where the power supply 2 is connected to the P2 terminal and the N2 terminal of the semiconductor module 10a will be described. In this case, the potential rise is smallest at the emitter terminal of the Z-phase IGBT 21, which is closest to the N2 terminal, and the potential rise is largest at the emitter terminal of the X-phase IGBT 13. Since the power supply 2 is not connected to the P3 terminal, the comparator 81 of the power supply connection terminal voltage detection circuit 80 outputs an L-level signal to disable the AND circuits 92-94 of the selection signal generation circuit 90 and enable the AND circuits 95-97.

When the selection signal generating circuit 90 receives the identification signal Six from the phase identification circuit 50, the AND circuit 97 outputs an H-level signal, and the OR circuit 99 outputs an H-level selection signal SH, controlling the conduction of the transmission gate 74 of the variable resistance circuit 70a. As a result, in the variable resistance circuit 70a, the voltage converted by the current sense resistors Rs1-Rs4 is divided by the voltage division ratio of the current sense resistors Rs1-Rs3 and the current sense resistor Rs4, and the resulting voltage is output as the current detection signal Vsense, which is supplied to the inverting input terminal of the comparator 40.

At this time, in the overcurrent detection circuit of the Y-phase control IC 34, the phase identification circuit 50 outputs the identification signal Siy, so in the selection signal generation circuit 90, the AND circuit 96 outputs the H-level selection signal SM1, and in the variable resistance circuit 70a, the transmission gate 73 is controlled to be conductive. As a result, in the variable resistance circuit 70a, the voltage converted by the current sense resistors Rs1-Rs4 is divided by the voltage division ratio of the current sense resistors Rs1, Rs2 and the current sense resistors Rs3, Rs4, and the resulting voltage is output as the current detection signal Vsense, which is supplied to the inverting input terminal of the comparator 40.

In the overcurrent detection circuit of the Z-phase control IC 35, the phase identification circuit 50 outputs the identification signal Siz, so in the selection signal generation circuit 90, the AND circuit 95 outputs an H-level signal, and the OR circuit 98 outputs an H-level selection signal SL, and in the variable resistance circuit 70a, the transmission gate 71 is controlled to be conductive. As a result, the current detection signal Vsense converted to a voltage by the current sense resistors Rs1-Rs4 is supplied to the inverting input terminal of the comparator 40 without being attenuated.

Figure 7 is a circuit diagram showing an example of an overcurrent detection circuit of a control IC in a semiconductor module according to the fifth embodiment. The overcurrent detection circuit of the fifth embodiment varies the reference voltage applied to the comparator 40 only for the X-phase and Z-phase depending on whether the power supply 2 is connected to the P1 terminal or the P2 terminal. In Figure 7, components that are the same as or equivalent to those shown in Figure 5 are given the same reference numerals and detailed description thereof is omitted. Figure 7 shows the X-phase control IC 33b of the fifth embodiment, and the Y-phase and Z-phase control ICs will be described with reference to this X-phase control IC 33b.

The control IC 33b of the semiconductor module according to the fifth embodiment includes a selection signal generating circuit 90a and a variable reference voltage circuit 60b that are simplified versions of the selection signal generating circuit 90 and the variable reference voltage circuit 60a of the semiconductor module according to the third embodiment.

In the selection signal generating circuit 90a, the input terminal of the inverter circuit 91 is connected to the output terminal of the power supply connection terminal voltage detection circuit 80 and one of the input terminals of the AND circuits 92 and 94, and the output terminal of the inverter circuit 91 is connected to one of the input terminals of the AND circuits 95 and 97. The other input terminals of the AND circuits 92 and 95 are connected to the output terminal of the AND circuit 53 of the phase identification circuit 50, and the other input terminals of the AND circuits 94 and 97 are connected to the output terminal of the AND circuit 55 of the phase identification circuit 50. One input terminal of the OR circuit 98 is connected to the output terminal of the AND circuit 94, and the other input terminal of the OR circuit 98 is connected to the output terminal of the AND circuit 55. One input terminal of the OR circuit 99 is connected to the output terminal of the AND circuit 92, and the other input terminal of the OR circuit 99 is connected to the output terminal of the AND circuit 97. The output terminal of the OR circuit 99 outputs the selection signal SH, and the output terminal of the OR circuit 98 outputs the selection signal SL.

The variable reference voltage circuit 60b has resistors R11, R12, R13, and R14, and transmission gates 61, 62, and 63. One terminal of the resistor R11 is connected to the line of the Vdd power supply, and the other terminal of the resistor R11 is connected to one terminal of the resistor R12 and the input terminal of the transmission gate 63. The other terminal of the resistor R12 is connected to one terminal of the resistor R13 and the input terminal of the transmission gate 62. The other terminal of the resistor R13 is connected to one terminal of the resistor R14 and the input terminal of the transmission gate 61, and the other terminal of the resistor R14 is connected to the ground line. The output terminals of the transmission gates 61, 62, and 63 are connected to the non-inverting input terminal of the comparator 40. The selection signal SH output by the selection signal generation circuit 90 is input to the control input terminal of the transmission gate 63. The identification signal Siy output by the phase identification circuit 50 is input to the control input terminal of the transmission gate 62. The selection signal SL output by the selection signal generation circuit 90 is input to the control input terminal of the transmission gate 61.

Here, the positive terminal of the power supply 2 is connected to the P3 terminal of the semiconductor module 10a, and a voltage Vp3 of a predetermined value obtained by dividing the voltage of the power supply 2 is input to the power supply connection terminal voltage detection circuit 80. In this case, the power supply connection terminal voltage detection circuit 80 outputs an H-level signal.

When the phase identification circuit 50 outputs an H-level identification signal Six, the selection signal generation circuit 90a causes only the AND circuit 94 to output an H-level signal, and the OR circuit 98 to output an H-level selection signal SL, thereby controlling the conduction of the transmission gate 61 of the variable reference voltage circuit 60b. Therefore, in the variable reference voltage circuit 60b, the voltage Vref11 obtained by dividing the voltage Vdd by resistors R11-R13 and resistor R13 is supplied to the non-inverting input terminal of the comparator 40 as a reference voltage.

In the Y-phase control IC 34, the phase identification circuit 50 outputs an identification signal Siy, which controls the conduction of the transmission gate 62. As a result, in the variable reference voltage circuit 60b, the voltage Vref12 obtained by dividing the voltage Vdd by the resistors R11, R12 and the resistors R13, R14 is supplied to the non-inverting input terminal of the comparator 40 as a reference voltage. In the Z-phase control IC 35, the phase identification circuit 50 outputs the identification signal Siz, so that in the selection signal generation circuit 90a, the AND circuit 92 outputs an H-level signal, and the OR circuit 99 outputs an H-level selection signal SH. As a result, in the variable reference voltage circuit 60b, the transmission gate 63 is controlled to be conductive, and the voltage Vref13 obtained by dividing the voltage Vdd by the resistors R11 and the resistors R12-R13 is supplied to the non-inverting input terminal of the comparator 40 as a reference voltage.

On the other hand, when the power supply 2 is connected to the P2 and N2 terminals of the semiconductor module 10a and nothing is connected to the P3 terminal, a voltage Vp3 of 0V is input to the power supply connection terminal voltage detection circuit 80, and the comparator 81 outputs an L-level signal. At this time, in the selection signal generation circuit 90a, the inverter circuit 91 outputs an H-level signal upon receiving the L-level signal, and the AND circuits 95 and 97, which input an H-level signal to one of their input terminals, become effective.

Therefore, when the phase identification circuit 50 receives an H-level identification signal Six, the AND circuit 97 outputs an H-level signal, and the OR circuit 99 outputs an H-level selection signal SH. As a result, in the variable reference voltage circuit 60b, the transmission gate 63 is controlled to be conductive, and the voltage Vref13 is set as the reference voltage. Also, when the phase identification circuit 50 receives an H-level identification signal Siz, the AND circuit 95 outputs an H-level signal, and the OR circuit 98 outputs an H-level selection signal SH. As a result, in the variable reference voltage circuit 60b, the transmission gate 61 is controlled to be conductive, and the voltage Vref11 is set as the reference voltage. Note that in the overcurrent detection circuit of the Y-phase control IC 34, there is no change in the voltage output by the variable reference voltage circuit 60b as the reference voltage, and it remains at voltage Vref12.

Figure 8 is a circuit diagram showing an example of an overcurrent detection circuit of a control IC included in a semiconductor module according to the sixth embodiment. The overcurrent detection circuit of the sixth embodiment changes the current detection signal Vsense applied to the comparator 40 depending on whether the power supply 2 is connected to the P1 terminal or the P2 terminal. In Figure 8, components that are the same as or equivalent to those shown in Figures 6 and 7 are given the same reference numerals and detailed descriptions thereof are omitted. Figure 8 shows the X-phase control IC 33c of the sixth embodiment, and the Y-phase and Z-phase control ICs will be described with reference to this X-phase control IC 33c.

The control IC 33c of the semiconductor module according to the sixth embodiment includes a selection signal generating circuit 90a and a variable resistance circuit 70b that are simplified versions of the selection signal generating circuit 90 and the variable resistance circuit 70a of the semiconductor module according to the fourth embodiment.

The variable resistance circuit 70b has current sense resistors Rs1, Rs2, and Rs3, and transmission gates 71, 72, and 73. One terminal of the current sense resistor Rs1 is connected to the OC terminal and the input terminal of the transmission gate 71. The other terminal of the current sense resistor Rs1 is connected to one terminal of the current sense resistor Rs2 and the input terminal of the transmission gate 72. The other terminal of the current sense resistor Rs2 is connected to one terminal of the current sense resistor Rs3 and the input terminal of the transmission gate 73, and the other terminal of the current sense resistor Rs3 is connected to the ground line. The output terminals of the transmission gates 71, 72, and 73 are connected to the inverting input terminal of the comparator 40.

Here, we will explain the case where the positive terminal of the power supply 2 is connected to the P3 terminal of the semiconductor module 10a. At this time, the power supply connection terminal voltage detection circuit 80 outputs an H level signal.

The phase identification circuit 50 of the X-phase control IC 33c outputs an H-level identification signal Six and L-level identification signals Siy and Siz. The selection signal generation circuit 90a outputs an H-level selection signal SL and an L-level selection signal SL. Therefore, in the variable resistance circuit 70b, only the transmission gate 71 is controlled to be conductive, so that the current detection signal Vsense converted to a voltage by the current sense resistors Rs1, Rs2, and Rs3 is supplied to the inverting input terminal of the comparator 40 without being attenuated.

In the overcurrent detection circuit of the Y-phase control IC 34, the phase identification circuit 50 outputs the identification signal Siy, so that the transmission gate 72 in the variable resistance circuit 70b is controlled to be conductive. As a result, in the variable resistance circuit 70b, the voltage converted by the current sense resistors Rs1-Rs3 is divided by the voltage division ratio of the current sense resistor Rs1 to the current sense resistors Rs2 and Rs3, and the resulting voltage is output as the current detection signal Vsense, which is supplied to the inverting input terminal of the comparator 40.

In the overcurrent detection circuit of the Z-phase control IC 35, the phase identification circuit 50 outputs the identification signal Siz, so the selection signal generation circuit 90a outputs an H-level selection signal SH. As a result, in the variable resistance circuit 70b, the transmission gate 73 is controlled to be conductive, so that the voltage converted by the current sense resistors Rs1-Rs3 is divided by the voltage division ratio of the current sense resistors Rs1, Rs2 and the current sense resistor Rs3, and the resulting voltage is output as the current detection signal Vsense and supplied to the inverting input terminal of the comparator 40.

Next, a case where the power supply 2 is connected to the P2 terminal and the N2 terminal of the semiconductor module 10a will be described. At this time, since the power supply 2 is not connected to the P3 terminal, the power supply connection terminal voltage detection circuit 80 outputs an L-level signal to disable the AND circuits 92 and 94 of the selection signal generation circuit 90a and enable the AND circuits 95 and 97.

Therefore, the selection signal generating circuit 90a receives the identification signal Six from the phase identification circuit 50 and outputs an H-level selection signal SH, controlling the conduction of the transmission gate 73 of the variable resistance circuit 70b. As a result, in the variable resistance circuit 70b, the voltage converted by the current sense resistors Rs1-Rs3 is divided by the voltage division ratio of the current sense resistors Rs1, Rs2 and the current sense resistor Rs3, and the resulting voltage is output as the current detection signal Vsense, which is supplied to the inverting input terminal of the comparator 40.

At this time, in the overcurrent detection circuit of the Y-phase control IC 34, the phase identification circuit 50 outputs the identification signal Siy, so that the variable resistance circuit 70b maintains the conduction control of the transmission gate 72.

In the overcurrent detection circuit of the Z-phase control IC 35, the phase identification circuit 50 outputs the identification signal Siz, so the selection signal generation circuit 90a outputs an H-level selection signal SL, and the variable resistance circuit 70b controls the conduction of the transmission gate 71. As a result, the current detection signal Vsense converted to a voltage by the current sense resistors Rs1-Rs3 is supplied to the inverting input terminal of the comparator 40 without being attenuated.

In the above embodiment, an example has been described in which an IGBT is used as the power semiconductor element of the semiconductor module 10, 10a. However, the power semiconductor element may also be a power transistor or a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

1 Motor 2 Power supply 10, 10a Semiconductor module 11, 13, 15, 17, 19, 21 IGBT
12, 14, 16, 18, 20, 22 FWD
23, 24, 24a, 25-28, 33, 33a, 33b, 33c, 34, 35 Control IC
29-32 Power supply 40 Comparator 41 Reference voltage source 50 Phase identification circuit 51, 52 Inverter circuit 53-55 AND circuit 60, 60a, 60b Variable reference voltage circuit 61-64 Transmission gate 70, 70a, 70b Variable resistance circuit 71-74 Transmission gate 80 Power supply connection terminal voltage detection circuit 81 Comparator 90, 90a Selection signal generation circuit 91 Inverter circuit 92-97 AND circuit 98, 99 OR circuit Lxp, Lyp, Lzp Parasitic inductance N, N1, N2 Negative power supply terminal P, P1, P2 Positive power supply terminal P3 Power supply connection terminal R1, R2, R11-R15, R21, R22, R31, R32 Resistor Rs, Rs1-Rs4 Current sense resistor

Claims (10)

a first negative power supply terminal and a second negative power supply terminal provided on opposite sides of the package to which a power supply is selectively connected;
a plurality of power semiconductor elements arranged along a line interconnecting the first negative power supply terminal and the second negative power supply terminal, the power semiconductor elements having main electrodes connected to the line;
A plurality of control ICs for driving the power semiconductor elements;
a power supply connection terminal provided on the same side of the package as the first negative power supply terminal and to which a voltage of the power supply is applied,
The control IC includes:
a power supply connection terminal voltage detection circuit that detects whether or not a voltage of the power supply is applied to the power supply connection terminal;
a phase identification circuit that identifies a position along the line corresponding to a distance from the first negative power supply terminal or the second negative power supply terminal of the power semiconductor device to be driven;
a selection signal generating circuit that generates a selection signal based on a detection result of the power supply connection terminal voltage detection circuit and an identification result of the phase identification circuit;
a current sense resistor that receives a sense current proportional to a main current of the power semiconductor device, converts the sense current into a voltage, and outputs a current detection signal;
a variable reference voltage source having a plurality of voltage sources, one of the voltage sources being selected by the selection signal in response to the selection signal and outputting the selected voltage as a reference voltage;
a comparator for comparing the current sense signal with the selected reference voltage;
A semiconductor module comprising an overcurrent detection circuit having the above-mentioned configuration. 2. The semiconductor module according to claim 1 , wherein the selection signal generating circuit reverses the order of the arrangement positions of the power semiconductor elements identified by the phase identifying circuit in accordance with a detection result of the power supply connection terminal voltage detecting circuit. 2. The semiconductor module according to claim 1, wherein the selection signal generated by the selection signal generation circuit selects, in the variable reference voltage source, the voltage sources that output increasing voltages in order of their arrangement positions from the first negative power supply terminal identified by the phase identification circuit when the power supply connection terminal voltage detection circuit detects the application of the power supply voltage, and selects, in the variable reference voltage source, the voltage sources that output increasing voltages in order of their arrangement positions from the second negative power supply terminal identified by the phase identification circuit when the power supply connection terminal voltage detection circuit does not detect the application of the power supply voltage. 2. The semiconductor module according to claim 1, wherein first to third power semiconductor elements are arranged along the line from a side of the first negative power supply terminal, the variable reference voltage sources of the first to third control ICs of the first to third power semiconductor elements have four voltage sources that output different reference voltages, and the selection signal generation circuit selects the three voltage sources that output increasing voltages in order of their arrangement position from the first negative power supply terminal when the power supply connection terminal voltage detection circuit detects application of the power supply voltage, and selects the three voltage sources that output increasing voltages in order of their arrangement position from the second negative power supply terminal when the power supply connection terminal voltage detection circuit does not detect application of the power supply voltage. 2. The semiconductor module according to claim 1, wherein first, second and third power semiconductor elements are arranged along the line from a side of the first negative power supply terminal, the variable reference voltage sources of the first, second and third control ICs of the first, second and third power semiconductor elements have three voltage sources which output different reference voltages, and the selection signal generation circuit of the first control IC selects the voltage source which outputs the highest voltage and the selection signal generation circuit of the third control IC selects the voltage source which outputs the lowest voltage when the power supply connection terminal voltage detection circuit detects application of a voltage of the power supply, and when the power supply connection terminal voltage detection circuit does not detect application of a voltage of the power supply, the selection signal generation circuit of the third control IC selects the voltage source which outputs the highest voltage and the selection signal generation circuit of the first control IC selects the voltage source which outputs the lowest voltage, and the selection signal generation circuit of the second control IC always selects the voltage source which outputs an intermediate voltage. a first negative power supply terminal and a second negative power supply terminal provided on opposite sides of the package to which power is selectively applied;
a plurality of power semiconductor elements arranged along a line interconnecting the first negative power supply terminal and the second negative power supply terminal, the power semiconductor elements having main electrodes connected to the line;
A plurality of control ICs for driving the power semiconductor elements;
a power supply connection terminal provided on the same side of the package as the first negative power supply terminal and to which a voltage of the power supply is applied,
The control IC includes:
a power supply connection terminal voltage detection circuit that detects whether or not a voltage of the power supply is applied to the power supply connection terminal;
a phase identification circuit that identifies a placement position along the line corresponding to a distance from the first negative power supply terminal or the second negative power supply terminal of the power semiconductor element to be driven;
a selection signal generating circuit that generates a selection signal based on a detection result of the power supply connection terminal voltage detection circuit and an identification result of the phase identification circuit;
a variable resistor circuit having resistors connected in series, receiving a sense current proportional to a main current of the power semiconductor element, converting the sense current into a voltage, and selecting one of a plurality of divided current detection signals in response to the selection signal to output the selected current detection signal;
A reference voltage source that outputs a reference voltage;
a comparator for comparing the current detection signal with a reference voltage;
A semiconductor module comprising an overcurrent detection circuit having the above-mentioned configuration. 7. The semiconductor module according to claim 6 , wherein the selection signal generating circuit reverses the order of the arrangement positions of the power semiconductor elements identified by the phase identifying circuit in accordance with the detection result of the power supply connection terminal voltage detecting circuit. 7. The semiconductor module according to claim 6, wherein the selection signal generated by the selection signal generation circuit selects, in the variable resistor circuit, the current detection signals with increasing voltage division ratios in the order of arrangement positions from the first negative power supply terminal identified by the phase identification circuit when the power supply connection terminal voltage detection circuit detects the application of the power supply voltage, and selects, in the variable resistor circuit, the current detection signals with increasing voltage division ratios in the order of arrangement positions from the second negative power supply terminal identified by the phase identification circuit when the power supply connection terminal voltage detection circuit does not detect the application of the power supply voltage . 7. The semiconductor module according to claim 6, wherein first to third power semiconductor elements are arranged along said line from a side of said first negative power supply terminal, said variable resistance circuits of first to third control ICs of said first to third power semiconductor elements have four of said current detection signals divided at different voltage division ratios, and said selection signal generation circuit selects said current detection signals with increasing voltage division ratios in order of arrangement position from said first negative power supply terminal when said power supply connection terminal voltage detection circuit detects application of the power supply voltage, and selects said current detection signals with increasing voltage division ratios in order of arrangement position from said second negative power supply terminal when said power supply connection terminal voltage detection circuit does not detect application of the power supply voltage. A first, second and third power semiconductor element are arranged along the line from the side of the first negative power supply terminal, the variable resistance circuits of the first, second and third control ICs of the first, second and third power semiconductor elements have three current detection signals divided at different voltage division ratios, and when the power supply connection terminal voltage detection circuit detects application of a voltage from the power supply, the selection signal generation circuit of the first control IC selects the current detection signal divided at the smallest voltage division ratio and the selection signal of the third control IC selects the current detection signal divided at the smallest voltage division ratio. 7. The semiconductor module of claim 6, wherein the generation circuit selects the current detection signal divided by the largest voltage division ratio, and when the power supply connection terminal voltage detection circuit does not detect the application of voltage from the power supply, the selection signal generation circuit of the third control IC selects the current detection signal divided by the smallest voltage division ratio and the selection signal generation circuit of the first control IC selects the current detection signal divided by the largest voltage division ratio, and the selection signal generation circuit of the second control IC always selects the current detection signal divided by an intermediate voltage division ratio.

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