JP7474061B2 - Interface device, data processing device, cache control method, and program - Google Patents

Description

The present invention relates to an interface device, a data processing device, a cache control method, and a program, and in particular to a shared cache memory.

In recent years, there has been a demand for a single product to realize a variety of functions. For example, in a product that has multiple data processing units, a method is known in which a variety of functions are realized by combining the data processing units to be used depending on the application.

In such a configuration, the processing speed can be improved by making data transfer between data processing units more efficient. For example, Patent Document 1 discloses a method of connecting two processors via a shared cache memory device. According to the method of Patent Document 1, the shared cache memory device monitors data writing by the first processor, and when data requested by the second processor is written, it transfers this data to the second processor.

JP 2012-43031 A

Data processing units are manufactured according to various concepts and by various manufacturers. For this reason, the data processing specifications or constraints, such as the processing unit of data processing, of each data processing unit are often different from each other. For this reason, a device connecting a previous data processing unit to a subsequent data processing unit is often unable to immediately transfer data received from the previous data processing unit to the subsequent data processing unit. Therefore, it is necessary to at least temporarily store the data received from the previous data processing unit in some kind of memory unit. Such processing requires additional circuitry or an additional processing load.

The present invention aims to improve the efficiency of data transfer processing from one processing unit to another in an interface device that connects processing units to each other.

In order to achieve the object of the present invention, for example, an interface device of the present invention has the following arrangement:
1. An interface device that serves as a shared cache for a plurality of processing units, comprising:
a first port that acquires data from a first processing unit included in the plurality of processing units;
a second port that outputs data acquired from the first processing unit to a second processing unit included in the plurality of processing units;
a cache unit that caches data acquired from the first processing unit;
a control unit that controls whether or not to write back the data written to the cache unit to a storage unit different from the cache unit based on information acquired from the second processing unit ,
2. An interface device according to claim 1, wherein the information obtained from said second processing unit indicates that it is not necessary to write back data requested by said second processing unit from said cache means to said storage means .

In an interface device that connects processing units to each other, data transfer processing from one processing unit to another can be made more efficient.

FIG. 1 is a block diagram showing an example of the configuration of a data processing device according to an embodiment. FIG. 1 is a block diagram showing an example of a connection between pre-stage processing and post-stage processing according to an embodiment. FIG. 4 is a diagram for explaining a data transfer operation. FIG. FIG. 1 is a block diagram showing an example of the configuration of an interface device according to an embodiment. FIG. 4 is a block diagram showing an example of the configuration of a cache determinator 412.

The following embodiments are described in detail with reference to the attached drawings. Note that the following embodiments do not limit the invention according to the claims. Although the embodiments describe multiple features, not all of these multiple features are necessarily essential to the invention, and multiple features may be combined in any manner. Furthermore, in the attached drawings, the same reference numbers are used for the same or similar configurations, and duplicate explanations are omitted.

[Embodiment 1]
(Example of configuration of data processing device)
Fig. 1 is a block diagram showing an example of the configuration of a data processing device to which the interface device according to the first embodiment can be applied. The processing target of the data processing device is not particularly limited, but Fig. 1 shows an image processing device that performs image processing on image data. The data processing device shown in Fig. 1 includes a CPU circuit unit 100, an image reading unit 120, an image input unit 130, an image processing unit 150, and an image display unit 160.

The image reading unit 120 has a lens 124, a CCD sensor 126, and a signal processing unit 127. The image of the original 110 is focused on the CCD sensor 126 via the lens 124. The CCD sensor 126 then generates an analog electrical signal representing the image. The signal processing unit 127 performs correction processing for each of the colors R, G, and B, and further performs analog/digital conversion to generate a full-color digital image signal (pixel value). The digital image signal thus generated is input to the image input unit 130. Hereinafter, a collection of digital image signals (pixel values) for multiple pixels contained in one image will be referred to as image data.

The image processing unit 150 performs image processing on the image data input to the image input unit 130. Examples of image processing include, but are not limited to, processing to compensate for individual differences in sensor elements, color correction processing such as input gamma correction, spatial filtering processing, color space conversion processing, density correction processing, and halftone processing. The image processing unit 150 can create image data for printing, for example, by performing image processing for printing an image. Note that the image processing unit 150 may also perform image processing on video data that includes image data for multiple frames.

The image display unit 160 displays the image data after image processing by the image processing unit 150. The image display unit 160 may display the image after image processing on an image display device such as a display. The data processing device may also have an image printing unit 170 instead of or in addition to the image display unit 160. The image printing unit 170 performs printing according to the image data after image processing by the image processing unit 150. The image printing unit 170 may be a printer equipped with an inkjet head or a thermal head, etc., that records an image on recording paper based on the digital image signal of the image data.

The CPU circuit section 100 includes a CPU 102, which is a processor for arithmetic control, a ROM 104, which is a memory for storing fixed data or programs, a RAM 106, which is a memory into which data or programs are temporarily loaded, and an external storage device 108. The CPU circuit section 100 can comprehensively control the sequence of processing performed by the data processing device by controlling the image reading section 120, the image processing section 150, the image display section 160, and the image printing section 170. The external storage device 108 is a storage medium such as a disk that can store parameters, programs, and correction data used by the data processing device. Data, programs, etc. may be loaded from the external storage device 108 to the RAM 106.

As described above, data is transferred between the image input unit 130, image processing unit 150, image display unit 160, and image printing unit 170. This data transfer may be performed via the RAM 106 or the external storage device 108. For example, a WDMAC 192 (Write Direct Memory Access Controller) outputs a digital image signal input to the image input unit 130. The WDMAC 192 can store image data in the RAM 106 or the external storage device 108 via the shared bus 190. Similarly, the WDMAC 196 can store image data from the image processing unit 150 in the RAM 106 or the external storage device 108.

In addition, the RDMAC 194 (Read Direct Memory Access Controller) can read image data stored in the RAM 106 or the external storage device 108 via the shared bus 190, and input a digital image signal of the pixel to be processed to the image processing unit 150. Similarly, the RDMAC 198 can also input image data read from the RAM 106 or the external storage device 108 to the image display unit 160 or the image printing unit 170.

The CPU 102, image input unit 130, image processing unit 150, image display unit 160, and image printing unit 170 can set and activate the operation of such WDMACs 192, 196 and RDMACs 194, 198.

(Connection between pre-processing and post-processing)
As described above, data is transferred between the image input unit 130, image processing unit 150, image display unit 160, and image printing unit 170. However, the specifications or constraints of data processing may differ between these processing units. The interface device according to the first embodiment can connect the processing units while absorbing the differences in the specifications or constraints of data processing between the processing units.

In the following description, the interface device according to the first embodiment is an interface device that functions as a shared cache for multiple processing units. This interface device acquires data from a front-stage processing unit (first processing unit) included in the multiple processing units and outputs the data to a rear-stage processing unit (second processing unit) included in the multiple processing units. FIG. 2(A) shows a part of a data processing device according to the first embodiment. As shown in FIG. 2(A), a shared cache I/F 250 (hereinafter simply referred to as I/F 250), which is an interface device according to this embodiment, connects a front-stage processing block 220 and a rear-stage processing block 230. Hereinafter, the front-stage processing block 220 will be simply referred to as front-stage processing 220, and the rear-stage processing block 230 will be simply referred to as rear-stage processing 230.

The processing unit 224 included in the front-stage processing 220 may be, for example, the image processing unit 150. In this case, the RDMAC 222 and the WDMAC 226 are the RDMAC 194 and the WDMAC 196, respectively. The processing unit 234 included in the back-stage processing 230 may be, for example, the image display unit 160. In this case, the RDMAC 232 is the RDMAC 198. At least one of the RDMAC 222 and the WDMAC 236 may be omitted.

In this example, the pre-processing 220 generates a data group by performing a first data processing on the input data. The post-processing 230 then performs a second data processing on this data group, thereby generating a processing result obtained by performing the first data processing and the second data processing on the input data.

The interface device according to the first embodiment may connect between other processing units shown in FIG. 1. It is not essential that the processing units generate or modify data by data processing. For example, the pre-processing 220 may be the image input unit 130, which may output the received data as is. The post-processing 230 may be the image display unit 160, which may output the received data as is. The types of processing units to which the interface device according to the first embodiment connects are not limited to those shown in FIG. 1. These processing units may be realized by hardware such as a pipeline circuit, or may be realized by a combination of a processor and a program (software).

When each processing unit performs data processing on the data to be processed, it can perform sequential processing on partial data included in the data to be processed. For example, when performing image processing on image data, it can process each pixel in raster scan order. On the other hand, it is also possible to divide the image data into regions and perform processing on each region in sequence.

For example, two-dimensional division of image data can be used as a region division method for image data. In this case, the image data is divided into multiple tile regions (hereinafter, sometimes simply referred to as tiles or blocks). Here, the image in one tile is called a partial image. Below, data processing performed for each tile is explained. In the following example, the processing unit (or processing granularity) is a partial image. The following data processing for each tile can be called tile processing or block processing. Note that one tile may correspond to one pixel.

When performing image processing on image data, the image data before processing is read, and then the image data after processing is generated. FIG. 3(A) shows an example of image data 300 generated in the pre-stage processing 220. The image data 300 is divided into a number of tiles, and FIG. 3(A) shows tiles 302 to 308 out of the multiple tiles. FIG. 4(A) shows an example of such a tile. The size of each tile is not particularly limited, and the length TL and height TH may be any number of pixels. In FIG. 3(A), one tile is a rectangular area of 5 pixels by 5 pixels.

In the pre-stage processing 220, a partial image is generated in tile units (also called tile scanning or block scanning). Here, data for each pixel of the partial image is generated sequentially in the order of the arrows shown in tile 302. That is, tiles 302, 304, 306, and 308 are generated in sequence in the pre-stage processing 220, and thus processed image data is obtained. In addition, the pre-stage processing 220 outputs a partial image in tile units. That is, tiles 302, 304, 306, and 308 are output sequentially from the pre-stage processing 220. Data for each pixel of the partial image is output sequentially in the order of the arrows shown in tile 302. At this time, the coordinates of the pixel being scanned in the entire image can be calculated from the position of the tile in the entire image and the scanning position in the tile.

Figure 3 (A) also shows an example of image data 300 referenced in subsequent processing 230. The image data generated in the pre-stage processing 220 and the image data referenced in subsequent processing 230 are the same, but the image data 300 is referenced in raster scan order in subsequent processing 230. That is, in subsequent processing 230, processing is performed on the entire image by referencing the data of each pixel in the order of line 312, line 314, and line 316. In this example, subsequent processing 230 may reference line 312 of image data 300 to generate data for the corresponding line in the image data obtained by image processing of image data 300.

In this way, the latter-stage processing 230 performs image processing using the image data output from the former-stage processing 220. However, the output order of the data of each pixel from the former-stage processing 220 is different from the reference order of the data of each pixel by the latter-stage processing 230. Due to such differences in specifications or constraints between the two connected processing units, data is temporarily held in some kind of buffer between the time when the data is output from the former-stage processing 220 and the time when the data is input to the latter-stage processing 230. The I/F 250 can provide such a buffer. For example, the former-stage processing 220 can transmit data included in each of a plurality of tiles having a first size set in the image to the I/F 250 for each tile. Also, the latter-stage processing 230 can receive data included in each of a plurality of tiles having a second size different from the first size set in the image from the I/F 250 for each tile.

(Example of the configuration of an interface device)
5, the I/F 250 according to this embodiment, which connects the pre-stage processing 220 and the post-stage processing 230, has a cache memory 434 that caches data acquired from the pre-stage processing 220. The I/F 250 also has a cache determination unit 412. The cache determination unit 412 can control whether or not data written to the cache memory 434 is written back to a storage unit other than the cache memory 434, based on information acquired from the post-stage processing 230. In this way, the cache determination unit 412 can realize cache control in the I/F 250.

In the following, the storage destination for transfer data secured in a storage unit other than the cache memory 434, such as the RAM 106 or the external storage device 108, will be collectively referred to as a global buffer. For example, a DRAM can be used as the global buffer. In addition, the cache memory 434 is an on-chip memory, such as an SRAM, and is a memory that can be read and written at higher speeds than the global buffer.

In a typical cache memory, when data is written to the cache memory, the same data is also written to the main memory (write through) to prevent data inconsistencies. Alternatively, data written to the cache memory is written back to the main memory before being discarded (write back). However, I/F 250 can control whether data written to cache memory 434 is written to the global buffer and then discarded, or whether the data is discarded without writing it to the global buffer.

By using an I/F 250 having such a configuration, it is possible to improve the efficiency of data transfer processing from the pre-stage processing 220 to the post-stage processing 230. More specifically, it is possible to improve the processing speed and reduce power consumption compared to the case where the entire image data output from the pre-stage processing 220 is written to the global buffer 240. That is, when the entire image data obtained by the pre-stage processing 220 is written to the global buffer 240 and read from the global buffer 240, memory access corresponding to the data amount of two images occurs. In this embodiment, a portion of the data obtained from the pre-stage processing 220 is not written to the global buffer 240, so that it is possible to suppress the decrease in access speed and the increase in power consumption that comes with an increase in memory access.

In addition, when an I/F 250 having such a configuration is used, the capacity of the cache memory 434 can be reduced. In other words, it is no longer necessary to provide a cache memory capable of storing the entire image data output from the pre-stage processing 220. By reducing the capacity of such cache memories, which often have large circuit scales, the manufacturing costs of the product can be reduced.

Figure 4 is a block diagram showing an example of the configuration of the I/F 250. The I/F 250 includes a write port 402, which is a first port that acquires data from the pre-stage processing 220, and a read port 404, which is a second port that outputs the data acquired from the pre-stage processing 220 to the post-stage processing 230. The I/F 250 is also connected to a Network on Chip 210 (hereinafter referred to as NoC 210). The global buffer 240 is also connected to the NoC 210, and the I/F 250 includes an access port 406 that inputs and outputs data to and from the global buffer 240 via the NoC 210. As shown in Figure 2 (A), the I/F 250 can access the global buffer 240 via the access port 406, the NoC 210, and a controller 245 such as a DRAM controller. As shown in FIG. 5, I/F 250 is connected to pre-stage processing 220 and post-stage processing 230 without going through NoC 210.

Furthermore, the I/F 250 has a cache memory 434 that caches data obtained from the front-stage processing 220. The I/F 250 also has a cache determination unit 412 that controls whether or not data written to the cache memory 434 is written back to the global buffer 240 based on information obtained from the back-stage processing 230.

Below, a specific example of the configuration of the I/F 250 will be described with reference to FIG. 5. In this example, the I/F 250 is a multi-port shared cache that can simultaneously accept requests to the write port 402 and the read port 404.

A write request, synchronization information, and write data are input to the I/F 250 via the write port 402. The write data is pixel data input from the front-stage processing 220. The write request is information obtained from the front-stage processing 220 indicating a request to receive the write data. The write request can include information specifying the write data. In the following example, the write request indicates a memory address in the global buffer 240 where the write data is stored (however, as described below, the write data may not be stored in the global buffer 240). On the other hand, the write request may indicate the pixel position of the pixel corresponding to the write data. The synchronization information is information (first information) obtained from the front-stage processing 220. This data can indicate that the write data is data to be transferred to the back-stage processing 230. Details will be described later.

Also, a read request and synchronization information are input to the I/F 250 via the read port 404, and read data is output from the I/F 250. The read data is pixel data input to the post-stage processing 230. The read data is write data input from the pre-stage processing 220, and is stored in the cache memory 434 or the global buffer 240. The read request is information obtained from the post-stage processing 230 indicating a request to receive the read data. The read request may include information specifying the read data. In the following example, the read request indicates the memory address of the global buffer 240 where the read data is stored (however, as described later, the read data may not be stored in the global buffer 240). On the other hand, the read request may indicate the pixel position of the pixel corresponding to the read data. The synchronization information is information (second information) obtained from the post-stage processing 230. This information can indicate, for example, that it is not necessary to write back the read data from the cache memory 434 to the global buffer 240. Details will be described later.

In this embodiment, the data amount of the write data and the read data is the same, and the address specification method of the write request and the read request is also the same. In addition, the data amount of the write data and the read data is not particularly limited. For example, the write data and the read data may be data of one pixel, or may be data of pixels included in a pixel block of a predetermined size (for example, 1 pixel vertically by 8 pixels horizontally). In addition, as described above, the output order of the data of each pixel from the pre-stage processing 220 may be different from the reference order of the data of each pixel by the post-stage processing 230. That is, the write port 402 can obtain data included in a data group such as image data from the pre-stage processing 220 in a first order. On the other hand, the read port 404 can output data included in a data group to the post-stage processing 230 in a second order different from the first order.

The I/F 250 has a prefetch unit 410, an intermediate FIFO 420, and a fetch unit 430. The prefetch unit 410 can perform cache judgment and prefetch operations. In this embodiment, the prefetch unit 410 accepts a write request to the write port 402 and a read request to the read port 404. The prefetch unit 410 then uses the cache judgment unit 412 of the prefetch unit 410 to perform cache judgment for each request. That is, the cache judgment unit 412 can perform a cache hit or cache miss judgment. Specifically, when the cache judgment unit 412 judges that data corresponding to the memory address of the global buffer 240 specified in the write request is stored in the cache memory 434, it judges that there is a cache hit. On the other hand, when the cache judgment unit 412 judges that the data is not stored, it judges that there is a cache miss. In addition, if the cache determination unit 412 determines that the read data specified in the read request is stored in the cache memory 434, it performs a cache hit determination, and if it determines that the data is not stored, it performs a cache miss determination.

The cache determination result for the write request, the write request, and the write data are sent from the prefetch unit 410 via the intermediate FIFO 420 to the data acquisition unit 432 of the fetch unit 430. The data acquisition unit 432 stores the write data in the cache memory 434.

For a normal write request, the data acquisition unit 432 can perform the operation that is performed when writing to a normal cache memory. For example, when the prefetch unit 410 judges a write request as a cache hit, the cache memory 434 stores data at the address specified in the write request. Therefore, the fetch unit 430 overwrites the cache memory 434 with the write data sent from the prefetch unit 410 to the data acquisition unit 432. Also, when the prefetch unit 410 judges a write request as a cache miss, the cache memory 434 does not store data at the address specified in the write request. In this case, the prefetch unit 410 issues a read request to the global buffer 240 via the access port 406. The fetch unit 430 then overwrites the data received from the global buffer 240 with the write data, and stores the obtained data in the cache memory 434.

On the other hand, in this embodiment, when the front-stage processing 220 transfers data to be transferred to the back-stage processing 230 to the I/F 250, it issues a write request to the I/F 250 specifying a preload command. In this case, the prefetch unit 410 does not issue a read request to the global buffer 240 even if it determines that the write request is a cache miss. In this case, the data acquisition unit 432 stores the write data input in synchronization with the write request in the cache memory 434.

The cache determination result for the read request and the read request are also sent from the prefetch unit 410 to the data acquisition unit 432 via the intermediate FIFO 420. In response to the read request, the data acquisition unit 432 can perform the same operations that are normally performed when writing to a cache memory.

For example, when the prefetch unit 410 judges whether there is a cache hit in response to a read request, the data at the address specified in the read request is stored in the cache memory 434. Therefore, the prefetch unit 410 does not need to issue a read request to the global buffer 240. When the read request reaches the fetch unit 430, the data acquisition unit 432 retrieves the data indicated in the read request from the cache memory 434 and transfers it to the read port 404 as read data.

On the other hand, if the prefetch unit 410 judges the read request to be a cache miss, the data at the address specified in the read request is not stored in the cache memory 434. Therefore, the prefetch unit 410 issues a read request to the global buffer 240 via the access port 406. Then, data including the data at the memory address specified in the read request is input to the fetch unit 430, just as when a cache miss is judged for the read request. When the read request reaches the fetch unit 430, the data acquisition unit 432 receives the data from the global buffer 240 and stores it in the cache memory 434. The data acquisition unit 432 then transfers the data indicated in the read request to the read port 404 as read data.

As described above, I/F 250 can perform appropriate processing for write and read requests.

Next, the configuration of the cache determination unit 412 will be described with reference to FIG. 6. In the following example, the full associative method is used as the associative (line selection) method, and the I/F 250 performs cache operations according to the full associative method. Since the I/F 250 is a multi-port shared cache, requests are input from multiple ports to the cache determination unit 412. FIG. 6 shows the multiple ports as port [0] 512, port [1] 514, ..., and port [N-1] 516. The above-mentioned write port 402 and read port 404 are any of these ports.

The selection circuit 518 selects a request input from each of the ports 512 to 516. The address indicated in the selected read request or write request is stored in the address register 521. In addition, the synchronization information input to the write port 402 or the read port 404 is stored in the synchronization information register 530.

The cache determination unit 412 can store eight cache tags 414. In this example, the I/F 250 is an eight-node fully associative cache device. Each of the eight cache tags 414 is assigned a predetermined number ([0] to [7]), and these numbers indicate the "relative" cache line number of the corresponding cache memory. In the example of FIG. 6, the cache memory 434 has eight cache lines, and data is stored in the eight cache lines according to the FIFO method. The number of cache lines and the capacity of each cache line are not particularly limited and can be set as appropriate.

The cache determination unit 412 can also store eight pieces of synchronization information 532. Each piece of synchronization information 532 corresponds to one of the eight cache tags 414 and is assigned the same number ([0] to [7]). The synchronization information 532 can indicate the synchronization information input to the write port 402, the synchronization information input to the read port 404, or the result of an operation between the synchronization information input to the write port 402 and the synchronization information input to the read port 404. In the following example, the synchronization information 532 is the synchronization information input to the write port 402, or the result of an operation between the synchronization information input to the write port 402 and the synchronization information input to the read port 404.

In the following example, the "relative" cache line number of the cache line in which the oldest data is stored is [0], and the "relative" cache line number of the cache line in which the newest data is stored is [7]. Also, when a cache miss is determined, the "relative" cache line number of the cache line in which new data will be stored (the cache line in which the data to be discarded is stored) becomes [7].

The cache determination unit 412 has eight comparators 523, each of which corresponds to one of the eight cache tags 414. The comparators 523 compare the address stored in the corresponding cache tag 414 with the address stored in the address register 521, and output a comparison result 524 indicating whether the addresses "match" to the determiner 525.

Here, if any one of the eight comparison results 524 output from the eight comparators 523 indicates a "match," the determiner 525 determines that there is a cache hit. On the other hand, if none of the eight comparison results 524 indicates a "match," the determiner 525 determines that there is a cache miss.

If it is determined to be a cache miss (YES at branch 526), the cache tag 414 is updated to have the address held in the address register 521 as its value. In FIG. 6, the cache tag 414 is stored in a memory area having a shift register. If the determination result is a cache miss, a shift operation is performed and the value of the cache tag is moved to the downstream cache tag. That is, the value of cache tag [0] changes to the value of cache tag [1], and the value of cache tag [1] changes to the value of cache tag [2]. The movement is repeated in a similar manner, and the value of cache tag [6] changes to the value of cache tag [7]. The value of cache tag [7] then changes to the value of the address stored in the address register 521.

In this way, in the example of Figure 6, a "FIFO (round robin)" cache tag replacement method is used in which the value of the old cache tag [0] is discarded. By adopting such a method in a fully associative cache device, the device can be simplified.

If a cache miss is determined, the synchronization information 532 is updated to retain the value stored in the synchronization information register 530. In the example of FIG. 6, the synchronization information 532 is stored in a memory area having a shift register, similar to the cache tag 414. If a cache miss is determined, a shift operation of the synchronization information 532 is performed, similar to the cache tag 414, and the value of the synchronization information is moved to the downstream synchronization information. That is, the value stored in the synchronization information register 530 is written to the synchronization information [7], and the value of the old synchronization information [0] is discarded.

On the other hand, if a cache hit is determined, such updates to the cache tag 414 and synchronization information 532 are not performed. On the other hand, if a cache hit is determined, the modifier 535 modifies the synchronization information 532 corresponding to the cache tag 414 determined to be a cache hit. In other words, the modifier 535 modifies the number ([0] to [7]) of the cache tag 414 that has a value matching the address stored in the address register 521 and the value of the synchronization information 532 that has the same number.

The determiner 525 outputs the cache determination result indicating a cache hit or a cache miss as a cache miss flag 528. If the determination result is a cache hit, the determiner 525 outputs the number ([0] to [7]) of the cache tag 414 having a value matching the address stored in the address register 521 as the line number 527. On the other hand, if the determination result is a cache miss, the determiner 525 outputs 7 (i.e., the number of the cache tag [7]) as the line number 527. Furthermore, when the cache determination unit 412 determines a cache miss, it also outputs the value 540 of the cache tag [0] to be discarded by the shift operation and the value 542 of the synchronization information [0] to be discarded as the cache determination result. According to this information, the prefetch unit 410 and the fetch unit 430 can perform the above-mentioned operations.

When a cache hit is determined, the fetch unit 430 that received the write request stores the write data in the cache line indicated by line number 527. When a read request is received, the fetch unit 430 reads the read data from the cache line indicated by line number 527.

On the other hand, if it is determined to be a cache miss, the fetch unit 430 discards the data stored in the cache line [7] indicated by the line number 527 according to the value 542 of the synchronization information [0], or writes it back to the global memory. When performing a write back, the fetch unit 430 performs a write back to the address indicated by the cache tag value 540 of the global memory. Furthermore, when the fetch unit 430 receives a write request, it stores the write data in the cache line [7] indicated by the line number 527. Furthermore, when the fetch unit 430 receives a read request, it writes the data received from the global buffer 240 to the cache line [7] indicated by the line number 527.

(Example of operation)
In this embodiment, the I/F 250 transfers the processing results of the pre-stage processing 220 to the post-stage processing 230, and also saves the processing results that cannot be transferred in the global buffer 240. Such processing control can be realized, for example, by using synchronization information as follows.

In this embodiment, when the front-stage processing 220 transfers the processing result to the rear-stage processing 230, the front-stage processing 220 issues a write request to the I/F 250 using a preload command. In the example of FIG. 6, when the front-stage processing 220 issues a preload command, it inputs synchronization information with a value of "1" to the I/F 250.

As described above, when a preload command is input, the cache determination unit 412 performs a cache miss determination. That is, as described above, it writes the address to the cache tag, and updates the synchronization information 532 so that it retains the value "1" of the synchronization information input from the previous stage processing. Also, as described above, in this case, the prefetch unit 410 does not issue a read request to the global buffer 240, and the write data that is the processing result of the previous stage processing 220 is stored in the cache memory 434.

On the other hand, the post-stage processing 230 makes a read request to the I/F to obtain the processing result of the pre-stage processing 220. In the example of FIG. 6, when making a read request, the post-stage processing 230 inputs synchronization information with a value of "1" to the I/F 250. As described above, the cache determination unit 412 makes a cache determination according to the address indicated in the read request, and if it is determined to be a cache hit, the modifier 535 modifies the synchronization information 532. In this embodiment, the modifier 535 performs an XOR (Exclusive-OR) operation on the synchronization information 532 corresponding to the cache tag 414 determined to be a cache hit and the value of the synchronization information register 530. Then, the synchronization information 532 corresponding to the cache tag 414 determined to be a cache hit is updated with the value obtained by the XOR operation. In this embodiment, when data from the pre-stage processing 220 is stored in the cache memory 434 by a preload command, the value of the corresponding synchronization information 532 becomes "1" as described above. On the other hand, the value of the synchronization information register 530 when a read request is received is "0" as described above. Therefore, when a read request is made for data stored in cache memory 434, the value of the corresponding synchronization information 532 changes from "1" to "0."

As the processing of the front-stage process 220 and the back-stage process 230 progresses, the cache tags are updated, and some cache tags are discarded by the cache determination unit 412 as described above. At this time, the value 540 of the cache tag to be discarded, the value 542 of the synchronization information to be discarded, and the line number 527 are input to the fetch unit 430.

When the input synchronization information value 542 is "0", the data from the pre-stage processing 220 corresponding to the address indicated by the cache tag value 540 has been transferred to the post-stage processing 230 in accordance with a read request from the post-stage processing 230. Therefore, there is no need to save this data in the global buffer 240. This data has been stored in the cache line corresponding to line number 527 of the cache memory 434 by a preload command. Therefore, when the input synchronization information value 542 is "0", the fetch unit 430 discards the data of the cache line corresponding to line number 527 held by the cache memory 434.

On the other hand, if the input synchronization information value 542 is "1", the data from the pre-stage processing 220 corresponding to the address indicated by the cache tag value 540 has not been transferred to the post-stage processing 230 because there is no read request from the post-stage processing 230. This data is stored in the cache line corresponding to line number 527 of the cache memory 434 by a preload command. Therefore, if the input synchronization information value 542 is "1", the fetch unit 430 evacuates the data stored in the cache line corresponding to line number 527 of the cache memory 434 to the global buffer 240. Specifically, the fetch unit 430 stores (writes back) this data at the address of the global buffer 240 indicated by the cache tag value 540.

As described above, the write data is temporarily stored in the cache memory in response to a write request from the front-stage processing 220. Then, whether or not to write back this write data to the global buffer 240 is controlled by a read request from the back-stage processing 230. In this way, whether or not to execute a write-back operation for the write data sent by the front-stage processing 220 is determined by the back-stage processing 230 that receives the data. More specifically, the synchronization information input to the read port 404, which indicates that the read data obtained from the back-stage processing 230 does not need to be written back from the cache memory 434 to the global buffer 240, is referenced. Then, whether or not to write back the data to be discarded is switched at least in accordance with this synchronization information. In the above example, when discarding data written to the cache memory 434, whether or not to perform a write-back is switched in accordance with this synchronization information.

In the above specific example, when the preload command is used to indicate that the write data is data to be transferred to the subsequent processing 230, "1" is stored as the synchronization information value 542 in association with the data stored in the cache memory 434. This synchronization information indicates that the write data obtained from the previous processing 220 is data to be transferred to the subsequent processing 230. In addition, the data thus stored in the cache memory 434 is not obtained from the global buffer 240, but is obtained directly from the previous processing 220. On the other hand, when requesting the data thus stored in the cache memory 434, the subsequent processing 230 can input "0" as the synchronization information to the read port 404. This synchronization information indicates that the read data obtained from the subsequent processing 230 does not need to be written back from the cache memory 434 to the global buffer 240. In accordance with this information, the fetch unit 430 discards the data written in the cache memory 434 without writing it back to the global buffer 240.

In this way, the fetch unit 430 controls whether or not to write back data written to the cache memory 434 to the global buffer 240 based on both the synchronization information obtained from the previous stage processing 220 and the synchronization information obtained from the subsequent stage processing 230. In particular, in the above example, "0", which is the calculation result of the synchronization information obtained from the previous stage processing 220 and the synchronization information obtained from the subsequent stage processing 230, is stored as the synchronization information value 542. Then, write-back control was performed according to this synchronization information value 542. However, this configuration is merely one example. For example, the synchronization information obtained from the previous stage processing 220 and the synchronization information obtained from the subsequent stage processing 230 may each be stored as the synchronization information value 542.

(Example of operation when tile scanning is performed in later processing)
By using the I/F 250 as in the first embodiment, such an operation can be realized regardless of the scanning order used in the front-stage processing 220 and the rear-stage processing 230. In the first embodiment, for example, as shown in FIG. 3A, the front-stage processing 220 performs tile scanning and the rear-stage processing 230 performs raster scanning, but the front-stage processing 220 and the rear-stage processing 230 are not limited to this. For example, the method of the first embodiment is effective even when the front-stage processing 220 performs tile scanning according to tiles of a predetermined size and the rear-stage processing 230 performs tile scanning according to tiles of a different size. In such a case, the rear-stage processing 230 can, for example, obtain pixel data of each pixel in one tile from the I/F 250, perform processing using the obtained pixel data, and generate processed pixel data of each pixel in this tile. The rear-stage processing 230 can generate processed image data by repeating such processing for each tile for each tile. In this case as well, the I/F 250 can output data requested by the post-stage processing 230 from the cache memory 434, or obtain it from the global buffer 240 and output it, as described above.

Meanwhile, in such processing of a single tile, pixel data of pixels outside the tile may be referenced. For example, when the post-processing 230 performs filtering processing such as an FIR filter on image data, pixel data of surrounding pixels may be referenced to calculate pixel data for a pixel. In such cases, in addition to the pixel data for each pixel in a single tile, the post-processing 230 obtains pixel data for a larger tile that includes the surrounding pixels of this tile from the I/F 250.

In the example of Figures 4 (B) to (E), when processing the first tile, the post-processing 230 obtains data in area 391, which is a larger tile, and similarly when processing the second to fourth tiles, it obtains data in areas 392 to 394, which are larger tiles. In Figures 4 (B) to (E), areas from which pixel data is obtained two or more times by the post-processing 230 are shown hatched. Hereinafter, such areas are referred to as overlap areas. For example, when the post-processing 230 performs filter processing that references a total of 25 pixels, 5 pixels vertically and 5 pixels horizontally, centered on the pixel to be processed, the width of the overlap area is 2 pixels.

Below, an example of the operation of the interface device according to this embodiment when such an overlapping area exists will be described with reference to FIG. 3B. In FIG. 3B, the post-processing 230 is attempting to obtain image data of area 350 from the I/F 250. When making a read request for data in area 351 of area 350, the post-processing 230 sets "1" as synchronization information at the time of the read request, as in the case of FIG. 3A. Here, area 351 is an area that is not an overlapping area, that is, an area that is not referenced in the processing of subsequent tiles. In this case, as described above, when a cache hit occurs, the data stored in the cache memory 434 is discarded without being written back.

In this way, when requesting data from I/F 250, post-processing 230 can determine whether or not to request the data again in a later process. In addition, depending on the determination that the data will not be requested again, synchronization information ("1") indicating that the requested data does not need to be written back from cache memory 434 to global buffer 240 can be sent to I/F 250.

On the other hand, when the post-processing 230 makes a read request for data in area 352 of area 350, it sets the synchronization information to "0" when making the read request. Here, area 352 is an overlap area, that is, an area that is referenced in the processing of the subsequent tile. In this case, even if there is a cache hit, the value of the synchronization information 532 corresponding to the data stored in the cache memory 434 remains "1" as a result of the XOR operation. Therefore, even if there is a cache hit, the data stored in the cache memory 434 is written back to the global buffer 240. As a result, it becomes possible to obtain the data of the referenced area from the global buffer 240 when processing the subsequent tile.

In this way, it is possible to control the synchronization information transmitted to the I/F 250, which indicates the need to write back data requested by the post-stage processing 230 from the cache memory 434 to the global buffer 240. When requesting data contained in a tile region from the I/F 250, the post-stage processing 230 can perform such control depending on whether the data is contained in another tile region (i.e., whether it is contained in an overlap region).

Note that the operation of the interface device according to this embodiment is not limited to the above. For example, in the example of FIG. 3C, the post-processing 230 acquires data in area 360 when processing one tile. Here, in the example of FIG. 3C, after reading row 381, row 382 is read. Therefore, when reading data in area 375 to process another tile, it is highly likely that data in area 364 at the bottom end of area 360 has been discarded from the cache memory. Therefore, in order to save the data in area 364 to the global buffer 240, the post-processing 230 sets "0" as the synchronization information when making a read request for the data in area 364.

On the other hand, in the example of FIG. 3(C), the data in area 370 is read after the data in area 360 has been read. Therefore, although area 370 includes area 362, the data in area 362 is a cache hit when the data in area 370 is read. In other words, since there is no need to save the data in area 362 to the global buffer 240, the post-stage processing 230 may set "1" as the synchronization information when making a read request for the data in area 364.

The type of the post-stage processing 230 is not particularly limited, and this embodiment can also be applied when the post-stage processing 230 performs processing to change the size of an image, such as resolution conversion (arbitrary magnification processing). When performing resolution conversion using a region division method such as tile processing, the size of the region referenced in the processing or the size of the region output by the processing may vary depending on the position of the tile in the image, depending on the magnification ratio. On the other hand, since the post-stage processing 230 can detect such a change in the size of the referenced region, it is possible to obtain the data required for processing by changing the number of read requests according to the change in the size of the region. In addition, since the post-stage processing 230 can detect the change in the size of the referenced region and the change in the size of the output region, it can also detect the change in the overlap region described above. Therefore, the post-stage processing 230 can control whether or not to perform a write-back operation by changing the value of the synchronization information as described above.

As described above, according to this embodiment, the I/F 250 can directly transfer at least a portion of the data processed by the pre-stage processing 220 to the post-stage processing 230 without temporarily storing it in the global buffer 240. The I/F 250 also saves only the data that could not be directly transferred in this way to the global buffer 240. In this way, by directly connecting the pre-stage processing 220 and the post-stage processing 230 using the I/F 250, it is possible to select data that is directly transferred to the post-stage processing 230 without saving it in the global buffer 240 and data that is saved in the global buffer 240. Therefore, it is possible to improve the processing speed and reduce power consumption compared to the case where the entire image data output from the pre-stage processing 220 is written to the global buffer 240. In this way, by using the I/F 250, it is possible to make the data transfer process from the pre-stage processing 220 to the post-stage processing 230 more efficient.

The I/F 250 can perform such a selection operation according to the size of the cache memory 434. In order to directly transfer data from the pre-stage processing 220 to the post-stage processing 230, the post-stage processing 230 needs to make a read request before the data is evacuated to the global buffer 240. Therefore, the larger the capacity of the cache memory 434, the later the time limit of the read request for direct data transfer. After direct data transfer, the I/F 250 discards the data from the cache memory 434 without writing it back to the global buffer 240, so the amount of access to the global buffer 240 decreases. Therefore, it is possible to adjust the balance between the size of the cache memory and the amount of access to the global buffer 240. The larger the capacity of the cache memory 434, the more loosely the pre-stage processing 220 and the post-stage processing 230 can be coupled, and the operation of the I/F 250 on the system becomes more stable.

[Embodiment 2]
In the first embodiment, the pre-stage processing 220 and the post-stage processing 230 in one chip are connected. However, the pre-stage processing 220 and the post-stage processing 230 may be mounted on separate chips. In the second embodiment, as shown in FIG. 2B, the chip 265 (chip B) has an I/F 250 and a post-stage processing 230. The I/F 250 has the same function as in the first embodiment, and is connected to the pre-stage processing 220 of a chip 260 (chip A) different from the chip 265. The WDMAC 226 of the pre-stage processing 220 issues a write request of the processing result by the processing unit 224 to an address of the global buffer 240 of the chip 265. In FIG. 2B, PCIe is used as an example of an interface between chips, and the PCIe 228 of the chip 260 converts the write request into a transfer protocol of PCIe and transfers it to the chip 265. The PCIe 238 of the chip 265 receives the transferred data from the chip 260 and issues a write request to the I/F 250. The functions of the post-stage processing 230, the NoC 210, the controller 245, and the global buffer 240 of the chip 265 are similar to those in the first embodiment.

This configuration allows data transfer between processing units across multiple chips while absorbing differences in data processing specifications or constraints between processing units. In this example, it is not necessary to transfer data greater than the amount of data output from the front-end processing 220. In this example, the chip 265 having the back-end processing 230 has an I/F 250 and a global buffer 240. Therefore, this configuration allows the balance between the size of the cache memory in the chip 265 and the amount of access to the global buffer 240 to be adjusted. The front-end processing 220 of the chip 260 can transfer predetermined synchronization information via the inter-chip interface in the same way as in embodiment 1. In addition, the I/F 250 of the chip 265 can correct the synchronization information received from the front-end processing 220 with the synchronization information received from the back-end processing 230 in the same way as in embodiment 1.

[Modifications of the First and Second Embodiments]
The correction of the synchronization information in the first and second embodiments will be described in more detail below. When using the same method as in the first embodiment, the correction of the synchronization information can be performed as follows. That is, the synchronization information for the desired cache line can be calculated using the synchronization information input to the write port 402 together with the write request and the synchronization information input to the read port 404 together with the read request. Then, when a cache miss occurs, the synchronization information [0] for the oldest cache line [0] is discarded from the I/F 250. At this time, if the value of the synchronization information [0] to be discarded is 1, the cache data can be written back to the global buffer 240 (e.g., DRAM).

On the other hand, when data is sent and received between chips as in the second embodiment, it may be desirable to give priority to transmitting data from the write port to the read port. In such a case, the above-mentioned operation without write-back can be used. For example, input from the write port 402 can be stalled (temporarily stopped), and read requests from the read port 404 can be processed with priority. Then, when a read request for the oldest cache line [0] is input, the value of the synchronization information [0] changes from 1 to 0, and the cache data of the cache line [0] can be discarded, the input stall (temporary stop) of the write port 402 can be released.

According to this embodiment, by giving priority to sending data to the read port 404 over receiving data from the write port 402, it is possible to suppress the amount of data written back to the global buffer 240. In addition, since the amount of data re-read from the global buffer 240 is also suppressed, it is possible to reduce the access bandwidth to the global buffer 240 (e.g., DRAM) and shorten the transmission latency from the write port 402 to the read port 404.

Furthermore, a control method using the synchronization information will be described in detail. In the method of the first embodiment, the synchronization information is a 1-bit flag, and the data transfer ratio between the data received from the write port 402 and the data sent to the read port 404 is 1:1. On the other hand, the synchronization information may be a count value of N bits (N is 1 or more). As an example, a case will be described where the received data from the write port 402 is read from the read port 404 7 times. In this case, the value of the synchronization information input to the write port 402 together with the write request can be set to 7. The synchronization information (value = 7) thus input is written as the synchronization information [7] for the cache line [7]. Then, each time a read request to the read port 404 hits the cache, 1 is subtracted from the synchronization information for the corresponding cache line. Then, when the cache data is discarded from the oldest cache line [0], if the value of the corresponding synchronization information [0] is 0, no write back is performed, and if it is 1 or more, writing back to the global buffer 240 (e.g., DRAM) is performed. In this case, the data transfer ratio from the write port 402 to the read port 404 can be controlled to 1:7.

In addition, by devising a way to use the synchronization information, the data transfer ratio can be controlled even if the data transfer ratio between the data received from the write port 402 and the data sent to the read port 404 is not determined in advance. For example, by using 8-bit synchronization information, the pre-stage processing 220 can write synchronization information having a value of 0xFF (infinite multiple) from the write port 402 to the I/F 250 together with the write request. At this time, the pre-stage processing 220 does not necessarily need to know how the sent data will be used in the post-stage processing 230. The post-stage processing 230 that uses the data can decide what the data transfer ratio should be. In this case, too, it is possible to determine whether to write back or discard the cache data of the cache line by calculating the value of the synchronization information input to the read port 404 together with the read request and the synchronization information for the cache line that has been hit.

For example, the post-processing 230 can read the desired cache data as many times as necessary by a read request to the read port 404. If the desired data is not in the cache memory, the data and synchronization information reread from the global buffer 240 (e.g., DRAM) are sent to the read port 404. Then, when the desired data is finally read by a read request to the read port 404, the synchronization information for the cache line can be forcibly overwritten with a value of 0. The cache data of such a cache line is discarded from the cache memory without being written back to the global buffer 240. The post-processing 230 can overwrite such synchronization information using the synchronization information input to the read port 404 together with the read request.

According to such an embodiment, the data transfer ratio between the data sent by the pre-stage processing 220 and the data received by the post-stage processing 230 can be easily controlled. In particular, as in the above embodiment, the post-stage processing 230 controls the synchronization information, making it possible to realize a flexible data transfer ratio. In this case, the pre-stage processing 220 simply transmits the data.

[Embodiment 3]
In the above-described embodiment, it is desirable to use a large cache memory in order to transmit and receive image data in different scan orders, to take into account overlapping areas in filter processing, etc. The larger the cache memory, the more it is possible to suppress accesses for saving and re-reading data to a global buffer (e.g., DRAM), thereby reducing the access bandwidth to the global buffer.

Therefore, instead of conventional SRAM, a next-generation non-volatile memory such as spin-transfer torque magnetic RAM (STT-MRAM) can be used as the cache memory. In addition, FRAM (registered trademark), ReRAM, PCM, and the like, which are called next-generation memories, can also be used. For example, STT-MRAM has smaller circuit elements than SRAM, so it is easy to have a capacity four times larger or more. Therefore, the capacity of the cache memory can be increased. Furthermore, the power consumption of STT-MRAM can be about 1/60 of that of SRAM for read access, but about 1.6 times larger for write access. However, as in the above modification, the interface device according to one embodiment of the present invention can easily control the number of reads by the rear-stage processing 230 relative to one write by the front-stage processing 220, that is, the data transfer ratio. Therefore, the effect of suppressing power consumption by using STT-MRAM can be utilized.

As described above, by using next-generation memory such as STT-MRAM or non-volatile memory as cache memory, it is possible to increase the cache capacity and improve the efficiency of data transmission. Furthermore, when the data transfer ratio of the read port to the write port is high, power consumption can be effectively reduced by using STT-MRAM.

[Embodiment 4]
The pre-processing 220 may be a sensing device such as an imaging sensor. For example, an imaging sensor often transmits imaging data in a simple raster scan order. The post-processing 230 may perform high-quality image processing on the imaging data. According to the above-mentioned embodiment, it is possible to perform scan conversion to use image processing in tile regions that can reduce memory, and control of overlapping regions for filter processing. According to the above-mentioned embodiment, the pre-processing 220 can simply transmit data, and the post-processing 230 can receive data in a variety of ways by controlling synchronization information. Therefore, the above-mentioned embodiment can be used such that a sensing device such as an imaging sensor transmits simple data to a shared cache I/F, and the post-processing 230, which performs complex image processing, receives data according to its function and operation.

Other Examples
The present invention can also be realized by a process in which a program for implementing one or more of the functions of the above-described embodiments is supplied to a system or device via a network or a storage medium, and one or more processors in a computer of the system or device read and execute the program. The present invention can also be realized by a circuit (e.g., ASIC) that implements one or more of the functions.

The invention is not limited to the above-described embodiment, and various modifications and variations are possible without departing from the spirit and scope of the invention. Therefore, the following claims are appended to disclose the scope of the invention.

220: Pre-processing, 230: Post-processing, 250: Shared cache I/F, 402: Write port, 404: Read port, 410: Prefetch unit, 430: Fetch unit

Claims (19)

1. An interface device that serves as a shared cache for a plurality of processing units, comprising:
a first port that acquires data from a first processing unit included in the plurality of processing units;
a second port that outputs data acquired from the first processing unit to a second processing unit included in the plurality of processing units;
a cache unit that caches the data acquired from the first processing unit;
a control unit that controls whether or not to write back the data written to the cache unit to a storage unit different from the cache unit based on information acquired from the second processing unit ,
2. An interface device according to claim 1, wherein the information obtained from said second processing unit indicates that it is not necessary to write back data requested by said second processing unit from said cache means to said storage means . The first port obtains data included in a data group from the first processing unit in a first order;
2. The interface device according to claim 1, wherein the second port outputs the data included in the data group to the second processing unit in a second order different from the first order. 3. The interface device according to claim 1, wherein the control means controls whether or not to write back the data written to the cache means, further based on the information acquired from the first processing unit. 4. The interface device according to claim 3 , wherein the information obtained from the first processing unit indicates that the data is to be transferred to the second processing unit. 5. The interface device according to claim 3, wherein the control means stores, in association with the data written in the cache means, information acquired from the first processing unit, information acquired from the second processing unit, or a result of an operation between the information acquired from the first processing unit and the information acquired from the second processing unit. The control means
the data written to the cache means is not obtained from the storage means,
When the information acquired from the first processing unit indicates that the data is data to be transferred to the second processing unit, and the information acquired from the second processing unit indicates that the data requested by the second processing unit does not need to be written back from the cache means to the storage means,
6. The interface device according to claim 3 , wherein the data written in the cache means is discarded without being written back to the storage means. 7. The interface device according to claim 1, wherein the control means, when discarding the data written to the cache means, switches whether or not to write back the data to be discarded based on at least information obtained from the second processing unit. 8. The interface device according to claim 1, wherein said cache means performs a cache operation according to a full associative method. 9. The interface device according to claim 1, wherein said storage means is a DRAM. 10. The interface device according to claim 1, wherein the data is image data. An interface device according to any one of claims 1 to 10 , comprising a first chip having the interface device according to any one of claims 1 to 10 and the second processing unit, and connected to the first processing unit of a second chip different from the first chip. A data processing device comprising: the first processing unit, the second processing unit, and the interface device according to any one of claims 1 to 11 . The first processing unit generates a data group by a first data processing on input data,
13. The data processing device according to claim 12, wherein the second processing unit performs a second data processing on the data group to generate a processing result obtained by performing the first data processing and the second data processing on the input data. the first processing unit transmits data included in each of a plurality of tile regions having a first size set in an image to the interface device for each tile region;
14. The data processing device according to claim 12, wherein the second processing unit receives, from the interface device, data contained in each of a plurality of tile regions set in the image and having a second size different from the first size, for each tile region. 15. The data processing device according to claim 12, wherein the second processing unit, when requesting data from the interface device, determines whether or not to request the data again in a later process, and, in response to a determination that the data will not be requested again, transmits information to the interface device indicating that the requested data does not need to be written back from the cache means to the storage means. The second processing unit receives data included in each of a plurality of tile regions set in an image from the interface device for each tile region;
15. A data processing device according to claim 12, characterized in that, when requesting data contained in a tile area from the interface device, information indicating the need to write back the data requested by the second processing unit from the cache means to the storage means is controlled depending on whether the data is contained in another tile area, and is sent to the interface device. The data processing device further comprises a network and the storage means connected to the network;
the data processing device is connected to the network;
The data processing device according to claim 12 , wherein the data processing device is connected to the first processing unit and the second processing unit without passing through the network. A cache control method performed by an interface device that serves as a shared cache for a plurality of processing units, the interface device comprising: a first port that acquires data from a first processing unit included in the plurality of processing units; a second port that outputs the data acquired from the first processing unit to a second processing unit included in the plurality of processing units; and cache means that caches the data acquired from the first processing unit, the method comprising:
a step of controlling whether or not to write back the data written to the cache means to a storage means other than the cache means based on information acquired from the second processing unit ;
A cache control method, characterized in that the information obtained from the second processing unit indicates that data requested by the second processing unit does not need to be written back from the cache means to the storage means . A program for causing a computer to function as the control means of the interface device according to any one of claims 1 to 11 .

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