JP7445388B2 - Digital input devices and programmable logic controllers - Google Patents

Description

The present invention relates to programmable logic controllers and digital input devices.

A digital input device serving as an input module of a programmable logic controller (hereinafter referred to as PLC) is generally composed of a CR filter circuit or a photocoupler. If this photocoupler fails or the wiring route within the printed circuit board fails, digital input signals from an external device (industrial system) cannot be correctly input.

Digital input devices are used in various industrial systems such as large-scale plants and machine tools. Generally, industrial systems are designed to operate only when certain conditions are met using interlock circuits. If digital input signals cannot be input correctly, these industrial systems may malfunction, potentially causing serious accidents.

JP2011-69694

Currently, in order to detect a failure in a digital input device, for example, a maintenance worker must go to the location where the PLC is installed, stop the operation of the industrial system, and then disconnect the wiring of the external device and confirm the failure. need to be done.

Furthermore, if the PLC is installed in a remote location or in an inaccessible position in an industrial system, it is difficult to confirm a failure of the digital input device.

An object of the present invention is to enable automatic failure detection of a digital input device without stopping an external device.

The present application provides a plurality of solutions to the above problems. One example includes a data input circuit that inputs data from an external device, and an internal circuit that supplies the data to a data bus connected to a CPU module, and the data input circuit includes a test signal generation circuit, and the data input circuit includes a test signal generation circuit; The data input circuit is a digital input device characterized in that it supplies a test signal to the internal circuit during a time when data from the external device is not supplied to the data bus.

According to the present invention, it is possible to automatically detect a failure of a digital input device without stopping an external device.

1 is a diagram showing the device configuration of a PLC system of Example 1. FIG. 1 is a configuration diagram of a digital input device according to a first embodiment; FIG. FIG. 3 is a diagram showing data access timing and failure determination timing between a CPU module and a digital input device. It is a diagram showing a test pattern generation processing flow. FIG. 3 is a diagram showing a pattern of external data DATA. It is a figure showing the trend judgment flow of external data DATA. It is a figure showing a self-diagnosis processing flow of a digital input device.

EMBODIMENT OF THE INVENTION Hereinafter, the form for carrying out this invention (henceforth "this Example") is demonstrated using drawings.

FIG. 1 is a diagram showing a system configuration of a PLC according to a first embodiment. In the PLC of the first embodiment, a power supply module 11, a CPU module 12, and a digital input device group 13 are connected to a base 10. Data access from the CPU module 12 to the digital input devices is via the data access bus of the base 10. In the digital input/output device group 13 of this embodiment, N+1 digital input/output devices are connected, and from the 0th digital input device 14 to the Nth digital input device 16 are connected to one CPU module 12. Further, data access is performed sequentially to the plurality of digital input/output devices 14 to 16.

FIG. 2 is a configuration diagram of the digital input/output device according to the first embodiment. Power supply is omitted. The digital input device in FIG. 2 is shown connected to an external device 21. As shown in FIG. The digital input device includes an internal circuit 22, an input circuit 23, and a photocoupler 24 arranged between the internal circuit 22 and the input circuit 23.

The internal circuit 22 is a logic circuit and is connected to a data access bus.
The input circuit 23 is a circuit for taking in data from the external device 21 such as an RC filter.

The photocoupler 24 configures an isolated digital input device by converting external data DATA from the external device 21 from an electrical signal into an optical signal and transmitting it to the internal circuit 22, thereby preventing the intrusion of electrical disturbances. .

The input circuit 23 of this embodiment includes an external disconnection circuit 25, a test signal generation circuit 26, and existing input circuits such as an RC filter from the connection end side with the external device 21.

The external disconnection circuit 25 performs control to disconnect and reconnect the external device 21 and the input circuit 23 electrically using an external signal, and outputs the control state.

The test signal generation circuit 26 is triggered by receiving the disconnection output from the external disconnection circuit 25 and starts outputting the test signal TSS to the internal circuit 22, and is triggered by receiving the reconnection output from the external disconnection circuit 25. or when the test signal TSS is output a predetermined number of times as a trigger, the output of the test signal TSS to the internal circuit 22 is stopped.

If the internal circuit 22 detects the test signal TSS as the input signal INS, it is determined to be normal, and if it cannot detect the test signal TSS as the input signal INS, it determines it to be a failure.

Next, the process of determining a failure will be explained using a timing diagram. FIG. 3 is a diagram showing data access timing and failure determination timing of the CPU module 12 and the 0th digital input/output device 14. Before explaining the timing, each signal will be explained first.

The 0th chip select signal CS0 to the Nth chip select signal CSN are chip select signals from the CPU module 12.

The address signal ADR is a signal that specifies an address space into which the CPU module 12 takes in external data DATA acquired from the external device 21.

The refresh cycle T2 is a cycle time during which the CPU module 12 takes in external data DATA from a desired digital input/output device IO.

The testable time T1 is a time during which failure diagnosis can be performed on the 0th digital input/output device 14.

Before the testable time T1 during the refresh cycle T2, that is, the time T0 when the chip select signal CS0 is LOW, the external data DATA is supplied from the 0th digital input/output device 14 to the CPU module 12, and the testable time is reached. During T1 (while the 0th clock signal IN0 is HIGH), the external data DATA is not supplied to the CPU module 12 from the 0th digital input/output device 14.

The external disconnection signal DVS tests the external disconnection circuit 23 to electrically disconnect and reconnect the external circuit 21 from the digital input/output device 14 using the LOW/HIGH status or switching of the 0th chip select signal as a trigger. This is a signal to notify the signal generation circuit 26.

The test signal TSS is a test signal that the test signal generation circuit 26 outputs to the internal circuit 22 using the disconnection signal DVS as a trigger. In the end, when the 0th chip select signal changes from LOW to HIGH, external disconnection and test signal output are performed, and when the 0th chip select signal changes from HIGH to LOW, reconnection is performed by the external cutout circuit and output of the test signal is stopped. .

The internal signal INS is a signal detected by the internal circuit 22 as an internal input.

First, the CPU module 12 sends each chip select signal (0th chip select signal CS0 to Nth chip select signal CSN) and address signal ADR to the 0th digital input/output device 14 to the Nth digital input/output device 16. is supplied through the data access bus.

The internal circuit 22 of the 0th digital input/output device 14 is triggered by the 0th clock signal CS0 becoming LOW, performs data access with the CPU module 12, and outputs external data DATA to the data access bus.

Similarly, the first digital input/output device IO1 accesses data with the CPU module 12 while the first clock signal CS1 is LOW, and the Nth digital input/output device 16 accesses data with the CPU module 12 while the Nth clock signal CSN is LOW. I do.

The external disconnection circuit 25 of the 0th digital input/output device 14 detects that the 0th chip select signal CS0 changes from LOW to HIGH using a signal from the internal circuit 22 supplied via the wiring 27, and detects this. An external disconnection signal DVS is sent to the test signal generation circuit 26 as a trigger.

The test signal generation circuit 26 generates a test signal TSS using the external disconnection signal DVS from the external disconnection circuit 25 as a trigger, and outputs the test signal TSS to the internal circuit 22. This test signal outputs a test signal by the output of the external extraction circuit 25 when the 0th chip select signal changes from LOW to HIGH, and outputs the test signal by the output of the external extraction circuit 25 when the 0th chip select signal changes from HIGH to LOW. stop.

If the internal circuit 22 cannot detect the same number of times as the test signal TSS as the internal input INS, it determines that there is a failure, and if it detects the same number of times as the test signal TSS as the internal input INS, it determines that there is no failure. do.

If it is determined that there is a failure, the failure is reported to the user or maintenance worker using an LED provided in the 0th digital input/output device 14, or the CPU module 12 is notified of the failure. The CPU module 12 that has been notified uses the abnormal signal to the interlock circuit to safely stop the industrial system. Furthermore, the CPU module notifies users and maintenance workers of the malfunction by displaying an abnormality display on the LED.

Note that the number of inputs N of the test signal TSS can be arbitrarily set depending on the installation environment of the PLC, such as the noise environment where the PLC is installed. Further, the number of times the test signal TSS can be inputted is determined by the testable time T1. Further, the testable time T1 changes depending on the number of digital input devices installed in the PLC and the program in the CPU module 12, and there are cases where the test input signal cannot be input N times within the testable time. If the test input signal cannot be input N times within the testable time, it is also possible to distribute the test signal to the next refresh cycle T2.

As described above, the digital input/output device of this embodiment can be used to operate not only the individual digital input devices but also the PLC system and the external devices connected to the digital input devices without stopping the operation. It is now possible to perform failure determination.

In the second embodiment, it is possible to set the test signal, which was tested using a fixed pattern in the first embodiment.

FIG. 4 is a diagram showing a test pattern generation processing flow. This processing is performed by the internal circuit 22 and the test signal generation circuit 26.

First, the internal circuit 22 acquires the testable time T1 from the CPU module 12 and supplies it to the test signal generation circuit 26.

The test signal generation circuit 26 compares the total test time TTS with the testable time T1.

If the total test time TTS is shorter than the testable time T1, the test is performed within the testable time T1 of one refresh cycle T2. If not, the number of pulses that can be tested in one test time TTS is determined from the one test time TTS and the one pulse test time TTSP. Specifically, it is calculated by dividing one test time TTS by one pulse test time TTSP.

Next, the number of cycles to be tested is determined from the total number of tests and the number of pulses tested in one cycle, and the test signal generation circuit 26 generates a test signal. Specifically, the number of cycles to perform the test is determined by dividing the total number of tests by the number of pulses tested in one cycle.

The test signal generation circuit 26 supplies the test signal TSS to the internal circuit 22 and also supplies the result as a criterion.

It is sufficient that the setting result of the test signal TSS can be shared between the test signal generation circuit 26 that generates the test signal and the internal circuit 22 that makes the determination, so it may be done by either one.

In the previous embodiments, it was assumed that failure determination was performed every cycle (always), but in this embodiment, failure determination is not performed all the time, and the internal circuit 22 constantly monitors the trend of the external data DATA and detects the trend. A failure judgment is made only if it comes off.

FIG. 5 is a diagram showing a pattern of external data DATA. The external data DATA can be classified into four patterns: "always on pattern", "always off pattern", "(constant) periodic on pattern", and "irregular on pattern". In this embodiment, first, it is determined which of the four patterns the external data DATA is classified into.

FIG. 6 is a diagram showing a trend determination flow for external data DATA. Start the determination and monitor the "ON time pattern" and "OFF time pattern". If the ON time is longer than the OFF time, it is determined that the pattern is "always on". If not, the ON time and OFF time are similarly monitored, and if the OFF time is larger than the ON time, it is determined that the pattern is "always OFF pattern". If not, the period of ON is monitored, and if the period of ON is constant, it is determined to be a "periodic ON pattern". Otherwise, it is determined that the pattern is an "irregular ON pattern." Here, if it is determined that the pattern is a periodic ON pattern or an irregular ON pattern, since the external data DATA is changing between ON and OFF, it is determined that there is no circuit failure and no failure determination is performed. If it is determined to be an "always on pattern" or "always off pattern" and the pattern deviates from the trend, a failure determination is made.

FIG. 7 is a diagram showing a self-diagnosis processing flow of the digital input device.

When the power of the PLC is first turned on, a clock signal and an address signal test are input to the internal circuit 22. Using this as a trigger, the test signal generation circuit 26 determines a test signal. When an external disconnection circuit is provided as in the first embodiment, the control result thereof is used as a trigger.

Next, the internal circuit 22 determines the pattern of the external data DATA and monitors the trend.

If the external data DATA is a "constantly ON pattern" or "constantly OFF pattern" and the input signal is ON or OFF, trend monitoring is performed again.

If not, it is determined that it has deviated from the trend, and the process moves to a failure determination operation. Note that a function may be provided that allows a setting to forcibly shift to a failure determination operation even when the trend is not deviated from.

When proceeding to the failure determination operation, first the number of failure determinations is counted. Next, the number of failure determinations is compared, and if it is N or more, it is determined that the trend of the input signal has changed, and pattern determination of the input signal is performed again. If not, perform failure determination. If the result of failure determination is normal, trend monitoring is performed again. If not, it is determined that there is a failure, and an abnormality is displayed on the LED of the digital input device, and the CPU module 12 is notified of the abnormality. The notified CPU module 12 uses the abnormal signal to the interlock circuit to safely stop the industrial system. Furthermore, the CPU module notifies maintenance workers of the failure by displaying an abnormality display on the LED.

10...Base 11...Power supply module 12...CPU module I3...Digital input device group 14...0th digital input device 15...1st digital input device 16...Nth digital input device

20...Digital input device 21...External circuit 22...Internal circuit 23...Input circuit 24...Photocoupler 25...External disconnection circuit 26...Test signal generation circuit

CS0...0th chip select signal CS1...1st chip select signal CSN...Nth chip select signal ADR...Address signal DATA...External data DVS...External disconnection signal INS...Internal input T0...Time during which external data is supplied to the CPU module T1...Testable time within refresh cycle T2...Refresh cycle TSS...Test signal TTS...Test time TTSP...Test time for one pulse

Claims (5)

A data input circuit that inputs data from an external device, an internal circuit that supplies the data to a data bus connected to a CPU module, and a photocoupler between the data input circuit and the internal circuit,
The data input circuit includes an external disconnection circuit and a test signal generation circuit,
The internal circuit obtains a testable time from the CPU module, which is a time during which a test for failure determination is possible during a refresh cycle, which is a cycle time during which the CPU module takes in the data, and generates the test signal. and performing a test for determining the failure using a test signal supplied from the test signal generation circuit during the testable time;
The external disconnection circuit controls disconnection and reconnection to the external device based on a chip select signal supplied from the CPU module,
The test signal generation circuit is triggered by receiving a disconnection output from the external disconnection circuit to start outputting the test signal to the internal circuit, and is triggered by receiving a reconnection output from the external disconnection circuit. stopping the output of the test signal to the internal circuit,
Comparing the testable time and the test time for performing the test for failure determination,
If the test time is shorter than the testable time, the internal circuit performs the test for failure determination in one refresh cycle;
If the test time is greater than or equal to the testable time, calculate the number of pulses to be tested in one refresh cycle by dividing the testable time by the test time of one pulse;
Calculating the number of refresh cycles for performing the test for failure determination by dividing the total number of tests required for the failure determination by the number of pulses tested in one refresh cycle;
A digital input device characterized in that the test for fault determination is performed by distributing the test signal to a plurality of the refresh cycles equal to the calculated number of the refresh cycles. In claim 1,
A digital input device characterized in that the data from the external device is monitored and the failure determination is made when the data deviates from a trend. In claim 2,
A digital input device characterized by having a function of monitoring data from the external device and forcibly determining the failure even if the data does not deviate from a trend. In claim 1,
A digital input device characterized in that when the result of the failure determination is a failure, the digital input device itself notifies a user or the CPU module is notified to stop a programmable logic controller. a base on which a data access bus can be used ; a plurality of digital input devices connected to the base; and a CPU module connected to the base and configured to access data to the digital input devices via the data access bus. Equipped with
The digital input device includes a data input circuit that inputs data from an external device, an internal circuit that is connected to the data access bus and supplies the data to the data access bus , and a combination of the data input circuit and the internal circuit. Equipped with a photocoupler placed between, an external disconnection circuit , and a test signal generation circuit,
The CPU module supplies each digital input device with a testable time, which is a time during which a test for failure determination can be performed during a refresh cycle, which is a cycle time during which the CPU module takes in the data, and a clock signal;
The digital input device electrically disconnects the external device with the external disconnection circuit based on the clock signal during a time when the data is not supplied to the CPU module;
The test signal generation circuit starts outputting a test signal to the internal circuit upon receiving a disconnection output from the external disconnection circuit, and upon receiving a reconnection output from the external disconnection circuit as a trigger. , by stopping the output of the test signal to the internal circuit, the test signal is supplied to the internal circuit while the external device is disconnected, and the internal circuit is configured to control the testable time to the CPU module. and supplying it to the test signal generation circuit, and performing a test for the failure determination using the test signal supplied from the test signal generation circuit during the testable time,
The test signal generation circuit includes:
Comparing the testable time and the test time for performing the test for failure determination,
If the test time is shorter than the testable time, the internal circuit performs the test for failure determination in one refresh cycle;
If the test time is greater than or equal to the testable time, calculate the number of pulses to be tested in one refresh cycle by dividing the testable time by the test time of one pulse;
Calculating the number of refresh cycles for performing the test for failure determination by dividing the total number of tests required for the failure determination by the number of pulses tested in one refresh cycle;
A programmable logic controller characterized in that the test for fault determination is performed by distributing the test signal to a plurality of the refresh cycles equal to the calculated number of the refresh cycles.

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