JP7439767B2 - Network interface card, computer, circuit information rewriting method and program - Google Patents

Description

[Description of related applications]
The present invention is based on the priority claim of Japanese patent application: Japanese Patent Application No. 2018-231098 (filed on December 10, 2018), and the entire contents of the application are incorporated and described in this document by reference. shall be taken as a thing.
The present invention relates to a network interface card, a computer, a method and program for rewriting circuit information.

Software virtualization is progressing in the operating facilities of telecommunications carriers, including large-scale data centers and VNFs (Virtual Network Functions), and configurations in which multiple systems are integrated on a single general-purpose server are becoming commonplace. There is. On the other hand, it has been pointed out that this type of configuration lacks performance in terms of communication functions that were implemented using software.

Under these circumstances, a product called a Smart NIC (SNIC) has appeared, which is a network interface card (hereinafter referred to as NIC) equipped with an FPGA (Field-Programmable Gate Array). This SNIC implements some modules in the SNIC as FPGA circuits for so-called packet processing, such as changing and forwarding packet headers and payloads, which were previously performed by the CPU, and whose performance cannot be achieved with software processing. There is. This is expected to eliminate software bottlenecks and improve performance.

Patent Documents 1 to 4 disclose methods for rewriting FPGA circuit information without interrupting communications or services in a communication device or the like equipped with an FPGA. Furthermore, Patent Documents 5 and 6 disclose methods for rewriting firmware and control programs without interrupting services.

JP2017-69777A International Publication No. 2017/170311 Japanese Patent Application Publication No. 2015-176343 Japanese Patent Application Publication No. 2008-177900 Japanese Patent Application Publication No. 2010-79837 Japanese Patent Application Publication No. 2007-202068

The following analysis is provided by the present invention. In devices such as the above-mentioned SNIC, although a large performance improvement can be expected, updating of circuit information of the FPGA may occur. While the circuit information is being updated, it is necessary to restart the FPGA and read the circuit information, so there is a problem that processing cannot be performed during this time. In this regard, Patent Document 1 discloses a configuration in which a plurality of communication processing circuits are configured in a variable area inside an FPGA, and one of the communication processing circuits is switched to operate, while the other circuit configuration can be updated.

However, in the configuration of Patent Document 1, two communication processing circuits are disposed in the variable region, which poses problems such as restrictions on circuit size and an increase in the cost of the device itself. This point also applies to Patent Documents 3, 5, and 6.

In addition, Patent Document 2 only discloses a configuration in which an FPGA is coupled to a CPU, in which the CPU performs VM data processing that was performed by the FPGA while the FPGA program is being upgraded. Furthermore, when considering application to SNIC, the method of Patent Document 2 cannot be adopted because it does not have an element that can substitute for FPGA processing. Further, the method of Patent Document 4 temporarily stops data transmission from the router during an FPGA upgrade, and cannot be said to not stop services to users in a narrow sense.

The present invention provides a network interface card, computer, and circuit information rewriting method that can contribute to reducing the impact on system availability caused by rewriting circuit information in a network interface card equipped with a programmable logic circuit represented by an FPGA. and programs.

According to a first viewpoint, a programmable logic circuit that processes input packets according to recorded circuit information; and a programmable logic circuit disposed at an input end and an output end of the programmable logic circuit, respectively; a pair of switches capable of switching between a first mode in which the packet is sent to the programmable logic circuit and a second mode in which the packet is bypassed without going through the programmable logic circuit; and a switch that processes the packet in place of the programmable logic circuit. a computer-side interface that transmits the packet to a computer equipped with a processor capable of executing a programmable application program; A network interface card is provided, comprising a switch control circuit for switching to a mode, and configured to allow the computer to process packets in place of the programmable logic circuit when rewriting the circuit information.

According to a second viewpoint, a computer equipped with the above network interface card is provided.

According to a third aspect, a programmable logic circuit that processes input packets according to recorded circuit information; and a programmable logic circuit that is arranged at an input end and an output end of the programmable logic circuit, respectively; a pair of switches capable of switching between a first mode in which the packet is sent to the programmable logic circuit and a second mode in which the packet is bypassed without going through the programmable logic circuit; and a switch that processes the packet in place of the programmable logic circuit. a computer-side interface that transmits the packet to a computer equipped with a processor capable of executing a programmable application program; a switch control circuit for switching to a mode, the method for rewriting the circuit information of a network interface card, comprising: starting an application program capable of executing packet processing in place of the programmable logic circuit; rewriting the circuit information by switching the switch from the first mode to the second mode and rewriting the circuit information, and then switching the pair of switches from the second mode to the first mode; A method is provided. The method is tied to a specific machine, a computer equipped with a network interface card.

According to a fourth aspect, a programmable logic circuit that processes input packets according to recorded circuit information; and a programmable logic circuit disposed at an input end and an output end of the programmable logic circuit, respectively; a pair of switches capable of switching between a first mode in which the packet is sent to the programmable logic circuit and a second mode in which the packet is bypassed without going through the programmable logic circuit; and a switch that processes the packet in place of the programmable logic circuit. a computer-side interface that transmits the packet to a computer equipped with a processor capable of executing a programmable application program; a switch control circuit for switching to a mode, a program for rewriting the circuit information of a network interface card, the program comprising: starting an application program capable of executing packet processing in place of the programmable logic circuit; A process of switching a pair of switches from the first mode to the second mode, and a process of switching the pair of switches from the second mode to the first mode after rewriting the circuit information. A program is provided that causes the computer to execute the following. Note that this program can be recorded on a computer-readable (non-transitory) storage medium. That is, the present invention can also be implemented as a computer program product.

According to the present invention, in a network interface card equipped with a programmable logic circuit, it is possible to reduce the impact on system availability caused by rewriting the circuit information. That is, the present invention converts the network interface card described in the background art into one in which availability is less likely to be impaired due to rewriting of circuit information.

FIG. 1 is a diagram showing the configuration of an embodiment of the present invention. FIG. 3 is a diagram for explaining the operation of an embodiment of the present invention. FIG. 3 is a diagram for explaining the operation of an embodiment of the present invention. FIG. 1 is a diagram showing the configuration of a first embodiment of the present invention. 3 is a flowchart showing the operation of the first embodiment of the present invention. 2 is a flowchart showing details of an FPGA update process according to the first embodiment of the present invention. It is a figure showing the composition of the 2nd embodiment of the present invention. It is a flowchart showing the operation of the second embodiment of the present invention. It is a figure showing the composition of the 3rd embodiment of the present invention. 1 is a diagram showing the configuration of a computer equipped with a network interface card of the present invention.

First, an overview of an embodiment of the present invention will be described with reference to the drawings. Note that the drawing reference numerals added to this summary are added to each element for convenience as an example to aid understanding, and are not intended to limit the present invention to the illustrated embodiment. Furthermore, connection lines between blocks in the drawings and the like referred to in the following description include both bidirectional and unidirectional connections. The unidirectional arrows schematically indicate the main signal (data) flow, and do not exclude bidirectionality. Also, ports or interfaces are provided at the input/output connection points of each block in the figure, but they are not shown. The program is executed via a computer device, and the computer device includes, for example, a processor, a storage device, an input device, a communication interface, and, if necessary, a display device. Further, the computer device is configured to be able to communicate with equipment within the device or externally (including a computer) via a communication interface, regardless of whether it is wired or wireless. Furthermore, in the following description, "A and/or B" is used to mean at least one of A and B.

In one embodiment of the present invention, as shown in FIG. 1, the present invention includes a programmable logic circuit 11, a pair of switches 12 and 13, a computer side interface (IF) 14, and a switch control circuit 15. This can be realized using the network interface card 10.

More specifically, the programmable logic circuit 11 processes input packets according to recorded circuit information. Switches 12 and 13 are arranged at the input and output ends of the programmable logic circuit 11, respectively. The switches 12 and 13 are configured to be able to switch between a first mode in which packets are sent to the programmable logic circuit 11 and a second mode in which packets are bypassed without going through the programmable logic circuit 11. In place of the programmable logic circuit 11, the computer 20 is equipped with a processor capable of executing an application program capable of processing packets. The computer side interface (IF) 14 is capable of transmitting packets to the computer 20. The switch control circuit 15 is capable of switching the pair of switches 12 and 13 to the second mode when rewriting the circuit information of the programmable logic circuit 11. In the above configuration, the network interface card 10 uses the computer to process packets instead of the programmable logic circuit 11 when rewriting the circuit information.

For example, during normal operation, a pair of switches 12, 13 are set to a first mode that sends packets to programmable logic circuit 11, as shown in FIG. As a result, similar to the SNIC described above, software bottlenecks are eliminated and performance can be expected to improve.

On the other hand, when rewriting the circuit information of the programmable logic circuit 11, the pair of switches 12 and 13 are switched to the second mode, as shown in FIG. Then, while the circuit information of the programmable logic circuit 11 is being rewritten, the computer processes the packet instead of the programmable logic circuit 11. Therefore, it is possible to rewrite the circuit information of the programmable logic circuit 11 without stopping the service to the user.

[First embodiment]
Next, a first embodiment of the present invention will be described in detail with reference to the drawings. FIG. 4 is a diagram showing the configuration of the first embodiment of the present invention. Referring to FIG. 4, a detailed configuration of an IA server 200 equipped with the SNIC 100 and a program group (APL/OS) 210 running on the IA server 200 is shown. Note that the IA server 200 is an abbreviation for Intel Architecture server. Furthermore, APL/OS is an abbreviation for Application and Operating System, respectively.

APP201 in FIG. 4 indicates a packet processing program main body that processes packets exchanged with the network side using the SNIC 100. The APP 201 uses the NIC Driver 203 to send and receive packets on the SNIC 100 . Further, the APP 201 can control and manage the circuit information of the FPGA 111 via the FPGA Driver 204.

The APP 201 instructs the S-SW 112 and N-SW 113 via the FPGA Driver 204 regarding rules for switching operation modes and identifying exceptional packets (described later). Further, the APP 201 manages starting and stopping the Alt-SIM 202 . Specifically, the APP 201 activates the Alt-SIM 202 before starting the update of the FPGA 111, and controls the Alt-SIM 202 to perform a series of packet processing instead of the FPGA 111. Further, upon receiving the activation notification of the FPGA 111, the APP 201 stops the Alt-SIM 202 when the Alt-SIM 202 becomes unnecessary.

Further, the APP 201 has a function of assisting memory synchronization between the Alt-SIM 202 and the FPGA 111, which synchronizes memory contents such as packet count information of the FPGA 111. For this memory synchronization, for example, a method may be adopted in which a memory space for synchronization with the FPGA 111 is prepared on the OS, and information in the DRAM 118 is synchronized by periodically exchanging packets with the modules 120 (described later) in the FPGA 111. can. Furthermore, the APP 201 has a function of passing a synchronized memory area (space) prepared in the OS to the Alt-SIM 202 in order to complete memory synchronization before starting the update of the FPGA 111. Furthermore, the APP 201 performs memory synchronization between the Alt-SIM 202 and the FPGA 111 before switching processing to the FPGA 111. A packet for memory synchronization with the modules 120 (described later) at this time is called an exception packet. A specific example of the exception packet will be detailed later.

The NIC Driver 203 is a driver that controls packet transmission and reception of the SNIC 100.

The FPGA Driver 204 is a driver for controlling the FPGA 111 within the SNIC 100. Updating the circuit information of the FPGA, etc. can be executed using this driver. Further, the FPGA Driver 204 notifies the APP 201 of completion of startup of the FPGA 111 and the like.

The CPU/RAM 205 represents a general group of physical components that constitute a computer typified by the IA server 200 (see FIG. 10). Note that CPU is an abbreviation for Central Processing Unit, and RAM is an abbreviation for Random Access Memory.

Next, the configuration of the SNIC 100 will be explained. Referring to FIG. 4, a configuration including an FPGA 111, an S-SW 112, an N-SW 113, an Ether Network Controller 114, a PCIE Controller 115, a QSFP 117, and a FLASH 119 is shown.

The FPGA 111 includes an area (Writable FPGA) 116 that can be rewritten with arbitrary circuit information and a permanent circuit, and processes input packets according to processing logic defined by the circuit information. Furthermore, at startup, the FPGA loads circuit information from the FLASH 119 and writes the circuit information into a rewritable area (Writable FPGA) 116 . In FIG. 4, this circuit information is shown as modules 120. The FPGA 111 has dedicated interfaces with the FLASH 119, PCIE Controller 115, and DRAM 118. In FIG. 4, these are indicated as FLASH-IF, PCIE-IF, and RAM-IF, respectively.

The Ether Network Controller 114 is a dedicated hardware chip that performs low layer network processing within the SNIC 100. The Ether Network Controller 114 provides an interface with the above-mentioned OS and various drivers. Therefore, the Ether Network Controller 114 takes on the function of the computer-side interface (IF) 14 described above.

PCIE Controller 115 is a hardware module for controlling FPGA 111. Specifically, the PCIE Controller 115 instructs the FPGA 111 to restart the FPGA 111 and update its circuit information under control from the FPGA Driver. Further, the PCIE Controller 115 notifies the state of the FPGA 111 to the APP 201 via the FPGA Driver. The PCIE Controller 115 also functions as a switch control circuit (see switch control circuit 15) that switches the S-SW 112 and N-SW 113 according to instructions from the APP 201.

The FLASH 119 is composed of a non-volatile flash memory and holds circuit information of the FPGA 111. Rewriting of the FLASH 119 can be performed by writing to the FLASH 119 from an external storage medium or the like via the OS on the CPU or the NIC Driver 203.

DRAM 118 is a Dynamic RAM included in SNIC 100. DRAM 118 is generally volatile and is used by modules 120 in FPGA 111 to store temporary information for processing.

The modules 120 are processing logic written in the rewritable area (Writable FPGA) 116 of the FPGA 111 . The modules 120 function as an offload destination for part of the processing of the APP 201, thereby eliminating the software bottleneck of the entire system. Furthermore, the modules 120 has a mechanism for packetizing information in the DRAM and performing memory synchronization with the Alt-SIM 202 via the APP 201 by exchanging packets with the APP 201 .

The QSFP 117 is an interface for inputting packets to the SNIC 100. This QSFP 117 becomes a cable connection point. Note that QSFP is an abbreviation for Quad Small Form-factor Pluggable and is a transceiver standard.

Next, a configuration for continuing packet processing while updating the circuit information of the FPGA 111 described above will be described.

The S-SW 112 is a module that determines and executes whether to transfer a packet (upstream packet) received from the outside via the QSFP 117 of the SNIC 100 to the FPGA 111 or to the N-SW 113 without passing through the FPGA 111. Further, the S-SW 112 has a function of transferring a packet (downstream packet) received from the N-SW 113 or the FPGA 111 to outside the SNIC via the QSFP 117.

The S-SW 112 has the following two operating modes, and the operating mode can be switched by the APP 201 via the PCIE Controller 115.

A) FPGA via mode (corresponding to the first mode):
The S-SW 112 transfers the upstream packet to the FPGA 111.
B) Bypass mode (corresponds to the second mode):
The S-SW 112 transfers all upstream packets other than exception packets to the N-SW 113, and transfers the exception packets to the FPGA 111. Here, the exception packet refers to a packet that matches a rule instructed by the APP 201 via the PCIE Controller 115. For example, a packet having a specific VLAN ID (VID), a specific MAC address, etc. can be specified as an exception packet, and the corresponding packet can be sent to the FPGA 111. In this embodiment, this exception packet is used for memory synchronization. The details will be described later.

The N-SW 113 is a module that determines and executes whether to transfer a packet (downlink packet) received from the Ether Network Controller 114 to the FPGA 111 or to the S-SW 112 without passing through the FPGA 111. Further, the N-SW 113 has a function of transferring a packet (upstream packet) received from the FPGA 111 or the S-SW 112 of the SNIC 100 to the Ether Network Controller 114.

The N-SW 113 has the following two operating modes, and like the S-SW 112, the operating mode can be switched by the APP 201 via the PCIE Controller 115.

A) FPGA via mode (corresponds to the first mode):
The N-SW 113 transfers the downlink packet to the FPGA.
B) Bypass mode (corresponds to the second mode):
The N-SW 113 transfers all downstream packets other than the exception packet to the S-SW 112, and transfers the exception packet to the FPGA 111. Here, the exception packet refers to a packet that matches a rule instructed by the APP 201 via the PCIE Controller 115. For example, a packet having a specific VLAN ID (VID), a specific MAC address, etc. can be specified as an exception packet, and the corresponding packet can be sent to the FPGA 111.

The Alt-SIM 202 is an alternative module (computer program) that performs the same processing as the modules 120 in the FPGA 111. It can be switched and used when the modules 120 in the FPGA 111 cannot operate. However, the processing performance of the Alt-SIM 202 may be lower than that of the Alt-SIM 202 of the FPGA 111.

Next, the operation of this embodiment will be explained in detail with reference to the drawings. FIG. 5 is a flowchart showing the operation of the first embodiment of the present invention. Referring to FIG. 5, first, the APP 201 activates the Alt-SIM 202 in order to update the circuit of the FPGA 111 (step S001).

Next, the APP 201 performs memory synchronization with the FPGA 111 (step S002). This memory synchronization can be performed by reflecting the difference from the last synchronization.

Next, after confirming the activation of the Alt-SIM 202, the APP 201 passes the memory area that has been synchronized with the FPGA 111 to the Alt-SIM 202 (step S003). Thereafter, the Alt-SIM 202 is in a state where it can execute the same processing as the modules 120.

Next, the APP 201 switches the N-SW 113 and the S-SW 112 to bypass mode via the FPGA Driver 204 (step S004). At this time, in order to pass the memory synchronization packet, the APP 201 specifies a rule for specifying the exception packet for memory synchronization to the N-SW 113 and S-SW 112.

Next, the APP 201 switches its operation to process the packet received from the NIC Driver 203 using the Alt-SIM 202 (step S005). Specifically, a process is performed in which the packet received from the NIC Driver 203 is passed to the Alt-SIM 202, and the packet output from the Alt-SIM 202 is sent to the N-SW 113 side.

Next, the APP 201 instructs the FPGA Driver 204 to update the FPGA 111 (step S006). Thereafter, circuit information is updated on the FPGA 111 side.

FIG. 6 is a flowchart showing details of update processing of the FPGA 111 in this embodiment. When the FPGA Driver 204 receives an update instruction for the FPGA 111 from the APP 201 (Step S101), the FPGA Driver 204 downloads new circuit information and places it in the FLASH 119 (Step S102).

Next, the FPGA driver 204 instructs the FPGA 111 to restart (step S103).

Next, the FPGA 111 restarts and loads new circuit information from the FLASH 119 (step S104).

Thereafter, the FPGA 111 starts operating using the new circuit information (step S105). The FPGA Driver 204 notifies the APP 201 of the completion of startup of the FPGA 111 (step S106).

Referring again to FIG. 5, the operation of the FPGA 111 after startup is completed will be described. When the APP 201 receives the activation completion notification of the FPGA 111 (step S008), it performs memory synchronization between the Alt-SIM 202 and the FPGA 111 (step S009).

After the memory synchronization is completed, the APP 201 instructs the FPGA Driver 204 to switch the S-SW 112 and N-SW 113 to the FPGA mode (step S010).

Finally, the APP 201 stops the Alt-SIM 202 (step S011).

As explained above, according to this embodiment, even while the circuit information of the FPGA 111 is being updated, the S-SW 112 and N-SW 113 continue to transfer packets, the alternative module processes the packets, and the service continues. be able to. Specifically, even when the FPGA 111 shown in FIG. 6 is updated, the Alt-SIM 202 continues processing as an alternative module, thereby preventing the service from completely stopping. Further, as is clear from the above description, this embodiment has the advantage that the rewritable area 116 of the FPGA 111 can be fully utilized, even in comparison with the method described in the patent document described in the background art. .

Note that in the above embodiment, exception packets are set in the bypass mode of the S-SW 112 and N-SW 113 for memory synchronization, but a virtual switch may be interposed between the SNIC 100 and the APP 201. is assumed. In this case, appropriate settings can be made to allow the exception packet to pass through the virtual switch as well. For example, an appropriate instruction may be issued to an SDN (Software Defined Network) controller that controls the virtual switch. Even in this case, memory synchronization can be performed by treating the memory synchronization packet independently from other packets.

[Second embodiment]
Next, a second embodiment of the present invention in which the configuration for performing memory synchronization is modified will be described in detail with reference to the drawings. FIG. 7 is a diagram showing the configuration of the second embodiment of the present invention. The difference from the first embodiment shown in FIG. 4 is that a module called D-CTRL 121 is added between the DRAM 118 and the FPGA 111. Further, in accordance with this, changes have been made to the PCIE Controller 115a and the APP 201a. Since the other configurations are basically the same as those of the first embodiment, the differences will be mainly described below.

This embodiment utilizes the characteristic that the DRAM 118 is energized even when the FPGA 111 is restarted, and the internal storage information does not disappear. That is, by having the Alt-SIM 202 directly refer to the DRAM 118 even while the FPGA 111 is being restarted, memory synchronization itself can be omitted. After the startup of the FPGA 111 is completed, the FPGA 111 can continue processing by reattaching the DRAM 118 to the FPGA.

The D-CTRL 121 is a module (memory control unit) that controls access from the FPGA 111 or Alt-SIM 202 to the DRAM 118. The D-CTRL 121 is also connected to the PCIE Controller 115a. The D-CTRL 121 only allows access from the FPGA 111 during normal times. When there is an instruction from the PCIE Controller 115a, the D-CTRL 121 performs control to allocate part or all of the area of the DRAM 118 to an application on the OS represented by the Alt-SIM 202.

PCIE Controller 115a is a hardware module for controlling FPGA 111. Specifically, the PCIE Controller 115a instructs the FPGA 111 to restart the FPGA 111 and update its circuit information under control from the FPGA Driver. Further, the PCIE Controller 115a notifies the state of the FPGA 111 to the APP 201a via the FPGA Driver. The PCIE Controller 115a also functions as a switch control circuit (see switch control circuit 15) that switches the S-SW 112 and N-SW 113 according to instructions from the APP 201a.

Furthermore, the PCIE Controller 115a of this embodiment instructs the D-CTRL 121 to switch the access entity to the DRAM. Specifically, the PCIE Controller 115a changes the entity that can access the DRAM 118 from the FPGA 111 to the Alt-SIM 202. Furthermore, the PCIE Controller 115a changes the entity that can access the DRAM 118 from the Alt-SIM 202 to the FPGA 111.

The APP 201a issues an instruction via the FPGA Driver 204 to make the memory area of the DRAM 118 accessible to the application. This allows the Alt-SIM 202 to directly refer to the DRAM 118. Further, the APP 201a performs processing to return the memory area of the DRAM 118 to a state where it can be referenced from the FPGA 111 via the FPGA Driver 204.

Next, the operation of this embodiment will be explained in detail with reference to the drawings. FIG. 8 is a flowchart showing the operation of the second embodiment of the present invention. Referring to FIG. 8, first, the APP 201a activates the Alt-SIM 202 in order to update the circuit of the FPGA 111 (step S201).

Next, the APP 201a switches the access entity of the DRAM 118 to the application (step S202). This instruction is given via the FPGA Driver 204, PCIE Controller 115a, and D-CTRL 121.

Next, the APP 201a confirms the activation of the Alt-SIM 202 and gives the Alt-SIM 202 access rights to the DRAM 118 (Step S203). Thereafter, the Alt-SIM 202 is in a state where it can execute the same processing as the modules 120.

Next, the APP 201a switches the N-SW 113 and the S-SW 112 to bypass mode via the FPGA Driver 204 (step S204).

Next, the APP 201a switches its operation to process the packet received from the NIC Driver 203 using the Alt-SIM 202 (step S205). Specifically, a process is performed in which the packet received from the NIC Driver 203 is passed to the Alt-SIM 202, and the packet output from the Alt-SIM 202 is sent to the N-SW 113 side.

Next, the APP 201a instructs the FPGA Driver 204 to update the FPGA 111 (step S206). Thereafter, circuit information is updated on the FPGA 111 side. Updating of circuit information on the FPGA 111 side is the same as in the first embodiment, and therefore a description thereof will be omitted.

When the APP 201a receives the activation completion notification of the FPGA 111 (step S208), the APP 201a returns the access subject of the DRAM 118 from the Alt-SIM 202 to the FPGA 111 (step S209). This allows the FPGA 111 to refer to the DRAM 118 from now on.

After that, the APP 201a instructs the FPGA Driver 204 to switch the S-SW 112 and N-SW 113 to the FPGA mode (step S210).

Finally, the APP 201a stops the Alt-SIM 202 (step S211).

As explained above, even in the second embodiment, the S-SW 112 and N-SW 113 continue to transfer packets even while the circuit information of the FPGA 111 is being updated, and the alternative module processes the packets, thereby providing services. Can be continued. Specifically, even when the FPGA 111 shown in FIG. 6 is updated, the Alt-SIM 202 continues processing as an alternative module, thereby preventing the service from completely stopping. Furthermore, in comparison with the first embodiment, there is an advantage that processing of exception packets for memory synchronization can be omitted.

Although each embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiments, and may be further modified, replaced, or adjusted without departing from the basic technical idea of the present invention. can be added. For example, the network configuration, the configuration of each element, and the form of message expression shown in each drawing are examples to help understand the present invention, and the present invention is not limited to the configuration shown in these drawings.

For example, the present invention is also applicable to a type of SNIC in which the functions of the NIC chip are also realized by FPGA. In this case, the S-SW 112a and the N-SW 113a are arranged at the input/output end of the rewritable area (Writable FPGA) 116 in the FPGA 111, as shown in FIG. 9 (third embodiment).

Further, the functions implemented in the FPGA 111 of each embodiment described above are not limited to communication processing such as communication encryption and packet ordering. For example, the FPGA 111 may be responsible for higher layer processing as described below.

(1) Web service The present invention is also applicable to, for example, a SNIC that realizes a Web service in which dynamic Web content is generated by a circuit on the FPGA 111 and static content is responded to by the APP 201 on the IA server 200 side. It is possible.

Generally, dynamic web content creation uses more CPU resources, so by implementing a circuit that generates dynamic web pages on the FPGA 111, it is possible to speed up the response and improve the user experience. You can expect it.
For example, dynamic web page creation is performed by accessing an external DB (database) to obtain user registration information (purchase history, etc.) or by calling an API (Application Programming Interface) of an external service. In this way, dynamic Web page generation often involves using other services via a network. By implementing these functions in the FPGA 111 in the SNIC, further performance improvement can be expected.

At this time, the web service session manages not only the context information of the security layer such as SSL/TLS, but also the context of the user session (for example, even if you press the back button of the browser, the screen transition that is impossible for that user session) Therefore, the web service may not be able to generate the same web page as before). Note that SSL and TLS are abbreviations for Secure Sockets Layer and Transport Layer Security, respectively.

For the SNIC of the present invention, this context information is maintained on DRAM 118 within SNIC 100. By configuring this context information to be synchronized with an alternative module (equivalent to the above Alt-SIM 202) that generates an alternative dynamic web page, it is possible to avoid user session interruption even when updating the circuit within the FPGA 111. . This also has the advantage that the user does not have to worry about logging into the Web service again.

(2) Image recognition application As a driving support service, it is envisaged that a service will be provided that analyzes and processes videos taken with an in-vehicle camera at a mobile edge data center, recognizes dangerous objects, and notifies nearby vehicles. The present invention is also applicable to SNICs that implement such services.

At this time, by implementing image analysis processing in the FPGA 111, performance (for example, number of recognition items/second) can be improved. Improving this image recognition engine requires daily updates, but by applying the present invention, it becomes possible to update the image recognition engine without stopping the service. Note that, at this time, it is also preferable to decide the update timing of the image recognition engine, taking into consideration the characteristics of the service. For example, in the case of cars, there is a characteristic that the number of users (number of cars) is small at night. Using this, it is possible to update the analysis engine at night, when performance degradation is acceptable, while avoiding service interruptions.

Further, the IA server of the first to third embodiments described above is exemplified in a configuration including a CPU (Central Processing Unit) 9010, a communication interface 9020, a memory 9030, and an auxiliary storage device 9040 in FIG.

Finally, preferred embodiments of the present invention will be summarized.
[First form]
(Refer to the network interface card from the first perspective above)
[Second form]
The pair of switches on the network interface card described above are
In the second mode, a configuration may be adopted that operates to send a packet for memory synchronization with the computer side to the programmable logic circuit.
[Third form]
The pair of switches of the network interface card described above may be arranged at the input end and the output end of the variable area inside the programmable logic circuit, respectively.
[Fourth form]
The above-mentioned network interface card further includes:
The application program may include a memory control unit that allows the programmable logic circuit to access the memory used to temporarily store information.
[Fifth form]
The programmable logic circuit of the network interface card described above is configured to be able to take over the processing performed by the computer after the circuit information is rewritten by taking over the information in the memory from the memory control unit. It is preferable.
[Sixth form]
(Refer to the computer from the second viewpoint above)
[Seventh form]
(Refer to the method for rewriting circuit information from the third viewpoint above)
[Eighth form]
(See the program from the fourth perspective above)
Note that the sixth to eighth forms described above can be developed into second to fifth forms, similar to the first form.

In addition, each disclosure of the above-mentioned patent documents is incorporated into this book by reference. Within the scope of the entire disclosure of the present invention (including the claims), changes and adjustments to the embodiments and examples are possible based on the basic technical idea thereof. In addition, various combinations or selections (parts) of various disclosed elements (including each element of each claim, each element of each embodiment or example, each element of each drawing, etc.) within the framework of the disclosure of the present invention are also available. (including deletion) is possible. That is, it goes without saying that the present invention includes the entire disclosure including the claims and various modifications and modifications that a person skilled in the art would be able to make in accordance with the technical idea. In particular, numerical ranges stated herein should be construed as specifically stating any numerical value or subrange within the range, even if not otherwise stated. Furthermore, each of the disclosures in the documents cited above may be used, in part or in whole, in combination with the statements in this book as part of the disclosure of the present invention, if necessary, in accordance with the spirit of the present invention. It is deemed to be included in the disclosure of this application.

10 Network interface card 11 Programmable logic circuit 12, 13 Switch 14 Computer side interface (IF)
15 Switch control circuit 20 Computer 100, 100a, 100b SNIC
111 FPGA
112, 112a S-SW
113, 113a N-SW
114 Ether Network Controller
115, 115a PCIE Controller
116 Writable area (Writable FPGA)
117 QSFP
118 DRAM
119 FLASH
120 modules
121 D-CTRL
200 IA server 201, 201a APP
202 Alt-SIM
203 NIC Driver
204 FPGA Driver
205 CPU/RAM
210 Program group (APL/OS)
9000 Computer 9010 CPU
9020 Communication interface 9030 Memory 9040 Auxiliary storage device

Claims (9)

a programmable logic circuit that processes input packets according to recorded circuit information;
A first mode that is arranged at an input end and an output end of the programmable logic circuit and sends a packet to the programmable logic circuit, and a second mode that bypasses the programmable logic circuit without going through the programmable logic circuit. A pair of switchable switches,
a computer-side interface that transmits the packet to a computer equipped with a processor capable of executing an application program capable of processing the packet in place of the programmable logic circuit;
a switch control circuit that switches the pair of switches to a second mode when rewriting the circuit information of the programmable logic circuit;
A network interface card configured to allow the computer to process packets in place of the programmable logic circuit when the circuit information is rewritten. The pair of switches are:
2. The network interface card of claim 1, operative in said second mode to send a packet to said programmable logic circuit for memory synchronization with said computer side. 3. The network interface card according to claim 1, wherein said pair of switches are arranged at an input end and an output end of a variable area inside said programmable logic circuit, respectively. 2. The network interface card according to claim 1, further comprising a memory control unit that allows access from the application program side to a memory used by the programmable logic circuit to temporarily store information. 5. The network interface according to claim 4, wherein the programmable logic circuit is configured to be able to take over the processing performed by the computer after rewriting the circuit information by taking over the information of the memory from the memory control unit. card. a programmable logic circuit that processes input packets according to recorded circuit information;
A first mode that is arranged at an input end and an output end of the programmable logic circuit and sends a packet to the programmable logic circuit, and a second mode that bypasses the programmable logic circuit without going through the programmable logic circuit. A pair of switchable switches,
a computer-side interface that transmits the packet to a connected computer;
a switch control circuit that switches the pair of switches to a second mode when rewriting the circuit information of the programmable logic circuit;
A computer equipped with a network interface card configured to enable the computer to process packets in place of the programmable logic circuit when rewriting the circuit information. 7. The computer of claim 6, operative to send memory synchronization packets to the programmable logic circuit in the second mode. a programmable logic circuit that processes input packets according to recorded circuit information;
A first mode that is arranged at an input end and an output end of the programmable logic circuit and sends a packet to the programmable logic circuit, and a second mode that bypasses the programmable logic circuit without going through the programmable logic circuit. A pair of switchable switches,
a computer-side interface that transmits the packet to a computer equipped with a processor capable of executing an application program capable of processing the packet in place of the programmable logic circuit;
A method for rewriting the circuit information of a network interface card, comprising: a switch control circuit that switches the pair of switches to a second mode when rewriting the circuit information of the programmable logic circuit;
activating an application program capable of processing packets in place of the programmable logic circuit;
switching the pair of switches from the first mode to the second mode;
after rewriting the circuit information, switching the pair of switches from the second mode to the first mode;
How to rewrite circuit information. a programmable logic circuit that processes input packets according to recorded circuit information;
A first mode that is arranged at an input end and an output end of the programmable logic circuit and sends a packet to the programmable logic circuit, and a second mode that bypasses the programmable logic circuit without going through the programmable logic circuit. A pair of switchable switches,
a computer-side interface that transmits the packet to a computer equipped with a processor capable of executing an application program capable of processing the packet in place of the programmable logic circuit;
A program for rewriting the circuit information of a network interface card, comprising: a switch control circuit that switches the pair of switches to a second mode when rewriting the circuit information of the programmable logic circuit;
activating an application program capable of processing packets in place of the programmable logic circuit;
a process of switching the pair of switches from the first mode to the second mode;
after rewriting the circuit information, switching the pair of switches from the second mode to the first mode;
A program that causes the computer to execute.

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