JP7416345B1 - Power amplifier and bias circuit - Google Patents

Abstract

A power amplifier according to the present disclosure includes a plurality of transistors connected in series and a bias circuit, the bias circuit including a step-down circuit that steps down a power supply voltage, and a resistor circuit connected to the output of the step-down circuit. and between the gate terminals of adjacent transistors from the second transistor next to the first transistor connected to the ground terminal side to the last transistor connected to the power terminal side. , a plurality of first resistors connected between the gate terminal of the second transistor and the ground terminal, and the step-down circuit has a first value when the control signal is a second value. The configuration is such that the amount of pressure drop is greater than when

Description

TECHNICAL FIELD This disclosure relates to power amplifiers and bias circuits.

Non-Patent Document 1 discloses a technique for operating a CMOS (Complementary Metal-Oxide-Semiconductor) as a power amplifier.

S. Pornpromlikit, et al. , A Watt-Level Stacked-FET Linear Power Amplifier in Silicon-on-Insulator CMOS, IEEE Transactions on Microwave Theory and T echniques, vol. 58, no. 1, pp. 57-64, Jan. 2010.

Power amplifiers for mobile terminals mainly use GaAs HBTs (Heterojunction Bipolar Transistors). The reasons for this are that it is normally off and can operate with a single power supply, and that it can operate with a Li-ion battery voltage of 3.7V. Furthermore, a power amplifier using a GaAs HBT has a higher power density than a GaAs FET (Field Effect Transistor) in an output power range of about several watts. Therefore, the chip area can be reduced when the power amplifier is made into an integrated circuit. Furthermore, a much higher yield can be achieved compared to GaAs-based FETs.

However, recent power amplifiers, band switching switches, and antenna switches generally include a CMOS control circuit that enables digital control in addition to the GaAs HBT in order to simplify control within the terminal. GaAs HBT chips, which are not Si-based, are difficult to integrate with digital control circuits. Furthermore, GaAs HBT chips are more expensive to mass produce than CMOS chips. Against this background, there has been a strong desire for CMOS power amplifiers.

The standard voltage for a CMOS FET is 1.2V for a 65nm process and 1.8V for a 0.18μm process, which is considerably lower than the battery voltage of 3.7V. Therefore, the battery voltage cannot be directly used in a power amplifier configured with one stage of CMOS FETs. Against this background, stacked power amplifiers that are capable of operating CMOS as a power amplifier at as high a power supply voltage as possible are attracting attention, as shown in Non-Patent Document 1, for example.

However, in a stacked power amplifier, if the gate voltage of the transistor is set to zero in the standby state, there is a possibility that a voltage that significantly exceeds the withstand voltage value will be applied as the gate-drain voltage or drain-source voltage of the transistor. Ta.

An object of the present disclosure is to obtain a power amplifier and a bias circuit that can provide a voltage that does not exceed a breakdown voltage to a transistor.

A power amplifier according to the present disclosure each has a source terminal, a drain terminal, and a gate terminal, and the drain terminal and source terminal of adjacent transistors are connected to a power supply terminal that provides a power supply voltage and a grounding terminal. a plurality of transistors connected in series with a terminal for use with the terminal, and when a control signal input from the outside is a first value, the plurality of transistors are in an operating state, and when the control signal is a second value, the plurality of transistors are in an operating state. a bias circuit configured to supply gate voltage to gate terminals of the plurality of transistors so that the plurality of transistors are in a standby state, and in the operating state, the plurality of transistors are in a standby state. Amplify the signal input from the gate terminal of the first transistor that is connected to the ground terminal side among the transistors, and amplify the signal input from the gate terminal of the first transistor that is connected to the ground terminal side among the plurality of transistors. The bias circuit includes a step-down circuit that steps down the power supply voltage, and a resistor circuit connected to the output of the step-down circuit, and the resistor circuit is connected to the first one of the plurality of transistors. A plurality of first resistors are connected between gate terminals of adjacent transistors from a second transistor next to the transistor to the final transistor, and between the gate terminal of the second transistor and a ground terminal. , the step-down circuit includes a source follower connected between a terminal that provides the power supply voltage and the resistor circuit, and the bias circuit controls the voltage of the first voltage when the control signal is the second value. By being configured such that the gate voltage of the source follower is smaller than when the control signal is at the second value, the step- down circuit lowers the voltage at a lower voltage when the control signal is at the second value than at the first value. It is designed to increase the amount.

A bias circuit according to the present disclosure includes a step-down circuit that steps down a power supply voltage, and a resistor circuit connected to the output of the step-down circuit, which is connected in series between a power supply terminal that provides the power supply voltage and a ground terminal. The plurality of transistors connected to the plurality of transistors are in an operating state when a control signal input from the outside has a first value, and are in a standby state when the control signal is a second value. is configured to supply a gate voltage to the gate terminal of the plurality of transistors, and in the operating state, the plurality of transistors are configured to supply a gate voltage to the gate terminal of the first transistor connected to the grounding terminal side most among the plurality of transistors. The signal is amplified and outputted from the drain terminal of the last transistor connected to the power supply terminal side among the plurality of transistors, and the resistor circuit The step-down circuit includes a plurality of first resistors connected between the gate terminals of adjacent transistors from the transistor to the final transistor and between the gate terminal and the ground terminal of the second transistor, a source follower connected between a terminal for providing the power supply voltage and the resistor circuit; By being configured so that the gate voltage of the follower is small, the step-down circuit is configured such that when the control signal is at the second value, the voltage step-down amount is larger than when the control signal is at the first value. has been done.

In the power amplifier and bias circuit according to the present disclosure, gate voltages of transistors in an operating state and a standby state can be provided by changing the step-down amount of the step-down circuit. Therefore, a voltage that does not exceed the withstand voltage can be provided to the transistor.

1 is a diagram illustrating a circuit configuration of a power amplifier according to Embodiment 1. FIG. FIG. 2 is a diagram illustrating a circuit configuration of a cascode power amplifier according to a comparative example. FIG. 3 is a diagram illustrating a bias state of a cascode power amplifier according to a comparative example. FIG. 2 is a diagram illustrating the configuration of stacked amplification stages in a four-stage stacked power amplifier. FIG. 7 is a diagram illustrating an example in which the bias circuit of a cascode power amplifier according to a comparative example is modified for use in a stacked power amplifier. FIG. 3 is a diagram illustrating an example of a bias state of the power amplifier according to the first embodiment. FIG. 3 is a diagram illustrating a circuit configuration of a power amplifier according to a second embodiment. FIG. 7 is a diagram illustrating a circuit configuration of a power amplifier according to a third embodiment.

A power amplifier and a bias circuit according to each embodiment will be described with reference to the drawings. Identical or corresponding components may be given the same reference numerals and repeated descriptions may be omitted.

Embodiment 1.
FIG. 1 is a diagram illustrating a circuit configuration of a power amplifier 100 according to the first embodiment. Power amplifier 100 includes a plurality of transistors Ma1, Ma2, Ma3, Ma4 and a bias circuit 50. Each of the transistors Ma1 to Ma4 is an FET. Each of the plurality of transistors Ma1 to Ma4 has a source terminal, a drain terminal, and a gate terminal. The plurality of transistors Ma1 to Ma4 are connected in series between the power supply terminal 10 that provides the power supply voltage Vdd and the ground terminal GND by connecting the drain terminals and source terminals of adjacent transistors. The plurality of transistors Ma1 to Ma4 constitute a stacked amplification stage 80.

The CMOS process of the stacked amplification stage 80 is, for example, 65 nm CMOS, and the standard breakdown voltage is, for example, 1.2V. The transistors Ma1 to Ma5 are 65 nm nMOS with a withstand voltage of 1.2V. For example, a 5V CMOS can be used for the bias circuit 50. In the bias circuit 50, the transistors Mc1 to Mc4 are pMOS with a withstand voltage of 5V, and the transistors Mb1 to Mb4 are nMOS with a withstand voltage of 5V.

The capacitors C2 to C4 are capacitors that connect the gates of the stacked transistors Ma2 to Ma4 to GND in terms of RF (Radio Frequency). Capacitors C2-C4 do not have their gates completely grounded in terms of RF as in a common gate amplifier. The capacitance values of the capacitors C2 to C4 are set such that Vg2 to Vg4 vary in conjunction with the drain voltages of the transistors Ma2 to Ma4 at the operating frequency.

The bias circuit 50 is configured to supply gate voltages to the gate terminals of the plurality of transistors Ma1 to Ma4 in response to a control signal Ven inputted from the outside. When the control signal Ven is at the first value, a predetermined bias current Id flows through the plurality of transistors Ma1 to Ma4, and a gate voltage is supplied so that the transistors are in an operating state. When the control signal Ven is at the second value, the gate voltage is supplied so that the bias current Id becomes 0 and the plurality of transistors Ma1 to Ma4 enter a standby state. Thereby, unnecessary current consumption can be suppressed when the power amplifier 100 does not perform an amplification operation. In the example of FIG. 1, the first value of the control signal Ven is High and the second value is Low. The terminal Ven to which the control signal Ven is input is generally also called an enable terminal.

The bias circuit 50 includes a reference current source Iref for causing a predetermined current to flow through the first transistor Ma1 in an operating state. Transistors Mc3 and Mc4 constitute a current mirror. Therefore, a current I1 having a value corresponding to the reference current source Iref flows. Further, transistors Ma5 and Ma1 constitute a current mirror. Therefore, a bias current Id having a value corresponding to the current I1 flows.

In the operating state, the plurality of transistors Ma1 to Ma4 amplify the signal input from the gate terminal of the first transistor Ma1 connected to the grounding terminal GND side, and amplify the signal input from the gate terminal of the first transistor Ma1 connected to the side closest to the power supply terminal 10. output from the drain terminal. A signal is input to the gate terminal of the first transistor Ma1 from the input terminal IN via the input matching circuit 81. The signal output from the drain terminal of the final transistor Ma4 is output to the outside of the power amplifier 100 from the output terminal OUT via the output matching circuit 82.

In the power amplifier 100, when the power supply voltage Vdd is boosted to, for example, 4.8V, the power supply voltage Vbat of the bias circuit 50 is boosted in conjunction with Vdd in order to apply the necessary voltage as the gate voltage Vg4 of the final transistor Ma4. There is a need to. In other words, the power supply voltage Vbat of the power supply terminal 12 is Vdd. The point that Vbat and Vdd must be linked is different from the bias circuit 151 of the cascode power amplifier 101 according to a comparative example described later.

The bias circuit 50 includes a step-down circuit 14 that steps down the power supply voltage Vbat, and a resistance circuit 16 connected to the output of the step-down circuit 14. The resistor circuit 16 has resistors R1 and R2 connected between the gate terminals of adjacent transistors from the second transistor Ma2 next to the first transistor Ma1 to the final transistor Ma4 among the plurality of transistors Ma1 to Ma4. Furthermore, the resistance circuit 16 includes a resistance R3 connected between the gate terminal of the second transistor Ma2 and the ground terminal GND.

The step-down circuit 14 is configured such that the amount of step-down is larger when the control signal Ven is at the second value than when it is at the first value. This will be explained using a specific example. The bias circuit 50 includes a binary reference current source Icon. A control signal Ven is input to the reference current source Icon via an inverter INV. The reference current source Icon has a function of flowing binary currents Ia and Ib according to the inverted voltage of the control signal Ven. Here, Ib>Ia. That is, the reference current source Icon flows the first current Ia when the control signal Ven is the first value, and flows the second current Ib larger than the first current Ia when the control signal Ven is the second value.

The step-down circuit 14 includes an nMOS source follower Mb3 connected between the power supply terminal 12 that provides the power supply voltage Vbat and the resistor circuit 16. A resistor R4 is connected between the power supply terminal 12 and the gate terminal of the source follower Mb3. The bias circuit 50 also includes a current mirror for causing a current corresponding to the current of the reference current source Icon to flow through the resistor R4. This current mirror is composed of transistors Mc1, Mc2, Mb1, and Mb2. A current I2 having a value corresponding to the current of the reference current source Icon flows through a current mirror made up of transistors Mc1 and Mc2. A current I3 having a value corresponding to the current I2 flows through the current mirror made up of the transistors Mb1 and Mb2.

That is, due to the current mirror constituted by the transistors Mc1, Mc2, Mb1, and Mb2, when the current of the reference current source Icon is Ib, the current flowing through the resistor R4 becomes larger than when the current is Ia. In this way, the bias circuit 50 is configured such that the current flowing through the resistor R4 is larger when the control signal Ven is at the second value than when it is at the first value. In other words, it can be said that the bias circuit 50 is configured such that the gate voltage of the source follower Mb3 is lower when the control signal Ven is at the second value than when it is at the first value. The source voltage of source follower Mb3 follows the gate voltage. Therefore, in the step-down circuit 14, when the control signal Ven is at the second value, the amount of step-down is larger than when it is at the first value.

The amount of step-down of the step-down circuit 14 when the control signal Ven is at the second value is set so that the gate-source voltage of the transistors from the second transistor Ma2 to the final transistor Ma4 becomes 0V. As a result, the plurality of transistors Ma1 to Ma4 can be put into the operating state when the control signal Ven is the first value, and put into the standby state when the control signal Ven is the second value.

Next, problems in a four-stage stacked power amplifier using a 65 nm CMOS process in which the standard voltage of the FET is 1.2V will be explained using a comparative example. FIG. 2 is a diagram illustrating a circuit configuration of a cascode power amplifier 101 according to a comparative example. Cascode power amplifier 101 includes a cascode amplification stage 181 and a bias circuit 151.

The cascode amplification stage 181 includes cascode-connected power amplification transistors Mm11 and Mm12. The gate terminal of transistor Mm11, which is a common source amplification stage, is connected to the gate terminal of transistor Mn3 via resistor Rgg1. Transistor Mm11 and transistor Mn3 constitute a current mirror. As a result, a bias is applied to the transistor Mm11. The gate terminal of the transistor Mm12, which is a common gate amplification stage, is connected to the connection point between the transistor Mp4 and the resistor Rgref2 via the resistor Rgg2. In this way, a constant voltage is applied to the gate terminal of the transistor Mm12 via the resistor Rgref2.

Further, a capacitor Cg1 is connected between the gate terminal of the transistor Mn3 and the ground terminal. A capacitor Cg2 is connected between the gate terminal of the transistor Mm12 and the ground terminal. Iref is a reference current source.

The transistors Mm11 and Mn3 are manufactured using a 65 nm 1.2V process. The transistors Mm12 and Mp1 to Mp5 are manufactured by a 5V withstand voltage process using an oxide film thicker than the gate oxide film thickness of 65 nm.

Next, the operations of the inverter INV and transistors Mp4 and Mp5 that control ON/OFF of the circuit will be explained. When the voltage at the terminal Ven is High, the transistors Mp4 and Mp5 are ON, and a predetermined drain current flows through the transistors Mm11 and Mm12. On the other hand, when the voltage at the terminal Ven is Low, the transistors Mp4 and Mp5 are turned off, and the drain currents of the transistors Mm11 and Mm12 become zero. At this time, the gate voltage of the transistor Mm11 is 0V, and the gate voltage of the transistor Mm12 is also 0V. Note that the power supply voltage Vbat of the bias circuit 151 is constant at 3.7 V, which is the standard voltage of a Li-ion battery.

FIG. 3 is a diagram illustrating the bias state of the cascode power amplifier 101 according to the comparative example. FIG. 3 shows an example of the voltage state of each node with respect to the power supply voltage Vdd of the cascode power amplifier 101 and the value of the control signal Ven. In FIG. 3, Operation indicates an operating state, and Stand-by indicates a standby state. For example, assume that the power supply voltage Vdd is boosted to 5V. At this time, as shown in Operation (A), each node and the inter-node voltage satisfy the breakdown voltages of 1.2V and 5V. Also in Stand-by (A1) and (A2), each node and the inter-node voltage satisfy the withstand voltage.

On the other hand, when the voltage is increased to Vdd=6V, the drain-source voltage Vds (m12) of the transistor Mm12 becomes 6V, which exceeds the withstand voltage value of 5V, as shown in Stand-by (B1). However, if the voltage increase of Vdd is limited to 5V, the problem of exceeding the breakdown voltage can be avoided.

FIG. 4 is a diagram illustrating the configuration of a stacked amplification stage 80 in a four-stage stacked power amplifier. In the stacked amplification stage 80, fine CMOS is vertically stacked to enable high output operation. In the stacked amplification stage 80, by vertically stacking a plurality of transistors each having a low breakdown voltage, the insufficient breakdown voltage can be overcome. Furthermore, the 65 nm nMOS has a lower ON resistance and a higher mutual conductance gm than an nMOS having a breakdown voltage of 5V. Therefore, the high frequency characteristics are better than using a 5V transistor. Therefore, higher efficiency and gain can be expected than the configuration shown in FIG.

Furthermore, compared to 2 GHz or less, which was the mainstream up to the 4th generation mobile communication system, the mainstream frequency bands in the 5th generation mobile communication system are high frequencies such as the 3.5 GHz band and 4.5 GHz band. For this reason, in a 5V withstand voltage nMOS having a thicker gate oxide film than a 65 nm CMOS, it may be difficult to perform a high-gain, high-efficiency amplification operation.

Assuming that the plurality of amplification transistors Ma1 to Ma4 operate equally in the stacked amplification stage 80, it is possible to operate up to the power supply voltage Vdd=4.8V. The standard voltage of a Li-ion battery is 3.7V, but it is assumed that it is boosted to 4.8V by a DC-DC converter for high output power operation and operates with an output power of 1W. Note that Vg1 is connected to the gate of the first transistor Ma1 in a DC manner.

Next, consider a case where the bias circuit of the concept shown in FIG. 2 is applied to the stack type amplifier stage 80 of FIG. 4. FIG. 5 is a diagram illustrating an example in which the bias circuit 151 of the cascode power amplifier 101 according to the comparative example is modified for use in a stacked power amplifier. In the bias circuit 152 shown in FIG. 5, in addition to the resistor Rgref2 in FIG. 2, resistors Rgref3 and Rgref4 are added. Gate voltages Vg2, Vg3, and Vg4 are generated from connection nodes of resistors Rgref2, Rgref3, and Rgref4.

When the stacked amplification stage 80 and the bias circuit 152 are combined, no problem with breakdown voltage occurs because bias is applied to Vg1 to Vg4 in the operating state. However, in the standby state, when Vdd=4.8V, Vbat=4.8V, and Ven=0V, all gate voltages Vg1 to Vg4 of transistors Ma1 to Ma4 become 0V. At this time, 4.8V is applied to the gate-drain voltage and drain-source voltage Vds of the final transistor Ma4. This value significantly exceeds the breakdown voltage value of 1.2V. Similarly, at the standard voltage of Vdd=3.7V, Vds=3.7V in the final transistor Ma4, which also exceeds the withstand voltage value.

Of course, by setting Vdd and Vbat to 0V at the same time as Ven=0V, the problem of the breakdown voltage of the nMOS in the standby state can be solved. However, in general, in a mobile phone terminal, when the power of the terminal is not turned off, the control signal Ven is only set to Low, but Vbat and Vdd are not set to 0V.

In contrast, in the power amplifier 100 and the bias circuit 50 of the present embodiment, by changing the amount of step down of the step-down circuit 14, the gate voltages of the plurality of transistors Ma2 to Ma4 can be provided in the operating state and the standby state. Therefore, even if the bias current is set to 0 when boosting the power supply voltage Vdd, a voltage that does not exceed the withstand voltage can be provided to the transistors Ma2 to Ma4.

This will be explained in more detail. First, the operating state in which the drain current necessary for the amplification operation is flowing will be described. The first transistor Ma1 constitutes a current mirror with the transistor Ma5, which is an nMOS of the same type. As a result, a predetermined bias current Id flows. In this way, the bias current of the first transistor Ma1 determines the bias current Id of the entire amplifier.

The source terminal of source follower Mb3 is connected to the gate terminal of final transistor Ma4. The gate terminal of the third transistor Ma3 is connected to the gate terminal of the final transistor Ma4 via a resistor R1. The gate terminal of the second transistor Ma2 is connected to the gate terminal of the third transistor Ma3 via a resistor R2.

The gate voltage Vg (Mb3) of the source follower Mb3 is determined by the voltage drop amount R4·I3 due to the resistor R4 and the current I3. In this embodiment, as described above, by appropriately increasing the step-down amount R4 and I3 in the standby state compared to the operating state, transistors Ma2 to Ma4 are turned off while maintaining the 1.2V withstand voltage standard. . When turning off the transistors Ma1 to Ma4, the value of the reference current source Icon is switched from Ia to Ib. At this time, I3 increases due to the current mirror. As a result, the voltage drop amount by R4·I3 increases, and the gate voltage Vg (Mb3) of the source follower decreases. Accordingly, Vg4, Vg3, and Vg2 decrease, and transistors Ma2 to Ma4 can be turned off.

Regarding Vg1, when the transistor Mb4 is turned on, the gate voltage of the transistor Ma5 becomes 0V, and the gate voltage Vg1 of the first transistor Ma1 also becomes 0V. This turns off the first transistor Ma1.

FIG. 6 is a diagram illustrating an example of a bias state of power amplifier 100 according to the first embodiment. FIG. 6 shows examples of bias states in an operation state and a standby state. The power supply voltage Vdd is set to 4.8V. Furthermore, the gate-source voltage for causing the transistors Ma1 to Ma4 to flow a predetermined drain current is set to 0.4V.

In a stacked power amplifier, transistors Ma1 to Ma4 basically have the same gate width and are applied with the same gate-source voltage and drain-source voltage. Therefore, when Vdd=4.8V, a voltage of 1.2V is applied between the drain and source of each of the transistors Ma1 to Ma4. At this time, since the drain voltage of the first transistor Ma1 is 1.2V, 1.2+0.4=1.6V is required as Vg2. Similarly, 2.8V and 4.0V are required as Vg3 and Vg4, respectively.

Therefore, the gate voltage Vg (Mb3) of the source follower Mb3 may be set so that the source potential of the source follower Mb3 is 4.0V. In the example of FIG. 6, the gate-source voltage of the source follower Mb3, which is an nMOS with a withstand voltage of 5V, is set to 0.5V. Further, the current I4 and the resistance values of the resistors R1, R2, and R3 are set so that Vg4=4.0V, Vg3=2.8V, and Vg2=1.6V. Also, since Vdd=4.8V and Vg(Mb3)=4.5V, R4·I3=0.3V. Therefore, since (R1+R2+R3).I4=4.0V, (R2+R3).I4=2.8V, and R3.I4=1.6V hold, once I4 is determined, the values of resistors R1 to R3 are uniquely determined.

In the standby state of FIG. 6, the drain current is set to 0 while maintaining the drain-source voltage of each of the transistors Ma1 to Ma4 at 1.2V. Therefore, at the same time that Vg1 is set to 0V, the gate-source voltages of the transistors Ma2 to Ma4 are also set to 0V. This can be achieved by increasing I3 and changing the voltage drop amount R4·I3 from 0.3V to 0.7V. At this time, since the same current I4 as in the operating state is flowing through the resistors R1 to R3, Vg4 to Vg2 are shifted by the amount of increase in the voltage drop. As a result, Vg4=3.6V, Vg3=2.4V, and Vg2=1.2V, and the gate-source voltages of transistors Ma2 to Ma4 all become 0V. In other words, the gate-source voltages of the transistors Ma2 to Ma4 are in the same voltage state as the first transistor Ma1. Therefore, the drain currents of the transistors Ma1 to Ma4 can be reduced to 0 while satisfying the 1.2V withstand voltage standard.

As described above, according to the present embodiment, in both the operating state and the standby state, while maintaining the withstand voltage specifications of the plurality of transistors Ma1 to Ma4, the state in which the idle current necessary for the amplification operation flows and the state in which the drain current flows 0 state can be easily realized.

Furthermore, CMOS transistors have achieved low power consumption and high speed operation based on scaling laws. For example, with a gate length of 0.5 μm and a gate oxide film thickness of 130 Å, operation is possible only up to 3 GHz, but with a gate length of 0.18 μm and a gate oxide film of 30 Å, operation at about 10 GHz is possible. On the other hand, with a gate length of 0.5 μm, it is possible to guarantee operation for 10 years even when applying up to 5 V, but with a gate length of 0.18 μm, the applied voltage must be 1.8 V to guarantee operation for 10 years. It is necessary to do up to When applying approximately 2.5 to 3 V to a 0.18 μm transistor, the life span is shortened to approximately 0.5 to 1 year, for example.

In this way, in order to guarantee the 10-year operation required for normal semiconductor products, it is essential that the voltage between the terminals of the transistors used in the circuit adhere to the voltage range determined by the CMOS process used. Become. According to the bias circuit of this embodiment, voltages within the range determined by the process can be provided to all transistors. Therefore, shortening of the life of the power amplifier can be suppressed, and the long life guaranteed by the process can be maintained.

Further, in this embodiment, an appropriate voltage can be provided to the plurality of transistors Ma1 to Ma4 with a simple configuration of the step-down circuit 14 consisting of the source follower Mb3 and the resistor R4, and resistor division. Further, the voltage step-down amount of the source follower Mb3 is controlled using a current mirror that reflects the value of the reference current source Icon. Therefore, an appropriate voltage can be provided at low cost with a simpler configuration. For example, if the gate voltage of each amplification stage is precisely controlled by a digital-to-analog converter (DAC), the voltage during amplification operation and the voltage when OFF can be appropriately applied. However, the area of the bias circuit increases, which may lead to an increase in cost. In contrast, in this embodiment, the gate voltage of each amplification stage can be controlled using a small-scale circuit.

As a modification of this embodiment, the number of series-connected transistors included in the stacked amplification stage 80 is not limited, and may be two or more. Further, the configuration of the bias circuit 50 is not limited to that shown in FIG. 1 either. The bias circuit 50 switches the plurality of transistors Ma1 to Ma4 between an operating state and a standby state by making the amount of voltage step down of the step-down circuit 14 larger when the control signal is at the second value than when it is at the first value. It is sufficient if the configuration is such that it can be switched between.

Further, Vdd and Vbat in this embodiment are the same power source. Vdd and Vbat may be supplied from different power supplies as long as they have the same voltage value.

The above-described modification can be applied as appropriate to the power amplifier and bias circuit according to the following embodiments. Note that the power amplifier and bias circuit according to the following embodiments have many features in common with the first embodiment, so the explanation will focus on the differences from the first embodiment.

Embodiment 2.
FIG. 7 is a diagram illustrating a circuit configuration of power amplifier 200 according to the second embodiment. Power amplifier 200 differs from power amplifier 100 of the first embodiment in the configuration of bias circuit 250. The bias circuit 250 further includes a current mirror for causing a current corresponding to the current of the reference current source Iref to flow through the resistance circuit 16. The current mirror is composed of a transistor Ma5 and a transistor Ma6 connected between the resistor R3 and the ground terminal GND. Other configurations are similar to those of the first embodiment.

Transistor Ma6 conducts a mirror current of transistor Ma5. A drain terminal of transistor Ma6 is connected to resistor R3. As a result, the value of the current I4 becomes a value determined by the mirror ratio of the reference current source Iref and the transistors Ma5 and Ma6. Note that the transistor Mb5 is turned on in the standby state similarly to the transistor Mb4. As a result, the drain voltage of the transistor Ma6 becomes 0V in the standby state.

In the first embodiment, the value of current I4 changes between the operating state and standby state. Therefore, the values of Vg4 to Vg2 may have some error with respect to the target voltage value. In contrast, in this embodiment, the value of current I4 is set based on reference current source Iref. Therefore, even when the gate voltage Vg (Mb3) of the source follower Mb3 changes from 4.5V to 4.1V, the current I4 does not change. In other words, the same amount of current flows through the resistance circuit 16 in the operating state and in the standby state. Therefore, Vg4 to Vg2 can be set as target voltage values in both the operating state and the standby state.

Embodiment 3.
FIG. 8 is a diagram illustrating a circuit configuration of power amplifier 300 according to the third embodiment. Power amplifier 300 differs from power amplifier 200 of the second embodiment in the configuration of bias circuit 350. In the bias circuit 350, transistors Mc5 to Mc8, which are PMOS transistors with a withstand voltage of 5 V, are further added to the paths of the currents I1 to I4. Transistors Mc5 to Mc8 are controlled by a signal from terminal Ven2.

In the first and second embodiments, even if the drain currents of the transistors Ma1 to Ma4 become 0, the current on the bias circuit side is not cut off. In Embodiments 1 and 2, the bias current Id can be set to 0 without exceeding the withstand voltage by flowing the necessary current into the bias circuit and setting the gate-source voltage of the transistors Ma1 to Ma4 to 0. This is because However, if the power supply voltage Vdd of the stacked power amplifier is 1.2V or less, even if the gate voltages Vg2 to Vg4 are set to 0V when Ven=0V as in the bias circuit 152 of FIG. 5, the transistors Ma1 to A voltage exceeding the breakdown voltage is not applied to Ma4.

In the present embodiment, the bias circuit 350 further includes a circuit that blocks the current flowing through the resistance circuit 16 when the control signal Ven is at the second value, for example, when the power supply voltage Vdd=Vbat is 1.2 V or less. . The circuit that interrupts the current flowing through the resistance circuit 16 corresponds to the transistors Mc5 to Mc8. When the control signal Ven is at the second value, that is, in the standby state, the transistors Mc5 to Mc8 are turned off by the signal Ven2. This allows the current in the bias circuit 350 to be completely cut off. Note that in the operating state, the transistors Mc5 to Mc8 are turned on by the signal Ven2.

The technical features described in each embodiment may be used in combination as appropriate.

10, 12 power supply terminal, 14 step-down circuit, 16 resistor circuit, 50 bias circuit, 80 stacked amplifier stage, 81 input matching circuit, 82 output matching circuit, 100 power amplifier, 101 cascode power amplifier, 151 bias circuit, 152 bias Circuit, 181 Cascode amplifier stage, 200 Power amplifier, 250 Bias circuit, 300 Power amplifier, 350 Bias circuit, C2, C3, C4, Cg1, Cg2 Capacitor, GND Grounding terminal, Icon Reference current source, IN Input terminal, INV Inverter, Iref reference current source, Ma1 to Ma6 transistors, Mb1, Mb2 transistors, Mb3 source follower, Mb4, Mb5 transistors, Mc1 to Mc8 transistors, Mm11, Mm12 transistors, Mn3 transistors, Mp1 to Mp5 transistors, OUT output terminals, R1 to R4 resistance, Rgg1, Rgg2 resistance, Rgref2 to Rgref4, Ven, Ven2 terminal

Claims (9)

Each transistor has a source terminal, a drain terminal, and a gate terminal, and the drain terminal and source terminal of adjacent transistors are connected to each other in series between the power supply terminal that provides the power supply voltage and the ground terminal. multiple connected transistors,
The plurality of transistors are configured such that when the control signal inputted from the outside has a first value, the plurality of transistors are in an operating state, and when the control signal is a second value, the plurality of transistors are in a standby state. a bias circuit configured to supply a gate voltage to a gate terminal of the transistor;
Equipped with
In the operating state, the plurality of transistors amplify a signal input from the gate terminal of the first transistor connected to the grounding terminal side among the plurality of transistors, and Output from the drain terminal of the final transistor connected to the power supply terminal side,
The bias circuit includes a step-down circuit that steps down the power supply voltage, and a resistance circuit connected to the output of the step-down circuit,
The resistance circuit is arranged between the gate terminals of adjacent transistors from the second transistor next to the first transistor to the final transistor among the plurality of transistors, and between the gate terminal of the second transistor and a grounding terminal. and a plurality of first resistors connected to;
The step-down circuit includes a source follower connected between a terminal that provides the power supply voltage and the resistor circuit,
The bias circuit is configured such that when the control signal is at the second value, the gate voltage of the source follower is smaller than when the control signal is at the first value; A power amplifier characterized in that the power amplifier is configured such that when the control signal is at the second value, the voltage step-down amount is larger than when the control signal is at the first value . The step-down circuit further includes a second resistor connected between a terminal that provides the power supply voltage and a gate terminal of the source follower,
2. The bias circuit is configured such that when the control signal is at the second value, a larger current flows through the second resistor than when the control signal is at the first value . The power amplifier described in . The bias circuit is
a first reference current source that causes a first current to flow when the control signal is the first value, and causes a second current larger than the first current to flow when the control signal is the second value;
a first current mirror for causing a current corresponding to the current of the first reference current source to flow through the second resistor;
The power amplifier according to claim 2 , further comprising: The step-down amount of the step-down circuit when the control signal is at the second value is set such that the gate-source voltage of the transistors from the second transistor to the final transistor is 0V. The power amplifier according to any one of claims 1 to 3 . 4. The power amplifier according to claim 1, wherein the bias circuit includes a second reference current source for causing a predetermined current to flow through the first transistor in the operating state. . a second reference current source;
a second current mirror for causing a current corresponding to the current of the second reference current source to flow through the resistance circuit;
The power amplifier according to any one of claims 1 to 3 , comprising: 7. The power amplifier according to claim 6 , wherein the same amount of current flows through the resistance circuit in the operating state and the standby state. The power source according to any one of claims 1 to 3 , wherein the bias circuit further includes a circuit that blocks current flowing through the resistance circuit when the control signal is at the second value. amplifier. A step-down circuit that steps down the power supply voltage;
a resistor circuit connected to the output of the step-down circuit;
Equipped with
A plurality of transistors connected in series between a power supply terminal that provides the power supply voltage and a ground terminal are in an operating state when a control signal input from the outside has a first value; configured to supply a gate voltage to the gate terminals of the plurality of transistors so as to enter a standby state when the value is 2;
In the operating state, the plurality of transistors amplify a signal input from the gate terminal of the first transistor connected to the grounding terminal side among the plurality of transistors, and Output from the drain terminal of the final transistor connected to the power supply terminal side,
The resistance circuit is arranged between the gate terminals of adjacent transistors from the second transistor next to the first transistor to the final transistor among the plurality of transistors, and between the gate terminal of the second transistor and a grounding terminal. and a plurality of first resistors connected to;
The step-down circuit includes a source follower connected between a terminal that provides the power supply voltage and the resistor circuit,
The bias circuit is configured such that when the control signal is at the second value, the gate voltage of the source follower is smaller than when the control signal is at the first value; A bias circuit characterized in that the bias circuit is configured such that when the signal is at the second value, the voltage step-down amount is larger than when the signal is at the first value.

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