JP7415271B2 - Driving device, display device, and driving method of the driving device - Google Patents

Description

The present disclosure relates to a driving device, a display device, and a method of driving the driving device.

In recent years, in the field of display devices, flat panel display devices in which pixels including light emitting parts are arranged in a matrix have become mainstream. One type of flat display device is an organic display device that uses a so-called current-driven electro-optical device, for example, an organic electroluminescence (EL) device, in which the luminance of light changes depending on the value of the current flowing through the light-emitting part. There is an EL display device.

In a flat display device typified by this organic EL display device, a batch light emission drive in which light is emitted all at once during a blanking period may be used. By using the batch light emission drive, the display timing within the panel surface becomes uniform, which is effective when it is desired to accurately control the display delay on the video signal output side. However, when introducing the batch light emission drive, it is necessary to control on/off of the switching transistors all at once, and there is a possibility that the rush current generated when switching the switching transistors exceeds a specified value.

Japanese Patent Application Publication No. 2012-128407

One embodiment of the present disclosure provides a driving device, a display device, and a driving method for the driving device, which can suppress rush current even when the devices are collectively driven to emit light.

In order to solve the above problems, in the present disclosure, the gate of a switching transistor is connected in series to an organic EL element in a pixel circuit and a drive transistor that supplies a current to the organic EL element according to the potential of the gate electrode. A drive device that outputs a signal,
a generation circuit that generates a first gate signal;
a buffer that outputs the first gate signal input from the generation circuit as the gate signal,
The buffer is provided with a driving device in which at least two inverters are connected in parallel.

The buffer may be capable of changing the number of inverters to be driven.

Depending on the light emission mode of the organic EL element, at least one of the two inverters may be non-driven.

In the first light emission mode, the at least two inverters may be driven, and in a second light emission mode different from the first light emission mode, the number of inverters to be driven may be reduced compared to the first light emission mode.

The first light emitting mode may be a mode in which organic EL elements in each row are caused to emit light in sequence in a pixel section in which the pixel circuits are arranged in a matrix.

The second light emitting mode may be a mode in which at least a plurality of rows of organic EL elements emit light simultaneously in a pixel section in which the pixel circuits are arranged in a matrix.

In order to further reduce the rush current per unit time at the gate of the switching transistor, the number of inverters driven in the buffer may be further reduced.

In order to solve the above problems, in the present disclosure, the gate of a switching transistor is connected in series with an organic EL element in a pixel circuit and a drive transistor that supplies a current according to the potential of a gate electrode to the organic EL element. A drive device that outputs a signal,
A generation circuit that sequentially delays an original signal corresponding to the on time of the input gate signal for each row and outputs the gate signal as the gate signal for each row,
A driving device is provided in which gate signals corresponding to a plurality of rows of the pixel circuits have overlapping on-times, and start and end times of the on-times of the gate signals are different from each other.

The generation circuit is
a plurality of delay elements connected in series, the plurality of delay elements sequentially delaying the original signal corresponding to the on-time for each row;
The gate signal for each row may be output based on the original signal corresponding to the on time delayed for each row.

The generation circuit is
a shift register that sequentially delays the original signal corresponding to the on-time row by row according to a transmission clock;
The gate signal for each row may be output based on the original signal corresponding to the on time delayed for each row.

In order to solve the above problems, the present disclosure includes an organic EL element, a drive transistor that supplies a current to the organic EL element according to a signal potential of a gate electrode, and a drive transistor connected in series with the organic EL element and the drive transistor. a pixel section including a plurality of pixels arranged in a matrix, including a switching transistor connected to the organic EL element and controlling light emission of the organic EL element according to a control signal;
a driving device that drives the plurality of pixels;
A display device comprising:
The drive device is
a generation circuit that generates a first gate signal;
A display device is provided, comprising: a buffer that outputs a first gate signal input from the generation circuit as the gate signal, the buffer having at least two inverters connected in parallel.

A downstream plane of the two reflecting planes perpendicular to the optical axis may constitute a downstream reflecting member of the pair of reflecting members.

In the first light emission mode, the at least two inverters may be driven, and in a second light emission mode different from the first light emission mode, the number of inverters to be driven may be reduced compared to the first light emission mode.

The first light emitting mode may be a mode in which the organic EL elements in the pixel portion are caused to emit light sequentially row by row.

The second light emitting mode may be a mode in which at least a plurality of rows of organic EL elements in the pixel portion emit light simultaneously.

In order to further reduce the rush current per unit time at the gate of the switching transistor, the number of inverters to be driven may be further reduced.

In order to solve the above problems, in the present disclosure, the gate of a switching transistor is connected in series with an organic EL element in a pixel circuit and a drive transistor that supplies a current according to the potential of a gate electrode to the organic EL element. A driving method for a driving device that outputs a signal, the method comprising:
a generation step of generating a first gate signal;
an output step of outputting the first gate signal as the gate signal via a buffer;
a changing step of changing the on-resistance of the buffer;
A driving method for a driving device is provided.

In the changing step, the on-resistance of the buffer may be increased in order to further reduce the rush current per unit time at the gate of the switching transistor.

FIG. 1 is an explanatory diagram showing a configuration example of a display device according to an embodiment of the present disclosure. FIG. 3 is an explanatory diagram showing a more detailed configuration example of the display device according to the embodiment. FIG. 3 is an explanatory diagram showing an example of a pixel circuit of the display device according to the embodiment. FIG. 3 is a diagram illustrating a driving example of line sequential driving. An example of batch light emission drive is shown. The figure which shows the comparative example of the timing chart of batch light emission drive. FIG. 1 is a diagram showing a detailed configuration example of a driving scanner according to the present embodiment. The figure which shows the example of a structure of a buffer. The figure which shows the example of the truth table of a logic circuit. The figure which shows the example of the whole timing chart in a drive scanner. 11 is a partially enlarged view of the timing chart during simultaneous driving in FIG. 10. FIG. FIG. 3 is a diagram illustrating a configuration example of a pixel circuit. FIG. 7 is a diagram showing a timing chart of batch light emission drive when the pixel circuit is configured with N-channel transistors. FIG. 7 is a diagram showing a detailed configuration example of a driving scanner according to a second embodiment. FIG. 7 is a diagram showing an example of a truth table of a logic circuit according to a second embodiment. FIG. 7 is a diagram showing an example of an overall timing chart in a driving scanner according to a second embodiment. 17 is a partially enlarged view of the timing chart during simultaneous driving in FIG. 16. FIG. FIG. 7 is a diagram showing a detailed configuration example of a driving scanner according to a third embodiment. FIG. 7 is a diagram showing an example of a truth table of a logic circuit according to a third embodiment. FIG. 7 is a diagram showing an example of an overall timing chart in a driving scanner according to a third embodiment. FIG. 7 is a diagram showing another configuration example of the driving scanner according to the third embodiment. FIG. 7 is a circuit diagram of a pixel circuit in a display device according to a fourth embodiment. FIG. 7 is a timing chart diagram of a pixel circuit according to a fourth embodiment.

Hereinafter, embodiments of a driving device, a display device, and a driving method for the driving device will be described with reference to the drawings. The main components of the driving device, the display device, and the driving method for the driving device will be mainly explained below. There may be parts or functions. The following description does not exclude components or features not shown or described.

(First embodiment)
FIG. 1 is an explanatory diagram showing a configuration example of a display device 100 according to an embodiment of the present disclosure. Hereinafter, a configuration example of a display device 100 according to an embodiment of the present disclosure will be described using FIG. 1.

As shown in FIG. 1, the display device 100 includes a pixel section 110, a horizontal selector 120, and a vertical scanner 130.
The pixel section 110 has a configuration in which pixels each provided with an organic EL element or other self-luminous element are arranged in a matrix. In the pixel section 110, scanning lines are provided horizontally in units of lines for pixels arranged in a matrix, and signal lines are provided in each column so as to be orthogonal to the scanning lines.

The horizontal selector 120 sequentially transfers predetermined sampling pulses and sequentially latches the image data using the sampling pulses, thereby distributing the image data to each signal line. Further, the horizontal selector 120 performs analog-to-digital conversion processing on the image data distributed to each signal line, thereby generating a drive signal that indicates the luminance of each pixel connected to each signal line on a time-division basis. Horizontal selector 120 outputs this drive signal to the corresponding signal line.

The vertical scanner 130 responds to the driving of the signal line by the horizontal selector 120, generates a driving signal for each pixel, and outputs it to the scanning line. As a result, the display device 100 sequentially drives each pixel arranged in the pixel section 110 by the vertical scanner 130, causes each pixel to emit light at the signal level of each signal line set by the horizontal selector 120, and displays a desired image from pixel to pixel. section 110. Note that the vertical scanner 130 according to this embodiment corresponds to the driving device.

FIG. 2 is an explanatory diagram showing a more detailed configuration example of the display device 100 according to the embodiment of the present disclosure. Hereinafter, a configuration example of the display device 100 according to an embodiment of the present disclosure will be described using FIG. 2.

In the pixel section 110 (FIG. 1), a pixel 111R that displays red, a pixel 111G that displays green, and a pixel 111B that displays blue are arranged in a matrix.

The vertical scanner 130 includes a drive scanner (Drive Scan) 132 and a write scanner (Write Scan) 134. By supplying signals from each scanner to pixels arranged in a matrix in the pixel section 110, transistors Tr1 to Tr3 (described later in FIG. 3) provided in each pixel are turned on and off.

FIG. 3 is an explanatory diagram showing an example of a pixel circuit of the display device 100 according to an embodiment of the present disclosure. Hereinafter, a configuration example of the display device 100 according to an embodiment of the present disclosure will be described using FIG. 3.

FIG. 3 shows a pixel circuit for one pixel arranged in a matrix in the pixel section 110. The pixel circuit 111 includes transistors Tr1 to Tr3, a capacitor Cs, and an organic EL element EL. The transistors Tr1 to Tr3 are, for example, P-channel transistors. Furthermore, the transistors Tr1 to Tr3 are, for example, MOS-FETs. Note that since the transistors Tr1 to Tr3 are P-channel transistors, they are turned off when a high level signal is applied to their gates, and turned on when a low level signal is applied to their gates.

The transistor Tr1 has a gate electrode connected to the scanning line Ws, a drain electrode connected to the signal line Vs of the horizontal selector 120, and a source electrode connected to the gate of the transistor Tr2. The transistor Tr1 is a sampling transistor that writes the signal voltage Vsig to the gate node (gate electrode) of the transistor Tr2 by sampling the signal voltage Vsig supplied from the write horizontal selector 120.

The capacitor Cs is connected between the gate node and the source node of the transistor Tr2, and holds the signal voltage Vsig written by sampling by the transistor Tr1.
The transistor Tr2 has a source electrode connected to the power supply node of the power supply VCC, and a drain electrode connected to the drain electrode of the transistor Tr3. The transistor Tr2 is a drive transistor that drives the organic EL element EL by causing a drive current corresponding to the holding voltage of the capacitor Cs to flow through the organic EL element EL.

The transistor Tr3 has a gate electrode connected to the drive line Ds, and a source electrode connected to the anode of the organic EL element EL. The transistor Tr3 is a switching transistor that controls light emission/non-light emission of the organic EL element EL under the drive of the light emission control signal DS output from the drive scanner 132.

An example of display driving of the display device 100 will be described based on FIGS. 4 and 5. FIG. 4 is a diagram showing an example of line sequential driving. FIG. 5 is a diagram showing a driving example of batch light emission driving. As shown in FIGS. 4 and 5, this driving device is capable of line sequential driving and batch light emission driving (hereinafter sometimes referred to as simultaneous driving). The horizontal axis in FIGS. 4 and 5 represents time, and the vertical axis represents vertical scanning, that is, the order of row selection in the pixel section 110 (FIG. 1). The top row shows the vertical synchronization signal Vsync. Note that in this embodiment, driving to cause the organic EL elements EL of each row in the display device 100 to emit light sequentially is referred to as line sequential driving, and driving to cause multiple rows of organic EL elements EL to emit light at the same time is referred to as batch light emitting driving. Further, the line sequential drive according to this embodiment corresponds to the first light emission mode, and the batch light emission drive corresponds to the second light emission mode. That is, in the first light emission mode, the organic EL elements EL in each row of the display device 100 are caused to emit light in sequence, and in the second light emission mode, the organic EL elements EL in multiple rows are caused to emit light at the same time.

As shown in FIG. 4, in line sequential driving, light emission is repeated for each row in the order of row selection. In this case, each row is controlled in the following order: correction, writing of the signal voltage Vsig, light emission, and non-light emission. In the non-light-emitting period, a black display period is realized by bringing the organic EL element EL into a non-light-emitting state. In this way, by using the duty drive that inserts the black display period, it is possible to improve the moving image display performance. After the signal voltage Vsig is written to make the organic EL element emit light, the switching transistors connected in series with the current source transistor are sequentially turned off to cut off the current flowing through the EL element. A black display period is realized by setting EL to a non-emitting state.

More specifically, when writing the signal voltage Vsig, the low-level gate signal WS of the scanning line Ws is supplied, and the transistor Tr1 is turned on. Therefore, the voltage Vsig, which is the gradation display data of the i row, is input to the pixel circuit of the i row, which is the target row. As a result, the capacitor Cs is charged with a charge corresponding to the input signal voltage Vsig, and gradation display data is written.

In the pixel circuit of the target row, a high-level signal WS is input to the scanning line Ws, and the transistor Tr1 is turned off. A low level signal DS is input to the drive line Ds, and the transistor Tr3 is turned on. For this reason, a current shown in equation (1), for example, corresponding to the charge charged in the capacitor Cs and the potential of the gate electrode of the transistor Tr2 is supplied to the organic EL element EL, and the luminance of the gradation according to this supplied current is The organic EL element EL emits light. Here, it is assumed that the voltage of the power supply VCC is Vcc, the capacitance of the capacitor Cs is Cox, and the threshold voltage is Vth. The above-mentioned correction means, for example, correction of variations in threshold voltage Vth from pixel circuit to pixel circuit.
In the non-emission period, a high-level gate signal DS is input to the drive line Ds in the pixel circuit 111 of the target row, and the transistor Tr3 is turned off. As a result, no current is supplied to the organic EL element EL, and the organic EL element EL does not emit light.

As shown in FIG. 5, correction and writing of the signal voltage Vsig is performed for each target row, similar to line sequential driving. On the other hand, light emission and light extinction are performed simultaneously in all rows of the pixel section 110. In this way, the display device 100 is capable of simultaneous light emission drive in which light is emitted all at once during the blanking period. By using the batch light emission drive, the display timing within the panel surface becomes uniform, which is effective when it is desired to accurately control the display delay on the video signal output side.

FIG. 6 is a diagram showing a comparative example of a timing chart of batch light emission drive. The horizontal axis is time. The top row shows the horizontal synchronization signal Hsync. Below that, signals DS1 to DSn of the drive line Ds are shown, respectively. Here, n indicates a signal of the nth row drive line Ds of the pixel section 110. For example, the signal DS1 indicates the signal of the drive line Ds of the first row of the pixel section 110, the signal DS2 indicates the signal of the drive line Ds of the second row of the pixel section 110, and the signal DS3 indicates the signal of the drive line Ds of the pixel section 110. The signal of the drive line Ds in the third row is shown. In FIG. 6, only up to the signal DS3 is shown for simplicity, but the driving scanner 132 outputs signals DS1 to DSn for n lines. Similarly, in the drawings below, only three lines of scanning lines, etc. are shown for simplicity, but the actual configuration has n lines of scanning lines, signals, etc.

As shown in FIG. 6, the pixel circuits 111 in each row start emitting light at the same time when the gate signals DS1 to DSn all become low signals, that is, fall all at once. Thereafter, the signals DS1 to DSn are simultaneously high signals, that is, they rise all at once, so that they simultaneously shift to non-emission mode.

If the switching transistor Tr3 is also used for purposes other than light emission control, for example, intra-pixel variation correction driving, it is necessary to perform on/off control within the 1H period of writing the signal voltage Vsig. For this purpose, the drive scanner 132 is designed so that the signals DS1 to DSn, which are gate line pulses of the switching transistor Tr3, operate with a steep slope. On the other hand, when the pulse slope is steep, as shown in equations (2) and (3), when the time required for charging and discharging the gate is tg, the current Ig for charging and discharging increases as tg becomes shorter. do. Here, it is assumed that the gate line load of the switching transistor Tr3 is Cg, the gate amplitude is Vg, the time required for charging and discharging is tg, and the current for charging and discharging is Ig.

In the case of line sequential driving, the gate line load Cg is for one row of pixels. However, when charging and discharging the gate line load on the entire surface of the display device 100, the gate line load Cg doubles according to the number of vertical pixels, and therefore the charging/discharging current also doubles according to the number of vertical pixels. Therefore, in the comparative example, it is difficult to satisfy the power drop condition, which is the allowable range of the drive circuit power supply due to the charge/discharge current during batch drive, while satisfying the pulse slope required during line sequential drive. There is a fear.
Note that in this embodiment, the current Ig flowing at time tg immediately after the switching transistor Tr3 is turned on or off is referred to as a rush current. This rush current is a charging/discharging current that flows immediately after the switching transistor Tr3 is turned on, and is sometimes called an inrush current, a starting current, or an inrush current.

Here, the detailed configuration and operation example of the drive scanner 132 according to this embodiment will be explained using FIGS. 7 to 11. FIG. 7 is a diagram showing a detailed configuration example of the driving scanner 132 according to this embodiment. As shown in FIG. 7, the driving scanner 132 includes a generation circuit 136 that generates a first gate signal, and a buffer circuit 138 that outputs the first gate signal input from the generation circuit 136 as gate signals DS1 to DSn. Be prepared. Further, the generation circuit 136 includes a plurality of shift registers (S/R) 136a and a plurality of logic circuits (Logic) 136b, and the buffer circuit 138 includes a plurality of buffers 138a.

The plurality of shift registers (S/R) 136a synchronize the start pulse Start Plus with the vertical clock signal VCK, propagate it in order, and output it in order as a signal SRn row by row. Here, n is the number of rows of the pixel section 110.

The logic circuit (Logic) 136b performs logical operations according to the input of the signal SRn, the signal EN, and the signal EM. Details of the logic circuit 136b will be described later using FIG. 9.

FIG. 8 is a diagram showing an example of the configuration of the buffer 138a. As shown in FIG. 8, buffer 138a has inverters 140 and 142 connected in parallel. Inverters 140, 142 are designed with different component dimensions, for example. This buffer 138a can separate at least one of the inverters 140 and 142 from the signal line DSn. This changes the on-resistance of the buffer 138a and modulates the pulse slopes of the gate signals DS1 to DSn.

Inverter 140 is, for example, a first CMOS inverter. In the first CMOS inverter, a P-type MOS transistor and an N-type MOS transistor are cascade-connected between the VCC power supply node and the ground. On the other hand, the inverter 142 is, for example, a second CMOS inverter.

The second CMOS inverter has two P-type MOS transistors and two N-type MOS transistors connected in cascade between, for example, a node of the VCC power supply and ground. A control signal EM is input to the gate of the P-type MOS transistor on the VCC power supply side, and an inverted control signal EM is input to the gate of the N-type MOS transistor on the ground side. As a result, when the control signal EM is at a high level, the inverter 142 becomes non-driven.

With this configuration, when writing signals and correcting variations, inverters 140 and 142 are driven to output gate signals DS1 to DSn with low on-resistance. That is, the control signal EM is set to low level. This makes it possible to output steeper pulses.

On the other hand, during the batch light emission drive, the inverter 142 is not driven, and the gate signals DS1 to DSn are output with the on-resistance being higher than that during signal writing and variation correction. That is, the EM signal is set to high level. This makes it possible to output a pulse with a more tilted pulse, that is, a pulse with a longer time tg (formula (3)). In this way, when writing signals and correcting variations, a buffer with high drive capacity (low on-resistance) is used to charge and discharge and output steep pulses, and when driving a batch light emission, a buffer with high drive capacity is used using the control signal EM. The pulse slope is modulated by separating it from the charging/discharging path and charging/discharging it with a buffer with low drive capability (high on-resistance).

FIG. 9 is a diagram showing an example of a truth table of the logic circuit 136b. As shown in FIG. 9, the logic circuit 136b changes the value of the gate signal DSn based on the output signal SRn of the shift register 136a, and the values of the control signals EN and EM. Here, a high level signal is indicated by 1, and a low level signal is indicated by 0. The same applies to the following explanation.

When the output signal SRn is 1, the logic circuit 136b outputs 0 as the output signal DSn if the control signal EN is 1, regardless of the value of the control signal EM; 1 is output as the output signal DSn. On the other hand, when the output signal SRn is 0, the logic circuit 136b outputs 1 as the output signal DSn if the control signal EM is 0, regardless of the value of the control signal EN; If there is, 0 is output as the output signal DSn.

FIG. 10 is a diagram showing an example of an overall timing chart for the driving scanner 132. From the top: vertical synchronization signal Vsync, horizontal synchronization signal Hsync, vertical clock VCK, start pulse StartPlus, control signals EN, EM, output signal SRn of shift register 136a (SR1 to SR3 as an example), gate signal DSn (DS1 to DS3 as an example) ) is shown. The left side is driving during signal writing and variation correction, and the right side is driving during simultaneous driving. The vertical clock VCK is a transmission clock of the shift register 136a. Further, the vertical clock VCK, the start pulse StartPlus, and the control signals EN and EM are signals input from a higher-level control device (not shown) of the drive scanner 132, and the gate signal DSn is a signal output from the drive scanner 132. It is.

FIG. 11 is a partially enlarged view of the timing chart during simultaneous driving in FIG. 10. In FIG. 11, the left side is driving during simultaneous driving, and the right side is driving during signal writing/variation correction.

As shown in FIG. 10, when writing signals and correcting variations, a high-level start pulse StartPlus is input to the drive scanner 132. As a result, the output signal SRn of the shift register 136a is synchronized with the vertical clock VCK and is sequentially outputted in a pulse form as a high-level output signal SRn to the logic circuit 136b. Control signals EN and EM are also input to the logic circuit 136b.

During signal writing and variation correction, the control signal EM is at a low level. That is, as shown in FIG. 8, inverter 140 and inverter 142 are driven, and the on-resistance of buffer 138a is low. In this case, when the control signal EN is a high level signal and the output signal SRn is a high level signal, the gate signal DSn becomes a low level signal. That is, the low level period of the gate signal DSn is synchronized with the high level signal of the control signal EN, and the period is equivalent to the high level signal period of the control signal EN. In this way, at the time of signal writing/variation correction, the inverter 140 and the inverter 142 are driven and the on-resistance of the buffer 138a is in a low state, so the low level signal of the gate signal DSn changes abruptly from high level to low level and from low level to low level. Switch to high level.

On the other hand, during simultaneous driving, a low-level start pulse StartPlus is input to the driving scanner 132. As a result, the output signal SRn of the shift register 136a is always outputted to the logic circuit 136b as a low level signal in synchronization with the vertical clock VCK.

Further, the control signal EM is at a high level. That is, as shown in FIG. 8, the inverter 142 is not driven and the on-resistance of the buffer 138a is higher. In this case, if the control signal EM is a high level signal without changing the level of the control signal EN, the gate signal DSn becomes a low level signal, and if the control signal EM is a low level signal, the gate signal DSn becomes a high level signal. . Further, in this case, since the on-resistance of the buffer 138a is higher, the low level signal of the gate signal DSn smoothly switches from high to low level and from low to high level. That is, as shown in FIG. 11, the simultaneous rise and fall of the pulses of the gate signals DS1 to DSn are outputted with a slope. As a result, the time tg expressed by equation (3) becomes longer, and the current Ig, which is a rush current, is suppressed.

Since the current Ig, which is a rush current, can be suppressed in this way, there is no need to reinforce the power supply wiring, and an increase in the frame of the display device 100 can be suppressed. Further, since there is no need to select components in consideration of rush current when driving the display device 100 all at once, or to perform intermittent control of the voltage applied to the pixel circuits, it is possible to reduce the size and cost by reducing the number of control components.

As explained above, according to the present embodiment, the drive scanner 132 that outputs the gate signal of the switching element Tg3 has the buffer circuit 138 that outputs the gate signals DS1 to DSn input from the generation circuit 136, and 138a is configured by connecting at least two inverters 140 and 142 in parallel. Thereby, by driving or not driving at least one of the two inverters 140 and 142, the on-resistance of the buffer 138a can be changed. Therefore, when driving the display device 100 to emit light at once, at least one of the two inverters 140 and 142 is not driven, and the on-resistance of the buffer 138a is set to a higher state, so that the gate signals DS1 to DSn pulses rise simultaneously. The slope of simultaneous falling can be made larger. Thereby, the current Ig (formula (3)), which is a rush current, can be suppressed.

On the other hand, during signal writing/variation correction, by driving the two inverters 140 and 142, the on-resistance of the buffer 138a is brought to a lower state. The downward slope can be made smaller. This allows the correction and writing time to be made shorter.

(Modified example of the first embodiment)
Although the transistors Tr1 to Tr3 of the pixel circuit 111 in the display device 100 according to the first embodiment are configured with P-channel type transistors, in the display device 100 according to the modification example of the first embodiment, the transistors Tr1 to Tr3 are configured as N-channel type transistors. They differ in that they are constructed using type transistors. Below, differences from the display device 100 according to the first embodiment will be explained.

FIG. 12 is a diagram showing a configuration example of the pixel circuit 111. As shown in FIG. 12, transistors Tr1 to Tr3 are N-channel transistors. That is, the transistor Tr3 is connected between the power supply node of the power supply voltage VCCP and the source node (source electrode) of the transistor Tr2, and is driven by the light emission control signal DS output from the drive scanner 132 to drive the organic EL element. Controls emission/non-emission of EL.

The drain electrode of the transistor Tr2 is connected to the anode of the organic EL element EL. The transistor Tr2 is a drive transistor that drives the organic EL element EL by causing a drive current corresponding to the holding voltage of the capacitor Cs to flow through the organic EL element EL.

FIG. 13 is a diagram showing a timing chart of batch light emission drive when transistors Tr1 to Tr3 are configured with N-channel transistors. The horizontal axis is time. The top row shows the horizontal synchronization signal (Hsync). Below that, gate signals DS1 to DS3 of the drive line Ds are shown, respectively. Since the transistors Tr1 to Tr3 are N-channel transistors, the high level and low level of the gate signals DS1 to DS3 are reversed from the example shown in FIG. 11. Furthermore, even when the transistors Tr1 to Tr3 are configured with N-channel transistors, by setting the on-resistance of the buffer 138a to a higher state, the slopes of the simultaneous rise and fall of the gate signals DS1 to DSn pulses can be further reduced. You can make it bigger. Thereby, the current Ig (formula (3)), which is a rush current, can be suppressed.

On the other hand, during signal writing/variation correction, by driving the two inverters 140 and 142, the on-resistance of the buffer 138a is brought to a lower state, so that the simultaneous rising and falling of the gate signals DS1 to DSn pulses The slope of can be made smaller. This allows the correction and writing time to be made shorter.

(Second embodiment)
In the display device 100 according to the first embodiment, the current Ig, which is a rush current, is suppressed by changing the rising and falling slopes of the gate signals DS1 to DSn pulses, but the display device 100 according to the second embodiment The difference is that the generation timing of current Ig, which is a rush current, is shifted by shifting the rising and falling timings of the gate signals DS1 to DSn pulses. Below, differences from the display device 100 according to the first embodiment will be explained.

FIG. 14 is a diagram showing a detailed configuration example of the driving scanner 132 according to the second embodiment. As shown in FIG. 14, the generation circuit 136 differs from the display device 100 according to the first embodiment in that it includes a plurality of delay elements 136c. The plurality of delay elements 136c are connected in series, delay the control signal EM for each row, and output it as a control signal EMn to the logic circuit 136b for each row.

Furthermore, the plurality of buffers 138b of the buffer circuit 138 have a configuration in which the on-resistance cannot be changed. That is, the on-resistance of the buffer 138b is in a low on-resistance state in which the rising and falling edges of the pulse are steep.

FIG. 15 is a diagram showing an example of a truth table of the logic circuit 136b according to the second embodiment. As shown in FIG. 9, the logic circuit 136b changes the value of the gate signal DSn based on the values of the output signal SRn, control signals EN, and EMn of the shift register 136a. Here, a high level signal is indicated by 1, and a low level signal is indicated by 0. Control signal EMn is an output signal for each row n of delay element 136c.

When the output signal SRn is 0, the logic circuit 136b outputs 1 as the output signal DRn if the control signal EMn is 0, regardless of the value of the control signal EN; 0 is output as the output signal DRn.

FIG. 16 is a diagram showing an example of an overall timing chart for the driving scanner 132 according to the second embodiment. From the top: vertical synchronization signal Vsync, horizontal synchronization signal Hsync, vertical clock VCK, start pulse StartPlus, control signal EN, control signal EMn (EM1 to EM3 as an example), output signal SRn of the shift register 136a (SR1 to SR3 as an example), Gate signals DSn (DS1 to DS3 as examples) are shown. The left side is driving during signal writing and variation correction, and the right side is driving during simultaneous driving. Further, the vertical clock VCK1, the start pulse StartPlus, and the control signals EN and EM are signals input to the drive scanner 132 from a higher-level control device (not shown), and the gate signal DSn is a signal output from the drive scanner 132. be.

FIG. 17 is a partially enlarged view of the timing chart during simultaneous driving in FIG. 16. In FIG. 17, the left side is driving during simultaneous driving, and the right side is driving during signal writing/variation correction.

As shown in FIG. 16, when the output signal SRn is 1, regardless of the value of the control signal EM, if the control signal EN is 1, 0 is output as the gate signal DSn; For example, 1 is output as the gate signal DSn. That is, at the time of signal writing/variation correction, the gate signals DS1 to DSn according to the first embodiment are the same.

On the other hand, when the output signal SRn is 0, the gate signals DS1 to DSn are inverted signals of the control signals EM1 to EMn. As described above, the control signals EM1 to EMn are outputted after the control signal EM is sequentially delayed by the plurality of delay elements 136c. That is, as shown in FIG. 17, gate signals DS1 to DSn are inverted signals of control signals EM1 to EMn, and are sequentially delayed and output. In this way, the generation circuit 136 sequentially delays the control signal EM, which is the original signal corresponding to the on-time of the input gate signal, row by row, and outputs it as gate signals DS1 to DSn for each row. As a result, gate signals DS1 to DSn can be obtained in which the on-times of the signals overlap and the start and end times of the on-times of the signals are different.

As described above, according to the present embodiment, the driving scanner 132 that outputs the gate signal of the switching element Tg3 sequentially delays the control signal EM by the plurality of delay elements 136c, and outputs the control signal EM as the control signals EM1 to EMn. Gate signals DS1 to DSn are sequentially output as inverted signals of control signals EM1 to EMn. This makes it possible to shift the rising and falling timings of the gate signals DS1 to DSn pulses, and it is possible to shift the generation timing of the current Ig (formula (3)), which is a rush current.

(Third embodiment)
In the display device 100 according to the second embodiment, the timing of the rise and fall of the gate signals DS1 to DSn pulses is shifted by the delay element 136c, thereby shifting the generation timing of the current Ig, which is a rush current. The display device 100 according to this embodiment is different in that a shift register that transmits data using a faster clock is added and the rise and fall timings of the gate signals DS1 to DSn pulses are shifted. Below, differences from the display device 100 according to the second embodiment will be explained.

FIG. 18 is a diagram showing a detailed configuration example of the driving scanner 132 according to the third embodiment. As shown in FIG. 18, the generation circuit 136 differs from the display device 100 according to the second embodiment in that it includes a plurality of shift registers 136d connected in series. Further, the buffer circuit 138 is different from the display device 100 according to the second embodiment in that the buffer circuit 138 is incorporated in the logic circuit 136e.

FIG. 19 is a diagram showing an example of a truth table of the logic circuit 136b according to the third embodiment. As shown in FIG. 19, the logic circuit 136b changes the value of the gate signal DSn based on the value of the output signal SRn of the shift register 136a in the nth row, the control signal EN, and the output signal EMSRn of the shift register 136d in the nth row. Here, a high level signal is indicated by 1, and a low level signal is indicated by 0.

When the output signal SRn is 0, the logic circuit 136e outputs 1 as the output signal DSn if the control signal EMSRn is 0, regardless of the value of the control signal EN, and if the control signal EMSRn is 1, 0 is output as the output signal DSn.

FIG. 20 is a diagram showing an example of an overall timing chart for the driving scanner 132 according to the third embodiment. From the top: vertical synchronization signal Vsync, horizontal synchronization signal Hsync, first vertical clock VCK1, start pulse StartPlus, control signal EN, second vertical clock VCK2, output signal SRn for each shift register 136a (SR1 to SR3 as an example), shift register The output signal EMSRn (for example, EMSR1 to EMSR3) and gate signal DSn (for example, DS1 to DS3) are shown every 136d. The left side is driving during signal writing and variation correction, and the right side is driving during simultaneous driving. The second vertical clock VCK2 is a transmission clock for the shift register 136b.

As shown in FIG. 20, when the output signal SRn is 1, regardless of the value of the control signal EM, if the control signal EN is 1, 0 is output as the gate signal DSn; For example, 1 is output as the gate signal DSn. That is, during signal writing and variation correction, the gate signals DS1 to DSn according to the second embodiment are the same.

On the other hand, when the output signal SRn is 0, the gate signals DS1 to DSn are inverted signals of the control signals EMSR1 to EMSRn. The control signals EMSR1 to EMSRn are sequentially delayed by the shift register 136d while the control signal EM is synchronized with the second vertical clock VCK2, and then outputted. That is, as shown in FIG. 20, similar to the gate signals DS1 to DSn shown in FIG. 16, the control signals EM1 to EMn are inverted signals and are sequentially delayed and output. In this way, the generation circuit 136 sequentially delays the control signal EM, which is the original signal corresponding to the on time of the input gate signal, for each row in synchronization with the second vertical clock VCK2, and generates the gate signal for each row. Output as DS1 to DSn. As a result, gate signals DS1 to DSn can be obtained in which the on-times of the signals overlap and the start and end times of the on-times of the signals are different.

FIG. 21 is a diagram showing another configuration example of the driving scanner 132 according to the third embodiment. As shown in FIG. 218, the input signal to the logic circuit 136b may be changed for each row. In this case, it becomes possible to perform light emission control for each row.

As described above, according to the present embodiment, the drive scanner 132 that outputs the gate signal of the switching element Tg3 sequentially delays the control signal EM in synchronization with the second vertical clock VCK2 using the shift register 136d, and The gate signals DS1 to DSn are sequentially output as inverted signals of the control signals EMSR1 to EMSRn. This makes it possible to shift the rising and falling timings of the gate signals DS1 to DSn pulses, and it is possible to shift the generation timing of the current Ig (formula (3)), which is a rush current.

(Fourth embodiment)
In the display device 100 according to the fourth embodiment, correction driving will be described in detail. FIG. 21 is an explanatory diagram showing a more detailed configuration example of the display device 100 according to the embodiment of the present disclosure. Hereinafter, a configuration example of the display device 100 according to an embodiment of the present disclosure will be described using FIG. 22.

FIG. 22 is a circuit diagram showing a circuit example of the pixel circuit 20A in the display device according to the fourth embodiment. The light emitting section of the pixel circuit 20A is composed of an organic EL element 21. The organic EL element 21 is an example of a current-driven electro-optical element whose luminance changes depending on the value of current flowing through the device.

As shown in FIG. 22, the pixel circuit 20A includes an organic EL element 21 and a drive circuit that drives the organic EL element 21 by passing a current through the organic EL element 21. The organic EL element 21 has a cathode electrode connected to a common power supply line 34 that is wired in common to all pixels 20 .

A drive circuit that drives the organic EL element 21 has a drive transistor 22 , a sampling transistor 23 , a switching transistor 24 , a holding capacitor 25 , and an auxiliary capacitor 26 . Note that it is assumed that the drive transistor 22 is formed not on an insulator such as a glass substrate but on a semiconductor such as silicon, and that a P-channel transistor is used as the drive transistor 22.

Further, in this example, similar to the drive transistor 22, the sampling transistor 23 and the switching transistor 24 are assumed to be formed on a semiconductor, and are configured to use P-channel transistors. Therefore, the drive transistor 22, the sampling transistor 23, and the switching transistor 24 have four terminals, source/gate/drain/back gate, instead of three terminals, source/gate/drain. Power supply voltage Vcc is applied to the back gate.

In the pixel circuit 20A having the above configuration, the sampling transistor 23 writes into the storage capacitor 25 by sampling the signal voltage Vsig supplied from the signal output section 60 through the signal line Vs. The switching transistor 24 is connected between the power supply node of the power supply voltage Vcc and the source electrode of the drive transistor 22, and controls whether or not the organic EL element 21 emits light while being driven by the light emission control signal DS.

The storage capacitor 25 is connected between the gate electrode and the source electrode of the drive transistor 22. This holding capacitor 25 holds the signal voltage Vsig written by sampling by the sampling transistor 23. The drive transistor 22 drives the organic EL element 21 by causing a drive current corresponding to the holding voltage of the holding capacitor 25 to flow through the organic EL element 21 . The auxiliary capacitor 26 is connected between the source electrode of the drive transistor 22 and a fixed potential node, for example, a power supply node of power supply voltage Vcc. This auxiliary capacitor 26 suppresses fluctuations in the source potential of the drive transistor 22 when the signal voltage Vsig is written, and has the function of adjusting the gate-source voltage Vgs of the drive transistor 22 to the threshold voltage Vth of the drive transistor 22. to do.

Next, the basic circuit operation of the display device 100 according to this embodiment will be explained using the timing chart of FIG. 23. FIG. 23 is a timing chart.

The timing waveform diagram in FIG. 23 includes the control signal WS of the scanning line Ws, the control signal DS of the drive line Ds, the potential Vref/Vofs/Vsig of the signal line Vs, the source potential Vs of the drive transistor 22, the gate potential Vg, and , shows how the anode potential Vano of the organic EL element 21 changes.

Note that since the sampling transistor 23 and the switching transistor 24 are of the P-channel type, a low potential state of the write scan signal WS and the light emission control signal DS becomes an active state, and a high potential state becomes an inactive state. The sampling transistor 23 and the switching transistor 24 are conductive when the write scan signal WS and the light emission control signal DS are active, and are non-conductive when the write scan signal WS and the light emission control signal DS are inactive.

The end of the light emitting period of the pixel circuit 20A, that is, the organic EL element 21 is determined at the timing (time t8) when the potential WS of the scanning line 31 transitions from a high potential to a low potential and the sampling transistor 23 becomes conductive. Specifically, in a state where the first reference voltage Vref is output from the signal output unit 60 to the signal line Vs, the potential WS of the scanning line 31 changes from a high potential to a low potential, so that the gate of the drive transistor 22 Since the -source voltage Vgs becomes equal to or lower than the threshold voltage Vth of the drive transistor 22, the drive transistor 22 is cut off.

When the drive transistor 22 is cut off, the path for supplying current to the organic EL element 21 is cut off, so that the anode potential Vano of the organic EL element 21 gradually decreases. Eventually, when the anode potential Vano of the organic EL element 21 becomes equal to or lower than the threshold voltage Vthel of the organic EL element 21, the organic EL element 21 becomes completely extinguished.

At time t1, the potential WS of the scanning line 31 transitions from a high potential to a low potential, so that the sampling transistor 23 becomes conductive. At this time, since the second reference voltage Vofs is being output from the signal output section 60 to the signal line Vs, the gate potential Vg of the drive transistor 22 becomes the second reference voltage Vofs.

Further, at time t1, the potential DS of the drive line Ds is in a low potential state and the switching transistor 24 is in a conductive state, so the source potential Vs of the drive transistor 22 becomes the power supply voltage Vcc. At this time, the gate-source voltage Vgs of the drive transistor 22 becomes Vgs=Vofs-Vcc.

Here, in order to perform a threshold value correction operation (threshold value correction process) to be described later, it is necessary to make the gate-source voltage Vgs of the drive transistor 22 larger than the threshold voltage Vth of the drive transistor 22. Therefore, each voltage value is set so that |Vgs|=|Vofs−Vcc|>|Vth|.

In this way, the initialization operation of setting the gate potential Vg of the drive transistor 22 to the second reference voltage Vofs and the source potential Vs of the drive transistor 22 to the power supply voltage Vcc is performed before performing the next threshold value correction operation. This is the operation of preparation (threshold correction preparation). Therefore, the second reference voltage Vofs and the power supply voltage Vcc are the respective initialization voltages for the gate potential Vg and source potential Vs of the drive transistor 22.

Next, at time t2, the control signal EM is a low level signal (FIG. 9) as described above. Therefore, inverter 140 and inverter 142 are driven to output potential DS with low on-resistance. That is, at time t2, when the potential DS of the drive line Ds abruptly transitions from a low potential to a high potential and the switching transistor 24 becomes non-conductive, the source potential Vs of the drive transistor 22 becomes floating, and the gate of the drive transistor 22 becomes floating. The threshold value correction operation is started while the potential Vg is maintained at the second reference voltage Vofs. That is, the source potential Vs of the drive transistor 22 starts to fall (decrease) toward the potential (Vg−Vth) obtained by subtracting the threshold voltage Vth from the gate potential Vg of the drive transistor 22.

In this way, with the initialization voltage Vofs of the gate potential Vg of the drive transistor 22 as a reference, the source potential Vs of the drive transistor 22 is changed toward the potential (Vg - Vth) obtained by subtracting the threshold voltage Vth from the initialization voltage Vofs. This operation is a threshold value correction operation. As this threshold value correction operation progresses, the gate-source voltage Vgs of the drive transistor 22 eventually converges to the threshold voltage Vth of the drive transistor 22. A voltage corresponding to this threshold voltage Vth is held in the holding capacitor 25.

Then, at time t3, when the potential WS of the scanning line 31 transitions from a low potential to a high potential and the sampling transistor 23 becomes non-conductive, the threshold value correction period ends. After that, at time t4, the signal voltage Vsig of the video signal is output from the signal output unit 60 to the signal line Vs, and the potential of the signal line Vs is switched from the second reference voltage Vofs to the signal voltage Vsig.

Next, at time t5, the potential WS of the scanning line 31 transitions from a high potential to a low potential, so that the sampling transistor 23 becomes conductive, and the signal voltage Vsig is sampled and written into the pixel circuit 20A. This write operation of the signal voltage Vsig by the sampling transistor 23 causes the gate potential Vg of the drive transistor 22 to become the signal voltage Vsig.

When writing the signal voltage Vsig of the video signal, the auxiliary capacitor 26 connected between the source electrode of the drive transistor 22 and the power supply node of the power supply voltage Vcc is configured to prevent the source potential Vs of the drive transistor 22 from changing. It has the effect of suppressing the Then, when the drive transistor 22 is driven by the signal voltage Vsig of the video signal, the threshold voltage Vth of the drive transistor 22 is canceled out by the voltage corresponding to the threshold voltage Vth held in the storage capacitor 25.

At this time, the gate-source voltage Vgs of the drive transistor 22 opens (increases) in accordance with the signal voltage Vsig, but the source potential Vs of the drive transistor 22 is still in a floating state. Therefore, the charge in the storage capacitor 25 is discharged according to the characteristics of the drive transistor 22. At this time, charging of the equivalent capacitance Cel of the organic EL element 21 is started by the current flowing through the drive transistor 22.

As the equivalent capacitance Cel of the organic EL element 21 is charged, the source potential Vs of the drive transistor 22 gradually decreases as time passes. At this time, variations in the threshold voltage Vth of the drive transistor 22 from pixel to pixel have already been canceled, and the drain-source current Ids of the drive transistor 22 depends on the mobility μ of the drive transistor 22. Note that the mobility μ of the drive transistor 22 is the mobility of the semiconductor thin film forming the channel of the drive transistor 22.

Here, the drop in the source potential Vs of the drive transistor 22 acts to discharge the charge stored in the storage capacitor 25. In other words, the amount of decrease (amount of change) in the source potential Vs of the drive transistor 22 is negatively fed back to the storage capacitor 25. Therefore, the drop in the source potential Vs of the drive transistor 22 becomes the amount of negative feedback.

In this way, by applying negative feedback to the holding capacitor 25 with a feedback amount corresponding to the drain-source current Ids flowing through the drive transistor 22, the dependence of the drain-source current Ids of the drive transistor 22 on the mobility μ is reduced. You can cancel gender. This canceling operation (cancelling process) is a mobility correction operation (mobility correction process) that corrects variations in the mobility μ of the drive transistor 22 from pixel to pixel.

More specifically, the greater the signal amplitude Vin (=Vsig-Vofs) of the video signal written to the gate electrode of the drive transistor 22, the greater the drain-source current Ids, so the absolute value of the feedback amount of negative feedback also increases. growing. Therefore, mobility correction processing is performed in accordance with the signal amplitude Vin of the video signal, that is, the light emission brightness level. Furthermore, when the signal amplitude Vin of the video signal is constant, the greater the mobility μ of the drive transistor 22, the greater the absolute value of the feedback amount of negative feedback, so it is possible to eliminate variations in the mobility μ from pixel to pixel. .

At time t6, the potential WS of the scanning line 31 transitions from a low potential to a high potential, and the sampling transistor 23 becomes non-conductive, thereby ending the signal writing & mobility correction period.

At time t7, the control signal EM is a high level signal (FIG. 9) as described above. Therefore, the inverter 142 is not driven and outputs the potential DS with a higher on-resistance. That is, after the mobility correction is performed at time t2, at time t7, as shown in the circle 220, the potential DS of the drive line Ds smoothly transitions from a high potential to a low potential, so that the switching transistor 24 becomes conductive. As a result, current is supplied from the power supply node of power supply voltage Vcc to the drive transistor 22 through the switching transistor 24. In this way, it is possible to output a pulse with a more tilted pulse, that is, a pulse with a longer time tg (formula (3)). As a result, when writing signals and correcting variations, a buffer with high drive capacity (low on-resistance) is charged and discharged to output a steep pulse, and when controlling light emission, a control signal EM is used to charge and discharge a buffer with high drive capacity. By separating it from the path, the pulse slope is modulated.

At this time, since the sampling transistor 23 is in a non-conductive state, the gate electrode of the drive transistor 22 is electrically separated from the signal line Vs and is in a floating state. Here, when the gate electrode of the drive transistor 22 is in a floating state, the storage capacitor 25 is connected between the gate and the source of the drive transistor 22, so that the gate electrode of the drive transistor 22 is linked to fluctuations in the source potential Vs of the drive transistor 22. The gate potential Vg also fluctuates.

That is, the source potential Vs and gate potential Vg of the drive transistor 22 rise while maintaining the gate-source voltage Vgs held in the storage capacitor 25. Then, the source potential Vs of the drive transistor 22 increases to the light emission voltage Voled of the organic EL element 21 according to the saturation current of the transistor.

In this way, the operation in which the gate potential Vg of the drive transistor 22 varies in conjunction with the variation in the source potential Vs is a bootstrap operation. In other words, in the bootstrap operation, the gate potential Vg and source potential Vs of the drive transistor 22 are varied while maintaining the gate-source voltage Vgs held in the holding capacitor 25, that is, the voltage across the holding capacitor 25. This is an action to do.

Then, as the drain-source current Ids of the drive transistor 22 starts to flow into the organic EL element 21, the anode potential Vano of the organic EL element 21 rises in accordance with the current Ids. Eventually, when the anode potential Vano of the organic EL element 21 exceeds the threshold voltage Vthel of the organic EL element 21, a drive current begins to flow through the organic EL element 21, so that the organic EL element 21 starts emitting light.

In the series of circuit operations described above, each operation of threshold value correction preparation, threshold value correction, writing of the signal voltage Vsig (signal writing), and mobility correction is performed, for example, in one horizontal period (1H).

Note that although the case where a driving method in which the threshold value correction process is executed only once has been described here as an example, this driving method is only an example, and the driving method is not limited to this driving method. For example, in addition to the 1H period in which threshold correction is performed together with mobility correction and signal writing, so-called split threshold correction is performed in which the threshold correction is performed multiple times by dividing it over a plurality of horizontal periods preceding the 1H period. It is also possible to adopt a driving method.

As explained above, according to the present embodiment, according to the driving method of dividing threshold correction, even if the time allocated as one horizontal period becomes shorter due to the increase in the number of pixels accompanying high definition, the threshold correction period As a result, sufficient time can be secured over multiple horizontal periods. Therefore, even if the time allocated to one horizontal period becomes shorter, sufficient time can be secured as the threshold value correction period, so that the threshold value correction process can be executed reliably.

Further, according to the present embodiment, the driving scanner 132 that outputs the gate signal of the switching element 24 drives the two inverters 140 and 142 at the start time t2 of threshold correction, thereby reducing the on-resistance of the buffer circuit 138. By setting the potential DS to a lower state, the slope of the simultaneous rise of the potential DS can be made smaller. Thereby, the threshold value correction time can be made shorter.

On the other hand, in the light emission drive t7, the driving scanner 132 that outputs the gate signal of the switching element 24 deactivates at least one of the two inverters 140 and 142, and sets the on-resistance of the buffer circuit 138 to a higher state. , the slope of the fall of the potential DS can be made larger. Thereby, the current Ig, which is a rush current, can be suppressed.

Note that the present technology can have the following configuration.

(1) A drive device that outputs a gate signal of a switching transistor connected in series to an organic EL element in a pixel circuit and a drive transistor that supplies a current to the organic EL element according to the potential of a gate electrode,
a generation circuit that generates a first gate signal;
a buffer that outputs the first gate signal input from the generation circuit as the gate signal,
The buffer is a driving device in which at least two inverters are connected in parallel.

(2) The drive device according to (1), wherein the buffer can change the number of inverters to be driven.

(3) The drive device according to (1) or (2), wherein at least one of the two inverters is not driven depending on the light emission mode of the organic EL element.

(4) In the first light emission mode, the at least two inverters are driven, and in a second light emission mode different from the first light emission mode, the number of inverters to be driven is reduced compared to the first light emission mode. The drive device according to any one of (3).

(5) The driving device according to (1), wherein the first light emitting mode is a mode in which the organic EL elements in each row sequentially emit light in a pixel section in which the pixel circuits are arranged in a matrix.

(6) The optical resonator according to (4), wherein the second light emission mode is a mode in which at least a plurality of rows of organic EL elements emit light simultaneously in a pixel section in which the pixel circuits are arranged in a matrix.

(7) The method according to any one of (1) to (6), wherein the number of inverters driven in the buffer is further reduced when the rush current per unit time at the gate of the switching transistor is further reduced. Drive device.

(8) A drive device that outputs a gate signal of a switching transistor connected in series to an organic EL element in a pixel circuit and a drive transistor that supplies a current to the organic EL element according to a potential of a gate electrode,
A generation circuit that sequentially delays an original signal corresponding to the on time of the input gate signal row by row and outputs the gate signal as the gate signal for each row,
In the driving device, the gate signals corresponding to the plurality of rows of the pixel circuits have on-times that overlap each other, and start and end times of the on-times of the gate signals are different from each other.

(9) The generation circuit is
a plurality of delay elements connected in series, the plurality of delay elements sequentially delaying the original signal corresponding to the on-time for each row;
The driving device according to (8), wherein the drive device outputs the gate signal for each row based on the original signal corresponding to the on time delayed for each row.

(10) The generation circuit is
a shift register that sequentially delays the original signal corresponding to the on-time row by row according to a transmission clock;
The driving device according to (8), wherein the driving device outputs the gate signal for each row based on the original signal corresponding to the on time delayed for each row.

(11) an organic EL element; a drive transistor that supplies a current to the organic EL element according to a signal potential of a gate electrode; and a drive transistor connected in series with the organic EL element and the drive transistor; a pixel section in which a plurality of pixels including a switching transistor for controlling light emission are arranged in a matrix;
a driving device that drives the plurality of pixels;
A display device comprising:
The drive device is
a generation circuit that generates a first gate signal;
A display device comprising: a buffer that outputs a first gate signal input from the generation circuit as the gate signal, the buffer having at least two inverters connected in parallel.

(12) In the first light emission mode, the at least two inverters are driven, and in a second light emission mode different from the first light emission mode, the number of inverters to be driven is reduced compared to the first light emission mode. The display device described in .

(13) The display device according to (12), wherein the first light emitting mode is a mode in which the organic EL elements sequentially emit light row by row in the pixel portion.

(14) The display device according to (12), wherein the second light emission mode is a mode in which at least a plurality of rows of organic EL elements emit light simultaneously in the pixel portion.

(15) The display device according to any one of claims 11 to 14, wherein the number of driven inverters is further reduced when the rush current per unit time at the gate of the switching transistor is further reduced.

(16) A driving method of a driving device that outputs a gate signal of a switching transistor connected in series with an organic EL element in a pixel circuit and a driving transistor that supplies a current to the organic EL element according to the potential of a gate electrode. There it is,
a generation step of generating a first gate signal;
an output step of outputting the first gate signal as the gate signal via a buffer;
a changing step of changing the on-resistance of the buffer;
A driving method for a driving device, comprising:

(17) The driving method of the driving device according to (16), wherein in the changing step, the on-resistance of the buffer is increased when the rush current per unit time at the gate of the switching transistor is further reduced.

20: Pixel circuit, 22: Driving transistor, 23: Sampling transistor, 24: Switching transistor, 100: Display device, 110: Pixel section, 111: Pixel circuit, 130: Vertical scanner (drive device), 132: Generation circuit, 136b : logic circuit, 136c: delay element, 136d: shift register, 138a: buffer, 140: inverter, 142: inverter, EL: organic EL element, Tr1: sampling transistor, Tr2: drive transistor, Tr3: switching transistor.

Claims (10)

A drive device that outputs a gate signal of a switching transistor connected in series with an organic EL element in a pixel circuit and a drive transistor that supplies a current to the organic EL element according to a potential of a gate electrode,
a generation circuit that generates a first gate signal;
a buffer that outputs the first gate signal input from the generation circuit as the gate signal,
The buffer has at least two inverters connected in parallel,
A driving device that deactivates at least one of the two inverters depending on the light emission mode of the organic EL element . The drive device according to claim 1, wherein the buffer can change the number of inverters to be driven. 3. The at least two inverters are driven in a first light emission mode, and in a second light emission mode different from the first light emission mode, the number of inverters to be driven is reduced compared to the first light emission mode. Drive device as described. 4. The driving device according to claim 3 , wherein the first light emitting mode is a mode in which organic EL elements in each row of a pixel section in which the pixel circuits are arranged in a matrix form sequentially emit light. 4. The driving device according to claim 3 , wherein the second light emitting mode is a mode in which at least a plurality of rows of organic EL elements emit light simultaneously in a pixel section in which the pixel circuits are arranged in a matrix. 6. The drive device according to claim 1, wherein when the rush current per unit time at the gate of the switching transistor is further reduced, the number of inverters driven in the buffer is further reduced. An organic EL element, a drive transistor that supplies a current to the organic EL element according to a signal potential of a gate electrode, and is connected in series with the organic EL element and the drive transistor, and controls light emission of the organic EL element by a control signal. a pixel section in which a plurality of pixels including a switching transistor to be controlled are arranged in a matrix;
a driving device that drives the plurality of pixels;
A display device comprising:
The drive device is
a generation circuit that generates a first gate signal;
a buffer that outputs the first gate signal inputted from the generation circuit as a gate signal, the buffer having at least two inverters connected in parallel, and in the first light emission mode, the at least two inverters A display device that drives an inverter , and in a second light emitting mode different from the first light emitting mode, the number of inverters to be driven is smaller than in the first light emitting mode. 8. The display device according to claim 7 , wherein the first light emitting mode is a mode in which the organic EL elements are caused to emit light sequentially row by row in the pixel section. 8. The display device according to claim 7 , wherein the second light emitting mode is a mode in which at least a plurality of rows of organic EL elements emit light simultaneously in the pixel section. 10. The display device according to claim 7 , wherein the number of driven inverters is further reduced when the rush current per unit time at the gate of the switching transistor is further reduced.