JP7401372B2 - Wafer processing method - Google Patents
Wafer processing method Download PDFInfo
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- JP7401372B2 JP7401372B2 JP2020056179A JP2020056179A JP7401372B2 JP 7401372 B2 JP7401372 B2 JP 7401372B2 JP 2020056179 A JP2020056179 A JP 2020056179A JP 2020056179 A JP2020056179 A JP 2020056179A JP 7401372 B2 JP7401372 B2 JP 7401372B2
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- 238000003672 processing method Methods 0.000 title claims description 16
- 230000002093 peripheral effect Effects 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 12
- 230000001681 protective effect Effects 0.000 claims description 12
- 238000012986 modification Methods 0.000 claims description 3
- 230000004048 modification Effects 0.000 claims description 3
- 235000012431 wafers Nutrition 0.000 description 137
- 238000003384 imaging method Methods 0.000 description 10
- 230000003287 optical effect Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 239000002390 adhesive tape Substances 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000009833 condensation Methods 0.000 description 1
- 230000005494 condensation Effects 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K26/00—Working by laser beam, e.g. welding, cutting or boring
- B23K26/50—Working by transmitting the laser beam through or within the workpiece
- B23K26/53—Working by transmitting the laser beam through or within the workpiece for modifying or reforming the material inside the workpiece, e.g. for producing break initiation cracks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
Description
本発明は、複数のデバイスが分割予定ラインによって区画されたデバイス領域と、デバイス領域を囲繞する外周余剰領域とが表面に形成されたウエーハを個々のデバイスチップに分割するウエーハの加工方法に関する。 The present invention relates to a wafer processing method for dividing a wafer having a device region in which a plurality of devices are partitioned by dividing lines and a peripheral surplus region surrounding the device region into individual device chips.
ＩＣ、ＬＳＩ等の複数のデバイスが分割予定ラインによって区画されたデバイス領域と、デバイス領域を囲繞する外周余剰領域とが表面に形成されたウエーハは個々のデバイスチップに分割され、分割されたデバイスチップは携帯電話、パソコン等の電気機器に利用される。 A wafer with a device area in which multiple devices such as ICs, LSIs, etc. are partitioned by dividing lines and an extra peripheral area surrounding the device area is divided into individual device chips, and the divided device chips are divided into individual device chips. is used in electrical devices such as mobile phones and computers.
ウエーハを個々のデバイスチップに分割する方法として、ウエーハに対して透過性を有する波長のレーザー光線の集光点を分割予定ラインに対応するウエーハの内部に位置づけてレーザー光線をウエーハに照射し改質層を分割予定ラインに沿って形成し、その後、ウエーハに外力を付与して個々のデバイスチップに分割する技術が提案されている（たとえば特許文献１参照）。 As a method of dividing a wafer into individual device chips, the focal point of a laser beam with a wavelength that is transparent to the wafer is positioned inside the wafer corresponding to the planned division line, and the laser beam is irradiated onto the wafer to form a modified layer. A technique has been proposed in which a wafer is formed along a planned dividing line and then divided into individual device chips by applying an external force to the wafer (for example, see Patent Document 1).
また、ウエーハに外力を付与する方法として、ウエーハの表面に保護部材を配設しウエーハの裏面を研削することでウエーハを所望の厚みに薄くすると共に、改質層からクラックを表面に到達させてウエーハを個々のデバイスチップに分割する技術も提案されている（たとえば特許文献２参照）。 Another method of applying external force to the wafer is to thin the wafer to a desired thickness by disposing a protective member on the surface of the wafer and grinding the back surface of the wafer, and also to allow cracks to reach the surface from the modified layer. A technique for dividing a wafer into individual device chips has also been proposed (see, for example, Patent Document 2).
しかし、ウエーハの外周余剰領域の外周面には面取り加工が施されており、分割予定ラインの延長線上の面取り加工が施された領域には改質層を形成することが困難である。このため、ウエーハの内部に分割予定ラインに沿って改質層を形成した後にウエーハに外力を付与すると、外周余剰領域における面取り加工が施された領域においては改質層が形成されていないことに起因して無秩序にクラックが発生することがあり、これによって外周余剰領域に隣接するデバイスが損傷するという問題がある。 However, the outer circumferential surface of the wafer's excess outer circumferential region is chamfered, and it is difficult to form a modified layer in the chamfered region on the extension line of the planned dividing line. Therefore, if an external force is applied to the wafer after forming a modified layer inside the wafer along the planned dividing line, the modified layer will not be formed in the chamfered area in the excess outer circumferential area. As a result, cracks may occur in a disordered manner, which causes a problem of damage to devices adjacent to the peripheral excess area.
上記事実に鑑みてなされた本発明の課題は、ウエーハの外周余剰領域に隣接するデバイスの損傷を防止することができるウエーハの加工方法を提供することである。 An object of the present invention, which has been made in view of the above facts, is to provide a wafer processing method that can prevent damage to devices adjacent to the peripheral surplus area of the wafer.
本発明は上記課題を解決するために以下のウエーハの加工方法を提供する。すなわち、複数のデバイスが分割予定ラインによって区画されたデバイス領域と、該デバイス領域を囲繞する外周余剰領域とが表面に形成されたウエーハを個々のデバイスチップに分割するウエーハの加工方法であって、ウエーハの表面に保護部材を配設する保護部材配設工程と、ウエーハに対して透過性を有する波長のレーザー光線の集光点をウエーハの裏面から外周余剰領域に対応するウエーハの内部に位置づけてレーザー光線をウエーハに照射し外周余剰領域に沿って第一のリング状改質層と該第一のリング状改質層を囲繞する第二のリング状改質層とを形成するリング状改質層形成工程と、ウエーハに対して透過性を有する波長のレーザー光線の集光点をウエーハの裏面から分割予定ラインに対応するウエーハの内部に位置づけてレーザー光線をウエーハに照射し分割予定ラインに沿って分割予定ライン改質層を形成する分割予定ライン改質層形成工程と、ウエーハの裏面を研削して所定の厚みに形成すると共に該分割予定ライン改質層から分割予定ラインに伸長するクラックによってウエーハを個々のデバイスチップに分割する分割工程と、を含み、該分割予定ライン改質層形成工程において、該分割予定ライン改質層の始点および終点が該第一のリング状改質層と該第二のリング状改質層との間に位置するようにレーザー光線の集光点を位置づけるウエーハの加工方法を本発明は提供する。 In order to solve the above problems, the present invention provides the following wafer processing method. That is, a wafer processing method in which a wafer having a surface formed with a device region in which a plurality of devices are partitioned by dividing lines and an outer peripheral surplus region surrounding the device region is divided into individual device chips, A protective member disposing step in which a protective member is disposed on the surface of the wafer, and a laser beam is emitted from the back surface of the wafer by positioning the convergence point of the laser beam with a wavelength that is transparent to the wafer inside the wafer corresponding to the outer peripheral surplus area. Forming a ring-shaped modified layer by irradiating the wafer with a first ring-shaped modified layer and forming a second ring-shaped modified layer surrounding the first ring-shaped modified layer along the outer peripheral surplus area. In the process, the convergence point of a laser beam with a wavelength that is transparent to the wafer is positioned inside the wafer from the back side of the wafer corresponding to the planned dividing line, and the laser beam is irradiated onto the wafer along the planned dividing line. A dividing line modified layer forming step in which a modified layer is formed, and the back surface of the wafer is ground to form a predetermined thickness, and the wafer is separated into individual wafers by cracks extending from the dividing line modified layer to the dividing line. a dividing step of dividing into device chips, and in the dividing line modified layer forming step, the starting point and end point of the dividing line modified layer are located between the first ring-shaped modified layer and the second ring-shaped modified layer. The present invention provides a wafer processing method in which the focal point of a laser beam is positioned between the wafer and the wafer.
好ましくは、該リング状改質層形成工程において形成する該第一のリング状改質層と該第二のリング状改質層との間隔を３００～１０００μｍに設定する。 Preferably, the interval between the first ring-shaped modified layer and the second ring-shaped modified layer formed in the ring-shaped modified layer forming step is set to 300 to 1000 μm.
本発明のウエーハの加工方法は、複数のデバイスが分割予定ラインによって区画されたデバイス領域と、該デバイス領域を囲繞する外周余剰領域とが表面に形成されたウエーハを個々のデバイスチップに分割するウエーハの加工方法であって、ウエーハの表面に保護部材を配設する保護部材配設工程と、ウエーハに対して透過性を有する波長のレーザー光線の集光点をウエーハの裏面から外周余剰領域に対応するウエーハの内部に位置づけてレーザー光線をウエーハに照射し外周余剰領域に沿って第一のリング状改質層と該第一のリング状改質層を囲繞する第二のリング状改質層とを形成するリング状改質層形成工程と、ウエーハに対して透過性を有する波長のレーザー光線の集光点をウエーハの裏面から分割予定ラインに対応するウエーハの内部に位置づけてレーザー光線をウエーハに照射し分割予定ラインに沿って分割予定ライン改質層を形成する分割予定ライン改質層形成工程と、ウエーハの裏面を研削して所定の厚みに形成すると共に該分割予定ライン改質層から分割予定ラインに伸長するクラックによってウエーハを個々のデバイスチップに分割する分割工程と、を含み、該分割予定ライン改質層形成工程において、該分割予定ライン改質層の始点および終点が該第一のリング状改質層と該第二のリング状改質層との間に位置するようにレーザー光線の集光点を位置づけるので、分割予定ライン改質層の始点または終点から無秩序にクラックが伸長したとしても、第一のリング状改質層と第二のリング状改質層とによってクラックが遮断されるため、クラックがデバイスに到達することがない。したがって、本発明のウエーハの加工方法によれば、ウエーハの外周余剰領域に隣接するデバイスの損傷を防止することができる。 The wafer processing method of the present invention includes dividing a wafer into individual device chips, the wafer having a device region in which a plurality of devices are partitioned by division lines and an outer peripheral surplus region surrounding the device region formed on the surface thereof. The processing method includes a protective member disposing step of disposing a protective member on the surface of the wafer, and a convergence point of a laser beam having a wavelength that is transparent to the wafer from the back surface of the wafer to the outer peripheral surplus area. A laser beam is positioned inside the wafer and the wafer is irradiated with a laser beam to form a first ring-shaped modified layer and a second ring-shaped modified layer surrounding the first ring-shaped modified layer along the outer peripheral surplus area. A process of forming a ring-shaped modified layer, and a laser beam with a wavelength that is transparent to the wafer is positioned inside the wafer from the back surface of the wafer corresponding to the dividing line, and the laser beam is irradiated onto the wafer to prepare the wafer for dividing. A dividing line modified layer forming step of forming a dividing line modified layer along the line, and grinding the back side of the wafer to form a predetermined thickness, and extending from the dividing line modified layer to the dividing line. a dividing step of dividing the wafer into individual device chips by cracking, and in the dividing line modified layer forming step, the starting point and end point of the dividing line modified layer form the first ring-shaped modified layer. Since the focal point of the laser beam is positioned between the layer and the second ring-shaped modified layer, even if cracks extend randomly from the starting point or end point of the planned dividing line modified layer, the first ring-shaped modified layer Since the cracks are blocked by the ring-shaped modified layer and the second ring-shaped modified layer, the cracks do not reach the device. Therefore, according to the wafer processing method of the present invention, it is possible to prevent damage to devices adjacent to the extra peripheral region of the wafer.
以下、本発明のウエーハの加工方法の好適実施形態について図面を参照しつつ説明する。 Hereinafter, preferred embodiments of the wafer processing method of the present invention will be described with reference to the drawings.
図１には、本発明のウエーハの加工方法によって加工が施されるウエーハ２が示されている。ウエーハ２は、たとえばシリコン等から形成され得る。円板状のウエーハ２の表面２ａは、ＩＣ、ＬＳＩ等の複数のデバイス４が格子状の分割予定ライン６によって区画されたデバイス領域８と、デバイス領域８を囲繞する外周余剰領域１０とが形成されている。図１では、便宜的にデバイス領域８と外周余剰領域１０との境界１２を二点鎖線で示しているが、実際には境界１２を示す線は存在しない。 FIG. 1 shows a wafer 2 that is processed by the wafer processing method of the present invention. The wafer 2 may be made of silicon or the like, for example. The surface 2a of the disk-shaped wafer 2 is formed with a device region 8 in which a plurality of devices 4 such as ICs and LSIs are partitioned by grid-like dividing lines 6, and an outer peripheral surplus region 10 surrounding the device region 8. has been done. In FIG. 1, the boundary 12 between the device region 8 and the peripheral surplus region 10 is shown by a two-dot chain line for convenience, but in reality, there is no line indicating the boundary 12.
図示の実施形態のウエーハの加工方法では、図１に示すとおり、まず、ウエーハ２の表面２ａに保護部材１４を配設する保護部材配設工程を実施する。保護部材１４としては、たとえば、ウエーハ２の直径と同一の直径を有する円形の粘着テープを用いることができる。 In the wafer processing method of the illustrated embodiment, as shown in FIG. 1, first, a protective member disposing step of disposing a protective member 14 on the surface 2a of the wafer 2 is carried out. As the protection member 14, for example, a circular adhesive tape having the same diameter as the wafer 2 can be used.
保護部材配設工程を実施した後、ウエーハ２に対して透過性を有する波長のレーザー光線の集光点をウエーハ２の裏面２ｂから外周余剰領域１０に対応するウエーハ２の内部に位置づけてレーザー光線をウエーハ２に照射し、外周余剰領域１０に沿って第一のリング状改質層と第一のリング状改質層を囲繞する第二のリング状改質層とを形成するリング状改質層形成工程を実施する。 After carrying out the protective member disposing process, the convergence point of the laser beam with a wavelength that is transparent to the wafer 2 is positioned inside the wafer 2 corresponding to the outer peripheral surplus area 10 from the back surface 2b of the wafer 2, and the laser beam is directed to the wafer 2. Formation of a ring-shaped modified layer by irradiating 2 to form a first ring-shaped modified layer and a second ring-shaped modified layer surrounding the first ring-shaped modified layer along the outer peripheral surplus region 10 Implement the process.
リング状改質層形成工程は、たとえば図２および図３に一部を示すレーザー加工装置１６を用いて実施することができる。レーザー加工装置１６は、ウエーハ２を吸引保持するチャックテーブル１８と、チャックテーブル１８に吸引保持されたウエーハ２にパルスレーザー光線ＬＢを照射する集光器２０と、チャックテーブル１８に吸引保持されたウエーハ２を撮像する撮像手段（図示していない。）とを備える。 The ring-shaped modified layer forming step can be carried out using, for example, a laser processing device 16, a part of which is shown in FIGS. 2 and 3. The laser processing device 16 includes a chuck table 18 that holds the wafer 2 by suction, a condenser 20 that irradiates the wafer 2 held by the chuck table 18 with a pulsed laser beam LB, and a wafer 2 held by the chuck table 18 by suction. and an imaging means (not shown) for imaging the image.
図２に示すとおり、チャックテーブル１８の上端には、吸引手段（図示していない。）に接続された多孔質の円形の吸着チャック２２が配置されている。チャックテーブル１８は、吸引手段で吸着チャック２２の上面に吸引力を生成し、吸着チャック２２の上面に載せられたウエーハ２を吸引保持する。 As shown in FIG. 2, a porous circular suction chuck 22 connected to suction means (not shown) is disposed at the upper end of the chuck table 18. The chuck table 18 uses suction means to generate suction force on the upper surface of the suction chuck 22, and suction-holds the wafer 2 placed on the upper surface of the suction chuck 22.
チャックテーブル１８は、吸着チャック２２の径方向中心を通って上下方向に延びる軸線を回転中心として回転自在に構成されていると共に、図２に矢印Ｘで示すＸ軸方向と、Ｘ軸方向に直交するＹ軸方向（図２に矢印Ｙで示す方向）とのそれぞれに進退自在に構成されている。なお、Ｘ軸方向およびＹ軸方向が規定するＸＹ平面は実質上水平である。 The chuck table 18 is configured to be rotatable about an axis that passes through the radial center of the suction chuck 22 and extends in the vertical direction. It is configured to be able to freely move forward and backward in the Y-axis direction (direction indicated by arrow Y in FIG. 2). Note that the XY plane defined by the X-axis direction and the Y-axis direction is substantially horizontal.
集光器２０は、レーザー加工装置１６のレーザー光線発振器（図示していない。）が発振したパルスレーザー光線ＬＢを集光する集光レンズ（図示していない。）を有する。レーザー加工装置１６の撮像手段は、可視光線により被加工物を撮像する通常の撮像素子（ＣＣＤ）と、被加工物に赤外線を照射する赤外線照射手段と、赤外線照射手段により照射された赤外線を捕らえる光学系と、光学系が捕らえた赤外線に対応する電気信号を出力する撮像素子（赤外線ＣＣＤ）とを含む（いずれも図示していない。）。 The condenser 20 has a condenser lens (not shown) that condenses the pulsed laser beam LB emitted by the laser beam oscillator (not shown) of the laser processing device 16 . The imaging means of the laser processing device 16 includes a normal imaging device (CCD) that images the workpiece using visible light, an infrared irradiation means that irradiates the workpiece with infrared rays, and an infrared ray irradiated by the infrared irradiation means that captures the infrared rays. It includes an optical system and an image sensor (infrared CCD) that outputs an electrical signal corresponding to the infrared rays captured by the optical system (none of which are shown).
リング状改質層形成工程では、図２に示すとおり、まず、ウエーハ２の裏面２ｂを上に向けて、チャックテーブル１８の上面でウエーハ２を吸引保持する。この際は、ウエーハ２の径方向中心と吸着チャック２２の径方向中心（チャックテーブル１８の回転中心）とを整合させる。 In the ring-shaped modified layer forming step, as shown in FIG. 2, first, the wafer 2 is suction-held on the upper surface of the chuck table 18 with the back surface 2b of the wafer 2 facing upward. At this time, the radial center of the wafer 2 and the radial center of the suction chuck 22 (the rotation center of the chuck table 18) are aligned.
次いで、レーザー加工装置１６の撮像手段（図示していない。）で上方からウエーハ２を撮像し、撮像手段で撮像したウエーハ２の画像に基づいて、ウエーハ２に対して透過性を有する波長のパルスレーザー光線ＬＢの集光点をウエーハ２の裏面２ｂから外周余剰領域１０に対応するウエーハ２の内部に位置づける。 Next, an imaging means (not shown) of the laser processing device 16 images the wafer 2 from above, and based on the image of the wafer 2 taken by the imaging means, a pulse of a wavelength that is transparent to the wafer 2 is generated. The condensing point of the laser beam LB is positioned inside the wafer 2 corresponding to the outer peripheral surplus area 10 from the back surface 2b of the wafer 2.
なお、撮像手段でウエーハ２を撮像した際には、ウエーハ２の裏面２ｂが上を向き、デバイス４や分割予定ライン６が形成されている表面２ａは下を向いているが、上述のとおり、撮像手段は、赤外線照射手段と、赤外線を捕らえる光学系と、赤外線に対応する電気信号を出力する撮像素子（赤外線ＣＣＤ）とを含むので、ウエーハ２の裏面２ｂから透かして表面２ａのデバイス４や分割予定ライン６を撮像することができる。これによって、ウエーハ２の裏面２ｂから外周余剰領域１０に対応するウエーハ２の内部にパルスレーザー光線ＬＢの集光点を位置づけることができる。 Note that when the wafer 2 is imaged by the imaging means, the back surface 2b of the wafer 2 faces upward, and the surface 2a on which the devices 4 and planned dividing line 6 are formed faces downward; however, as described above, The imaging means includes an infrared irradiation means, an optical system that captures infrared rays, and an imaging element (infrared CCD) that outputs an electric signal corresponding to infrared rays, so that it can be seen through the back surface 2b of the wafer 2 and the devices 4 and the like on the front surface 2a. The planned dividing line 6 can be imaged. Thereby, the condensing point of the pulsed laser beam LB can be positioned inside the wafer 2 corresponding to the outer peripheral surplus area 10 from the back surface 2b of the wafer 2.
次いで、図３に示すとおり、所定の回転速度でチャックテーブル１８を回転させることにより、外周余剰領域１０に沿ってパルスレーザー光線ＬＢの集光点をウエーハ２に対して相対的に移動させながら、パルスレーザー光線ＬＢを集光器２０からウエーハ２に照射する。これによって、外周余剰領域１０に対応するウエーハ２の内部に強度が小さい第一のリング状改質層２４を外周余剰領域１０に沿って形成することができる。 Next, as shown in FIG. 3, by rotating the chuck table 18 at a predetermined rotational speed, the condensing point of the pulsed laser beam LB is moved relative to the wafer 2 along the outer peripheral surplus area 10, and the pulsed laser beam LB is rotated at a predetermined rotation speed. A laser beam LB is irradiated onto the wafer 2 from a condenser 20. As a result, the first ring-shaped modified layer 24 having low strength can be formed inside the wafer 2 corresponding to the outer circumferential excess area 10 along the outer circumferential excess area 10 .
次いで、チャックテーブル１８を移動させ、第一のリング状改質層２４よりも径方向外側にパルスレーザー光線ＬＢの集光点を位置づける。次いで、所定の回転速度でチャックテーブル１８を回転させることにより、外周余剰領域１０に沿ってパルスレーザー光線ＬＢの集光点をウエーハ２に対して相対的に移動させながら、パルスレーザー光線ＬＢを集光器２０からウエーハ２に照射する。これによって、外周余剰領域１０に対応するウエーハ２の内部に強度が小さい第二のリング状改質層２６を外周余剰領域１０に沿って形成することができる。 Next, the chuck table 18 is moved to position the focal point of the pulsed laser beam LB radially outside the first ring-shaped modified layer 24 . Next, by rotating the chuck table 18 at a predetermined rotational speed, the condensing point of the pulsed laser beam LB is moved along the outer peripheral surplus area 10 relative to the wafer 2, and the pulsed laser beam LB is transferred to the condenser. The wafer 2 is irradiated from 20. As a result, a second ring-shaped modified layer 26 having low strength can be formed inside the wafer 2 corresponding to the surplus outer region 10 along the surplus outer region 10 .
図４（ａ）および図４（ｂ）を参照することによって理解されるとおり、第二のリング状改質層２６の直径は第一のリング状改質層２４の直径よりも大きく、第二のリング状改質層２６は第一のリング状改質層２４を囲繞している。第一のリング状改質層２４と第二のリング状改質層２６との間隔（ウエーハ２の径方向における間隔）は、たとえば３００～１０００μｍに設定することができる。 As understood by referring to FIGS. 4(a) and 4(b), the diameter of the second ring-shaped modified layer 26 is larger than the diameter of the first ring-shaped modified layer 24, and the second ring-shaped modified layer 26 has a diameter larger than that of the first ring-shaped modified layer 24. The ring-shaped modified layer 26 surrounds the first ring-shaped modified layer 24 . The interval between the first ring-shaped modified layer 24 and the second ring-shaped modified layer 26 (the interval in the radial direction of the wafer 2) can be set to, for example, 300 to 1000 μm.
このようなリング状改質層形成工程は、たとえば以下の条件で行うことができる。
ウエーハの直径 ：φ２００ｍｍ
デバイス領域の直径 ：φ１９０ｍｍ
外周余剰領域の範囲 ：φ１９０ｍｍ～φ２００ｍｍ
第一のリング状改質層の直径：φ１９３ｍｍ
第二のリング状改質層の直径：φ１９４ｍｍ
パルスレーザー光線の波長 ：１３４２ｎｍ
繰り返し周波数 ：９０ｋＨｚ
平均出力 ：０．６Ｗ
チャックテーブルの回転速度：０．５周／秒
Such a ring-shaped modified layer forming step can be performed, for example, under the following conditions.
Wafer diameter: φ200mm
Device area diameter: φ190mm
Range of extra peripheral area: φ190mm to φ200mm
Diameter of first ring-shaped modified layer: φ193mm
Diameter of second ring-shaped modified layer: φ194mm
Wavelength of pulsed laser beam: 1342nm
Repetition frequency: 90kHz
Average output: 0.6W
Chuck table rotation speed: 0.5 laps/sec
リング状改質層形成工程を実施した後、ウエーハ２に対して透過性を有する波長のレーザー光線の集光点をウエーハ２の裏面２ｂから分割予定ライン６に対応するウエーハ２の内部に位置づけてレーザー光線をウエーハ２に照射し分割予定ライン６に沿って分割予定ライン改質層を形成する分割予定ライン改質層形成工程を実施する。分割予定ライン改質層形成工程も、上記レーザー加工装置１６を用いて実施することができる。 After performing the ring-shaped modified layer forming step, the focal point of the laser beam with a wavelength that is transparent to the wafer 2 is positioned inside the wafer 2 corresponding to the planned dividing line 6 from the back surface 2b of the wafer 2, and the laser beam is A dividing line modified layer forming step is carried out in which the wafer 2 is irradiated with the wafer 2 to form a dividing line modified layer along the dividing line 6. The planned dividing line modified layer forming step can also be performed using the laser processing device 16 described above.
分割予定ライン改質層形成工程では、まず、チャックテーブル１８の上面でウエーハ２を吸引保持した状態において、レーザー加工装置１６の撮像手段で撮像したウエーハ２の画像に基づいて、分割予定ライン６をＸ軸方向に整合させると共に、Ｘ軸方向に整合させた分割予定ライン６の上方に集光器２０を位置づける。次いで、ウエーハ２の裏面２ｂから分割予定ライン６に対応するウエーハ２の内部であって、第一のリング状改質層２４と第二のリング状改質層２６との間に、ウエーハ２に対して透過性を有する波長のパルスレーザー光線ＬＢの集光点を位置づける。 In the dividing line modified layer forming step, first, with the wafer 2 being suction-held on the upper surface of the chuck table 18, the dividing line 6 is formed based on an image of the wafer 2 taken by the imaging means of the laser processing device 16. The condenser 20 is aligned in the X-axis direction and positioned above the planned dividing line 6 aligned in the X-axis direction. Next, the inside of the wafer 2 corresponding to the planned dividing line 6 from the back surface 2b of the wafer 2, between the first ring-shaped modified layer 24 and the second ring-shaped modified layer 26, is coated on the wafer 2. The focal point of the pulsed laser beam LB having a wavelength that is transparent to the laser beam is positioned.
次いで、図５（ａ）に示すとおり、所定の送り速度でチャックテーブル１８をＸ軸方向に移動させることにより、分割予定ライン６に沿ってパルスレーザー光線ＬＢの集光点をウエーハ２に対して相対的に移動させながら、パルスレーザー光線ＬＢを集光器２０からウエーハ２に照射する。これによって、分割予定ライン６に沿ってウエーハ２の内部に強度が小さい分割予定ライン改質層２８を形成することができる。分割予定ライン改質層２８を形成する際は、パルスレーザー光線ＬＢの集光点が第一のリング状改質層２４と第二のリング状改質層２６との間に到達したらパルスレーザー光線ＬＢの照射を停止する。 Next, as shown in FIG. 5(a), by moving the chuck table 18 in the X-axis direction at a predetermined feed rate, the focal point of the pulsed laser beam LB is moved relative to the wafer 2 along the dividing line 6. The pulsed laser beam LB is irradiated from the condenser 20 onto the wafer 2 while moving the wafer 2 . Thereby, a planned dividing line modified layer 28 having low strength can be formed inside the wafer 2 along the scheduled dividing line 6. When forming the planned dividing line modified layer 28, when the condensation point of the pulsed laser beam LB reaches between the first ring-shaped modified layer 24 and the second ring-shaped modified layer 26, the pulsed laser beam LB is Stop irradiation.
分割予定ライン改質層形成工程においては、図５（ｂ）ないし図５（ｄ）に示すとおり、分割予定ライン改質層２８の始点２８ａおよび終点２８ｂが第一のリング状改質層２４と第二のリング状改質層２６との間に位置するようにレーザー光線ＬＢの集光点を位置づけるのが重要である。 In the dividing line modified layer forming step, as shown in FIGS. 5(b) to 5(d), the starting point 28a and the ending point 28b of the dividing line modified layer 28 are connected to the first ring-shaped modified layer 24. It is important to position the condensing point of the laser beam LB so as to be located between it and the second ring-shaped modified layer 26.
次いで、分割予定ライン６のＹ軸方向の間隔の分だけ、集光器２０に対してチャックテーブル１８を相対的にＹ軸方向に割り出し送りする。そして、レーザー光線ＬＢの照射と割り出し送りとを交互に繰り返すことにより、Ｘ軸方向に整合させた分割予定ライン６のすべてに沿って分割予定ライン改質層２８を形成する。また、チャックテーブル１８を９０度回転させた上で、レーザー光線ＬＢの照射と割り出し送りとを交互に繰り返すことにより、先に分割予定ライン改質層２８を形成した分割予定ライン６と直交する分割予定ライン６のすべてに沿って分割予定ライン改質層２８を形成する。 Next, the chuck table 18 is indexed and sent in the Y-axis direction relative to the condenser 20 by an interval of the planned dividing line 6 in the Y-axis direction. Then, by alternately repeating the irradiation of the laser beam LB and the indexing feed, the planned dividing line modified layer 28 is formed along all the planned dividing lines 6 aligned in the X-axis direction. Further, by rotating the chuck table 18 by 90 degrees and repeating the irradiation of the laser beam LB and the indexing feed alternately, the division schedule is made perpendicular to the division schedule line 6 on which the division schedule line modified layer 28 was previously formed. A dividing line modification layer 28 is formed along all of the lines 6.
このような分割予定ライン改質層形成工程は、たとえば以下の条件で行うことができる。
パルスレーザー光線の波長 ：１３４２ｎｍ
繰り返し周波数 ：９０ｋＨｚ
平均出力 ：０．６Ｗ
チャックテーブルの送り速度：５００ｍｍ／ｓ
Such a planned division line modified layer forming step can be performed, for example, under the following conditions.
Wavelength of pulsed laser beam: 1342nm
Repetition frequency: 90kHz
Average output: 0.6W
Chuck table feed speed: 500mm/s
分割予定ライン改質層形成工程を実施した後、ウエーハ２の裏面２ｂを研削して所定の厚みに形成すると共に分割予定ライン改質層２８から分割予定ライン６に伸長するクラックによってウエーハ２を個々のデバイスチップに分割する分割工程を実施する。 After performing the dividing line modified layer forming step, the back surface 2b of the wafer 2 is ground to a predetermined thickness, and the wafer 2 is individually separated by cracks extending from the dividing line modified layer 28 to the dividing line 6. A dividing step is performed to divide the device into device chips.
分割工程は、たとえば図６に一部を示す研削装置３０を用いて実施することができる。研削装置３０は、ウエーハ２を吸引保持するチャックテーブル３２と、チャックテーブル３２に吸引保持されたウエーハ２を研削する研削手段３４とを備える。上面においてウエーハ２を吸引保持するチャックテーブル３２は上下方向に延びる軸線を中心として回転自在に構成されている。 The dividing step can be performed using, for example, a grinding device 30, a part of which is shown in FIG. The grinding device 30 includes a chuck table 32 that holds the wafer 2 under suction, and a grinding means 34 that grinds the wafer 2 that is suction-held on the chuck table 32. The chuck table 32, which holds the wafer 2 by suction on its upper surface, is configured to be rotatable about an axis extending in the vertical direction.
研削手段３４は、上下方向に延びるスピンドル３６と、スピンドル３６の下端に固定された円板状のホイールマウント３８とを含む。ホイールマウント３８の下面にはボルト４０によって環状の研削ホイール４２が固定されている。研削ホイール４２の下面の外周縁部には、周方向に間隔をおいて環状に配置された複数の研削砥石４４が固定されている。 The grinding means 34 includes a spindle 36 that extends in the vertical direction, and a disc-shaped wheel mount 38 fixed to the lower end of the spindle 36. An annular grinding wheel 42 is fixed to the lower surface of the wheel mount 38 by bolts 40. A plurality of grinding wheels 44 are fixed to the outer peripheral edge of the lower surface of the grinding wheel 42 and arranged in an annular manner at intervals in the circumferential direction.
図６を参照して説明を続けると、分割工程では、まず、ウエーハ２の裏面２ｂを上に向けて、チャックテーブル３２の上面でウエーハ２を吸引保持する。次いで、上方からみて反時計回りに所定の回転速度（たとえば３００ｒｐｍ）でチャックテーブル３２を回転させる。また、上方からみて反時計回りに所定の回転速度（たとえば６０００ｒｐｍ）でスピンドル３６を回転させる。次いで、スピンドル３６を下降させてウエーハ２の裏面２ｂに研削砥石４４を接触させた後、所定の研削送り速度（たとえば１．０μｍ／ｓ）でスピンドル３６を下降させる。これによって、ウエーハ２の裏面２ｂを研削してウエーハ２を所定の厚みに形成することができる。 Continuing the explanation with reference to FIG. 6, in the dividing step, first, the wafer 2 is suction-held on the upper surface of the chuck table 32 with the back surface 2b of the wafer 2 facing upward. Next, the chuck table 32 is rotated counterclockwise when viewed from above at a predetermined rotational speed (for example, 300 rpm). Further, the spindle 36 is rotated counterclockwise when viewed from above at a predetermined rotational speed (for example, 6000 rpm). Next, the spindle 36 is lowered to bring the grinding wheel 44 into contact with the back surface 2b of the wafer 2, and then the spindle 36 is lowered at a predetermined grinding feed rate (for example, 1.0 μm/s). Thereby, the back surface 2b of the wafer 2 can be ground to form the wafer 2 to a predetermined thickness.
ウエーハ２を研削している時には、研削送りによる押圧力がウエーハ２に作用するので、分割予定ライン改質層２８から分割予定ライン６に向かって分割予定ラインクラック２８´がウエーハ２の厚み方向に伸長する。このため、図６（ｂ）および図６（ｃ）に示すとおり、分割予定ラインクラック２８´によってウエーハ２が個々のデバイスチップ４６に分割される。なお、抗折強度を向上させるために分割予定ライン改質層２８を研削によって除去し、分割予定ラインクラック２８´のみを残すのが好ましい。 When the wafer 2 is being ground, a pressing force due to the grinding feed acts on the wafer 2, so that a splitting line crack 28' is formed in the thickness direction of the wafer 2 from the splitting line modified layer 28 toward the splitting line 6. Stretch. Therefore, as shown in FIGS. 6(b) and 6(c), the wafer 2 is divided into individual device chips 46 by the dividing line cracks 28'. In order to improve the bending strength, it is preferable to remove the planned dividing line modified layer 28 by grinding, leaving only the planned dividing line crack 28'.
また、ウエーハ２を研削している時には、分割予定ライン改質層２８の始点２８ａまたは終点２８ｂから無秩序にクラックが伸長するおそれがある。しかしながら、図示の実施形態では、分割予定ライン改質層２８の始点２８ａおよび終点２８ｂが第一のリング状改質層２４と第二のリング状改質層２６との間に位置しており、ウエーハ２を研削している時には第一・第二のリング状改質層２４、２６から第一・第二のリング状クラック２４´、２６´がウエーハ２の厚み方向に伸長するので、始点２８ａおよび終点２８ｂから伸長する無秩序なクラックが第一・第二のリング状改質層２４、２６および第一・第二のリング状クラック２４´、２６´によって遮断され、デバイス４に到達することがない。したがって、図示の実施形態によれば、ウエーハ２の外周余剰領域１０に隣接するデバイス４の損傷を防止することができる。 Furthermore, when the wafer 2 is being ground, cracks may extend randomly from the starting point 28a or ending point 28b of the planned dividing line modified layer 28. However, in the illustrated embodiment, the starting point 28a and the ending point 28b of the scheduled dividing line modified layer 28 are located between the first ring-shaped modified layer 24 and the second ring-shaped modified layer 26, When the wafer 2 is being ground, the first and second ring-shaped cracks 24' and 26' extend from the first and second ring-shaped modified layers 24 and 26 in the thickness direction of the wafer 2, so that the starting point 28a The disordered cracks extending from the end point 28b are blocked by the first and second ring-shaped modified layers 24, 26 and the first and second ring-shaped cracks 24', 26', and cannot reach the device 4. do not have. Therefore, according to the illustrated embodiment, it is possible to prevent damage to the devices 4 adjacent to the outer peripheral surplus region 10 of the wafer 2.
そして、ウエーハ２を個々のデバイスチップ４６に分割した後、外周が分割予定ラインクラック２８´のみによって規定される矩形状のデバイスチップ４６を次工程に搬送し、図６（ｃ）に灰色で示す部分（第一のリング状クラック２４´（弧状部）を外周に含むチップおよび第一のリング状クラック２４´よりも外側の部分）を破棄する。 After dividing the wafer 2 into individual device chips 46, the rectangular device chips 46 whose outer periphery is defined only by the dividing line crack 28' are transported to the next process, and are shown in gray in FIG. 6(c). The portion (the chip including the first ring-shaped crack 24' (arc-shaped portion) on the outer periphery and the portion outside the first ring-shaped crack 24') is discarded.
以上のとおりであり、図示の実施形態のウエーハの加工方法においては、始点２８ａおよび終点２８ｂから伸長する無秩序なクラックが第一・第二のリング状改質層２４、２６および第一・第二のリング状クラック２４´、２６´によって遮断され、デバイス４に到達することがなく、ウエーハ２の外周余剰領域１０に隣接するデバイス４の損傷を防止することができる。 As described above, in the wafer processing method of the illustrated embodiment, disordered cracks extending from the starting point 28a and the ending point 28b form the first and second ring-shaped modified layers 24, 26 and the first and second ring-shaped modified layers. The cracks are blocked by the ring-shaped cracks 24' and 26', and do not reach the devices 4, thereby preventing damage to the devices 4 adjacent to the peripheral surplus region 10 of the wafer 2.
なお、リング状改質層が１個の場合には、始点２８ａおよび終点２８ｂから伸長する無秩序なクラックによってデバイス４が損傷するのを防止するため、始点２８ａおよび終点２８ｂをリング状改質層の円周上に精密に合わせる必要がある。しかしながら、始点２８ａおよび終点２８ｂをリング状改質層の円周上に精密に合わせることは困難であるため、リング状改質層が１個であると、無秩序なクラックによってデバイス４が損傷するおそれがある。この点、図示の実施形態のウエーハの加工方法では、ウエーハ２の径方向に間隔をおいて第一・第二のリング状改質層２４、２６を形成しているので、始点２８ａおよび終点２８ｂを第一のリング状改質層２４と第二のリング状改質層２６との間に容易に位置づけることができ、無秩序なクラックを第一・第二のリング状改質層２４、２６および第一・第二のリング状クラック２４´、２６´によって遮断することができるので、デバイス４の損傷を確実に防止することができる。 In addition, when there is only one ring-shaped modified layer, in order to prevent the device 4 from being damaged by disordered cracks extending from the starting point 28a and the ending point 28b, the starting point 28a and the ending point 28b are connected to the ring-shaped modified layer. It must be precisely aligned on the circumference. However, since it is difficult to precisely align the starting point 28a and the ending point 28b on the circumference of the ring-shaped modified layer, if there is only one ring-shaped modified layer, there is a risk that the device 4 will be damaged by disordered cracks. There is. In this regard, in the wafer processing method of the illustrated embodiment, the first and second ring-shaped modified layers 24 and 26 are formed at intervals in the radial direction of the wafer 2, so the starting point 28a and the ending point 28b can be easily positioned between the first ring-shaped modified layer 24 and the second ring-shaped modified layer 26, and disordered cracks can be easily positioned between the first and second ring-shaped modified layers 24, 26 and Since it can be blocked by the first and second ring-shaped cracks 24' and 26', damage to the device 4 can be reliably prevented.
２：ウエーハ
２ａ：ウエーハの表面
２ｂ：ウエーハの裏面
４：デバイス
６：分割予定ライン
８：デバイス領域
１０：外周余剰領域
１４：保護部材
２４：第一のリング状改質層
２６：第二のリング状改質層
２８：分割予定ライン改質層
２８ａ：分割予定ライン改質層の始点
２８ｂ：分割予定ライン改質層の終点
４６：デバイスチップ
2: Wafer 2a: Front surface of wafer 2b: Back surface of wafer 4: Device 6: Planned division line 8: Device area 10: Surplus outer area 14: Protective member 24: First ring-shaped modified layer 26: Second ring shape modified layer 28: Scheduled division line modified layer 28a: Start point of scheduled division line modified layer 28b: End point of scheduled division line modified layer 46: Device chip
Claims (2)
ウエーハの表面に保護部材を配設する保護部材配設工程と、
ウエーハに対して透過性を有する波長のレーザー光線の集光点をウエーハの裏面から外周余剰領域に対応するウエーハの内部に位置づけてレーザー光線をウエーハに照射し外周余剰領域に沿って第一のリング状改質層と該第一のリング状改質層を囲繞する第二のリング状改質層とを形成するリング状改質層形成工程と、
ウエーハに対して透過性を有する波長のレーザー光線の集光点をウエーハの裏面から分割予定ラインに対応するウエーハの内部に位置づけてレーザー光線をウエーハに照射し分割予定ラインに沿って分割予定ライン改質層を形成する分割予定ライン改質層形成工程と、
ウエーハの裏面を研削して所定の厚みに形成すると共に該分割予定ライン改質層から分割予定ラインに伸長するクラックによってウエーハを個々のデバイスチップに分割する分割工程と、を含み、
該分割予定ライン改質層形成工程において、該分割予定ライン改質層の始点および終点が該第一のリング状改質層と該第二のリング状改質層との間に位置するようにレーザー光線の集光点を位置づけるウエーハの加工方法。 A wafer processing method for dividing a wafer in which a device region in which a plurality of devices are divided by dividing lines and a peripheral surplus region surrounding the device region into individual device chips is formed, the method comprising:
a protective member disposing step of disposing a protective member on the surface of the wafer;
The convergence point of a laser beam with a wavelength that is transparent to the wafer is positioned from the back surface of the wafer to the inside of the wafer corresponding to the outer circumferential excess area, and the laser beam is irradiated onto the wafer to form the first ring-shaped modification along the outer circumferential excess area. a ring-shaped modified layer forming step of forming a quality layer and a second ring-shaped modified layer surrounding the first ring-shaped modified layer;
The convergence point of a laser beam with a wavelength that is transparent to the wafer is positioned inside the wafer from the back surface of the wafer corresponding to the line to be divided, and the laser beam is irradiated onto the wafer to form the line-modified layer along the line to be divided. a dividing line modification layer forming step to form a dividing line;
A dividing step of grinding the back surface of the wafer to a predetermined thickness and dividing the wafer into individual device chips by cracks extending from the planned dividing line modified layer to the scheduled dividing line,
In the dividing line modified layer forming step, the starting point and end point of the dividing line modified layer are located between the first ring-shaped modified layer and the second ring-shaped modified layer. A wafer processing method that positions the focal point of the laser beam.
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| SG10202102605X SG10202102605XA (en) | 2020-03-26 | 2021-03-15 | Wafer processing method |
| CN202110306965.3A CN113451117A (en) | 2020-03-26 | 2021-03-23 | Method for processing wafer |
| TW110110757A TW202137307A (en) | 2020-03-26 | 2021-03-25 | Wafer processing method capable of preventing damage to a device adjacent to an outer peripheral surplus region of the wafer |
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| JP2009135342A (en) | 2007-11-30 | 2009-06-18 | Hamamatsu Photonics Kk | Workpiece cutting method |
| JP2009131942A (en) | 2007-11-30 | 2009-06-18 | Hamamatsu Photonics Kk | Grinding method of machining object |
| JP2013511155A (en) | 2009-11-17 | 2013-03-28 | クリー インコーポレイテッド | Device with crackstop |
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| ES2377521T3 (en) | 2002-03-12 | 2012-03-28 | Hamamatsu Photonics K.K. | Method to divide a substrate |
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| JP2009131942A (en) | 2007-11-30 | 2009-06-18 | Hamamatsu Photonics Kk | Grinding method of machining object |
| JP2013511155A (en) | 2009-11-17 | 2013-03-28 | クリー インコーポレイテッド | Device with crackstop |
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