JP7400169B2 - ワークロードのスタティックマッピングの順不同にパイプライン化された実行を可能にする方法及び装置 - Google Patents

ワークロードのスタティックマッピングの順不同にパイプライン化された実行を可能にする方法及び装置 Download PDF

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JP7400169B2
JP7400169B2 JP2020104328A JP2020104328A JP7400169B2 JP 7400169 B2 JP7400169 B2 JP 7400169B2 JP 2020104328 A JP2020104328 A JP 2020104328A JP 2020104328 A JP2020104328 A JP 2020104328A JP 7400169 B2 JP7400169 B2 JP 7400169B2
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ベハー マイケル
マオル モシェ
ガバイ ロネン
ロスナー ロニ
ウォルター ジギ
アガム オレン
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Intel Corp
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    • G06F9/5083—Techniques for rebalancing the load in a distributed system
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  • Engineering & Computer Science (AREA)
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JP2020104328A 2019-08-15 2020-06-17 ワークロードのスタティックマッピングの順不同にパイプライン化された実行を可能にする方法及び装置 Active JP7400169B2 (ja)

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US16/542,012 US11231963B2 (en) 2019-08-15 2019-08-15 Methods and apparatus to enable out-of-order pipelined execution of static mapping of a workload
US16/542,012 2019-08-15

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JP2021034020A JP2021034020A (ja) 2021-03-01
JP2021034020A5 JP2021034020A5 (enExample) 2022-06-21
JP7400169B2 true JP7400169B2 (ja) 2023-12-19

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US (2) US11231963B2 (enExample)
JP (1) JP7400169B2 (enExample)
KR (1) KR102684511B1 (enExample)
CN (2) CN112395010A (enExample)
DE (1) DE102020119519A1 (enExample)
TW (1) TWI802800B (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10901657B2 (en) * 2018-11-29 2021-01-26 International Business Machines Corporation Dynamic write credit buffer management of non-volatile dual inline memory module
US11231963B2 (en) 2019-08-15 2022-01-25 Intel Corporation Methods and apparatus to enable out-of-order pipelined execution of static mapping of a workload
US11875247B1 (en) * 2020-06-18 2024-01-16 Amazon Technologies, Inc. Input batching with serial dynamic memory access
US11704058B2 (en) * 2020-07-28 2023-07-18 Samsung Electronics Co., Ltd. Systems and methods for resource-based scheduling of commands
CN112003846B (zh) * 2020-08-13 2023-02-03 广州市百果园信息技术有限公司 一种信用阈值的训练、ip地址的检测方法及相关装置
EP4211566B1 (en) * 2020-10-26 2025-01-29 Google LLC Modulating credit allocations in memory subsystems
US11620159B2 (en) 2021-04-23 2023-04-04 Samsung Electronics Co., Ltd. Systems and methods for I/O command scheduling based on multiple resource parameters
US12001701B2 (en) * 2022-01-26 2024-06-04 Western Digital Technologies, Inc. Storage biasing for solid state drive accelerators

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040268083A1 (en) 2003-06-27 2004-12-30 Tatsunori Kanai Information processing system including processors and memory managing method used in the same system
US20120239833A1 (en) 2011-03-14 2012-09-20 Kabushiki Kaisha Toshiba Buffer management device, buffer management method, and storage device
US20160140071A1 (en) 2014-11-13 2016-05-19 Cavium, Inc. Arbitrated Access To Resources Among Multiple Devices
JP2017525047A (ja) 2014-07-30 2017-08-31 リニア アルジェブラ テクノロジーズ リミテッド 低電力コンピュータイメージング
US20190050261A1 (en) 2018-03-29 2019-02-14 Intel Corporation Arbitration across shared memory pools of disaggregated memory devices

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5418953A (en) * 1993-04-12 1995-05-23 Loral/Rohm Mil-Spec Corp. Method for automated deployment of a software program onto a multi-processor architecture
US9395990B2 (en) * 2013-06-28 2016-07-19 Intel Corporation Mode dependent partial width load to wider register processors, methods, and systems
US11153223B2 (en) * 2016-04-07 2021-10-19 International Business Machines Corporation Specifying a disaggregated compute system
US10289752B2 (en) * 2016-12-12 2019-05-14 Intel Corporation Accelerator for gather-update-scatter operations including a content-addressable memory (CAM) and CAM controller
GB2569275B (en) * 2017-10-20 2020-06-03 Graphcore Ltd Time deterministic exchange
GB2569271B (en) * 2017-10-20 2020-05-13 Graphcore Ltd Synchronization with a host processor
US11669372B2 (en) * 2018-12-13 2023-06-06 Intel Corporation Flexible allocation of compute resources
US11231963B2 (en) 2019-08-15 2022-01-25 Intel Corporation Methods and apparatus to enable out-of-order pipelined execution of static mapping of a workload

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040268083A1 (en) 2003-06-27 2004-12-30 Tatsunori Kanai Information processing system including processors and memory managing method used in the same system
JP2005018620A (ja) 2003-06-27 2005-01-20 Toshiba Corp 情報処理システムおよびメモリ管理方法
US20120239833A1 (en) 2011-03-14 2012-09-20 Kabushiki Kaisha Toshiba Buffer management device, buffer management method, and storage device
JP2012190415A (ja) 2011-03-14 2012-10-04 Toshiba Corp バッファ管理装置、バッファ管理方法及び記憶装置
JP2017525047A (ja) 2014-07-30 2017-08-31 リニア アルジェブラ テクノロジーズ リミテッド 低電力コンピュータイメージング
US20160140071A1 (en) 2014-11-13 2016-05-19 Cavium, Inc. Arbitrated Access To Resources Among Multiple Devices
US20190050261A1 (en) 2018-03-29 2019-02-14 Intel Corporation Arbitration across shared memory pools of disaggregated memory devices

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TW202109285A (zh) 2021-03-01
US11847497B2 (en) 2023-12-19
CN114895965B (zh) 2025-09-09
KR20210021263A (ko) 2021-02-25
DE102020119519A1 (de) 2021-02-18
CN114895965A (zh) 2022-08-12
US20220197703A1 (en) 2022-06-23
KR102684511B1 (ko) 2024-07-15
JP2021034020A (ja) 2021-03-01
US11231963B2 (en) 2022-01-25
CN112395010A (zh) 2021-02-23
US20190370073A1 (en) 2019-12-05
TWI802800B (zh) 2023-05-21

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