JP7398194B2 - Semiconductor device and display panel driving method - Google Patents

Description

The present disclosure relates to a technique for driving a display panel.

Examples of display panels include liquid crystal display panels and OLED (organic light emitting diode) display panels. The brightness of an image displayed on a self-emissive display panel, such as an OLED display panel, can be controlled by adjusting the ratio of pixels that are lit at each time to the total number of pixels. Increasing the ratio of lit pixels will increase the brightness of the image, and decreasing the ratio will decrease the brightness of the image.

In one embodiment, the semiconductor device supplies the display panel with an emission control signal that controls the lighting of the pixels so that a plurality of control cycles for lighting the pixels of the display panel are provided during the first vertical synchronization period. When the length of the first vertical synchronization period is changed, a next vertical synchronization period of the first vertical synchronization period is started at a timing according to the length of the control cycle. and a timing generator configured as follows.

In one embodiment, the semiconductor device sends an emission control signal that controls the lighting of the pixels of the display panel so that a plurality of control cycles for lighting the pixels of the display panel are provided in a first vertical synchronization period of the plurality of vertical synchronization periods. a panel interface configured to supply the image data to the display panel; a data interface configured to transmit an image data transmission request to the host during the first vertical synchronization period; and the plurality of vertical synchronization periods. generating a vertical synchronization signal that defines a timing for next asserting the vertical synchronization signal if the data interface does not start receiving image data within a predetermined period after sending the transmission request; and a timing generator configured to delay depending on the length of the control cycle.

In one embodiment, the display panel driving method includes supplying an emission control signal for controlling the lighting of the pixels of the display panel so that a plurality of control cycles for lighting the pixels of the display panel are provided in the first vertical synchronization period; The method includes starting a vertical synchronization period next to the first vertical synchronization period at a timing corresponding to the length of the control cycle when the length of the first vertical synchronization period is changed.

FIG. 1 is a block diagram showing the configuration of a display device in one embodiment. FIG. 2 is a circuit diagram showing the configuration of a pixel in one embodiment. 3 is a timing chart showing the operation of a display device in one embodiment. 3 is a timing chart showing the operation of a display device in one embodiment. 5 is a timing chart showing a comparative example of operation of a display device. FIG. 2 is a block diagram showing the configuration of a vertical synchronization signal generation circuit section and an emission control signal generation circuit section in one embodiment. 7 is a flowchart showing the operation of a vertical synchronization signal generation circuit section in one embodiment. 3 is a timing chart showing the operation of a display device in one embodiment. 3 is a timing chart showing the operation of a display device in one embodiment. 4 illustrates the operation of a display device in one embodiment. 4 illustrates the operation of a display device in one embodiment. 3 is a timing chart showing the operation of a display device in one embodiment. 4 illustrates the operation of a display device in one embodiment. 4 illustrates the operation of a display device in one embodiment.

As shown in FIG. 1A, in one embodiment, a display device 100 includes a display panel 1 and a display driver 2. As the display panel 1, for example, a self-luminous display panel such as an OLED display panel may be used. In one embodiment, the display device 100 is configured to display an image corresponding to image data received from the host 3 on the display panel 1 .

In one embodiment, the display panel 1 includes pixels 4 arranged in rows and columns, scan lines S[-1] to S[m], emission lines EM[1] to EM[m], and data lines D[ 1] to D[n] and a scan driver circuit section 5. In one embodiment, each pixel 4 is configured to emit light with a brightness corresponding to a specified gray level value.

Referring to FIG. 1B, in one embodiment, each pixel 4 has a so-called 7T1C configuration and includes PMOS transistors M1 to M7, a holding capacitor Cst, and a light emitting element 6. When an OLED display panel is used as the display panel 1, in one embodiment, an OLED element is used as the light emitting element 6. Note that although FIG. 1B shows the configuration of the pixel 4 connected to the emission line EM[i] and the data line D[j], in one embodiment, the other pixels 4 are similarly configured.

In one embodiment, when performing a write operation, ie, programming a drive voltage corresponding to a gray level value into the pixel 4, the emission line EM[i] is deasserted and the drive voltage is applied to the data line D[j]. In the supplied state, the scan lines S[i-2], S[i-1], and S[i] are operated in a predetermined sequence to write the drive voltage into the holding capacitor Cst. The holding capacitor Cst holds a holding voltage corresponding to the written drive voltage. In one embodiment, when the emission line EM[i] is deasserted, the PMOS transistors M1 and M6 are turned off and the light emitting device 6 stops emitting light. In one embodiment, after the write operation is completed, when the emission line EM[i] is asserted, the PMOS transistors M1, M6 are turned on and the light emitting element 6 corresponds to the holding voltage held on the holding capacitor Cst. It emits light depending on the brightness. Note that the pixel 4 may adopt various configurations other than the configuration shown in FIG. 1B, such as a 5T2C configuration or a 6T1C configuration.

Returning to FIG. 1A, in one embodiment, the scan driver circuit unit 5 drives the scan lines S[-1] to S[m] and the emission lines EM[1] to EM[m] to perform a write operation. is configured to select the row of pixels 4 on which the process is performed. In one embodiment, the row of pixels 4 is composed of pixels 4 arranged in a row in a direction parallel to the scan lines S[-1] to S[m] and the emission lines EM[1] to EM[m]. . In one embodiment, when performing a write operation on the pixel 4 located in the i-th row, the scan driver circuit unit 5 deasserts the emission line EM[i], and further deasserts the scan lines S[i-2], S [i-1] and S[i] are operated in a predetermined sequence.

In one embodiment, the scan driver circuit unit 5 is further configured to control the light emission from the pixels 4 in the rows in which no write operation is performed in accordance with the emission control signal received from the display driver 2. In one embodiment, the emission control signal is a signal that controls the lighting of the pixel 4. In one embodiment, an emission clock is supplied from the display driver 2 to the scan driver circuit unit 5, and permission and prohibition of lighting of the pixels 4 in each row are controlled in synchronization with the emission clock. In one embodiment, the corresponding emission line EM for a row of pixels 4 in which a write operation is performed is deasserted, inhibiting the pixels 4 in that row from emitting light.

In one embodiment, the display driver 2 is a semiconductor device including a data interface 11, a display memory 12, a data driver circuit section 13, a graphics engine 14, a register circuit section 15, a timing generator 16, and a panel interface 17. Configured as a device.

In one embodiment, data interface 11 communicates with host 3 to exchange various data with host 3 that is used to control display driver 2 . In one embodiment, data interface 11 is configured to receive image data and control data. In one embodiment, the image data includes commands that control the operation of the graphics engine 14 and/or tone data that describes the tone value of each pixel 4 to be written to the display memory 12. In one embodiment, the control data is used to control the operation of the display driver 2. In one embodiment, the data interface 11 is additionally configured to interpret commands included in the image data and control data and forward each command to a desired destination, such as the graphics engine 14 or the register circuit section 15. has been done. In one embodiment, data interface 11 is further configured to send control packets to host 3 under control of timing generator 16 . In one embodiment, the data interface 11 is configured to send tearing effect (TE) packets to the host 3 requesting the transmission of image data under the control of the timing generator 16 .

In one embodiment, display memory 12 stores tone data that specifies the tone value of each pixel 4.

In one embodiment, the data driver circuit unit 13 generates a drive voltage corresponding to a gradation value specified in the gradation data received from the display memory 12, and applies the generated drive voltage to the data lines D[1] to It is configured to write to each pixel 4 via [n].

In one embodiment, graphics engine 14 receives commands included in image data received from host 3 and updates tone data stored in display memory 12 in response to the commands.

In one embodiment, the register circuit section 15 holds various register values used to control the operation of the display driver 2. If the control data sent from the host 3 to the display driver 2 includes a register value, the register value may be held in the register circuit section 15 in one embodiment.

In one embodiment, timing generator 16 provides timing control for display driver 2 . For example, the timing generator 16 generates an internal vertical synchronization signal VSYNC used inside the display driver 2. In one embodiment, the vertical synchronization period in the display driver 2 is defined by an internal vertical synchronization signal VSYNC, and various timing controls in the display driver 2 are performed with reference to the internal vertical synchronization signal VSYNC.

In one embodiment, the panel interface 17 generates and supplies scan control signals to the scan driver circuit 5 to control the scan driver circuit 5 . In one embodiment, the scan control signal includes the above-mentioned emission control signal, and the scan driver circuit unit 5 controls the light emission of the pixel 4 according to the emission control signal. In one embodiment, the scan control signal includes the above-described emission control signal and the emission clock, and the scan driver circuit section 5 controls the light emission of the pixel 4 based on the emission control signal and the emission clock.

In one embodiment, as shown in FIG. 2, the scan driver circuit unit 5 controls the light emission of the pixels 4 in each row in synchronization with the emission clock according to the emission control signal. Note that in FIG. 2, the horizontal direction is the direction of the rows of pixels 4, that is, the direction along the scan lines S[-1] to S[m] and the emission lines EM[1] to EM[m], The vertical direction is the direction along the data lines D[1] to D[n].

In one embodiment, the lighting of the pixels 4 is repeatedly controlled at regular intervals. In one embodiment, the emission control signal is used to control whether to enable or disable lighting of the pixels 4 in each row, and is repeatedly asserted and deasserted at regular intervals. In the following, the cycle for controlling the lighting of the pixel 4 may be referred to as a control cycle. In one embodiment, the control cycle is a cycle in which the emission control signal is asserted and deasserted. In one embodiment, the length of each control cycle is constant and matches the period length of the emissions control signal. In the embodiment shown in FIG. 2, four control cycles are provided in one vertical synchronization period. In one embodiment, the emission control signal is repeatedly asserted and deasserted, resulting in an emission pulse appearing in the emission control signal. In embodiments in which one vertical synchronization period comprises four control cycles, the emission control signal comprises four emission pulses in one vertical synchronization period.

In one embodiment, a non-emissive area 7 in which the pixels 4 do not emit light is inserted at the edge of the display panel 1 based on an emission control signal. In one embodiment, a non-emissive area 7 is inserted at the edge of the display panel 1 while the emission control signal is deasserted. In FIG. 2, the emission control signal is illustrated as a low active signal. In one embodiment, a predetermined number of emission lines EM at the edges of the display panel 1 are deasserted when the emission control signal is deasserted, thereby inserting the non-emissive area 7 at the edge of the display panel 1. . In one embodiment, the non-emissive areas 7 are not inserted and the rows of pixels 4 at the edges of the display panel 1 emit light when the emission control signal is asserted.

In one embodiment, the non-emission area 7 moves sequentially in the direction along the data lines D[1] to D[n] in synchronization with the emission clock. In one embodiment, the non-emission area 7 is moved by shifting the deasserted emission line EM in the direction along the data lines D[1] to D[n] in synchronization with the emission clock.

In one embodiment, the longer the period during which the emission control signal is deasserted, the longer the period during which the non-emissive area 7 is inserted, and the data lines D[1] to D[ of the display panel 1 in the non-emissive area 7 become longer. n].

In one embodiment, the display brightness of the display panel 1, that is, the brightness of the entire image displayed on the display panel 1, is determined by the width of the non-light emitting area 7 in the direction along the data lines D[1] to D[n]. controlled. In one embodiment, as the proportion of the non-light-emitting area 7 in the display area of the display panel 1, that is, the area where the pixels 4 are provided increases, the display brightness of the display panel 1 decreases. In one embodiment, when the width of the non-light emitting area 7 is maximum, the pixels 4 in all rows do not emit light and the display brightness of the display panel 1 is at its lowest brightness. In one embodiment, the display brightness of the display panel 1 increases as the proportion occupied by the non-light-emitting area 7 decreases. In one embodiment, the display brightness of the display panel 1 is the highest when the width of the non-light emitting area 7 is the minimum.

In one embodiment, the display brightness of the display panel 1 is controlled by the percentage of time during each control cycle that the emission control signal is asserted. As the proportion of the period in which the emission control signal is deasserted increases in each control cycle, the width of the non-light-emitting area 7 increases and the display brightness decreases. Conversely, when the ratio of the period in which the emission control signal is asserted increases in each control cycle, the width of the non-light-emitting area 7 becomes narrower, and the display brightness becomes higher.

Referring to FIG. 3, in one embodiment, display device 100 operates as follows. In one embodiment, in the initial state, the host 3 has already completed the generation of image data #1 corresponding to the image to be displayed on the display panel 1 in the vertical synchronization period #1.

In one embodiment, when the display driver 2 is ready to receive image data from the host 3, it sends a request to send image data, for example a TE packet, to the host 3. In one embodiment, when host 3 receives the TE packet, host 3 starts sending image data #1 and data interface 11 of display driver 2 starts receiving image data #1.

In one embodiment, upon detecting the start of receiving image data #1, timing generator 16 asserts internal vertical synchronization signal VSYNC. In one embodiment, vertical synchronization period #1 is initiated in display driver 2 by assertion of internal vertical synchronization signal VSYNC. In one embodiment, the image data sent from the host 3 to the display driver 2 may include a predetermined command, in which case the data interface 11 sends the image data from the host 3 to the display driver 2 based on the predetermined command. The start of reception of image data #1 may be detected. In one embodiment, when detecting the start of reception based on a predetermined command, the predetermined command may be provided at the beginning of the image data.

In one embodiment, vertical synchronization period #1 includes a back porch period, a display period following the back porch period, and a front porch period following the display period. In one embodiment, preparation for writing a drive voltage to each pixel 4 in the display period is performed during the back porch period. In one embodiment, a driving voltage is written to each pixel 4 during the display period. In one embodiment, the scan driver circuit unit 5 sequentially selects the rows of pixels 4 in the display period, and the data driver circuit unit 13 selects the selected rows of pixels 4 via the data lines D[1] to D[n]. A drive voltage corresponding to the specified gradation value for the pixel 4 is written to the pixel 4 in the row. In one embodiment, preparation for operation in the next vertical synchronization period #2 occurs during the front porch period.

In one embodiment, the emission control signal controls the light emission of the pixels 4 of the display panel 1. In one embodiment, assertion and deassertion of emission lines EM[1] to EM[m] are controlled based on the emission control signal and the emission clock. Pixels 4 in rows in which no write operation is performed emit light when the corresponding emission line EM is asserted. When the corresponding emission line EM is deasserted, the pixel 4 stops emitting light. In FIG. 3, the waveform of the emission control signal is illustrated assuming that the emission control signal is a low active signal and becomes a low level when asserted. The pixels 4 in the row where the write operation is performed stop emitting light regardless of the state of the emission control signal.

In one embodiment shown in FIG. 3, multiple control cycles are provided in each vertical synchronization period. In one embodiment, each vertical synchronization period includes four control cycles by default. In one embodiment, "default" refers to the case where the vertical synchronization period is not extended. As discussed below, in one embodiment, the length of the vertical synchronization period may be changed and extended. In one embodiment, the default vertical synchronization period length is an integer multiple of the control cycle, and in the operation of FIG. 3, four times the length.

In one embodiment, in parallel, the host 3 performs image processing to generate image data #2 corresponding to the image to be displayed in the vertical synchronization period #2.

In one embodiment, display driver 2 sends a TE packet to host 3 when it is ready to receive image data #2 from host 3 after a predetermined period has elapsed after the start of vertical synchronization period #1. In one embodiment, host 3 begins transmitting image data #2 upon receiving the TE packet. Display driver 2 will start receiving image data #2.

In one embodiment, after detecting the start of receiving image data #2, timing generator 16 asserts internal vertical synchronization signal VSYNC. In one embodiment, this initiates vertical synchronization period #2 in display driver 2.

In one embodiment, similar to vertical sync period #1, vertical sync period #2 includes a back porch period, a display period, and a front porch period. In one embodiment, during the back porch period, preparations are made for writing a drive voltage to each pixel 4 during the display period. In one embodiment, a driving voltage is written to each pixel 4 during the display period. In one embodiment, the front porch period prepares for operation in the next vertical synchronization period #3. In one embodiment, the emission control signal additionally controls the light emission of the pixels 4 of the display panel 1.

In one embodiment, the host 3, on the other hand, generates image data #3 corresponding to the image to be displayed during the vertical synchronization period #3. In one embodiment, image processing to generate image data #3 takes time in the host 3, and generation of image data #3 is not completed by the time the TE packet is received.

In such an embodiment, host 3 cannot start transmitting image data #3 immediately after receiving the TE packet. In one embodiment, if the display driver 2 does not detect the start of receiving image data #3 before a predetermined period elapses after transmitting the TE packet to the host 3, the display driver 2 detects the front porch of the vertical synchronization period #2. The period is extended to wait for the host 3 to start transmitting image data #3. In one embodiment, such a situation may occur if the host 3 fails to start transmitting image data #3 before a predetermined period of time has elapsed after receiving the TE packet. The extended portion of the front porch period is illustrated in FIG. 3 as "extended FP." In one embodiment, the emission control signal continues to control the light emission of the pixel 4 even during the extended portion of the front porch period. In one embodiment, the extended portion of the front porch period may be provided with one or more control cycles. In one embodiment, the length of vertical synchronization period #2 is modified and extended by extending its front porch period. In such embodiments, the timing at which internal vertical synchronization signal VSYNC is next asserted will be delayed from the default timing.

In one embodiment, after the generation of image data #3 is completed, host 3 starts transmitting image data #3, and display driver 2 starts receiving image data #3. In one embodiment, when timing generator 16 detects the start of receiving image data #3, it asserts internal vertical synchronization signal VSYNC and starts vertical synchronization period #3.

In one embodiment, timing generator 16 is configured to adjust the timing at which vertical synchronization period #3 begins, in other words, the timing at which internal vertical synchronization signal VSYNC is asserted, depending on the length of the control cycle. . In one embodiment, information representing the length of the control cycle, for example, a register value specifying the period of the emission control signal, is stored in the register circuit section 15, and the timing at which vertical synchronization period #3 starts, i.e., the internal vertical The timing to assert the synchronization signal VSYNC may be determined according to the register value.

In one embodiment, the timing generator 16 may synchronize the timing at which the vertical synchronization period #3 starts, ie, the timing at which the internal vertical synchronization signal VSYNC is asserted, with the timing at which the last control cycle is completed. In one embodiment, timing generator 16 may align the timing at which vertical synchronization period #3 begins, ie, the timing at which internal vertical synchronization signal VSYNC is asserted, with the timing at which the last control cycle is completed; , may be matched. In one embodiment, the timing generator 16 determines when the vertical synchronization period #3 starts so that the length of the vertical synchronization period #2 is an integer multiple of the length of the control cycle or an integer multiple of the period of the emission control signal. It may be controlled so that FIG. 3 illustrates an operation in which the length of vertical synchronization period #2 is seven times the period of the emission control signal.

In one embodiment, such operation suppresses disturbances in image brightness control by the emission control signal and suppresses or prevents occurrence of flicker or undesired changes in brightness.

In one embodiment, display driver 2 starts receiving image data #3 from host 3 after the image processing performed in host 3 is completed. In accordance with this, in one embodiment, the timing at which the next vertical synchronization period #3 starts is set to the timing after the image processing performed in the host 3 is completed.

For example, as shown in the area surrounded by the broken line in FIG. 4, if the last control cycle of vertical synchronization period #2 and the timing at which vertical synchronization period #3 starts do not match, The last control cycle of 2 is not completely executed. In the example of FIG. 4, the period during which the emission control signal is deasserted is long, spanning from vertical synchronization period #2 to vertical synchronization period #3. When such an operation is performed, the user observing the display panel 1 may momentarily perceive that the brightness of the image has decreased.

In one embodiment, as shown in FIG. 3, the timing to start vertical synchronization period #3, i.e., the timing at which internal vertical synchronization signal VSYNC is asserted, is adjusted according to the length of the control cycle, and Disturbances are suppressed. In one embodiment, the timing at which vertical synchronization period #3 begins, i.e., the timing at which internal vertical synchronization signal VSYNC is asserted, is synchronized with the timing at which the last control cycle is completed, and the operation shown in FIG. Match. In one embodiment, this may result in the emission control signal being asserted and deasserted for the control cycles included in vertical synchronization period #2, even if vertical synchronization period #2 is extended. The length of the period is kept constant. In one embodiment, this effectively reduces or prevents the occurrence of flicker or undesired changes in brightness.

In one embodiment, the timing generator 16 may include the vertical synchronization signal generation circuit section 21 shown in FIG. 5, and the panel interface 17 may include the emission control signal generation circuit section 22 shown in FIG. . In one embodiment, the vertical synchronization signal generation circuit section 21 and the emission control signal generation circuit section 22 are configured to be able to realize the operation shown in FIG. 3.

In one embodiment, the vertical synchronization signal generation circuit section 21 includes a VSYNC timing control circuit section 23 and a vertical synchronization signal output stage 24 . In one embodiment, VSYNC timing control circuitry 23 determines when the internal vertical synchronization signal VSYNC is asserted. In one embodiment, the vertical synchronization signal output stage 24 is configured to output an internal vertical synchronization signal VSYNC, and asserts the internal vertical synchronization signal VSYNC at a timing determined by the VSYNC timing control circuitry 23.

In one embodiment, the VSYNC timing control circuitry 23 generates an internal vertical synchronization signal in response to a back porch register value 31, a display line register value 32, a front porch register value 33, and a memory write start signal stored in the register circuitry 15. It is configured to control the timing at which VSYNC is asserted. In one embodiment, back porch register value 31 is a register value that specifies the length of the back porch period, and display line register value 32 is a register value that specifies the length of the display period. In one embodiment, front porch register value 33 is a register value that specifies the length of the front porch period. In one embodiment, the memory write start signal is a signal that is asserted when data interface 11 receives a memory write start command from host 3. In one embodiment, the image data sent from the host 3 includes a memory write start command, and the VSYNC timing control circuit unit 23 detects the start of image data reception by the display driver 2 based on the memory write start signal. can do.

In one embodiment, the emission control signal generation circuit section 22 includes a pulse generator 25. In one embodiment, the register circuit section 15 stores emission control signal setting parameters, and the pulse generator 25 generates the emission control signal according to the emission control signal setting parameters. In one embodiment, the emission control signal configuration parameters specify the waveform of the emission control signal, such as the length of time that the emission control signal is asserted and the length of time that the emission control signal is deasserted in each control cycle. The emission control signal setting parameter may directly describe the length of the period in which the emission control signal is asserted and the length of the period in which the emission control signal is deasserted, or may be another parameter that can calculate these. In one embodiment, an internal vertical synchronization signal VSYNC is input to the pulse generator 25, and the operation of the pulse generator 25 is reset when the internal vertical synchronization signal VSYNC is asserted.

In one embodiment, the VSYNC timing control circuitry 23 may operate as shown in FIG. 6 to determine when to assert the internal vertical synchronization signal VSYNC after each vertical synchronization period begins.

In one embodiment, in step S01, the VSYNC timing control circuit unit 23 specifies the length of the default vertical synchronization period by adding a back porch register value 31, a display line register value 32, and a front porch register value 33. Calculate the parameter value SET_VSYNC.

In one embodiment, a memory write start signal is monitored in step S02. In one embodiment, if the memory write start signal is not asserted within a predetermined period after transmitting the TE packet to the host 3 during the front porch period, the front porch period is extended by a predetermined extension amount #1 in step S03. In one embodiment, the operation of extending the front porch period by a predetermined extension amount #1 is performed repeatedly until assertion of the memory write start signal is detected.

In one embodiment, when the memory write start signal is asserted, the emission control signal configuration parameters are referenced in step S04 to determine whether the length of the current vertical synchronization period is appropriately determined. In one embodiment, the length of the control cycle can be obtained from the emission control signal configuration parameter, and the timing of the completion of the current vertical synchronization period, i.e., the start of the next vertical synchronization period, is dependent on the length of the control cycle. It is adjusted accordingly.

In one embodiment, if the length of the current vertical synchronization period is correct, the internal vertical synchronization signal VSYNC is asserted upon completion of the front porch period and the next vertical synchronization period begins. In one embodiment, if the length of the current vertical synchronization period is determined to be an integer multiple of the control cycle as a result of extending the front porch period in step S03, the length of the current vertical synchronization period is determined to be an integer multiple of the control cycle. Internal vertical synchronization signal VSYNC is asserted.

In one embodiment, if the current vertical synchronization period length is not appropriate, the front porch period is further extended by an extension amount #2 in step S05. In one embodiment, extension amount #2 is determined based on emission control signal configuration parameters and depending on the length of the control cycle. In one embodiment, extension amount #2 may be determined such that the length of the current vertical synchronization period is an integer multiple of the length of the control cycle. In one embodiment, the internal vertical synchronization signal VSYNC is asserted upon completion of the extended front porch period.

In one embodiment, the length of the vertical synchronization period is extended to switch frame rates, as shown in FIG. In one embodiment, the length of the vertical synchronization period is increased by timing generator 16 delaying the timing at which the internal vertical synchronization signal VSYNC is asserted. In one embodiment, the frame rate of vertical synchronization period #1 is a first frame rate, and the length of vertical synchronization period #2 and subsequent vertical synchronization periods is extended such that the frame rate is equal to the first frame rate. The frame rate is switched to a second frame rate lower than that of the second frame rate. In one embodiment, the frame rate is switched from the first frame rate to the second frame rate by extending the front porch period of the vertical synchronization period.

In one embodiment, the timing at which vertical synchronization period #3 following vertical synchronization period #2 begins is synchronized with the timing at which the last control cycle of vertical synchronization period #2 is completed, and the operation illustrated in FIG. So they match. In one embodiment, the length of the control cycle is determined according to the frame rate before and after switching, so that the timing when vertical synchronization period #3 starts and the timing when the last control cycle of vertical synchronization period #2 is completed is determined. Synchronization or coincidence is achieved. In one embodiment, such operation reduces disturbances in the image brightness control by the emission control signal, thereby reducing or preventing the occurrence of flicker or undesired changes in brightness.

In one embodiment, the length of the vertical synchronization periods #1 and #2 are both set to an integral multiple of the control cycle, or the length of the control cycle is set to the length of the vertical synchronization periods #1 and #2. Such synchronization or coincidence is achieved by setting the length to be an integral multiple of the control cycle. In one embodiment, the frame rate in vertical synchronization period #1 is 90 Hz, and vertical synchronization period #1 includes four control cycles. In such embodiments, the length of vertical synchronization period #1 is four times the length of the control cycle, and the emission control signal includes four emission pulses. In one embodiment, the frame rate is switched to 60Hz during vertical synchronization period #2. In such an embodiment, the length of vertical synchronization period #2 and subsequent vertical synchronization periods is extended to six times the length of the control cycle. The timing at which the last control cycle of vertical synchronization period #2 is completed coincides with the timing at which vertical synchronization period #3 starts.

In one embodiment, a change in display brightness may occur as the frame rate switches due to an increase in the length of the vertical synchronization period. In one embodiment, the change in display brightness is caused by leakage current in the pixel 4. In one embodiment, the holding voltage of the pixel 4 is gradually reduced after writing the drive voltage. FIG. 7 shows an example of the holding voltage of the pixel 4 in the row in which the drive voltage is written first in each vertical synchronization period. The longer the length of the vertical synchronization period, the greater the drop in the holding voltage of the pixel 4, so if the length of the vertical synchronization period is extended, the display brightness may decrease. In one embodiment, the display brightness during vertical synchronization period #1 is 450 nits, and the display brightness during vertical synchronization period #2, which is longer than vertical synchronization period #1, is 440 nits. In one embodiment, such a change in display brightness may be visible as flicker.

In one embodiment, dimming is performed during frame rate switching, and the length of the vertical synchronization period is extended in stages, as shown in FIG. 8 . In one embodiment, the frame rate of vertical synchronization period #1 is a first frame rate, and the frame rate of vertical synchronization period #3 and subsequent vertical synchronization periods is set to a second frame rate that is lower than the first frame rate. be done. In one embodiment, such frame rate switching is achieved by setting the length of vertical synchronization period #3 and the subsequent vertical synchronization period to be longer than the length of vertical synchronization period #1.

In one embodiment, vertical sync period #2 between vertical sync periods #1 and #3 is used for display brightness dimming, and the length of vertical sync period #2 is greater than the length of vertical sync period #1. The length of the vertical synchronization period #3 is also set to be longer than the length of the vertical synchronization period #3. In such an embodiment, the display brightness in vertical synchronization period #2 is between the display brightness in vertical synchronization periods #1 and #3, and the speed of change in display brightness is slow. In one embodiment, the display brightness during vertical sync period #1 is 450 nits, the display brightness during vertical sync period #3 is 440 nits, and the display brightness during vertical sync period #2 is 445 nits. In one embodiment, flicker is suppressed by slowing down the rate at which the display brightness changes.

In one embodiment, the timing at which vertical synchronization period #3 following vertical synchronization period #2 is started is synchronized with the timing at which the last control cycle of vertical synchronization period #2 is completed, and the timing at which vertical synchronization period #3 following vertical synchronization period #2 is The timing at which the synchronization period starts is synchronized with the timing at which the last control cycle of vertical synchronization period #2 is completed. In the operation shown in FIG. 8, the timing at which vertical synchronization period #3 starts coincides with the timing at which the last control cycle of vertical synchronization period #2 is completed, and the vertical synchronization period following vertical synchronization period #3 starts. The timing coincides with the timing at which the last control cycle of vertical synchronization period #3 is completed. In one embodiment, such operation reduces disturbances in the image brightness control by the emission control signal, thereby reducing or preventing the occurrence of flicker or undesired changes in brightness.

In one embodiment, the lengths of vertical synchronization periods #1 to #3 are all set to integral multiples of the control cycle, or the length of the control cycle is set to the length of vertical synchronization periods #1 to #3. Such synchronization or coincidence is achieved by setting the length to be an integral multiple of the control cycle. In one embodiment, the frame rate in vertical synchronization period #1 is 90 Hz, and the frame rate in vertical synchronization period #3 and subsequent vertical synchronization periods is 60 Hz. In one embodiment, the length of vertical synchronization period #1 is four times the length of the control cycle, the length of vertical synchronization period #3 and subsequent vertical synchronization periods is six times the length of the control cycle, and the length of vertical synchronization period #1 is six times the length of the control cycle; 2 is five times the length of the control cycle. Such an operation can be realized by appropriately determining the length of the control cycle.

In the embodiments shown in FIGS. 9 and 10, multiple vertical synchronization periods are used for dimming when switching frame rates. In one embodiment, as shown in FIG. 9, the frame rate in vertical synchronization periods #1 and #2 is set to 90Hz, and the frame rate in vertical synchronization periods #5 and #6 and subsequent vertical synchronization periods is set to 60Hz. Set. In one embodiment, vertical synchronization periods #3, #4 are used for dimming. In one embodiment, the lengths of vertical synchronization periods #3, #4 are the same, longer than the lengths of vertical synchronization periods #1, #2, and shorter than the lengths of vertical synchronization periods #5, #6. In one embodiment, the length of vertical sync periods #1, #2 is four times the length of the control cycle, and the length of vertical sync periods #5, #6 and subsequent vertical sync periods are six times the length of the control cycle. be. In such an embodiment, the length of vertical synchronization periods #3 and #4 is set to five times the control cycle. In one embodiment, multiple vertical synchronization periods are used for dimming so that the display brightness changes more slowly and flicker is further suppressed.

In one embodiment, as shown in FIG. 10, the length of the vertical synchronization period is increased in steps over multiple vertical synchronization periods used for dimming. In one embodiment, the frame rate during vertical synchronization periods #1 and #2 is set to 90 Hz, and the frame rate during vertical synchronization periods #6 and #7 and subsequent vertical synchronization periods is set to 45 Hz. In one embodiment, the length of vertical sync periods #1, #2 is four times the length of the control cycle, and the length of vertical sync periods #6, #7, and subsequent vertical sync periods are eight times the length of the control cycle. be. In one embodiment, the length of the vertical synchronization period is extended in steps over the vertical synchronization periods #3 to #5 used for dimming. In one embodiment, the lengths of vertical synchronization periods #3, #4, and #5 are set to five times, six times, and seven times the control cycle, respectively. In one embodiment, such operation causes the display brightness to change more slowly, further reducing the occurrence of flicker.

In one embodiment, the length of the vertical synchronization period is changed and shortened to switch frame rates, as shown in FIG. In one embodiment, the length of the vertical synchronization period is shortened by the timing generator 16 accelerating the timing at which the internal vertical synchronization signal VSYNC is asserted. In one embodiment, the frame rate of vertical synchronization period #1 is a first frame rate, and the length of vertical synchronization period #3 and subsequent vertical synchronization periods is shortened to be less than the length of vertical synchronization period #1. Then, the frame rate of vertical synchronization period #3 and the subsequent vertical synchronization period is set to a second frame rate higher than the first frame rate. In one embodiment, the frame rate is switched from the first frame rate to the second frame rate by shortening the front porch period of vertical synchronization period #3 and subsequent vertical synchronization periods. In one embodiment, increasing the frame rate by decreasing the length of the vertical synchronization period is performed after decreasing the frame rate by increasing the length of the vertical synchronization period, as shown in FIGS. 7-10.

In one embodiment, switching the frame rate due to a reduction in the length of the vertical sync period may result in a change in display brightness similar to if the length of the vertical sync period were increased. To slow down the rate of change in display brightness, in one embodiment, dimming is performed at frame rate switches to reduce the length of the vertical synchronization period in steps.

In one embodiment, vertical sync period #2 between vertical sync periods #1 and #3 is used for display brightness dimming, and the length of vertical sync period #2 is greater than the length of vertical sync period #1. The length of the vertical synchronization period #3 is also set to be shorter than the length of the vertical synchronization period #3. In such an embodiment, the display brightness in vertical synchronization period #2 is between the display brightness in vertical synchronization periods #1 and #3, and the speed of change in display brightness is slow. In one embodiment, flicker is suppressed by slowing down the rate of change in display brightness.

In one embodiment, the timing at which vertical synchronization period #3 following vertical synchronization period #2 is started is synchronized with the timing at which the last control cycle of vertical synchronization period #2 is completed, and the timing at which vertical synchronization period #3 following vertical synchronization period #2 is The timing at which the synchronization period starts is synchronized with the timing at which the last control cycle of vertical synchronization period #2 is completed. In the operation shown in FIG. 11, the timing at which vertical synchronization period #3 starts coincides with the timing at which the last control cycle of vertical synchronization period #2 is completed, and the vertical synchronization period following vertical synchronization period #3 starts. The timing coincides with the timing at which the last control cycle of vertical synchronization period #3 is completed. Such an operation suppresses disturbances in image brightness control by the emission control signal, and suppresses or prevents occurrence of flicker or undesired changes in brightness.

In one embodiment, such synchronization or coincidence is achieved by setting the length of each of vertical synchronization periods #1 to #3 to be an integer multiple of the control cycle. In one embodiment, the frame rate in vertical synchronization period #1 is 60 Hz, and the frame rate in vertical synchronization period #3 and subsequent vertical synchronization periods is 90 Hz. In one embodiment, the length of vertical synchronization period #1 is six times the control cycle, the length of vertical synchronization period #3 and subsequent vertical synchronization periods is four times the length of the control cycle, and the length of vertical synchronization period #1 is four times the length of the control cycle; 2 is five times the length of the control cycle.

In the embodiments shown in FIGS. 12 and 13, multiple vertical synchronization periods are used for dimming when switching frame rates. In one embodiment, as shown in FIG. 12, the frame rate in vertical synchronization periods #1 and #2 is set to 60Hz, and the frame rate in vertical synchronization periods #5 and #6 and subsequent vertical synchronization periods is set to 90Hz. Set. In one embodiment, vertical synchronization periods #3, #4 are used for dimming. In one embodiment, the lengths of vertical synchronization periods #3, #4 are the same, longer than the lengths of vertical synchronization periods #1, #2, and shorter than the lengths of vertical synchronization periods #5, #6. In one embodiment, the length of vertical sync periods #1, #2 is four times the length of the control cycle, and the length of vertical sync periods #5, #6 and subsequent vertical sync periods are six times the length of the control cycle. be. In such an embodiment, the length of vertical synchronization periods #3 and #4 is set to five times the control cycle. In one embodiment, multiple vertical synchronization periods are used for dimming so that the display brightness changes more slowly and flicker is further suppressed.

In one embodiment, as shown in FIG. 13, the length of the vertical synchronization period is reduced in steps over multiple vertical synchronization periods used for dimming. In one embodiment, the frame rate during vertical synchronization periods #1 and #2 is set to 45 Hz, and the frame rate during vertical synchronization periods #6 and #7 and subsequent vertical synchronization periods is set to 90 Hz. In one embodiment, the length of vertical sync periods #1, #2 is eight times the length of the control cycle, and the length of vertical sync periods #6, #7, and subsequent vertical sync periods are four times the length of the control cycle. be. In one embodiment, the length of the vertical synchronization period is extended in steps over the vertical synchronization periods #3 to #5 used for dimming. In one embodiment, the lengths of vertical synchronization periods #3, #4, and #5 are set to seven times, six times, and five times the control cycle, respectively. In one embodiment, such operation causes the display brightness to change more slowly, further reducing the occurrence of flicker.

Although various embodiments of the present disclosure have been specifically described above, those skilled in the art will understand that the techniques described in this disclosure can be practiced with various modifications.

100: Display device 1: Display panel 2: Display driver 3: Host 4: Pixel 5: Scan driver circuit section 6: Light emitting element 7: Non-light emitting area 11: Data interface 12: Display memory 13: Data driver circuit section 14: Graphic Engine 15: Register circuit section 16: Timing generator 17: Panel interface 21: Vertical synchronization signal generation circuit section 22: Emission control signal generation circuit section 23: VSYNC timing control circuit section 24: Vertical synchronization signal output stage 25: Pulse generator 31: Back porch register value 32: Display line register value 33: Front porch register value

Claims (11)

A panel configured to supply an emission control signal for controlling lighting of the pixels of the self-luminous display panel to the self-luminous display panel so that a plurality of control cycles of lighting of the pixels of the self-luminous display panel are provided in each vertical synchronization period. interface and
a timing generator configured to start each vertical synchronization period at a timing such that the length of each vertical synchronization period is an integer multiple of the length of the control cycle;
Controlling lighting of the pixel,
inserting a non-emissive area whose width is controlled by the emission control signal at an edge of the self-emissive display panel in each of the control cycles;
moving the non-luminous area in a predetermined direction in the self-luminous display panel;
including;
When switching the frame rate such that the frame rate in the first vertical synchronization period is the first frame rate, and the frame rate in the second vertical synchronization period after the first vertical synchronization period is the second frame rate, The length of a third vertical synchronization period between the first vertical synchronization period and the second vertical synchronization period is between the length of the first vertical synchronization period and the length of the second vertical synchronization period,
A semiconductor device, wherein the difference between the length of the third vertical synchronization period and the length of the first vertical synchronization period is the length of one control cycle. The length of the fourth vertical synchronization period, which is between the first vertical synchronization period and the second vertical synchronization period and is the next vertical synchronization period after the third vertical synchronization period, is longer than the third vertical synchronization period. The semiconductor device according to claim 1, wherein the length is the same as that of the semiconductor device. the second frame rate is lower than the first frame rate;
The semiconductor device according to claim 1, wherein the length of the third vertical synchronization period is shorter than the length of the second vertical synchronization period and longer than the length of the first vertical synchronization period by the length of one control cycle. The fourth vertical synchronization period is between the first vertical synchronization period and the second vertical synchronization period, and the length of the fourth vertical synchronization period following the third vertical synchronization period is longer than the length of the third vertical synchronization period, and The semiconductor device according to claim 1, wherein the semiconductor device is shorter than the length of the second vertical synchronization period. The semiconductor device according to claim 4, wherein the length of the fourth vertical synchronization period is longer than the length of the third vertical synchronization period by the length of one control cycle. the second frame rate is higher than the first frame rate;
The semiconductor device according to claim 1, wherein the length of the third vertical synchronization period is longer than the length of the second vertical synchronization period and shorter than the length of the first vertical synchronization period by the length of one control cycle. The semiconductor device according to any one of claims 1 to 6, further comprising a driver circuit section that drives the pixels of the self-luminous display panel according to image data. supplying an emission control signal for controlling lighting of the pixels to the self-luminous display panel so that a plurality of control cycles for lighting the pixels of the self-luminous display panel are provided in each vertical synchronization period;
Starting each vertical synchronization period at a timing such that the length of each vertical synchronization period is an integral multiple of the length of the control cycle;
The frame rate is switched such that the frame rate of the first vertical synchronization period is a first frame rate, and the frame rate of a second vertical synchronization period after the first vertical synchronization period is a second frame rate. including;
Controlling lighting of the pixel,
inserting a non-emissive area whose width is controlled by the emission control signal at an edge of the self-emissive display panel in each of the control cycles;
moving the non-luminous area in a predetermined direction in the self-luminous display panel;
including;
The length of a third vertical synchronization period between the first vertical synchronization period and the second vertical synchronization period is between the length of the first vertical synchronization period and the length of the second vertical synchronization period,
A display panel driving method, wherein the difference between the length of the third vertical synchronization period and the length of the first vertical synchronization period is the length of one control cycle. The length of a fourth vertical synchronization period that is between the first vertical synchronization period and the second vertical synchronization period and that follows the third vertical synchronization period is the same as the length of the third vertical synchronization period. The display panel driving method according to claim 8. the second frame rate is lower than the first frame rate;
The display panel according to claim 8, wherein the length of the third vertical synchronization period is shorter than the length of the second vertical synchronization period and longer than the length of the first vertical synchronization period by the length of one control cycle. Driving method. the second frame rate is higher than the first frame rate;
The display panel drive according to claim 8, wherein the length of the third vertical synchronization period is longer than the length of the second vertical synchronization period and shorter than the length of the first vertical synchronization period by the length of one control cycle. Method.

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