JP7394533B2 - electronic equipment - Google Patents

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JP7394533B2
JP7394533B2 JP2019056742A JP2019056742A JP7394533B2 JP 7394533 B2 JP7394533 B2 JP 7394533B2 JP 2019056742 A JP2019056742 A JP 2019056742A JP 2019056742 A JP2019056742 A JP 2019056742A JP 7394533 B2 JP7394533 B2 JP 7394533B2
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electronic device
common electrode
insulating layer
light emitting
layer
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JP2019174807A (en
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宏浜 柯
建志 陳
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Innolux Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528Geometry or layout of the interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/08Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Led Device Packages (AREA)
  • Liquid Crystal (AREA)

Description

本発明は、電子装置に関し、更に詳しくは、共通電極設計の電子装置に関する。 TECHNICAL FIELD The present invention relates to electronic devices, and more particularly to electronic devices with a common electrode design.

表示装置関連技術は日々進歩を続け、表示装置の多くは能動型に向けて発展している。発光ダイオードを発光素子とし、液晶表示装置のバックライトモジュールに応用される以外、直接的に表示装置として公共情報表示器(Public Information Display、PID)、照明、装飾等にも応用されている。 Display device-related technology continues to advance day by day, and many display devices are evolving toward active types. Light emitting diodes are used as light emitting elements, and in addition to being applied to backlight modules of liquid crystal display devices, they are also directly applied as display devices to public information displays (PID), lighting, decoration, etc.

しかしながら、前述した従来の技術では、すなわち、従来の接合型電子装置の多くは受動型電子装置を使用しており、受動型電子装置は大量の集積回路(IC)素子が必要であるほか、コストが高すぎる、消費電力が多い等の欠点が存在する。能動型電子装置に変更して接合するには、能動型電子装置中の発光ダイオードの接合時に発生する熱や応力により回路が圧潰や破壊されやすく、実現が困難であった。 However, in the conventional technology mentioned above, many of the conventional junction type electronic devices use passive electronic devices, and passive electronic devices require a large number of integrated circuit (IC) devices and are expensive. It has disadvantages such as being too expensive and consuming a lot of power. It has been difficult to convert the active electronic device into a bonding device because the circuit is easily crushed or destroyed by the heat and stress generated during bonding of the light emitting diodes in the active electronic device.

そこで、本発明者は、上記の欠点が改善可能と考え、鋭意検討を重ねた結果、発光ダイオードの接合時に下方の回路及び電子素子の圧潰や破壊を回避することを見出した。 Therefore, the inventors of the present invention believed that the above-mentioned drawbacks could be improved, and as a result of intensive studies, they discovered that it is possible to avoid crushing and destruction of the circuits and electronic elements below when bonding light emitting diodes.

本発明は、こうした状況に鑑みてなされたものであり、その目的は、電子装置を提供することにある。
すなわち、共通電極の設計と合わせて前記共通電極が各発光素子のパッドに電気的に接続されることにより、発光素子の接合時の圧力や熱が平均的に分散され、回路の圧潰や破壊を回避させ、プロセスの歩留まり及び信頼性を高めることができる電子装置を提供することである。
The present invention has been made in view of these circumstances, and its purpose is to provide an electronic device.
In other words, by designing the common electrode and electrically connecting the common electrode to the pads of each light emitting element, the pressure and heat when bonding the light emitting elements is evenly distributed, preventing crushing or destruction of the circuit. An object of the present invention is to provide an electronic device that can avoid the above problems and improve the yield and reliability of the process.

上記課題を解決するために、本発明のある態様の電子装置は、基板と、前記基板に設置される複数の能動素子と、これら前記能動素子に設置されると共に複数の開口部を含む共通電極と、前記共通電極に設置され、同じ側に位置される第一パッド及び第二パッドを各々具備する複数の発光素子と、を備え、前記第一パッドはこれら前記開口部の1つに対応するように設置されると共にこれら前記能動素子の1つに電気的に接続され、且つ前記第二パッドは前記共通電極に電気的に接続される。 In order to solve the above problems, an electronic device according to an aspect of the present invention includes a substrate, a plurality of active elements installed on the substrate, and a common electrode installed on the active elements and including a plurality of openings. and a plurality of light emitting elements each having a first pad and a second pad installed on the common electrode and located on the same side, the first pad corresponding to one of the openings. and electrically connected to one of the active elements, and the second pad is electrically connected to the common electrode.

図1(A)は、本発明の一実施形態に係る部分の電子装置を示す断面図であり、図1(B)は、図1(A)の点線に沿う概略図である。FIG. 1(A) is a cross-sectional view showing a portion of an electronic device according to an embodiment of the present invention, and FIG. 1(B) is a schematic diagram taken along the dotted line in FIG. 1(A). 図2は、本発明の一実施形態に係る部分の電子装置を示す断面図である。FIG. 2 is a cross-sectional view showing a portion of an electronic device according to an embodiment of the present invention. 図3(A)は、本発明の他の実施形態に係る部分の電子装置を示す概略図であり、図3(B)は、本発明の他の実施形態に係る部分の電子装置を示す概略図である。FIG. 3(A) is a schematic diagram showing a portion of an electronic device according to another embodiment of the present invention, and FIG. 3(B) is a schematic diagram showing a portion of an electronic device according to another embodiment of the present invention. It is a diagram. 図4(A)は、本発明の他の実施形態に係る部分の電子装置を示す概略図であり、図4(B)は、本発明の他の実施形態に係る部分の電子装置を示す概略図である。FIG. 4(A) is a schematic diagram showing a portion of an electronic device according to another embodiment of the present invention, and FIG. 4(B) is a schematic diagram showing a portion of an electronic device according to another embodiment of the present invention. It is a diagram. 図5は、本発明の他の実施形態に係る部分の電子装置を示す断面図である。FIG. 5 is a cross-sectional view showing a portion of an electronic device according to another embodiment of the present invention. 図6は、本発明の他の実施形態に係る部分の電子装置を示す概略図である。FIG. 6 is a schematic diagram illustrating a partial electronic device according to another embodiment of the present invention. 図7(A)は、本発明の一実施形態に係る電子装置を示す俯瞰図であり、図7(B)は、本発明の一実施形態に係る電子装置を示す俯瞰図であり、図7(C)は、本発明の一実施形態に係る電子装置を示す俯瞰図であり、図7(D)は、本発明の一実施形態に係る電子装置を示す俯瞰図である。FIG. 7(A) is a bird's-eye view of an electronic device according to an embodiment of the present invention, and FIG. 7(B) is a bird's-eye view of an electronic device according to an embodiment of the present invention. 7(C) is a bird's-eye view of an electronic device according to an embodiment of the present invention, and FIG. 7(D) is a bird's-eye view of an electronic device according to an embodiment of the present invention. 図8は、本発明の他の実施形態に係る部分の電子装置を示す断面図である。FIG. 8 is a cross-sectional view showing a portion of an electronic device according to another embodiment of the present invention.

以下、本発明の実施の形態について、図面を参照して詳細に説明する。
なお、本発明は以下の例に限定されるものではなく、本発明の要旨を逸脱しない範囲で、任意に変更可能であることは言うまでもない。
また、明細書及び特許請求の範囲において使用される”第一”、”第二”、”第三”等の順序数は、請求する部材を修飾する用語にすぎず、これは前記請求部材のいかなる前の順序数を表すものではなく、特定の請求部材と他の請求部材の順序を表すものでもなく、製造方法上の順序を表すものでもない。これら前記順序数は命名されたある請求部材と同じ名前の別を請求部材とを明確に区別するために使用されるにすぎない。
さらに、本明細書及び特許請求の範囲において述べる”の上”、”上”または”上方”という位置の用語は、2つの部材が直接的に接触または非直接的に接触していることを指す用語である。
Embodiments of the present invention will be described in detail below with reference to the drawings.
It goes without saying that the present invention is not limited to the following examples, and can be modified as desired without departing from the gist of the present invention.
Further, ordinal numbers such as "first", "second", "third", etc. used in the specification and claims are merely terms modifying the claimed member, and these are terms used to modify the claimed member. It does not represent any prior ordinal number, it does not represent the order of a particular claimed member versus another claimed member, or it does not represent a manufacturing method order. These ordinal numbers are only used to clearly distinguish one named claim member from another claim member with the same name.
Additionally, the terms "on", "above", or "above" as used herein and in the claims refer to two members in direct or indirect contact. It is a term.

図1(A)は、本発明の一実施形態に係る部分の電子装置を示す断面図であり、図1(B)は、図1(A)に示される点線に沿ってなる概略図である。
図1に示されるように、本発明の電子装置は、基板1と、能動層2と、絶縁層3と、導電ユニット4と、共通電極5と、導電性バンプ7と、複数の発光素子6と、を備える。
前記共通電極5は、複数の開口部53を有し、各発光素子6は、第一パッド61及び第二パッド62を含む。
前記第一パッド61は、これら前記開口部53のうちの1つの中にある前記導電性バンプ7を貫通させ、且つ前記絶縁層3の前記導電ユニット4を貫通させ、前記能動層2に電気的に接続される。
また、前記第二パッド62は前記共通電極5に電気的に接続される。
FIG. 1(A) is a cross-sectional view showing a portion of an electronic device according to an embodiment of the present invention, and FIG. 1(B) is a schematic diagram taken along the dotted line shown in FIG. 1(A). .
As shown in FIG. 1, the electronic device of the present invention includes a substrate 1, an active layer 2, an insulating layer 3, a conductive unit 4, a common electrode 5, a conductive bump 7, and a plurality of light emitting elements 6. and.
The common electrode 5 has a plurality of openings 53, and each light emitting element 6 includes a first pad 61 and a second pad 62.
The first pad 61 passes through the conductive bump 7 in one of the openings 53 and through the conductive unit 4 of the insulating layer 3 to provide an electrical connection to the active layer 2. connected to.
Further, the second pad 62 is electrically connected to the common electrode 5.

発光素子の接合時に発生する熱や応力により回路が容易に圧潰されたり、破壊されたりするため、本発明では共通電極の設計により発光素子の接合時の圧力や熱を平均的に分散させ、下方の回路の圧潰や破壊を回避させ、プロセスの歩留まり及び信頼性を高める。 Since the circuit is easily crushed or destroyed by the heat and stress generated when the light emitting elements are bonded, the present invention uses a common electrode design to evenly disperse the pressure and heat when the light emitting elements are bonded, and This avoids crushing and destruction of circuits and increases process yield and reliability.

具体的には、図2は、本発明の一実施形態に係る部分の電子装置を示す断面図である。
まず、基板1が提供され、次に、前記基板1に複数の能動素子TFTを備える能動層2が形成される。
これら前記能動素子TFTは、半導体層21と、前記半導体層21に設置されるゲート絶縁層22と、前記ゲート絶縁層22に設置されるゲート23と、前記ゲート23に設置される第三絶縁層24と、前記第三絶縁層24に設置される第一電極25及び第二電極26と、を含む。
これら前記能動素子TFTは、本発明の実施形態においては薄膜トランジスタであり、第一電極25及び第二電極26はそれぞれドレイン極またはソース極である。
Specifically, FIG. 2 is a cross-sectional view showing a portion of an electronic device according to an embodiment of the present invention.
First, a substrate 1 is provided, and then an active layer 2 comprising a plurality of active device TFTs is formed on said substrate 1.
These active element TFTs include a semiconductor layer 21, a gate insulating layer 22 provided on the semiconductor layer 21, a gate 23 provided on the gate insulating layer 22, and a third insulating layer provided on the gate 23. 24, and a first electrode 25 and a second electrode 26 disposed on the third insulating layer 24.
These active element TFTs are thin film transistors in the embodiment of the present invention, and the first electrode 25 and the second electrode 26 are each a drain pole or a source pole.

次いで、前記能動層2に第一絶縁層31が形成され、その後に導電ユニット4が形成される。
前記第一絶縁層は、スルーホール311を備え、前記導電ユニット4は前記スルーホール311中に設置されると共に前記第一電極25に電気的に接続される。
Next, a first insulating layer 31 is formed on the active layer 2, and then a conductive unit 4 is formed.
The first insulating layer includes a through hole 311 , and the conductive unit 4 is installed in the through hole 311 and electrically connected to the first electrode 25 .

前記導電ユニット4には、第四絶縁層32が形成される。
リソグラフィプロセスにより、前記第四絶縁層32に第一パターン化金属層(51、71を含む)が形成される。
次いで、前記第一パターン化金属層(51、71を含む)に第五絶縁層33が形成され、且つ前記第五絶縁層33は、前記第一パターン化金属層(51、71を含む)に対応する第二開口部331を備える。
スパッタリングプロセスにより、前記第一パターン化金属層(51、71を含む)箇所に第二パターン化金属層(52、72を含む)が堆積し、これにより本実施形態の表示パネルが形成される。
最後に、表面実装技術(surface mount technique、SMT)により発光素子6が表示パネルに接合され、本実施形態の電子装置が形成される。
ちなみに、前述の各層は実施形態の例示にすぎず、本発明をこれに制限するものではない。
A fourth insulating layer 32 is formed on the conductive unit 4 .
A first patterned metal layer (including 51 and 71) is formed on the fourth insulating layer 32 by a lithography process.
Then, a fifth insulating layer 33 is formed on the first patterned metal layer (including 51, 71), and the fifth insulating layer 33 is formed on the first patterned metal layer (including 51, 71). A corresponding second opening 331 is provided.
A second patterned metal layer (including 52 and 72) is deposited at the first patterned metal layer (including 51 and 71) by a sputtering process, thereby forming the display panel of this embodiment.
Finally, the light emitting element 6 is bonded to the display panel by surface mount technique (SMT) to form the electronic device of this embodiment.
Incidentally, each of the above-mentioned layers is merely an example of the embodiment, and the present invention is not limited thereto.

ここで、前記基板1は、石英基板、ガラス基板、ウェハー、サファイア基板、または他の硬質基板である。
前記基板1は、フレキシブル基板または薄膜であり、その材料としてポリカーボネート(PC)、ポリイミド(PI)、ポリプロピレン(PP)、ポリエチレンテレフタレート(PET)、或いは他のプラスチック材料を含む。
前記ゲート23は、単層または多層構造であり、且つ材料として銅(Cu)、チタン(Ti)、アルミニウム(Al)等の金属が使用され、金属合金または導電材料で製造されるが、本発明はこれに限られない。
前記ゲート絶縁層22、前記第一絶縁層31、前記第三絶縁層24、前記第四絶縁層32、及び前記第五絶縁層33の材料として、窒化ケイ素、酸化ケイ素、酸窒化ケイ素、酸化アルミニウム、ポリマー、フォトレジスト、またはそれらの混合物を含み、且つ互いに同じまたは異なる材料で構成されるが、但し、本発明はこの限りではない。
前記第一電極25、第二電極26、前記導電ユニット4の材料として銅(Cu)、チタン(Ti)、アルミニウム(Al)、または導電材料等の金属材料が使用されるが、本発明はこれに限定されない。
前記第一パターン化金属層51、71及び前記第二パターン化金属層52、72は、単層または多層構造であり、且つその材料として銅(Cu)、ニッケル(Ni)、金(Au) 、銀(Ag)、金属合金、または導電材料等の金属材料が使用されて製造されるが、本発明はこれに制限されない。
ここでは、前記発光素子6は発光ダイオードであるが、本発明はこの限りではない。
Here, the substrate 1 is a quartz substrate, a glass substrate, a wafer, a sapphire substrate, or another hard substrate.
The substrate 1 is a flexible substrate or a thin film, and its material includes polycarbonate (PC), polyimide (PI), polypropylene (PP), polyethylene terephthalate (PET), or other plastic materials.
The gate 23 has a single-layer or multi-layer structure, and is made of a metal such as copper (Cu), titanium (Ti), or aluminum (Al), and is manufactured from a metal alloy or a conductive material. is not limited to this.
Materials for the gate insulating layer 22, the first insulating layer 31, the third insulating layer 24, the fourth insulating layer 32, and the fifth insulating layer 33 include silicon nitride, silicon oxide, silicon oxynitride, and aluminum oxide. , a polymer, a photoresist, or a mixture thereof, and may be composed of the same or different materials, but the present invention is not limited thereto.
Copper (Cu), titanium (Ti), aluminum (Al), or a metal material such as a conductive material is used as the material for the first electrode 25, the second electrode 26, and the conductive unit 4. but not limited to.
The first patterned metal layers 51, 71 and the second patterned metal layers 52, 72 have a single layer or multilayer structure, and are made of copper (Cu), nickel (Ni), gold (Au), Metal materials such as silver (Ag), metal alloys, or conductive materials may be used in the fabrication, but the invention is not limited thereto.
Here, the light emitting element 6 is a light emitting diode, but the present invention is not limited to this.

前述のプロセスを経て完成した本実施形態の電子装置は、基板1と、前記基板1に設置される複数の能動素子TFTと、これら前記能動素子TFTに設置されると共に複数の開口部53を含む共通電極5と、前記共通電極5に設置される複数の発光素子6と、を備える。
各発光素子6は、同じ側に位置される第一パッド61及び第二パッド62を含む。
前記第一パッド61は、これら前記開口部53のうちの1つに対応するように設置され、且つこれら前記能動素子TFTのうちの1つに電気的に接続され、前記第二パッド62は前記共通電極5に電気的に接続される。
The electronic device of this embodiment completed through the above-described process includes a substrate 1, a plurality of active element TFTs installed on the substrate 1, and a plurality of openings 53 installed in the active element TFTs. It includes a common electrode 5 and a plurality of light emitting elements 6 installed on the common electrode 5.
Each light emitting device 6 includes a first pad 61 and a second pad 62 located on the same side.
The first pad 61 is installed to correspond to one of the openings 53 and is electrically connected to one of the active element TFTs, and the second pad 62 is installed to correspond to one of the openings 53 and electrically connected to one of the active element TFTs. It is electrically connected to the common electrode 5.

前記共通電極5の設計により、前記発光素子6の接合時に、前記共通電極5によって接合時の圧力及び熱が平均的に分散されることにより、下方の回路が損壊を免れる。
また、共通電極5により光線が遮蔽されるため、放熱面積が増加し、これにより光線による漏電が減少し、或いは高熱による漏電が減少する。
Due to the design of the common electrode 5, when the light emitting elements 6 are bonded, pressure and heat at the time of bonding are uniformly dispersed by the common electrode 5, thereby avoiding damage to the circuit below.
Furthermore, since the common electrode 5 blocks the light rays, the heat dissipation area increases, thereby reducing the leakage caused by the light rays or the leakage caused by high heat.

本実施形態では、前記共通電極5は、第一共通電極層51(第一パターン化金属層と称する場合もある。)及び第二共通電極層52(第二パターン化金属層と称する場合もある。)を備えている。
そして、前記共通電極5の厚さT1は、0.02μm以上100μm以下である。
また、他の実施可能な厚さの範囲として、0.2μm以上10μm以下でもよく、また他の実施可能な厚さの範囲は、2μm以上5μm以下でもよいが、本発明はこれに限定されない。
In this embodiment, the common electrode 5 includes a first common electrode layer 51 (sometimes referred to as a first patterned metal layer) and a second common electrode layer 52 (sometimes referred to as a second patterned metal layer). ).
The thickness T1 of the common electrode 5 is 0.02 μm or more and 100 μm or less.
Further, another possible thickness range may be 0.2 μm or more and 10 μm or less, and another possible thickness range may be 2 μm or more and 5 μm or less, but the present invention is not limited thereto.

本実施形態では、前記電子装置は、これら前記開口部53のうちの1つの中に設置される導電性バンプ7を更に備える。
前記導電性バンプ7は、これら前記開口部53のうちの1つを貫通させ、且つ前記第一パッド61は前記導電性バンプ7を介してこれら前記能動素子TFTのうちの1つに電気的に接続される。
ここで、前記導電性バンプ7は、第一金属層71(第一パターン化金属層と称する場合もある。)及び第二金属層72(第二パターン化金属層と称する場合もある。)を含んでいる。
そして、前記導電性バンプ7の厚さT2は、0.02μm以上100μm以下であり、他の実施可能な厚さの範囲としては、0.2μm以上10μm以下でもよく、また他の実施可能な厚さの範囲としては、2μm 以上5μm以下でもよいが、本発明はこの限りではない。
図2に示されるように、前記導電性バンプ7と前記共通電極5との間は、距離D1で隔てられ、且つ前記距離D1は、2μm以上100μm以下であり、例えば、2μm以上10μm以下であるが、本発明はこれに制限されない。
本実施形態では、前記第一金属層71及び前記第二金属層72はカソード(Cathode)またはアノード(Anode)である。
In this embodiment, the electronic device further comprises a conductive bump 7 placed in one of the openings 53.
The conductive bump 7 passes through one of the openings 53, and the first pad 61 is electrically connected to one of the active element TFTs through the conductive bump 7. Connected.
Here, the conductive bump 7 includes a first metal layer 71 (sometimes referred to as a first patterned metal layer) and a second metal layer 72 (sometimes referred to as a second patterned metal layer). Contains.
The thickness T2 of the conductive bump 7 is 0.02 μm or more and 100 μm or less, and other possible thickness ranges include 0.2 μm or more and 10 μm or less, and other possible thicknesses. The range of the thickness may be 2 μm or more and 5 μm or less, but the present invention is not limited to this.
As shown in FIG. 2, the conductive bump 7 and the common electrode 5 are separated by a distance D1, and the distance D1 is 2 μm or more and 100 μm or less, for example, 2 μm or more and 10 μm or less. However, the present invention is not limited thereto.
In this embodiment, the first metal layer 71 and the second metal layer 72 are a cathode or an anode.

本実施形態では、前記電子装置は、これら前記能動素子TFTと前記共通電極5との間に設置される第一絶縁層31を更に備え、前記第一絶縁層31は、スルーホール311を含む。
前記電子装置は、前記スルーホール311中に設置される導電ユニット4を更に備え、前記導電性バンプ7は、前記導電ユニット4を介してこれら前記能動素子TFTのうちの1つに電気的に接続される。
本実施形態では、前記第一絶縁層31は、多層構造を選択的に有してもよく、例えば、前記第一絶縁層31がパッシベーション層312及び前記パッシベーション層312に設置される平面層313を具備してもよく、本発明はこれに限定されない。
前記パッシベーション層312及び前記平面層313の材料として、窒化ケイ素、酸化ケイ素、酸窒化ケイ素、酸化アルミニウム、ポリマー、フォトレジスト、或いはそれらの混合物を含むが、本発明はこれらに限られない。
In this embodiment, the electronic device further includes a first insulating layer 31 installed between the active element TFT and the common electrode 5, and the first insulating layer 31 includes a through hole 311.
The electronic device further comprises a conductive unit 4 installed in the through hole 311, and the conductive bump 7 is electrically connected to one of the active element TFTs via the conductive unit 4. be done.
In this embodiment, the first insulating layer 31 may selectively have a multilayer structure, for example, the first insulating layer 31 may include a passivation layer 312 and a planar layer 313 disposed on the passivation layer 312. However, the present invention is not limited thereto.
The materials of the passivation layer 312 and the planar layer 313 include, but are not limited to, silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, polymer, photoresist, or a mixture thereof.

また、一つの実施形態では、図1(A)に示されるように、互いに対応し合う2面の第一面101及び第二面102と、前記第一面101及び前記第二面102に連接される側面103と、を含む前記電子装置が基板載置部10を更に備える。
前記基板1は、前記第一面101、前記第二面102、及び前記側面103にそれぞれ設置される少なくとも3つの部分で構成される。
ここでは、前記基板載置部10は石英基板、ガラス基板、ウェハー、サファイア基板、硬軟混合板、または他の硬質基板である。
前記基板載置部10は、フレキシブル基板または薄膜であり、その材料としてポリカーボネート(PC)、ポリイミド(PI)、ポリプロピレン(PP)、ポリエチレンテレフタレート(PET)、或いは他のプラスチック材料を含むが、本発明はこれらに限定されない。
Further, in one embodiment, as shown in FIG. The electronic device further includes a substrate platform 10 .
The substrate 1 includes at least three parts installed on the first surface 101, the second surface 102, and the side surface 103, respectively.
Here, the substrate mounting part 10 is a quartz substrate, a glass substrate, a wafer, a sapphire substrate, a hard/soft mixed plate, or another hard substrate.
The substrate mounting section 10 is a flexible substrate or a thin film, and its material includes polycarbonate (PC), polyimide (PI), polypropylene (PP), polyethylene terephthalate (PET), or other plastic materials. is not limited to these.

また、一つの実施形態においては、図1(A)に示されるように、前記電子装置は、前記第二面102に対応するように設置されると共に前記能動層2に接合される駆動ユニット11を更に備える。
ここで、前記「接合」とは、2つの部材間が電気的に接続される、或いは2つの部材間が他の部材を介して電気的に接続されることを指す。
また、ここでは、前記駆動ユニット11は、集積回路であるが、本発明はこれに限られない。
Moreover, in one embodiment, as shown in FIG. It further includes:
Here, the term "joining" refers to electrically connecting two members, or electrically connecting two members via another member.
Moreover, although the drive unit 11 is an integrated circuit here, the present invention is not limited to this.

本実施形態では、これら前記開口部53の形状に特別制限はなく、前記導電性バンプ7がこれら前記開口部53のうちの1つを貫通させ、且つ前記第一パッド61が前記導電性バンプ7を介してこれら前記能動素子TFTのうちの1つに電気的に接続されるものであればよい。
例えば、これら前記開口部53が、円形、楕円形、矩形、または不規則形状を呈してもよく、本発明はこれらに限定されない。
なお、図3(A)は本発明の他の実施形態に係る部分の電子装置を示す概略図である。
図3(A)の電子装置は、これら前記開口部53が矩形である点以外は図1(A)、図1(B)、または図2に相似する。
In this embodiment, there is no particular restriction on the shape of the openings 53, and the conductive bump 7 passes through one of the openings 53, and the first pad 61 passes through the conductive bump 7. Any device may be used as long as it is electrically connected to one of the active element TFTs via the active element TFT.
For example, the openings 53 may have a circular, oval, rectangular, or irregular shape, but the present invention is not limited thereto.
Note that FIG. 3(A) is a schematic diagram showing a portion of an electronic device according to another embodiment of the present invention.
The electronic device of FIG. 3(A) is similar to FIG. 1(A), FIG. 1(B), or FIG. 2 except that the openings 53 are rectangular.

図3(B)は、本発明の他の実施形態に係る部分の電子装置を示す概略図である。図3(B)の電子装置は、後述の差異以外は図3(A)に相似する。
図3(A)に示されるように、前記電子装置の前記共通電極5は、複数の開口部53を有し、各開口部53は、発光素子6に対応するように設置される。
具体的には、各発光素子6の前記第一パッド61は、前記共通電極5の各開口部53に対応するように設置される。
FIG. 3(B) is a schematic diagram showing a portion of an electronic device according to another embodiment of the present invention. The electronic device in FIG. 3(B) is similar to FIG. 3(A) except for the differences described below.
As shown in FIG. 3A, the common electrode 5 of the electronic device has a plurality of openings 53, and each opening 53 is installed to correspond to a light emitting element 6.
Specifically, the first pad 61 of each light emitting element 6 is installed to correspond to each opening 53 of the common electrode 5.

本実施形態の電子装置において、図3(B)に示されるように、前記共通電極5は複数の開口部53を有し、各開口部53は複数の発光素子6に対応するように設置される。
具体的には、少なくとも2つのこれら前記発光素子6の前記第一パッド(図示省略)が、前記共通電極5のこれら前記開口部53のうちの1つに対応するように設置される。
本実施形態では、3つの発光素子6の第一パッドが前記共通電極5のうちの1つの開口部53に対応するように設置される。
In the electronic device of this embodiment, as shown in FIG. Ru.
Specifically, at least two of the first pads (not shown) of the light emitting elements 6 are installed to correspond to one of the openings 53 of the common electrode 5.
In this embodiment, the first pads of the three light emitting elements 6 are installed so as to correspond to one opening 53 of the common electrode 5.

図4(A)と図4(B)は、本発明の他の実施形態に係る部分の電子装置を示す概略図である。
図4(A)及び図4(B)の電子装置は、図3(A)及び図3(B)の電子装置に相似するが、差異としては、図3(A)及び図3(B)の電子装置のこれら前記発光素子6が単色発光ダイオードであるのに対し、本実施形態で使用されるこれら前記発光素子6は多色発光ダイオードである点である。
但し、本発明はこの限りではない。発光素子のパッドが共通電極に電気的に接続され、前記共通電極により接合時の圧力及び熱が平均的に分散されるのもであれば本発明の効果を達成可能である。
各発光素子は各々異なる色の光を発し、例えば赤色、青色、緑色、白色の光を発するが、本発明はこれらに限定されない。
FIGS. 4A and 4B are schematic diagrams showing parts of an electronic device according to another embodiment of the present invention.
The electronic devices in FIGS. 4(A) and 4(B) are similar to the electronic devices in FIGS. 3(A) and 3(B), but the differences are as follows: The light emitting elements 6 of the electronic device are monochrome light emitting diodes, whereas the light emitting elements 6 used in this embodiment are multicolor light emitting diodes.
However, the present invention is not limited to this. The effects of the present invention can be achieved as long as the pads of the light emitting elements are electrically connected to a common electrode and pressure and heat during bonding are evenly dispersed by the common electrode.
Each light emitting element emits light of a different color, for example, red, blue, green, and white light, but the present invention is not limited thereto.

図5は、本発明の他の実施形態に係る部分の電子装置を示す断面図である。図5の電子装置は、図2のものと相似し、その違いは前記電子装置が前記共通電極5に設置される光吸収層8を更に備える点である。
具体的には、前記共通電極5は第一領域R1及び第二領域R2を含み、前記第一領域R1は基板1の法線方向でこれら前記発光素子6と重畳し、前記第二領域R2は基板1の法線方向でこれら前記発光素子6と重畳せず、前記光吸収層8が前記第二領域R2に設置される。
但し、本発明はこれに限られず、例えば、前記光吸収層8が前記導電性バンプ7に設置され、発光素子の対比効果を更に強めて表示品質を向上させてもよい。
或いは、前記光吸収層8が前記第一領域R1に設置されてもよく、但し、光吸収層8が絶縁材料である場合は発光素子6のパッドに対応する開口部を有し、発光素子6と能動素子TFTとの電気的接続が維持される。
前記光吸収層8は黒色インク層、黒色樹脂層、粘着テープ、抗反射材料、黒色金属層、または吸光材料であるが、本発明はこれらに制限されず、前記光吸収層8が反射光を減らせ、発光素子の対比効果を増強可能な材料であればよい。
FIG. 5 is a cross-sectional view showing a portion of an electronic device according to another embodiment of the present invention. The electronic device of FIG. 5 is similar to that of FIG. 2, the difference being that the electronic device further includes a light absorption layer 8 disposed on the common electrode 5.
Specifically, the common electrode 5 includes a first region R1 and a second region R2, the first region R1 overlaps with the light emitting elements 6 in the normal direction of the substrate 1, and the second region R2 overlaps with the light emitting elements 6 in the normal direction of the substrate 1. The light absorption layer 8 is provided in the second region R2 without overlapping the light emitting elements 6 in the normal direction of the substrate 1.
However, the present invention is not limited thereto, and for example, the light absorption layer 8 may be provided on the conductive bump 7 to further strengthen the contrast effect of the light emitting elements and improve display quality.
Alternatively, the light absorption layer 8 may be installed in the first region R1; however, if the light absorption layer 8 is made of an insulating material, it has an opening corresponding to the pad of the light emitting element 6, and the light absorption layer 8 has an opening corresponding to the pad of the light emitting element 6. The electrical connection between the active element TFT and the active element TFT is maintained.
The light absorption layer 8 is a black ink layer, a black resin layer, an adhesive tape, an anti-reflection material, a black metal layer, or a light absorption material, but the present invention is not limited thereto. Any material may be used as long as it can reduce the amount of light and enhance the contrast effect of the light emitting element.

図6は、本発明の他の実施形態に係る部分の電子装置を示す概略図である。図6の電子装置は、図5のものと相似し、その差異は、前記光吸収層8が黒色金属層である点である。
具体的には、前記黒色金属層は、前記共通電極5に設置され、前記黒色金属層により前記共通電極5の全表面が覆われるが、本発明はこれに限られず、前記黒色金属層が前記発光素子6と重畳しない領域(例えば、図5の第二領域R2)にのみ設置されてもよく、或いは、前記黒色金属層が前記導電性バンプ7に設置されてもよい。
前記光吸収層8が黒色金属層である場合、これら前記発光素子6の再加工時に前記光吸収層8が損壊を免れる。
FIG. 6 is a schematic diagram illustrating a partial electronic device according to another embodiment of the present invention. The electronic device of FIG. 6 is similar to that of FIG. 5, the difference being that the light absorption layer 8 is a black metal layer.
Specifically, the black metal layer is installed on the common electrode 5, and the entire surface of the common electrode 5 is covered with the black metal layer, but the present invention is not limited to this. The black metal layer may be provided only in a region that does not overlap with the light emitting element 6 (for example, the second region R2 in FIG. 5), or the black metal layer may be provided on the conductive bump 7.
When the light-absorbing layer 8 is a black metal layer, the light-absorbing layer 8 is not damaged when the light-emitting elements 6 are reprocessed.

本実施形態では、前記黒色金属層の材料は酸化モリブデン、酸化銅、またはそれらの組み合わせであるが、本発明はこれらに制限されない。
前記黒色金属層の厚さは100A以上5μm以下であるが、本発明はこの限りではない。
In this embodiment, the material of the black metal layer is molybdenum oxide, copper oxide, or a combination thereof, but the present invention is not limited thereto.
Although the thickness of the black metal layer is 100 A or more and 5 μm or less, the present invention is not limited to this.

図7(A)~図7(D)は、本発明の一つの実施形態に係る電子装置を示す俯瞰図である。
図7(A)は、図3(A)の俯瞰図である。
また、図7(C)は、図4(A)の俯瞰図である。
さらにまた、図7(B)は、図6の俯瞰図である。
前記電子装置は、光吸収層8とする黒色金属層を備える。
俯瞰方向から見ると、発光素子6と重畳しない共通電極5に前記黒色金属層が設置され、前記共通電極5による発光素子6の光の反射を低減させ、発光素子6の対比効果を増強させ、表示品質を高めている。
図7(D)の電子装置は、図7(B)のものと相似し、その差異は、本実施形態では前記発光素子6が多色発光ダイオードである点であるが、本発明はこの限りではない。
7(A) to FIG. 7(D) are overhead views showing an electronic device according to one embodiment of the present invention.
FIG. 7(A) is an overhead view of FIG. 3(A).
Moreover, FIG. 7(C) is an overhead view of FIG. 4(A).
Furthermore, FIG. 7(B) is an overhead view of FIG. 6.
The electronic device includes a black metal layer serving as a light absorption layer 8.
When viewed from above, the black metal layer is installed on the common electrode 5 that does not overlap with the light emitting elements 6, reducing the reflection of light from the light emitting elements 6 by the common electrode 5, and enhancing the contrast effect of the light emitting elements 6, Improving display quality.
The electronic device of FIG. 7(D) is similar to that of FIG. 7(B), and the difference is that in this embodiment, the light emitting element 6 is a multicolor light emitting diode, but the present invention is limited to this. isn't it.

図8は、本発明の他の実施形態に係る部分の電子装置を示す断面図である。図8の電子装置は、図1~図6のものと相似し、その差異は、前記電子装置が前記共通電極5と前記導電性バンプ7との間に設置される第二絶縁層9を更に備える点である。
具体的には、前記第二絶縁層9は、これら前記開口部53中に設置されると共に前記第五絶縁層33に対応するように設置され、且つ少なくとも一部分の前記第二絶縁層9が前記共通電極5または前記導電性バンプ7に設置され、前記共通電極5及び前記導電性バンプ7にショートが発生しなくなる。
FIG. 8 is a cross-sectional view showing a portion of an electronic device according to another embodiment of the present invention. The electronic device of FIG. 8 is similar to those of FIGS. 1 to 6, the difference being that the electronic device further includes a second insulating layer 9 disposed between the common electrode 5 and the conductive bumps 7. The point is to be prepared.
Specifically, the second insulating layer 9 is installed in the openings 53 and in a manner corresponding to the fifth insulating layer 33, and at least a portion of the second insulating layer 9 is in the openings 53. The common electrode 5 or the conductive bump 7 is installed to prevent short circuit between the common electrode 5 and the conductive bump 7.

他の実施形態では、前述の図1~図8に掲示の電子装置は、例えば、接合電子装置、表示装置、アンテナ装置、検知(または感知)装置、或いはバックライト装置等を備え、但し、本発明はこれらに制限されない。 In other embodiments, the electronic devices shown in FIGS. 1 to 8 described above may include, for example, a junction electronic device, a display device, an antenna device, a sensing (or sensing) device, or a backlight device, etc. The invention is not limited thereto.

総合すると、本発明の電子装置は、共通電極の設計により、発光素子の接合時に生じる圧力及び熱を平均的に分散させることで下方の回路の損壊を回避させ、プロセスの歩留まり及び信頼性を高める。 Overall, the electronic device of the present invention can evenly distribute the pressure and heat generated during bonding of light emitting devices through the design of the common electrode, thereby avoiding damage to the underlying circuitry and increasing the yield and reliability of the process. .

本発明の電子装置は、各種表示装置に応用され、例えば、液晶(liquid-crystal、LC)、有機発光ダイオード(organic light-emitting diode、 OLED)、量子ドット(quantum dot、 QD)、蛍光(fluorescence)材料、燐光(phosphor)材料、発光ダイオード(light-emitting diode、LED)、マイクロ発光ダイオード(micro light-emitting diode or mini light-emitting diode)、または他の表示媒体による表示装置に応用されるが、本発明はこれらに限定されない。
本発明の実施形態において、発光ダイオードのチップサイズは約300μm乃至10mmであり、ミニ発光ダイオード(mini LED)のチップサイズは約100μm乃至300μmであり、マイクロ発光ダイオード(micro LED)のチップサイズは約1μm乃至100μmであるが、本発明はこれらに限られない。本発明の実施形態において、表示装置は、例えば、フレキシブルディスプレイ(flexible display)、タッチパネル(touch display)、曲面ディスプレイ(curved display)、またはタイル型ディスプレイ(tiled display)であるが、本発明はこれらに限られない。
The electronic device of the present invention can be applied to various display devices, such as liquid-crystal (LC), organic light-emitting diode (OLED), quantum dot (QD), fluorescence ) materials, phosphor materials, light-emitting diodes (LED), micro light-emitting diodes or mini light-emitting diodes, or other display media. However, the present invention is not limited thereto.
In an embodiment of the present invention, the chip size of the light emitting diode (mini LED) is about 300 μm to 10 mm, the chip size of the mini light emitting diode (mini LED) is about 100 μm to 300 μm, and the chip size of the micro light emitting diode (micro LED) is about Although the diameter is 1 μm to 100 μm, the present invention is not limited thereto. In embodiments of the present invention, the display device is, for example, a flexible display, a touch display, a curved display, or a tiled display; Not limited.

上述の実施形態は本発明の技術思想及び特徴を説明するためのものにすぎず、当該技術分野を熟知する者に本発明の内容を理解させると共にこれをもって実施させることを目的とし、本発明の特許請求の範囲を限定するものではない。
従って、本発明の精神を逸脱せずに行う各種の同様の効果をもつ改良又は変更は、後述の請求項に含まれるものとする。
The above-described embodiments are merely for explaining the technical idea and features of the present invention, and are intended to enable those familiar with the technical field to understand and implement the present invention. It does not limit the scope of the claims.
It is therefore intended that various similar improvements or changes made without departing from the spirit of the invention be covered by the following claims.

1 基板
2 能動層
21 半導体層
22 ゲート絶縁層
23 ゲート
24 第三絶縁層
25 第一電極
26 電二電極
3 絶縁層
31 第一絶縁層
311 スルーホール
312 パッシベーション層
313 平面層
32 第四絶縁層
33 第五絶縁層
331 第二開口部
4 導電ユニット
5 共通電極
51 第一共通電極層(第一パターン化金属層)
52 第二共通電極層(第二パターン化金属層)
53 開口部
6 発光素子
61 第一パッド
62 第二パッド
7 導電性バンプ
71 第一金属層(第一パターン化金属層)
72 第二金属層(第二パターン化金属層)
8 光吸収層
9 第二絶縁層
TFT 能動素子
10 基板載置部
101 第一面
102 第二面
103 側面
11 駆動ユニット
D1 距離
R1 第一領域
R2 第二領域
T1 厚さ
T2 厚さ
1 Substrate 2 Active layer 21 Semiconductor layer 22 Gate insulating layer 23 Gate 24 Third insulating layer 25 First electrode 26 Electrical electrode 3 Insulating layer 31 First insulating layer 311 Through hole 312 Passivation layer 313 Planar layer 32 Fourth insulating layer 33 Fifth insulating layer 331 Second opening 4 Conductive unit 5 Common electrode 51 First common electrode layer (first patterned metal layer)
52 Second common electrode layer (second patterned metal layer)
53 Opening 6 Light emitting element 61 First pad 62 Second pad 7 Conductive bump 71 First metal layer (first patterned metal layer)
72 Second metal layer (second patterned metal layer)
8 Light absorption layer 9 Second insulating layer TFT Active element 10 Substrate mounting part 101 First surface 102 Second surface 103 Side surface 11 Drive unit D1 Distance R1 First region R2 Second region T1 Thickness T2 Thickness

Claims (12)

基板と、
前記基板に設置される複数の能動素子と、
これら前記能動素子に設置されると共に複数の開口部を含む共通電極と、
前記共通電極に設置され、同じ側に位置される第一パッド及び第二パッドを各々具備する複数の発光素子と、
これら前記開口部のうちの1つに設置される導電性バンプと、前記共通電極と前記導電性バンプとの間に設置される絶縁層と、を備え、
前記前記共通電極と、前記導電性バンプとが、隙間によって隔てられており、
前記共通電極と、前記導電性バンプと、前記絶縁層とを、鉛直方向に沿った平面で切断した断面において、前記絶縁層の一部分が、前記隙間内に設けられており、前記絶縁層の別の一部分が、前記共通電極及び前記導電性バンプ上に設けられており、前記絶縁層の一部分と、前記絶縁層の別の一部分とが、繋がっており、
前記第一パッドは、これら前記開口部の1つに対応するように設置されると共に、前記導電性バンプを介してこれら前記能動素子の1つに電気的に接続され、且つ前記第二パッドは前記共通電極に電気的に接続されていることを特徴とする電子装置。
A substrate and
a plurality of active elements installed on the substrate;
a common electrode installed on these active elements and including a plurality of openings;
a plurality of light emitting elements each including a first pad and a second pad installed on the common electrode and located on the same side;
a conductive bump installed in one of the openings, and an insulating layer installed between the common electrode and the conductive bump,
the common electrode and the conductive bump are separated by a gap;
In a cross section of the common electrode, the conductive bump, and the insulating layer cut along a plane along the vertical direction, a part of the insulating layer is provided within the gap, and a portion of the insulating layer is a portion is provided on the common electrode and the conductive bump, and a portion of the insulating layer and another portion of the insulating layer are connected,
The first pad is located so as to correspond to one of the openings and is electrically connected to one of the active elements via the conductive bump, and the second pad is An electronic device, characterized in that the electronic device is electrically connected to the common electrode.
前記導電性バンプと前記共通電極との間の前記隙間の距離は、2μm以上100μm以下であることを特徴とする請求項1に記載の電子装置。 The electronic device according to claim 1, wherein a distance between the gap between the conductive bump and the common electrode is 2 μm or more and 100 μm or less. 前記絶縁層を第二絶縁層とした場合に、前記能動素子と、前記共通電極と、の間に設置される第一絶縁層を更に備え、前記第一絶縁層は、スルーホールを含み、前記電子装置は、前記スルーホール中に設置される導電ユニットを更に具備し、前記導電性バンプは、前記導電ユニットを介してこれら前記能動素子のうちの1つに電気的に接続されることを特徴とする請求項1に記載の電子装置。 When the insulating layer is a second insulating layer, the first insulating layer further includes a first insulating layer installed between the active element and the common electrode, the first insulating layer including a through hole, and the first insulating layer including the through hole. The electronic device further comprises a conductive unit installed in the through hole, and the conductive bump is electrically connected to one of the active elements via the conductive unit. The electronic device according to claim 1. 前記共通電極に設置される光吸収層を更に備えることを特徴とする請求項1に記載の電子装置。 The electronic device according to claim 1, further comprising a light absorption layer disposed on the common electrode. 前記光吸収層の材料として黒色金属層を含むことを特徴とする請求項4に記載の電子装置。 5. The electronic device according to claim 4, wherein the light absorption layer includes a black metal layer as a material. 前記光吸収層の材料として黒色樹脂層を含むことを特徴とする請求項4に記載の電子装置。 5. The electronic device according to claim 4, wherein the light absorption layer includes a black resin layer as a material. 各発光素子の前記第一パッドは前記共通電極の各開口部に対応するように設置されることを特徴とする請求項1に記載の電子装置。 The electronic device according to claim 1, wherein the first pad of each light emitting element is installed to correspond to each opening of the common electrode. 少なくとも2つのこれら前記発光素子の前記第一パッドは前記共通電極のこれら前記開口部のうちの1つに対応するように設置されることを特徴とする請求項1に記載の電子装置。 The electronic device according to claim 1, wherein the first pads of at least two of the light emitting elements are disposed to correspond to one of the openings of the common electrode. 前記共通電極の厚さは0.02μm以上100μm以下であることを特徴とする請求項1に記載の電子装置。 The electronic device according to claim 1, wherein the common electrode has a thickness of 0.02 μm or more and 100 μm or less. 少なくとも1つのこれら前記発光素子は多色発光ダイオードを備えることを特徴とする請求項1に記載の電子装置。 2. Electronic device according to claim 1, characterized in that at least one of said light emitting elements comprises a multicolor light emitting diode. 少なくとも1つのこれら前記能動素子は薄膜トランジスタを備えることを特徴とする請求項1に記載の電子装置。 2. Electronic device according to claim 1, characterized in that at least one of said active elements comprises a thin film transistor. 互いに対応し合う2面の第一面及び第二面と、前記第一面及び前記第二面に連接される側面と、を含む基板載置部を更に備え、前記基板は前記第一面、前記第二面、及び前記側面にそれぞれ設置される少なくとも3つの部分で構成されることを特徴とする請求項1に記載の電子装置。
The substrate further includes a substrate mounting section including two surfaces, a first surface and a second surface that correspond to each other, and a side surface connected to the first surface and the second surface, and the substrate has the first surface, The electronic device according to claim 1, comprising at least three parts installed on the second surface and the side surface, respectively.
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