JP7388052B2 - Power semiconductor test equipment and power semiconductor test method - Google Patents

Description

The present invention relates to a power semiconductor testing device and a power semiconductor testing method that perform a stress test on a power semiconductor having a configuration in which a switching element and a diode are connected in antiparallel.

Static characteristic tests, dynamic characteristic tests, etc. are performed in power semiconductor shipping inspection systems. Among these, dynamic characteristic tests include switching characteristic tests, reverse recovery characteristic tests, and avalanche tests. In particular, in reverse recovery characteristic tests and avalanche tests, electrical stress is applied to remove power semiconductors that have potential defects.

FIG. 6 is a diagram showing a reverse recovery characteristic test circuit for testing the reverse recovery characteristic of a power semiconductor, and FIG. 7 is a timing chart showing the operation of the reverse recovery characteristic test circuit.
The reverse recovery characteristic test circuit includes a power supply 101, capacitors 102 and 103, a switching element 104, a signal source 105, and an inductor 106. A power supply 101 is a power supply for a reverse recovery characteristic test circuit and supplies a voltage VDD.

The switching element 104 here employs a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). A drain terminal of the switching element 104 is connected to the positive terminal of the power supply 101, and a source terminal is connected to one terminal of the inductor 106 and a high potential terminal of the device under test (DUT). The other terminal of inductor 106 and the low potential terminal of device under test DUT are connected to the negative terminal of power supply 101. A signal source 105 that outputs a pulse signal is connected to the gate terminal and source terminal of the switching element 104.

The device under test DUT is a power MOSFET in this example, and therefore what is tested by this reverse recovery characteristic test circuit is a parasitic diode built into the power MOSFET. To test the reverse recovery characteristics of the parasitic diode of the power MOSFET, the gate terminal and source terminal of the power MOSFET are shorted to turn off the power MOSFET.

In this reverse recovery characteristic test circuit, the reverse recovery characteristic of the parasitic diode of the device under test DUT is tested by inputting a pulse signal shown by VGS in FIG. 7 from the signal source 105 to the switching element 104. That is, when the switching element 104 is turned on, the voltage VDD is applied to the parallel circuit of the device under test DUT and the inductor 106, and the drain-source voltage VDS of the device under test DUT becomes the voltage VDD. At this time, the parasitic diode of the device under test DUT is reverse biased, so no current flows through the device under test DUT, but current flows through the inductor 106 and energy is stored there.

Next, when the switching element 104 is turned off, the current flowing through the inductor 106 tries to continue flowing, so the current does not return to the power supply 101 but flows forward through the parasitic diode ( Source-drain current (ISD) of the device under test DUT.

Next, when the switching element 104 is turned on and voltage VDD is applied to the drain terminal of the device under test DUT while current is flowing through the parasitic diode, the parasitic diode of the device under test DUT performs reverse recovery operation. Start. In other words, the source-drain current ISD that was flowing in the forward direction through the parasitic diode suddenly decreases, and after reaching 0 ampere (A), the reverse recovery current flows in the reverse direction through the parasitic diode, and after passing its peak, it becomes reverse. The recovery current returns to 0A.

The above operation is repeated four times in the example of FIG. During this time, while the energy stored in the inductor 106 is circulating through the parasitic diode, the switching element 104 is turned on and the energy is stored in the inductor 106 again. Therefore, each time the switching element 104 is turned off, the source-drain current ISD flowing through the parasitic diode gradually increases.

After stress is applied to the parasitic diode of the device under test DUT in this manner, the drain-source voltage VDS or drain current of the device under test DUT is observed by a meter not shown. At this time, if there is no significant change in the drain-source voltage VDS or drain current, the device under test DUT is determined to be non-defective. On the other hand, if the drain-source voltage VDS drops to 0 volts (V) or a large current flows as a drain current, the device under test DUT is determined to be defective and is rejected.

FIG. 8 is a diagram showing an avalanche test circuit that performs an avalanche test on power semiconductors, and FIG. 9 is a timing chart showing the operation of the avalanche test circuit.
The avalanche test circuit includes a power supply 111, an inductor 112, and a signal source 113. A power supply 111 is a power supply for the avalanche test circuit and supplies voltage VDD. The device under test DUT is a power MOSFET in this example, and therefore, what is tested by this avalanche test circuit is the avalanche tolerance of the power MOSFET.

In the avalanche test circuit, the positive terminal of the power supply 111 is connected to one terminal of the inductor 112, and the other terminal of the inductor 112 is connected to the drain terminal of the power MOSFET, which is the high potential terminal of the device under test DUT. . The source terminal of the power MOSFET, which is a low potential terminal of the device under test DUT, is connected to the negative terminal of the power supply 111. A signal source 113 is connected to the gate terminal of the power MOSFET and the source terminal of the power MOSFET, which are control terminals of the device under test DUT.

In this avalanche test circuit, the avalanche tolerance of the power MOSFET is tested by inputting a pulse signal shown by VGS in FIG. 9 from the signal source 113 to the device under test DUT. That is, when the power MOSFET of the device under test DUT is turned on, the drain-source voltage VDS of the power MOSFET drops to 0V, and the drain current ID gradually begins to flow into the power MOSFET via the inductor 112.

Next, when the power MOSFET of the device under test DUT is turned off, the drain current ID of the power MOSFET decreases, and the drain-source voltage VDS of the power MOSFET rapidly increases. Although the drain-source voltage VDS rises to the element breakdown voltage and is clamped at the breakdown voltage, the remaining energy stored in the inductor 112 continues to flow as the drain current ID. The drain current ID at this time flows as an avalanche current and is consumed as heat inside the power MOSFET.

After that, in the device under test DUT, the drain-source voltage VDS of the power MOSFET is maintained at the voltage VDD, and the drain current ID of the power MOSFET is maintained at 0A. Here, after the power MOSFET of the device under test DUT is turned off, if the drain-source voltage VDS drops to 0V or the drain current ID suddenly increases, the device under test DUT is considered to be a defective product. is judged to be, and is excluded.

Although the reverse recovery characteristic test and the avalanche test described above are performed using independent test circuits, the test system becomes large-scale and the equipment cost increases. On the other hand, circuits that perform reverse recovery characteristic tests and avalanche tests are provided, and when performing reverse recovery characteristic tests or avalanche tests, the tests are performed by switching each circuit with a switch (for example, patented (See Reference 1).

Japanese Patent Application Publication No. 2010-107432

If the reverse recovery characteristic test and the avalanche test are performed sequentially using a switch, there is no need to transfer the device under test for each test, but the time required for each test is the same.

The present invention has been made in view of the above points, and an object of the present invention is to provide a power semiconductor testing device and a power semiconductor testing method that can further shorten the time required for a reverse recovery characteristic test and an avalanche test. do.

In order to solve the above-mentioned problems, the present invention provides a power semiconductor test apparatus that performs a stress test on a device under test, which is a power semiconductor in which a switching element and a diode are connected in antiparallel. This test equipment for power semiconductors includes a first signal generation section that generates a plurality of first pulse signals, a power supply section that outputs a power supply voltage, and a switch that is turned on or off in response to the first pulse signal. an element, a first inductor connected in series to the switching element, a second inductor connected between the switching element and the device under test, and a second pulse signal for driving the device under test. a second signal generating section that generates a switch, and receives a first pulse signal generated from the first signal generating section to the device under test and the first inductor connected in parallel. A diode reverse recovery test is performed by applying a switched power supply voltage when the element turns on or off, and the first pulse signal turns on during the off period, and the timing at which the maximum allowable avalanche current flows through the device under test. By causing the second signal generating section to generate a second pulse signal that turns off at , an avalanche test of the switching element is performed while a reverse recovery test is being performed.

Further, the present invention provides a power semiconductor testing method for performing a stress test on a device under test which is a power semiconductor in which a switching element and a diode are connected in antiparallel. This power semiconductor testing method performs a reverse recovery test on a diode by applying multiple pulse voltages to the device under test and the first inductor connected in parallel. An avalanche test of the switching element is performed by turning on the device under test for a predetermined period from the leading edge of the voltage rise and causing current to flow through the second inductor and the switching element.

The power semiconductor testing device and power semiconductor testing method configured as described above have the advantage that the avalanche test can be performed while the reverse recovery characteristic test is being performed, so that the test lead time can be shortened.

FIG. 1 is a diagram showing the configuration of a power semiconductor testing device according to a first embodiment. 5 is a timing chart showing operations of a reverse recovery characteristic test and an avalanche test. 5 is a timing chart showing signals generated during an avalanche test. FIG. 3 is a diagram showing the configuration of a power semiconductor testing device according to a second embodiment. FIG. 3 is a diagram showing the timing of an off signal generated during an avalanche test. FIG. 2 is a diagram showing a reverse recovery characteristic test circuit that performs a reverse recovery characteristic test of a power semiconductor. 5 is a timing chart showing the operation of the reverse recovery characteristic test circuit. FIG. 2 is a diagram showing an avalanche test circuit that performs an avalanche test on power semiconductors. 5 is a timing chart showing the operation of the avalanche test circuit.

Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the accompanying drawings. Note that in the drawings, parts indicated by the same reference numerals indicate the same constituent elements. Further, the device under test DUT tested by the power semiconductor testing apparatus of the present invention is a power semiconductor such as a power MOSFET having a structure in which a switching element and a diode are connected in antiparallel.

FIG. 1 is a diagram showing the configuration of a power semiconductor testing device according to the first embodiment, FIG. 2 is a timing chart showing operations of a reverse recovery characteristic test and an avalanche test, and FIG. 3 is a diagram showing the operation of a reverse recovery characteristic test and an avalanche test. It is a timing chart showing signals.

The power semiconductor testing apparatus 10 according to the first embodiment includes a power supply 11, capacitors 12 and 13, a switching element 14, and inductors L and Lp. The power semiconductor test apparatus 10 also includes a signal generator 15 and a gate driver 16 that drive the switching element 14, a signal generator 17 and a gate driver 18 that drive the device under test DUT, and a timer 19. There is. A power supply 11 is a power supply for the power semiconductor testing apparatus 10 and supplies a voltage VDD. Voltage VDD is stabilized by capacitors 12 and 13 connected in parallel to power supply 11, reducing switching noise.

The switching element 14 is an N-channel power MOSFET, and its drain terminal is connected to the positive terminal of the power supply 11, and its source terminal is connected to one terminal of the inductors L and Lp, respectively. The other terminal of the inductor Lp is connected to the high potential terminal of the device under test DUT, and the low potential terminal of the device under test DUT and the other terminal of the inductor L are connected to the negative terminal of the power supply 11.

The inductor L is used only for the reverse recovery characteristic test, and has an inductance of 10 microhenry (μH) to 20 μH, for example. The inductor Lp is mainly due to the parasitic inductance of the wiring, and has a value of, for example, 10 nanohenries (nH) to 100 nH. The value of this inductor Lp is determined by adjusting the length of the wiring from the source terminal of the switching element 14 to the high potential terminal of the device under test DUT. The device under test DUT is an N-channel power MOSFET, and has a structure in which a MOSFET 20 and a parasitic diode 21 are connected in antiparallel.

A gate driver 16 is connected to the gate terminal and source terminal of the switching element 14, and the gate driver 16 is connected to the output terminal of the signal generator 15 and is supplied with a pulse signal generated by the signal generator 15. Ru. The pulse signal supplied to the gate driver 16 becomes a gate signal (VGS) that drives the switching element 14.

The output terminal of the signal generator 15 is also connected to a timer 19. As shown in FIG. 3, the timer 19 detects the falling edge of any one (in the illustrated example, the second pulse signal) of the pulse signals (VGS of the switching element) generated by the signal generator 15. Signals Ton and Toff that are delayed by predetermined times T1 and T2 from the trailing edge are output. Note that the time T1 is set during the off period of the pulse signal. Further, the time T2 is calculated from the period (off period) of the pulse signal generated by the signal generator 15, the voltage VDD, the inductance of the inductor Lp, and the maximum allowable avalanche current allowed at the time of avalanche breakdown. The output terminal of the timer 19 is connected to a signal generator 17, and the signal generator 17 generates a gate signal for the device under test DUT (VGS of the DUT in FIG. 3) from the signals Ton and Toff output by the timer 19. The output terminal of the signal generator 17 is connected to a gate driver 18, and the output terminal of the gate driver 18 is connected to a control terminal and a low potential terminal of the device under test DUT, and receives the gate signal generated by the signal generator 17. It is supplied to the device under test DUT.

According to this power semiconductor test apparatus 10, after the device under test DUT is set in the power semiconductor test apparatus 10, an avalanche test is also performed while performing a reverse recovery characteristic test of the device under test DUT. There is. That is, as shown in FIG. 2, the reverse recovery characteristic test is started at time t0, and a pulse signal generated by the signal generator 15 is supplied to the switching element 14. When the switching element 14 is turned on, the voltage VDD is applied to the device under test DUT via the inductor Lp, and the voltage VDD is also applied to the inductor L. As a result, the drain-source voltage VDS of the device under test DUT becomes the voltage VDD. At this time, the parasitic diode 21 of the device under test DUT is reverse biased, so no current flows through the device under test DUT, but current flows through the inductor Lp and energy is stored there.

Next, when the switching element 14 is turned off at time t1, the current flowing through the inductor L tries to continue flowing, so the current does not return to the power supply 11 but flows through the parasitic diode 21 in the forward direction. (ISD of the DUT in Figure 2).

At time t2 when current is flowing through the parasitic diode 21, when the switching element 14 is turned on and voltage VDD is applied to the drain terminal of the device under test DUT, the parasitic diode 21 of the device under test DUT undergoes reverse recovery. Start operation. First, the current that was flowing in the forward direction through the parasitic diode 21 (ISD of the DUT in Figure 2) decreases rapidly, and after reaching 0A, a reverse recovery current flows in the reverse direction through the parasitic diode 21, and the current reaches its peak. Then, the reverse recovery current returns to 0A.

In the example of FIG. 2, the above operations are repeatedly performed using four pulse signals. Note that after the rising leading edge of the pulse signal (times t0, t2, t5, t7), the drain-source voltage VDS or drain current of the device under test DUT is observed, respectively. At this time, if there is no significant change in the drain-source voltage VDS or drain current, the device under test DUT is determined to be non-defective. On the other hand, if the drain-source voltage VDS drops to 0V or a large current flows as a drain current, the device under test DUT is determined to be a defective product and is rejected.

In the illustrated example, the avalanche test is performed when the third pulse signal is applied to the switching element 14. For this purpose, the timer 19 starts counting at the timing of the trailing edge of the falling edge of the second pulse signal (time t3), and at the timing (times t4, t6) after predetermined times T1, T2 have elapsed from the start of counting. Outputs signals Ton and Toff. The signal generator 17 generates a pulse signal that rises and falls at the timing of receiving the signals Ton and Toff from the timer 19, and the gate driver 18 drives the device under test DUT. As a result, the device under test DUT is turned on at the leading edge of the rising edge of the switching element 14 at time t5, and after the gate signal of the device under test DUT (VGS of the DUT in FIG. 3) falls at time t6. You will have to turn off at the edge.

When the device under test DUT is turned on at time t5, the source-drain current ISD due to the inductor L is circulating in the parasitic diode 21 of the device under test DUT. Therefore, a drain current ID in the opposite direction to the source-drain current ISD begins to flow through the inductor Lp (ISD decreases).

At time t6, the device under test DUT is turned off when the drain current ID increases (ISD decreases) and reaches the maximum allowable avalanche current. As a result, the drain current ID of the device under test DUT rapidly decreases, and the drain-source voltage (VDS of the DUT) rapidly increases. The drain-source voltage (VDS of the DUT) increases to the device breakdown voltage and is clamped at the breakdown voltage, but the remaining energy stored in the inductor Lp continues to flow as the drain current ID. The drain current ID at this time flows as an avalanche current and is consumed as heat inside the power MOSFET.

After that, in the device under test DUT, the drain-source voltage (VDS of the DUT) is maintained at the voltage VDD, and the drain current ID is maintained at 0A. Here, after the device under test DUT is turned off, if the drain-source voltage (VDS of the DUT) drops to 0V or the drain current ID suddenly increases, the device under test DUT will fail. It is judged to be a good product and is rejected.

According to this power semiconductor test apparatus 10, the avalanche test is performed while the reverse recovery characteristic test is being performed, rather than performing the reverse recovery characteristic test and the avalanche test by switching between them. Even the test time for the recovery characteristic test can be shortened. Therefore, the test lead time can be shortened.

FIG. 4 is a diagram showing the configuration of a power semiconductor testing apparatus according to the second embodiment, and FIG. 5 is a diagram showing the timing of an off signal generated during an avalanche test. In FIG. 4, the same or equivalent components as those shown in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

In the power semiconductor test apparatus 10 of the first embodiment, the timing at which the maximum permissible avalanche current is reached during an avalanche test is determined by calculation, whereas in the power semiconductor test of the second embodiment, The device 10a obtains the value through actual measurements. Note that the reverse recovery test is the same as the test described in the first embodiment, so the explanation of the operation of the reverse recovery test will be omitted here.

This power semiconductor testing device 10a includes a current detection resistor 22 and a current detector 23 for measuring drain current ID. Current detection resistor 22 is connected between the source terminal of the device under test DUT and the negative terminal of power supply 11 , and both terminals of current detection resistor 22 are connected to current detector 23 .

The timer 19a outputs a signal Ton delayed by a predetermined time T1 from the falling trailing edge of the pulse signal generated by the signal generator 15. This time T1 is set during the off period of the pulse signal.

The current detector 23 detects the drain current ID of the device under test DUT using the current detection resistor 22, detects whether the current has reached the maximum allowable avalanche current, and outputs a signal Toff. Specifically, the current detector 23 includes a comparator and a reference voltage that outputs a voltage corresponding to the maximum allowable avalanche current, and outputs a signal obtained by converting the drain current detected by the current detection resistor 22 by the comparator into a voltage and the reference voltage. Compare with voltage. When the signal obtained by converting the drain current into voltage exceeds the reference voltage, the comparator outputs the signal Toff. Note that in FIG. 5, the drain current ID is expressed by a source-drain current ISD in the opposite direction. That is, FIG. 5 explains that the timing at which the source-drain current ISD decreases and reaches the maximum allowable avalanche current IAS is the timing at which the signal Toff is output.

The signal generator 17 generates a gate signal (VGS of the DUT) that rises in response to the signal Ton output by the timer 19a, and turns on the device under test DUT. Thereafter, the switching element 14 is turned on, and the voltage VDD of the power supply 11 is applied to the series circuit of the inductor Lp, the device under test DUT, and the current detection resistor 22. As a result, the source-drain current ISD no longer flows, and the drain current ID begins to flow through the inductor Lp.

When the current detector 23 detects that the drain current ID has reached the maximum allowable avalanche current IAS and outputs the signal Toff, the signal generator 17 turns off the gate signal (VGS of the DUT) and turn off. As a result, the drain current ID of the device under test DUT rapidly decreases, and the drain-source voltage (VDS of the DUT) rapidly increases. The drain-source voltage (VDS of the DUT) increases to the device breakdown voltage and is clamped at the breakdown voltage, but the remaining energy stored in the inductor Lp continues to flow as the drain current ID. The drain current ID at this time flows as an avalanche current and is consumed as heat inside the power MOSFET.

After that, in the device under test DUT, the drain-source voltage (VDS of the DUT) is maintained at the voltage VDD, and the drain current ID is maintained at 0A. Here, after the device under test DUT is turned off, if the drain-source voltage (VDS of the DUT) drops to 0V or the drain current ID suddenly increases, the device under test DUT will fail. It is judged to be a good product and is rejected.

Note that in the above embodiment, the case where the device under test DUT is a power MOSFET has been described. However, in the present invention, an IGBT (Insulated Gate Bipolar Transistor) and an FWD (Free Wheeling Diode) can be modularized as the device under test DUT. Further, the present invention can be applied to a screening test for RC-IGBT (Reverse Conducting-IGBT) in which an IGBT section and a FWD section are integrated into one chip.

10, 10a Power semiconductor test equipment 11 Power supply 12, 13 Capacitor 14 Switching element 15 Signal generator 16 Gate driver 17 Signal generator 18 Gate driver 19, 19a Timer 20 MOSFET
21 Parasitic diode 22 Current detection resistor 23 Current detector DUT Device under test L, Lp Inductor

Claims (7)

In power semiconductor test equipment that performs stress tests on devices under test, which are power semiconductors in which switching elements and diodes are connected in antiparallel,
a first signal generating section that generates a plurality of first pulse signals;
a power supply unit that outputs power supply voltage;
a switching element that is turned on or turned off in response to the first pulse signal;
a first inductor connected in series to the switching element;
a second inductor connected between the switching element and the device under test;
a second signal generating section that generates a second pulse signal that drives the device under test;
Equipped with
The switching element is turned on or off in response to the first pulse signal generated from the first signal generating section with respect to the device under test and the first inductor that are connected in parallel. Performing a reverse recovery test of the diode by applying the switched power supply voltage,
The second signal generating unit generates the second pulse signal that is turned on during the off period of the first pulse signal and turned off at the timing when the maximum allowable avalanche current flows through the device under test. A power semiconductor testing device that performs an avalanche test on the switching element while performing a reverse recovery test . 2. The power semiconductor testing apparatus according to claim 1, wherein the second inductor is an inductor based on parasitic inductance of wiring. 3. The power semiconductor testing device according to claim 2, wherein the second inductor has an inductance of 10 to 100 nanohenries. The second signal generating section includes a timer that outputs an on signal and an off signal that are delayed by a predetermined first time and a second time from the falling trailing edge of the first pulse signal, and the second signal generating section 2. The power semiconductor testing device according to claim 1, wherein the power semiconductor test device outputs the second pulse signal in response to the on signal and the off signal from the power semiconductor test device. In a power semiconductor testing method that performs a stress test on a device under test, which is a power semiconductor in which a switching element and a diode are connected in antiparallel,
performing a reverse recovery test on the diode by applying a plurality of pulse voltages to the device under test and the first inductor connected in parallel;
Avalanche testing of the switching element by turning on the device under test for a predetermined period from the rising leading edge of any one of the plurality of pulse voltages and causing current to flow through the second inductor and the switching element. I do,
Power semiconductor test method. 6. The power semiconductor testing method according to claim 5 , wherein the predetermined period is a period until the current flowing through the switching element reaches a maximum allowable avalanche current. a timer that outputs an on signal delayed by a predetermined time from the falling trailing edge of the first pulse signal; and a timer that detects a current flowing through the device under test, and when the detected current is the maximum allowable avalanche current. a current detection circuit that outputs an OFF signal, and the second signal generation section receives the ON signal from the timer, receives the OFF signal from the current detection circuit, and outputs the second pulse signal. The power semiconductor testing device according to claim 1 .

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