JP7385536B2 - Software development support device and software development support method - Google Patents

Description

The present invention relates to a software development support device and a software development support method for developing control software in model-based development for controlling equipment.

In software development for embedded systems, which are computer systems that are built into machines and equipment to achieve specific functions, the equipment is controlled in real time by executing a control program that implements processing to control the equipment.

In recent years, in the development of control software, instead of writing the source code of the control software, developers sometimes write it using a "(control) model" that is easier to generate and has better visibility. This development method is called model-based development.

An example of a program development environment compatible with model-based development is MATLAB (registered trademark) from MathWorks (registered trademark). A developer describes a model using Simulink, which is a function of MATLAB (registered trademark). A model is described by functional units called blocks and connections indicating input/output relationships between the functional units.

A model that describes functions implemented by control software using Simulink (registered trademark) is called a control model. The process of adding information such as data type and bit rate necessary for generating source code based on this control model using, for example, dSpace (registered trademark)'s TargetLink (registered trademark) is called scaling. The source code generated based on the control model is called model source.

As a well-known example, Patent Document 1 discloses a technique that performs scaling on a control model and automates the process up to source code generation.

Furthermore, in software development, it is known that reuse development, in which software components are collected and reused, is an effective method, rather than generating software and programs from scratch.

As a known example, Patent Document 2 discloses a system in which software components to which category information is assigned are prepared, a software component that satisfies a development request is searched for, and source code can be used for development.

Japanese Patent Application Publication No. 2017-016416 Japanese Patent Application Publication No. 2008-040969

However, the control model does not express the specifications of the entire program, and the control specifications of the entire program are composed of multiple control models, and the information between the control models is a model (hereinafter referred to as a feature model) that expresses the characteristics of the entire control specification. ) is expressed by.

Although the technique disclosed in Patent Document 1 can generate a model source for a control model, it cannot generate a program that satisfies the specifications of the feature model.

Since a feature model is composed of a large number of control models, if code is generated from the control models each time a program that satisfies the specifications of the feature model is generated, it will take as much generation time as the number of control models to be used.

Although the technology described in Patent Document 2 makes it easy to search for software components, it does not manage source code units, but instead manages part of the source code as components by category, so it is difficult to understand the classification and processing dependencies. Designers themselves need to find appropriate parts and then generate source code.

Therefore, in order to generate an executable program, it is necessary to analyze the dependencies between control models from the feature model, define the execution order, and pass the variables to ensure consistency when using the same variables in different calculation cycles. Although it is necessary to define the process (buffering process) and compile execution information (MAKE file) that defines files and settings to be compiled, both Patent Documents 1 and 2 take the above three points into consideration. Not yet.

Furthermore, in the development of embedded software for automotive electronic control units (ECUs), for example, microcomputers containing multiple cores are required to counter the increase in heat generation and power consumption associated with improved performance of microcomputers (hereinafter referred to as microcomputers). It is now emerging, and there is a need for software to have a structure that can support multiple cores.

In view of the above-mentioned problems, the present invention generates a program from control specifications defined in a feature model, allows parts to be managed in model source units without adding category information to model sources, and , an object of the present invention is to provide a software development support device that can also support a processor including multiple cores.

The present invention is a software development support device having a first processor and a memory, which receives a feature model that describes a software control specification including an execution order of the control model, and controls the feature model constituting the feature model. a feature model analysis unit that analyzes the model, analyzes the calculation cycle of the control model and the execution order of the control model, and outputs the result as execution order information; a model source generation unit that generates a model source whose file name is the same as the control model, tests whether the generated model source matches the specifications of the control model, and then stores it in a model source storage unit; , a model source collection unit that collects a model source having the same name as the control model analyzed from the feature model from the model source storage unit; and a second processor that has a plurality of cores and executes the software. Receiving input processor information, and processing assignment information for each core based on the calculation cycle and execution order information in order to optimize the software for processing of the plurality of cores with respect to the collected model source. and a parallel processing generation unit that generates.

According to the present invention, software optimized for a processor including multiple cores can be developed. Furthermore, since the collection of source code, setting of execution order of calculations, setting of connection information, compilation, and allocation of processing to each core can be automatically carried out, it is possible to reduce the number of man-hours for design work.

Further, the present invention is not limited to the embodiments, and various applications can be made to embedded control devices other than ECUs and software development methods based on model information without departing from the scope of the present invention. Therefore, based on the feature model, it is possible to automatically output a program that satisfies the control specifications expressed by the feature model.

The details of at least one implementation of the subject matter disclosed herein are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the disclosed subject matter will be apparent from the following disclosure, drawings, and claims.

FIG. 2 is a relationship diagram between a control model and a feature model, showing an embodiment of the present invention. 1 is a diagram illustrating an example of a control model according to an embodiment of the present invention; FIG. FIG. 1 is a block diagram showing an example of the functions of a software development support device according to an embodiment of the present invention. 1 is a block diagram showing an example of the configuration of a software development support device according to an embodiment of the present invention. FIG. 1 is a flowchart illustrating an example of processing performed by a software development support device according to an embodiment of the present invention. FIG. 6 is a diagram illustrating a usage model identification process performed by a feature model analysis unit according to an embodiment of the present invention. 1 is an example of a calculation execution order list for each calculation cycle of a feature model analysis unit, showing an embodiment of the present invention. FIG. 7 is a diagram illustrating an example of the definition of variable connection processing for each calculation cycle of the feature model analysis unit according to an embodiment of the present invention. FIG. 3 is a diagram of a control model in which the same variable is used in different calculation cycles, showing an embodiment of the present invention. FIG. 2 is a configuration diagram of a connection processing addition unit of a software development support device, showing an embodiment of the present invention. FIG. 6 is a diagram illustrating an example of the calculation execution order definition for each calculation cycle of the connection processing addition unit according to the embodiment of the present invention. 1 is a configuration diagram of a parallel processing generation unit of a software development support device, showing an embodiment of the present invention; FIG. FIG. 2 is a diagram illustrating an embodiment of the present invention and illustrating an example in which parallel processing is assigned to two processor cores.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the relationship between the control models A102-A to G102-G and the feature model 101. The feature model 101 is composed of a plurality of control models A102-A2 to G102-G, and the execution order of each control model is determined by calculation of common variables and reference timing. The feature model 101 describes the control specifications of the entire software to be generated and the processing order of the control model.

In the following description, when the control models A to G are not individually specified, the symbol "control model 102" will be used, omitting the part after "-". Further, the same applies to the symbols of other constituent elements.

The output of control model A102-A is input to control model B102-B and control model E102-E. Control model B102-B performs predetermined processing on the output of control model A102-A and outputs it to control model C102-C. The control model D102-D performs predetermined processing on the output of the control model C102-C and outputs it to the control model G102-G.

The control model E102-E performs predetermined processing on the output of the control model A102-A and outputs it to the control model F102-F. The control model F102-F performs predetermined processing on the output of the control model E102-E and outputs it to the control model G102-G. The control model G102-G outputs the result of performing predetermined processing on the outputs of the control model D102-D and the control model F102-F.

Note that the control model 102 of this embodiment can be a model used in well-known model-based development, and is composed of a block diagram or the like that describes arithmetic processing in units of control.

FIG. 2 is a diagram showing an example of internal processing of the control model 102. Inside the control model 102, as shown in the figure, one or more processes A (211) to C (213) are performed on one or more input values X (201) to obtain one or more output values ( In this embodiment, two values (Y and Z) 202 and 203 are calculated. Further, the output values Y and Z (202, 203) also include information specifying the calculation core when calculation is performed by a multi-core processor.

FIG. 3A is a block diagram showing an example of the functions of the software development support device 301.

The software development support device 301 requires information on the control model 102 and feature model 303 as input. The model source generation unit 304 generates source code written in C language from the input control model 102 using an autocoding function such as TargetLink (registered trademark).

The source code output based on this control model 102 is called a model source. At this time, the control model 102 and the generated model source have the same file name excluding the extension, and the model source includes information on the calculation cycle to be executed.

In the model source generation unit 304 of this embodiment, the model source output from the control model 102 is one model source from one control model, but one calculation performed within the control model 102 is treated as one model source. You can also output it.

The model source generation unit 304 verifies equivalence between the generated source code and the input control model 102, and performs a unit test to determine whether input and output values of variables to the model source are in accordance with specifications.

When the content of the control model 102 is changed due to diversion or the like, the name is changed by adding a number indicating the number of updates to the end of the file name each time the file is updated, thereby preventing files with the same name from being duplicated.

The model source generated by the model source generation unit 304 is stored in the model source storage unit 305, and all control models 102 used in the feature model 101 are stored in the model source storage unit 305 in advance. The feature model analysis unit 306 analyzes the input feature model 101. (Detailed processing will be described later.)

The model source collection unit 307 collects model sources generated from the same control model 102 based on the control model information specified by the feature model analysis unit 306 from the model source storage unit 305, and creates a collected model source list 901 (see FIG. 9). ) is generated.

Each of the model sources collected by the model source collection unit 307 has already been subjected to a unit test, so there is no need to perform a new test or other confirmation work on the collected model sources.

For the model sources collected by the model source collection unit 307, a connection processing adding unit 308 defines connection information between the control models 102 (detailed processing will be described later).

The parallel processing generation unit 309 adds processing for multi-core processors (detailed processing will be described later). The parallel processing generation unit 309 uses the feature model analysis unit 306, the connection processing addition unit 308, and information on the number of cores of the processor of the controlled ECU input in the processor information 310, processing capacity, and address assignment information for each core. Generate parallel processing based on and apply it to the model source.

Since the model source to which parallel processing has been applied satisfies the information necessary for compilation, the compiling unit 311 can compile it. The compiling unit 311 converts the model source and the added connection processing into an executable file that can be processed on the processor. The file (program) compiled by the compile unit 311 is output from the program output unit 312.

FIG. 3B is a block diagram showing an example of the configuration of the software development support device 301. The software development support device 301 is a computer including a processor 11 , a memory 12 , a storage device 13 , an input/output device 14 , and a network device 15 .

The input/output device 14 includes an input device such as a keyboard, a mouse, or a touch panel, and an output device such as a display. Network device 15 is connected to network 16 and can communicate with other devices.

The memory 12 includes a model source generation section 304, a feature model analysis section 306, a model source collection section 307, a connection processing addition section 308, a parallel processing generation section 309, a compiling section 311, and a program output section 312. It is loaded as a program and executed by the processor 11. Furthermore, a model source storage unit 305 is stored in the memory 12 as data used by each program.

The processor 11 operates as a functional unit that provides predetermined functions by executing processes according to the programs of each functional unit. For example, the processor 11 functions as the model source generation unit 304 by executing processing according to the model source generation program. The same applies to other programs. Furthermore, the processor 11 also operates as a functional unit that provides functions for each of the plurality of processes executed by each program. A computer and a computer system are devices and systems that include these functional units.

An example of the processing performed by the software development support device 301 is shown in the flowchart of FIG. The feature model analysis unit 306 of the software development support device 301 identifies the control models 102 used in the feature models 303 and generates a list of control models 102 (401). This process will be described later with reference to FIG.

Next, the feature model analysis unit 306 extracts allocation information of cores that process the control model 102 (402). Note that the core assignment information can be extracted from the control model 102, for example. Then, the feature model analysis unit 306 analyzes the calculation cycle and calculation order of each control model 102 and generates a calculation execution order list (403). This process will be explained in detail with reference to FIG.

Furthermore, the model source generation unit 304 inputs the control model, generates a model source, and stores it in the model source storage unit 305. The model source collection unit 307 collects model sources corresponding to the calculation execution order list and outputs them to the connection processing addition unit 308.

After that, the connection processing addition unit 308 searches for control models 102 that use the same variables in different calculation cycles (404). As a result of the search, if there is a control model 102 that uses the same variable in different calculation cycles, the connection process addition unit 308 generates a source code for the variable connection process (405).

The parallel processing generation unit 309 allocates the generated source code to each calculation cycle of the connection destination (406). This process will be described later with reference to FIG. Then, the connection process addition unit 308 determines whether there is any variable connection process that has not been completed (407), and repeats the above steps 404 to 406 until all variable connection processes are completed. Execute.

The above process enables the software development support apparatus 301 to automatically add a variable connection process for passing variables between control models 102 that use the same variable in different calculation cycles.

FIG. 5 is a diagram illustrating an example of the usage model identification process of the feature model analysis unit 306. The feature model analysis unit 306 analyzes the calculation order of the control models 102 included in the input feature model 101, and assigns core allocation information 502-1, 502-2 set in advance to each control model 102.

The feature model analysis unit 306 generates a usage model and core assignment list 501 that includes the control model 102 to be used and core assignment information 502. The usage model and core assignment list 501 includes the control model 102 to be used and core assignment information 502 for the control models A 102-A to G 102-G.

Note that the core assignment information is information on the processor core of the controlled ECU that executes the program generated by the software development support device 301.

FIG. 6 is a diagram showing an example of a calculation execution order list 600 for each calculation cycle generated by the feature model analysis unit 306. The feature model analysis unit 306 analyzes the control cycle and execution order of each of the control models 102 extracted from the feature model 101, and generates an operation execution order list 600.

The calculation execution order list 600 includes, for example, a list 601 of control models 102 to be executed in a calculation cycle of 10ms, a list 602 of control models 102 to be executed in a calculation cycle of 20ms, and a list 602 of control models 102 to be executed in a calculation cycle of 100ms. A list 603 is included. In each list 601 to 603, the control models 102 are listed in the order of execution of calculations.

FIG. 7 is a diagram showing an example of variable connection processing definition 701 for each calculation cycle of the feature model analysis unit 306.

The variable connection process definition 701 for each calculation cycle includes the source code of the process executed by the control model 102 that uses the same variable in different calculation cycles.

FIG. 8 is a diagram illustrating an example of notation between control models 102 that use the same variables in different calculation cycles.

In the illustrated example, calculations are performed in 20ms from control model A (102-A), which performs calculations at a cycle of 10ms, to control model B (102-B), which also performs calculations at a cycle of 10ms. An example is shown in which variable information is passed to control model E (102-E).

The feature model does not include a process for passing variable information to the control model 102 with the same calculation cycle, but when passing variable information in a different calculation cycle, a block representing the connection process 804 is inserted between the control models 102. Ru. Therefore, the connection process 804 block can be searched for locations where variable information is passed in different calculation cycles.

FIG. 9 is a block diagram showing an example of the configuration of the connection processing addition unit 308. By applying the calculation execution order list 600 extracted by the feature model analysis unit 306 and the variable connection processing definition 701 to the collected model source list 901 collected by the model source collection unit 307 shown in FIG. 3A, the feature model 101 is A model source 1101 with connection processing added that matches the behavior of the model source is generated.

Specifically, the connection processing addition unit 308 acquires information on the file name of the model source and the calculation cycle of the model source from the collected model source list 901. Next, the MAKE file generation unit 904 uses the information on the file name of the model source to generate a MAKE file that defines a source file to be compiled.

The function execution order definition file generation unit 905 generates a function execution order definition file for each calculation cycle based on the calculation cycle information of the model source and the calculation execution order list 600 for each calculation cycle (see FIG. 10).

Further, the variable information transfer process definition file generation unit 906 generates a variable information transfer process definition file based on the variable connection process definition 701. Then, the connection processing application unit 907 adds the MAKE file generated in the above processing, the function execution order definition file, and the variable information passing processing definition file to the collected model source list 901, and adds the connection processing added model source 1101. and save it in the folder where the model source is stored.

FIG. 10 is a diagram illustrating an example of an operation execution order definition 1001 for each operation cycle of the connection processing addition unit 308.

The calculation execution order definition 1001 for each calculation cycle is written in source code that defines the execution order of the control model 102 for each calculation cycle.

FIG. 11 is a block diagram showing an example of the configuration of the parallel processing generation unit 309. The parallel processing generation unit 309 generates a control model for each core of the processor of the ECU to be controlled based on the information in the used processor information storage unit 1102 for the connection processing added model source 1101 output from the connection processing addition unit 308. 102 processes are assigned.

The used processor information storage unit 1102 stores the number of cores of the processor used in the electronic board (control target ECU) to which the software is written, the processing capacity of each core, and the address of each core at the time of inputting the feature model 101 or in advance. Allocation information is input as processor information 310. Further, the number of cores to be set is not limited to two cores, and may be set to a single core or a number of cores greater than two.

The parallel processing application unit 1103 allocates cores for each control model 102 based on the usage model and core allocation list 501 generated by the feature model analysis unit 306, the operation execution order definition 1001, and the information in the usage processor information storage unit 1102. Information 502 is given. Specifically, based on address assignment information determined for each microcomputer, the processing assigned to each core is defined in the address area of the corresponding core.

FIG. 12 shows an example in which parallel processing is assigned to a two-core processor. The illustrated example shows an example in which a program generated by the software development support device 301 is executed by the ECU 50 to be controlled.

The controlled ECU 50 includes a dual-core processor 51, a RAM (Random Access Memory) 52, a ROM (Read Only Memory) 53, and an interface (not shown).

The program generated by the software development support device 301 is written to the ROM 53, loaded to the RAM 52, and then executed by the first core 52-1 or the second core 52-2 of the processor 51.

The first core 52-1 is assigned the processing of control model A (102-A), control model B (102-B) and control model C (102-C), and the second core 52-2 is assigned the processing of control model A (102-A), control model B (102-B), and control model C (102-C). , control model E (102-E), and control model F (102-F).

In this way, the software development support device 301 divides and allocates processing to the first core 52-1 and the second core 52-2 in units of control models 102. By using the software development support device 301 of this embodiment, it is possible to automatically generate parallel processing that reflects the dependency relationship of the calculation processing expressed by the feature model 101.

The preferred embodiments of the present disclosure have been described above.

In this manner, in this embodiment, a program that satisfies the control specifications can be generated from the feature model 101 input to the software development support device 301. Furthermore, it is also possible to generate processing for multi-core processors.

This embodiment may be executed using one computer, or may be executed using different computers for each process. Alternatively, software development may be performed by transmitting and receiving the results of each step between multiple computers linked via a network such as the Internet.

<Conclusion>
As described above, the software development support device 301 of the above embodiment can have the following configuration.

(1) A software development support device (301) having a first processor (11) and a memory, which receives a feature model (101) that describes software control specifications including the execution order of a control model (102). Then, the control model (102) constituting the feature model (101) is analyzed, and the calculation cycle of the control model (102) and the execution order of the control model (102) are analyzed to obtain execution order information ( A feature model analysis unit (306) that outputs a calculation execution order list 600) receives the control model (102) and specifies a file name including the calculation cycle of the control model (102). a model source generation unit (304) that generates an identical model source, tests whether the generated model source matches the specifications of the control model (102), and then stores it in a model source storage unit; A model source collection unit (307) that collects a model source having the same name as the control model (102) analyzed from the feature model (101) from the model source storage unit (305), and a plurality of cores (first core 52- 1, a second processor (51) having a second core 52-2) and executing the software, and executes the software on the plurality of cores (51) with respect to the collected model sources. ); a parallel processing generation unit (309) that generates processing allocation information for each core based on the calculation cycle and execution order information (600) in order to optimize the processing of Support equipment.

With the above configuration, the software development support device 301 can develop software optimized for a processor including multiple cores.

(2) In the software development support device (301) according to (1) above, the feature model analysis unit (306) extracts variable information used by the control model (102) and analyzes the feature model. A connection process that acquires execution order information (600), calculation cycle, and variable information of the control model (102) from the unit (306), and adds a connection process of variables with different calculation cycles between the control models (102). an adding unit (308); a compiling unit (311) that compiles the model source to which the processing results of the connection processing addition unit (308) and the parallel processing generation unit (309) are applied; A software development support device further comprising: a program output unit (312) for outputting a program.

With the above configuration, the software development support device 301 can automatically collect source code, set the execution order of calculations, set connection information, compile, and allocate processing to each core, thereby reducing the man-hours of design work. can be achieved.

(3) In the software development support device (301) according to (2) above, the connection processing addition unit (308) uses the same variable at different calculation cycles between the control models (102). A software development support device characterized in that when a control model (102) is detected, a source code for the variable connection process is generated.

With the above configuration, the software development support apparatus 301 can automatically add connection processing for passing variables between control models 102 that use the same variables in different calculation cycles.

(4) In the software development support device according to (2) above, the connection processing addition unit (308) stores the execution order information and calculation cycle analyzed by the feature model analysis unit (306), and the connection process addition unit (308). Based on the variable connection process searched by the process addition unit (308) and the model source collected by the model source collection unit (307), an execution order definition file for each calculation cycle and variable information for each calculation cycle are created. A software development support device characterized by generating a transfer processing definition file and a MAKE file used during compilation and adding them to the collected model sources.

With the above configuration, the software development support device 301 can automatically collect source code, set the execution order of calculations, set connection information, compile, and allocate processing to each core, thereby reducing the man-hours of design work. can be achieved.

Note that the present invention is not limited to the above-described embodiments, and includes various modifications. For example, the embodiments described above are described in detail to explain the present invention in an easy-to-understand manner, and the present invention is not necessarily limited to having all the configurations described. Furthermore, it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, addition, deletion, or replacement of other configurations to some of the configurations of each embodiment may be applied singly or in combination.

Further, each of the above-mentioned configurations, functions, processing units, processing means, etc. may be partially or entirely realized in hardware by designing, for example, an integrated circuit. Moreover, each of the above-mentioned configurations, functions, etc. may be realized by software by a processor interpreting and executing a program that realizes each function. Information such as programs, tables, files, etc. that implement each function can be stored in a memory, a recording device such as a hard disk, an SSD (Solid State Drive), or a recording medium such as an IC card, an SD card, or a DVD.

Further, the control lines and information lines are shown to be necessary for explanation purposes, and not all control lines and information lines are necessarily shown in the product. In reality, almost all components may be considered to be interconnected.

101 Feature models 102-A to 102-G Control model 301 Software development support device 304 Model source generation unit 305 Model source storage unit 306 Feature model analysis unit 307 Model source collection unit 308 Connection processing addition unit 309 Parallel processing generation unit 310 Processor information Input section 311 Compilation section 312 Program output section 501 Usage model and core assignment list 502 Core assignment information 600 Operation execution order list 701 Variable connection processing definition 901 Collection model source list 904 MAKE file generation section 905 Function execution order definition file generation section 906 Variables Information delivery processing definition file generation section 907 Connection processing application section 1102 Processor information storage section 1103 Parallelization processing application section

Claims (8)

A software development support device having a first processor and a memory,
A feature model that describes the control specifications of the software including the execution order of the control model is received, the control models that make up the feature model are analyzed, and the calculation cycle of the control model and the execution order of the control model are determined. a feature model analysis unit that analyzes and outputs it as execution order information;
Accepting the control model, generating a model source that includes the calculation cycle of the control model and having the same file name as the control model, and checking whether the generated model source matches the specifications of the control model. a model source generation unit that stores the model source in the model source storage unit after testing;
a model source collection unit that collects a model source having the same name as the control model analyzed from the feature model from the model source storage unit;
receiving information about a second processor having a plurality of cores and executing the software, and calculating the calculation cycle for optimizing the software for processing of the plurality of cores with respect to the collected model sources; and a parallel processing generation unit that generates processing allocation information for each core based on the execution order information;
A software development support device characterized by having: The software development support device according to claim 1,
The feature model analysis unit extracts variable information used by the control model,
a connection process addition unit that acquires execution order information, calculation cycle, and variable information of the control model from the feature model analysis unit, and adds connection processing of variables with different calculation cycles between the control models;
a compiling unit that compiles the model source to which the processing results of the connection processing addition unit and the parallel processing generation unit are applied;
a program output unit that outputs the compiled program;
A software development support device further comprising: The software development support device according to claim 2,
The connection processing addition unit includes:
A software development support device characterized in that when a control model using the same variable in different calculation cycles is detected between the control models, a source code for the variable connection process is generated. The software development support device according to claim 2,
The connection processing addition unit performs execution order information and calculation cycles analyzed by the feature model analysis unit, connection processing of variables added by the connection processing addition unit, and model sources collected by the model source collection unit. Based on this, an execution order definition file for each calculation cycle, a variable information passing process definition file for each calculation cycle, and a MAKE file used during compilation are generated and added to the collected model sources. Features of software development support equipment. A software development support method for supporting software development on a computer having a first processor and a memory, the method comprising:
The computer receives a feature model that describes the control specifications of the software including the execution order of the control model, analyzes the control models that make up the feature model, and determines the calculation cycle of the control model and the control model. a feature model analysis step for analyzing the execution order of and outputting it as execution order information;
The computer receives the control model, generates a model source that includes the calculation cycle of the control model and has the same file name as the control model, and specifies that the generated model source matches the specifications of the control model. a model source generation step in which the model source is stored in the model source storage unit after testing whether the
a model source collection step in which the computer collects a model source having the same name as the control model analyzed from the feature model from the model source storage unit;
The computer receives information about a second processor that has a plurality of cores and executes the software, and optimizes the software for processing of the plurality of cores with respect to the collected model sources. a parallel processing generation step of generating processing allocation information for each core based on the calculation cycle and execution order information;
A software development support method characterized by comprising: The software development support method according to claim 5,
The feature model analysis step extracts variable information used by the control model,
a connection process addition step in which the computer acquires execution order information, calculation period, and variable information of the control model, and adds connection processing of variables having different calculation periods between the control models;
a compiling step in which the computer compiles the model source to which the processing results of the connection processing addition step and the parallel processing generation step are applied;
a program output step in which the computer outputs the compiled program;
A software development support method further comprising: 7. The software development support method according to claim 6,
The connection processing addition step is
A software development support method comprising: generating a source code for the variable connection process when a control model using the same variable in different calculation cycles is detected between the control models. 7. The software development support method according to claim 6,
The connection processing addition step includes the execution order information and calculation cycle analyzed in the feature model analysis step, the connection processing of the variables added in the connection processing addition step, and the model source collected in the model source collection step. Based on this, an execution order definition file for each calculation cycle, a variable information passing process definition file for each calculation cycle, and a MAKE file used during compilation are generated and added to the collected model sources. Characteristic software development support method.

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