JP2022011264A - Software development support device and software development support method - Google Patents

Abstract

To generate a program from control specifications defined by a feature model and deals with a processor including a plurality of cores.SOLUTION: A software development support device having a first processor comprises: a feature model analysis section that inputs a feature model including execution order of a control model and including control specifications of software, analyzes the control model in the feature model, analyzes an arithmetic period and the execution order, and outputs execution order information; a model source generation section that inputs the control model and generates a model source which includes the arithmetic period and of which filename is the same as the control model's filename; a model source collection section that collects the model source of which name is the same as the control model's name; and a parallel processing generation section that inputs information on a second processor having a plurality of cores and generates allocation information of processing for each core on the basis of the arithmetic period and the execution order information to optimize the software to processing of the plurality of cores with respect to the collected model source.SELECTED DRAWING: Figure 3A

Description

The present invention relates to a software development support device and a software development support method for developing control software in model-based development for controlling a device.

In software development of an embedded system, which is a computer system embedded in a machine or device to realize a specific function, the device is controlled in real time by executing a control program that implements a process for controlling the device.

In recent years, in the development of control software, instead of describing the source code of the control software, the developer may describe it by a "(control) model" that can be generated more easily and has good visibility. This development method is called model-based development.

As a program development environment corresponding to model-based development, for example, there is MATLAB (registered trademark) of MathWorks (registered trademark). The developer describes the model using Simulink, which is a function of MATLAB (registered trademark). The model is described by a functional unit called a block and a connection showing an input / output relationship between the functional units.

A model that describes the functions implemented by the control software using Simulink® is called a control model. Based on this control model, for example, using TargetLink (registered trademark) of dSpace (registered trademark), the process of adding information such as data type and bit rate necessary for generating source code is called scaling. The source code generated based on the control model is called a model source.

As a known example, Patent Document 1 discloses a technique of scaling a control model to automate the generation of source code.

Further, in software development, it is known as an effective method to carry out diversion development in which software parts are collected and reused, rather than generating software from scratch to generate a program.

As a known example, Patent Document 2 discloses a system in which software components to which category information is added are prepared, software components satisfying development requirements can be searched for, and source code can be diverted and developed.

Japanese Unexamined Patent Publication No. 2017-016416 Japanese Unexamined Patent Publication No. 2008-040969

However, the control model does not express the specifications of the entire program, and the control specifications of the entire program are composed of multiple control models and represent the characteristics of all the control specifications of the information between the control models (hereinafter referred to as the feature model). ).

In the technique of Patent Document 1, although the model source of the control model can be generated, the program satisfying the specifications of the feature model cannot be generated.

Since the feature model is composed of a large number of control models, if code generation is performed from the control model each time a program satisfying the specifications of the feature model is generated, it takes as many generation times as the number of control models to be used.

Although the technology described in Patent Document 2 makes it easy to search for software parts, it does not manage each source code, but manages a part of the source code as parts by category, so it depends on the classification and processing. It is necessary for the designer himself to find the appropriate part and then generate the source code.

Therefore, in order to generate an execution program, the work of analyzing the dependency between control models from the feature model and defining the execution order, and the passing to ensure the consistency of variables when the same variable is used in different calculation cycles. It is necessary to define the processing (buffering processing) and the compilation execution information (MAKE file) that defines the files to be compiled and the settings, but Patent Documents 1 and 2 above take the above three points into consideration. Not.

Furthermore, for example, in the development of embedded software for an electronic control unit for automobiles (Electronic Control Unit, hereinafter referred to as ECU), a microcomputer including multiple cores is used as a countermeasure against an increase in heat generation and power consumption due to performance improvement of a microcomputer (hereinafter referred to as a microcomputer). With the advent, it is required that the software be structured so that it can support multiple cores.

In view of the above problems, the present invention can generate a program from the control specifications defined in the feature model and manage the parts in the model source unit without adding the category information to the model source. The purpose is to provide a software development support device that can support processors including multiple cores.

The present invention is a software development support device having a first processor and a memory, and accepts a feature model that describes software control specifications including an execution order of the control model, and controls constituting the feature model. Includes a feature model analysis unit that analyzes the model, analyzes the calculation cycle of the control model, analyzes the execution order of the control model, and outputs it as execution order information, and accepts the control model and includes the calculation cycle of the control model. Generates a model source whose file name is the same as that of the control model, tests whether the generated model source matches the specifications of the control model, and then stores it in the model source storage unit. Information on a model source collector that collects a model source with the same name as the control model analyzed from the feature model from the model source storage and a second processor that has a plurality of cores and executes the software. Processing allocation information for each core based on the calculation cycle and execution order information in order to optimize the software for the processing of the plurality of cores for the collected model source by receiving the input processor information. It has a parallel processing generation unit and a parallel processing generation unit.

According to the present invention, it is possible to develop software optimized for a processor including a plurality of cores. In addition, since it is possible to automatically perform the collection of source code, the setting of the execution order of operations, the setting of connection information, the compilation, and the allocation of processing for each core, the man-hours for design work can be reduced.

Further, the present invention is not limited to the embodiment, and various applications can be applied to embedded control devices other than the ECU and software development methods based on model information as long as they do not deviate from the scope of the present invention. Therefore, it is possible to automatically output a program that satisfies the control specifications expressed by the feature model based on the feature model.

Details of at least one practice of the subject matter disclosed herein are set forth in the accompanying drawings and in the description below. Other features, embodiments, and effects of the disclosed subject matter are manifested in the following disclosures, drawings, and claims.

An embodiment of the present invention is shown, and is a relationship diagram between a control model and a feature model. It is a figure which shows the Example of this invention and shows an example of a control model. It is a block diagram which shows the Example of this invention and shows an example of the function of the software development support apparatus. It is a block diagram which shows the Example of this invention and shows an example of the structure of the software development support apparatus. It is a flowchart which shows the Example of this invention and shows an example of the process performed by the software development support apparatus. An embodiment of the present invention is shown, and it is a figure of the use model identification process performed in the feature model analysis unit. An embodiment of the present invention is shown, and is an example of a calculation execution order list for each calculation cycle of the feature model analysis unit. It is a figure which shows the Example of this invention and shows an example of the definition of the variable connection process for every operation cycle of a feature model analysis part. An embodiment of the present invention is shown, and it is a figure of a control model which uses the same variable in different operation cycles. An embodiment of the present invention is shown, and it is a block diagram of the connection processing addition part of a software development support apparatus. It is a figure which shows the Example of this invention and shows an example of the operation execution order definition for every operation cycle of the connection processing addition part. An embodiment of the present invention is shown, and it is a block diagram of the parallel processing generation part of the software development support apparatus. It is a figure which shows the Example of this invention and shows the example which assigned the parallel processing to two processor cores.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing the relationship between the control model A102-A to the control model G102-G and the feature model 101. The feature model 101 is composed of a plurality of control models A102-A2 to G102-G, and the execution order of each control model is determined by the calculation of common variables and the reference timing. The feature model 101 describes the control specifications of the entire software to be generated and the processing order of the control model.

In the following description, when the control models A to G are not individually specified, the reference numeral “control model 102” with the “−” and the like omitted is used. The same applies to the symbols of other components.

The output of the control model A102-A is input to the control model B102-B and the control model E102-E. The control model B102-B performs a predetermined process on the output of the control model A102-A and outputs the output to the control model C102-C. The control model D102-D performs a predetermined process on the output of the control model C102-C and outputs the output to the control model G102-G.

The control model E102-E performs a predetermined process on the output of the control model A102-A and outputs the output to the control model F102-F. The control model F102-F performs a predetermined process on the output of the control model E102-E and outputs the output to the control model G102-G. The control model G102-G outputs the result of performing predetermined processing on the outputs of the control model D102-D and the control model F102-F.

The control model 102 of this embodiment can use a model used in well-known model-based development, and is composed of a block diagram or the like that describes the arithmetic processing of the control unit.

FIG. 2 is a diagram showing an example of internal processing of the control model 102. Inside the control model 102, as shown in the figure, one or more processes A (211) to C (213) are performed on one or more input values X (201), and one or more output values ( In this embodiment, Y and Z) 202 and 203 are calculated. Further, the output values Y and Z (202, 203) also include information for designating the calculation core when the calculation is performed by the multi-core processor.

FIG. 3A is a block diagram showing an example of the function of the software development support device 301.

The software development support device 301 requires the information of the control model 102 and the feature model 303 as input. The model source generation unit 304 generates a source code written in C language by using an autocoding function such as TargetLink (registered trademark) for the input control model 102.

The source code output based on this control model 102 is called a model source. At this time, the control model 102 and the generated model source have the same file name excluding the extension, and the model source contains information on the calculation cycle to be executed.

In the model source generation unit 304 of this embodiment, the model source output from the control model 102 is from one control model to one model source, but one operation performed in the control model 102 is used as one model source. It may be output.

The model source generation unit 304 verifies the equivalence between the generated source code and the input control model 102, and performs a unit test to see if the input / output values of the variables for the model source are as specified.

When the content of the control model 102 is changed due to a diversion change or the like, the file with the same name is prevented from being duplicated by changing the name by adding a number of the number of updates to the end of the file name for each update.

The model source generated by the model source generation unit 304 is stored in the model source storage unit 305, and all the control models 102 used in the feature model 101 are stored in the model source storage unit 305 in advance. The feature model analysis unit 306 analyzes the input feature model 101. (Detailed processing will be described later.)

The model source collection unit 307 collects model sources generated from the same control model 102 based on the control model information specified by the feature model analysis unit 306 from the model source storage unit 305, and collects the model source list 901 (see FIG. 9). ) Is generated.

Since each model source collected by the model source collection unit 307 has been unit tested, it is not necessary to newly perform a confirmation work such as a test on the collected model source.

For the model source collected by the model source collection unit 307, the connection processing addition unit 308 defines the connection information between the control models 102 (detailed processing will be described later).

The parallel processing generation unit 309 adds processing for a multi-core processor (detailed processing will be described later). In the parallel processing generation unit 309, the feature model analysis unit 306, the connection processing addition unit 308, the information on the number of cores of the processor of the controlled target ECU input in the processor information 310, the processing capacity, and the address allocation information for each core. Generate parallel processing based on and apply it to the model source.

Since the model source to which parallel processing is applied satisfies the information required for compilation, compilation can be performed by the compilation unit 311. The compilation unit 311 converts the model source into an executable file that can be processed on the processor based on the added connection processing. The file (program) compiled by the compilation unit 311 is output from the program output unit 312.

FIG. 3B is a block diagram showing an example of the configuration of the software development support device 301. The software development support device 301 is a computer including a processor 11, a memory 12, a storage device 13, an input / output device 14, and a network device 15.

The input / output device 14 includes an input device such as a keyboard, a mouse, or a touch panel, and an output device such as a display. The network device 15 can be connected to the network 16 and communicate with other devices.

The memory 12 includes a model source generation unit 304, a feature model analysis unit 306, a model source collection unit 307, a connection processing addition unit 308, a parallel processing generation unit 309, a compilation unit 311 and a program output unit 312. It is loaded as a program and executed by the processor 11. Further, the memory 12 stores the model source storage unit 305 as data used by each program.

The processor 11 operates as a functional unit that provides a predetermined function by executing a process according to a program of each functional unit. For example, the processor 11 functions as the model source generation unit 304 by executing the process according to the model source generation program. The same applies to other programs. Further, the processor 11 also operates as a functional unit that provides each function of a plurality of processes executed by each program. A computer and a computer system are devices and systems including these functional parts.

An example of the processing performed by the software development support device 301 is shown in the flowchart of FIG. The feature model analysis unit 306 of the software development support device 301 identifies the control model 102 used in the feature model 303 and generates a list of the control model 102 (401). This process will be described later in FIG.

Next, the feature model analysis unit 306 extracts the allocation information of the core that performs the processing of the control model 102 (402). The core allocation information can be extracted from the control model 102, for example. Then, the feature model analysis unit 306 analyzes the calculation cycle and the calculation order of each control model 102 to generate a calculation execution order list (403). This process will be described in detail in FIG.

Further, the model source generation unit 304 inputs a control model, generates a model source, and stores it in the model source storage unit 305. The model source collection unit 307 collects the model sources corresponding to the calculation execution order list and outputs them to the connection processing addition unit 308.

After that, the connection processing addition unit 308 searches for the control model 102 using the same variable in different calculation cycles (404). As a result of the search, the connection processing addition unit 308 generates the source code of the variable connection processing when the control model 102 that uses the same variable in different calculation cycles exists (405).

The parallel processing generation unit 309 allocates the generated source code for each calculation cycle of the connection destination (406). This process will be described later in FIG. Then, the connection processing addition unit 308 determines whether or not there is a variable connection processing for which the processing has not been completed (407), and repeats the processing of steps 404 to 406 until all the variable connection processing is completed. Execute.

Through the above processing, the software development support device 301 can automatically add a variable connection processing for passing variables between control models 102 using the same variable in different calculation cycles.

FIG. 5 is a diagram showing an example of the use model specifying process of the feature model analysis unit 306. The feature model analysis unit 306 analyzes the calculation order of the control model 102 included in the input feature model 101, and assigns the core allocation information 502-1 and 502-2 preset for each control model 102.

The feature model analysis unit 306 generates a usage model and a core allocation list 501 including the control model 102 to be used and the core allocation information 502. The used model and the core allocation list 501 include the control model 102 to be used and the core allocation information 502 of the control models A102-A to the control model G102-G.

The core allocation information is information on the processor core of the controlled object ECU that executes the program generated by the software development support device 301.

FIG. 6 is a diagram showing an example of a calculation execution order list 600 for each calculation cycle generated by the feature model analysis unit 306. The feature model analysis unit 306 analyzes the control cycle and the execution order for each of the control models 102 extracted from the feature model 101, and generates an operation execution order list 600.

The calculation execution order list 600 is, for example, a list 601 of the control model 102 executed in a calculation cycle of 10 ms, a list 602 of the control model 102 executed in a calculation cycle of 20 ms, and a control model 102 executed in a calculation cycle of 100 ms. Listing 603 is included. In each list 601 to 603, the control model 102 is listed in the execution order of the operation.

FIG. 7 is a diagram showing an example of the variable connection processing definition 701 for each calculation cycle of the feature model analysis unit 306.

The variable connection process definition 701 for each operation cycle includes the source code of the process to be executed by the control model 102 that uses the same variable in different operation cycles.

FIG. 8 is a diagram showing an example of notation between control models 102 using the same variable in different calculation cycles.

In the illustrated example, the calculation is performed in 20 ms from the control model A (102-A) in which the calculation is performed in a cycle of 10 ms to the control model B (102-B) in which the calculation is also performed in a cycle of 10 ms. An example is shown in which variable information is passed to the control model E (102-E).

In the feature model, there is no process of passing variable information to the control model 102 of the same calculation cycle, but when passing variable information in different calculation cycles, a block representing the connection process 804 is inserted between the control model 102. To. Therefore, the block of the connection process 804 may be searched for the place where the variable information is passed to different calculation cycles.

FIG. 9 is a block diagram showing an example of the configuration of the connection processing addition unit 308. By applying the operation execution order list 600 extracted by the feature model analysis unit 306 and the variable connection processing definition 701 to the collection model source list 901 collected by the model source collection unit 307 shown in FIG. 3A, the feature model 101 Generates the connection process added model source 1101 that matches the behavior of the model source with.

Specifically, the connection processing addition unit 308 acquires the file name of the model source and the information of the calculation cycle of the model source from the collection model source list 901. Next, the MAKE file generation unit 904 generates a MAKE file that defines a target source file at the time of compilation by using the information of the file name of the model source.

The function execution order definition file generation unit 905 generates a function execution order definition file for each calculation cycle based on the information of the calculation cycle of the model source and the calculation execution order list 600 for each calculation cycle (see FIG. 10).

Further, the variable information passing process definition file generation unit 906 generates a variable information passing process definition file based on the variable connection process definition 701. Then, the connection process application unit 907 adds the MAKE file, the function execution order definition file, and the variable information transfer process definition file generated in the above process to the collection model source list 901, and the connection process added model source 1101. And save it in the folder where the model source is stored.

FIG. 10 is a diagram showing an example of a calculation execution order definition 1001 for each calculation cycle of the connection processing addition unit 308.

The operation execution order definition 1001 for each operation cycle is described by a source code that defines the execution order of the control model 102 for each operation cycle.

FIG. 11 is a block diagram showing an example of the configuration of the parallel processing generation unit 309. The parallel processing generation unit 309 controls the connection processing addition model source 1101 output from the connection processing addition unit 308 for each core of the processor of the controlled ECU based on the information of the processor information storage unit 1102 used. Allocate 102 processes.

The processor information storage unit 1102 used is the number of cores of the processor used in the electronic board (controlled ECU) to which the software is written at the time of input of the feature model 101, the processing capacity of each core, and the address of each core. The allocation information is input as the processor information 310. Further, the number of cores to be set is not limited to two cores, and it is possible to set a single core or a number of cores larger than two.

In the parallel processing application unit 1103, the core allocation for each control model 102 is based on the information of the usage model and core allocation list 501 generated by the feature model analysis unit 306, the calculation execution order definition 1001, and the usage processor information storage unit 1102. Information 502 is added. Specifically, the process assigned to each core is defined in the address area of the corresponding core based on the address allocation information defined for each microcomputer.

FIG. 12 shows an example in which parallel processing is assigned to a two-core processor. The illustrated example shows an example in which the program generated by the software development support device 301 is executed by the controlled object ECU 50.

The controlled ECU 50 has a dual-core processor 51, a RAM (Random access memory) 52, a ROM (Read Only memory) 53, and an interface (not shown).

The program generated by the software development support device 301 is written to the ROM 53, loaded into the RAM 52, and then executed by the first core 52-1 or the second core 52-2 of the processor 51.

The first core 52-1 is assigned the processing of the control model A (102-A), the control model B (102-B), and the control model C (102-C), and the second core 52-2 is assigned. , Control model E (102-E) and control model F (102-F) are assigned.

In this way, the software development support device 301 divides the processing into the first core 52-1 and the second core 52-2 in units of the control model 102 and allocates them. By using the software development support device 301 of this embodiment, it is possible to automatically generate a parallelization process that reflects the dependency of the arithmetic process expressed by the feature model 101.

The preferred embodiments of the present disclosure have been described above.

In this way, in this embodiment, it is possible to generate a program satisfying the control specifications from the feature model 101 input to the software development support device 301. Furthermore, it is possible to generate processing for a multi-core processor.

This embodiment may be executed using one computer, or may be executed using a different computer for each process. Alternatively, software development may be carried out by transmitting and receiving the results of each process between a plurality of computers linked by a network such as the Internet.

<Conclusion>
As described above, the software development support device 301 of the above embodiment can be configured as follows.

(1) A software development support device (301) having a first processor (11) and a memory, and accepts a feature model (101) that describes software control specifications including the execution order of the control model (102). Then, the control model (102) constituting the feature model (101) is analyzed, the calculation cycle of the control model (102) and the execution order of the control model (102) are analyzed, and the execution order information (execution order information ( The feature model analysis unit (306) that outputs as the calculation execution order list 600) and the control model (102) are received, and the file name includes the calculation cycle of the control model (102) and the file name is the control model (102). A model source generation unit (304) that generates the same model source, tests whether the generated model source matches the specifications of the control model (102), and then stores the model source in the model source storage unit, and the above. A model source collecting unit (307) that collects a model source having the same name as the control model (102) analyzed from the feature model (101) from the model source storage unit (305), and a plurality of cores (first core 52-). 1. The software is applied to the plurality of cores (51) with respect to the collected model source by receiving the information of the second processor (51) having the second core 52-2) and executing the software. ), A software development characterized by having a parallel processing generation unit (309) that generates processing allocation information for each core based on the calculation cycle and execution order information (600) in order to optimize the processing. Support device.

With the above configuration, the software development support device 301 can develop software optimized for a processor including a plurality of cores.

(2) In the software development support device (301) according to the above (1), the feature model analysis unit (306) extracts variable information used by the control model (102) and analyzes the feature model. Connection processing that acquires execution order information (600), calculation cycle, and variable information of the control model (102) from the unit (306), and adds connection processing of variables having different calculation cycles between the control models (102). An additional unit (308), a compile unit (311) that compiles the model source to which the processing results of the connection processing additional unit (308) and the parallel processing generation unit (309) are applied, and the compiled program. A software development support device further comprising a program output unit (312) for output.

With the above configuration, the software development support device 301 can automatically perform the collection of source code, the setting of the execution order of operations, the setting of connection information, the compilation, and the allocation of processing for each core, thus reducing the man-hours for design work. Can be planned.

(3) In the software development support device (301) according to the above (2), the connection processing addition unit (308) uses the same variable in different calculation cycles between the control models (102). A software development support device characterized in that a source code for connection processing of the variable is generated when an existing control model (102) is detected.

With the above configuration, the software development support device 301 can automatically add a connection process for passing variables between control models 102 that use the same variables in different calculation cycles.

(4) In the software development support device according to (2) above, the connection processing addition unit (308) has the execution order information and the calculation cycle analyzed by the feature model analysis unit (306), and the connection. Based on the connection processing of the variables searched by the processing addition unit (308) and the model source collected by the model source collection unit (307), the execution order definition file for each operation cycle and the variable information for each operation cycle. A software development support device characterized in that a transfer process definition file and a MAKE file used at compile time are generated and added to the collected model source.

With the above configuration, the software development support device 301 can automatically perform the collection of source code, the setting of the execution order of operations, the setting of connection information, the compilation, and the allocation of processing for each core, thus reducing the man-hours for design work. Can be planned.

The present invention is not limited to the above-described embodiment, and includes various modifications. For example, the above-described embodiment is described in detail in order to explain the present invention in an easy-to-understand manner, and is not necessarily limited to the one including all the configurations described. Further, it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. Further, for a part of the configuration of each embodiment, any of addition, deletion, or replacement of other configurations can be applied alone or in combination.

Further, each of the above configurations, functions, processing units, processing means and the like may be realized by hardware by designing a part or all of them by, for example, an integrated circuit. Further, each of the above configurations and functions may be realized by software by the processor interpreting and executing a program that realizes each function. Information such as programs, tables, and files that realize each function can be placed in a memory, a hard disk, a recording device such as an SSD (Solid State Drive), or a recording medium such as an IC card, an SD card, or a DVD.

In addition, the control lines and information lines indicate those that are considered necessary for explanation, and do not necessarily indicate all the control lines and information lines in the product. In practice, it can be considered that almost all configurations are interconnected.

101 Feature model 102-A to 102-G Control model 301 Software development support device 304 Model source generation unit 305 Model source storage unit 306 Feature model analysis unit 307 Model source collection unit 308 Connection processing addition unit 309 Parallel processing generation unit 310 Processor information Input unit 311 Compile unit 312 Program output unit 501 Used model and core allocation list 502 Core allocation information 600 Operation execution order list 701 Variable connection processing definition 901 Collection model source list 904 MAKE file generation unit 905 Function execution order definition file generation unit 906 Variable Information transfer processing definition file generation unit 907 Connection processing application unit 1102 Used processor Information storage unit 1103 Parallelization processing application unit

Claims (8)

A software development support device with a first processor and memory,
It accepts a feature model that describes software control specifications, including the execution order of the control model, analyzes the control model that constitutes the feature model, and determines the calculation cycle of the control model and the execution order of the control model. A feature model analysis unit that analyzes and outputs as execution order information,
The control model is accepted, a model source having the same file name as the control model including the calculation cycle of the control model is generated, and whether the generated model source matches the specifications of the control model. A model source generator that is stored in the model source storage after testing, and a model source generator
A model source collecting unit that collects a model source having the same name as the control model analyzed from the feature model from the model source storage unit, and a model source collecting unit.
The calculation cycle for optimizing the software for processing of the plurality of cores with respect to the collected model source by receiving the information of the second processor having the plurality of cores and executing the software. And a parallel processing generator that generates processing allocation information for each core based on execution order information,
A software development support device characterized by having. The software development support device according to claim 1.
The feature model analysis unit extracts variable information used by the control model and obtains it.
A connection processing addition unit that acquires execution order information, calculation cycle, and variable information of the control model from the feature model analysis unit and adds connection processing for variables having different calculation cycles between the control models.
A compiling unit that compiles the model source to which the processing results of the connection processing addition unit and the parallel processing generation unit are applied.
The program output section that outputs the compiled program and
A software development support device characterized by having more. The software development support device according to claim 2.
The connection processing addition part is
A software development support device characterized in that a source code for connection processing of the variables is generated when a control model using the same variable is detected in different calculation cycles between the control models. The software development support device according to claim 2.
The connection processing addition unit includes the execution order information and the calculation cycle analyzed by the feature model analysis unit, the connection processing of the variables added by the connection processing addition unit, and the model source collected by the model source collection unit. Based on, the execution order definition file for each calculation cycle, the variable information transfer processing definition file for each calculation cycle, and the MAKE file used at compile time are generated and added to the collected model source. Characterized software development support device. It is a software development support method that supports software development with a computer having a first processor and memory.
The computer accepts a feature model that describes software control specifications including the execution order of the control model, analyzes the control model that constitutes the feature model, and analyzes the calculation cycle of the control model and the control model. Feature model analysis step that analyzes the execution order of and outputs it as execution order information,
The computer accepts the control model, generates a model source having the same file name as the control model including the calculation cycle of the control model, and the generated model source is one with the specifications of the control model. A model source generation step to store in the model source storage after testing whether it is done,
A model source collection step in which the computer collects a model source having the same name as the control model analyzed from the feature model from the model source storage unit.
In order for the computer to receive information from a second processor having a plurality of cores and executing the software, and optimizing the software for processing of the plurality of cores for the collected model source. A parallel processing generation step that generates processing allocation information for each core based on the calculation cycle and execution order information,
A software development support method characterized by including. The software development support method according to claim 5.
In the feature model analysis step, the variable information used by the control model is extracted.
A connection processing addition step in which the computer acquires execution order information, calculation cycle, and variable information of the control model and adds connection processing of variables having different calculation cycles between the control models.
A compile step in which the computer compiles the model source to which the processing results of the connection processing addition step and the parallel processing generation step are applied.
A program output step in which the calculator outputs the compiled program,
A software development support method characterized by further including. The software development support method according to claim 6.
The connection processing addition step is
A software development support method comprising generating a source code for connection processing of the variables when a control model using the same variable is detected between the control models in different operation cycles. The software development support method according to claim 6.
The connection processing addition step includes the execution order information and the calculation cycle analyzed in the feature model analysis step, the connection processing of the variables added in the connection processing addition step, and the model source collected in the model source collection step. Based on, the execution order definition file for each calculation cycle, the variable information transfer processing definition file for each calculation cycle, and the MAKE file used at compile time are generated and added to the collected model source. Characteristic software development support method.

Images