JP7383822B2 - Base station shadow calculation - Google Patents

Description

RELATED APPLICATIONS This application is based on U.S. patent application Ser. Claim priority.

At least some embodiments disclosed herein relate to shadow computation at a base station. And, at least some embodiments disclosed herein relate to memory modules with computational capabilities. At least some embodiments disclosed herein also relate to systems having multiple such memory modules.

A base station can be considered a land station for land mobile services. This term can be used in the context of mobile telephones, wireless computer networks, and other wireless communications, and in land surveying. A cellular base station is a cellular-enabled mobile device site where antennas and electronic communication equipment are located. The location may be on a radio tower, tower, or other erected structure. Such structures can create cells (or adjacent cells) within a cellular network. The erected structure can support an antenna and one or more sets of transceivers, digital signal processors, control electronics, GPS receivers for timing, primary and backup power supplies, and shelter.

Generally, a base station may include computer hardware components. Computer hardware components can then be attached to printed circuit boards (PCBs). Computer hardware components can also be integrated into integrated circuits. Such an integrated circuit can be mounted on a PCB. PCBs can use conductive tracks, conductive pads, and other features to mechanically support and electrically connect electronic components.

A memory module can include a PCB with multiple memory components attached to the PCB. Examples of such memory modules include single in-line memory modules (SIMMs) and dual in-line memory modules (DIMMs). A single in-line memory module (SIMM) is a type of memory module that includes random access memory. SIMMs differ from dual in-line memory modules (DIMMs) in that the contacts on the SIMM are redundant on both sides of the module. This is not the case with DIMMs. DIMMs have separate electrical contacts on each side of the module. Another difference is that SIMMs typically have a 32-bit data path, while DIMMs typically have a 64-bit data path. DIMMs are commonly used in modern computers that are large enough to include one or more DIMMs, which can include multiple dynamic random access memory (DRAM) integrated circuits. For smaller computers, such as laptop computers, small outline dual in-line memory modules (SO-DIMMs) are often used.

Also, memory components can be integrated into a system-on-chip (SoC). An SoC is an integrated circuit (IC) that integrates computer components onto a single chip. Common computer components in an SoC include a central processing unit (CPU), memory, input/output ports, and secondary storage. An SoC can contain all its components on a single substrate or microchip, and some chips can be smaller than a quarter. An SoC may have various signal processing functions and may include a dedicated processor or coprocessor, such as a graphics processing unit (GPU). By being tightly integrated, SoCs can consume much less power than traditional multi-chip systems with comparable functionality. This makes SoCs useful for the integration of mobile computing devices (such as within smartphones and tablets). SoCs may also be useful in embedded systems and the Internet of Things, especially when smart devices are small.

The present disclosure will be more fully understood from the following detailed description and accompanying drawings of various embodiments of the disclosure.

1 illustrates an example networked system including a base station that can provide shadow computation in accordance with some embodiments of the present disclosure. 1 illustrates an example networked system including a base station that can provide shadow computation in accordance with some embodiments of the present disclosure. 3 illustrates a flowchart of example operations that may be performed by the base station shown in FIGS. 1 and 2, according to some embodiments of the present disclosure. FIG. 3 illustrates a flowchart of example operations that may be performed by the mobile device shown in FIGS. 1 and 2, according to some embodiments of the present disclosure. FIG. 4 illustrates an example memory module according to some embodiments of the present disclosure. 4 illustrates an example memory module according to some embodiments of the present disclosure. 1 illustrates an example memory module system according to some embodiments of the present disclosure. 1 illustrates an example memory module system according to some embodiments of the present disclosure. 1 illustrates an example networked system including a computing device in accordance with some embodiments of the present disclosure.

At least some embodiments disclosed herein relate to shadow computation at a base station. In some embodiments, mobile device computations are partially or completely offloaded to a base station, such as a cellular base station. A base station may include a computing device that includes a memory module or memory module system (such as a DIMM or system with multiple DIMMs) that is also configured with a dedicated controller or central processing unit. As a mobile device moves from the range of one base station to another, the mobile device's computational tasks may also move from one base station to another. For example, the closest base station can act as a shadow computing unit for the mobile device and perform shadow calculations.

At least some embodiments disclosed herein also include systems and methods for performing shadow calculations at a base station. The systems and methods can include initiating, at a base station (such as a cellular base station), a shadow computation of a main computation performed for a mobile device. The main computation may include computational tasks, and the shadow computation may be at least a portion or derivative of the main computation. The method can also include performing shadow calculations by the base station.

Additionally, at least some embodiments disclosed herein relate to memory modules with computing capabilities. And, at least some embodiments disclosed herein relate to systems having a plurality of such memory modules. Such memory modules and such systems may be included in any one of the base stations disclosed herein. More specifically, at least some embodiments disclosed herein include a memory module having a plurality of memory chips, at least one controller (e.g., a central processing unit or a dedicated controller), and an input of the memory module. including at least one interface configured to communicate output data. The input/output data bypasses at least one processor (eg, central processing unit) of the computing device in which the memory module is installed. The at least one interface device can then be configured to communicate input/output data to at least one other memory module of the computing device. Additionally, the memory module may be one of a plurality of memory modules of a memory module system. Additionally, a memory module or memory module system may be included in any one of the base stations disclosed herein.

In some embodiments, the memory module is a DIMM, SO-DIMM, registered DIMM (RDIMM), mini-RDIMM, socketed memory stack, or socketed system on a package for memory, or other type of package-on. package (PoP) or may contain them. And, in some embodiments, the memory module can be configured to include specialized chips such as GPUs, artificial intelligence (AI) accelerators, and/or processing-in-memory (PIM) units. In some embodiments, the memory module also connects peripherals (e.g., a display or other type user interface). For example, in some embodiments, the memory module provides wired or wireless connections or on-chip optical interconnects without going through a memory bus between the memory module and the main processor of the computing device that hosts the memory module. Results can be output to peripheral devices via . Such memory modules and other memory modules disclosed herein can be used to process graphics pipelines (e.g., data processing for geometry, projection, lighting, clipping, rasterization, shading, screen streaming, etc.) can be accelerated. Also, a system having multiple such memory modules in communication with each other can further speed up processing of the graphics pipeline.

FIG. 1 depicts an example networking system 100 shown including at least a base station 102 (which may be a cellular base station) and computing devices 122a, 122b, and 122c. As shown in FIG. 2, network system 100 is also shown including at least a mobile device 200 and base stations 222a, 222b, and 222c. Base stations 222a-222c may be cellular base stations. Networked system 100 may provide shadow computation in accordance with some embodiments of the present disclosure.

At least some of the illustrated components of FIG. 1 may be functionally and/or structurally similar to the illustrated components of FIG. 2. For example, computing devices 122a, 122b, and 122c may each have similar features and/or functionality as mobile device 200. And, for example, base station 102 may have similar features and/or functionality to base stations 222a, 222b, and 222c.

Networked system 100 of FIGS. 1 and 2 is networked via one or more communication networks 120. Networked system 100 of FIGS. The communication networks (network(s) 120) described herein include at least a local-to-device network such as Bluetooth, a wide area network (WAN), a local area network (LAN), an intranet, 4G or 5G, etc. mobile wireless networks, WiFi networks, extranets, the Internet, and/or any combination thereof. Networked system 100 may be part of a peer-to-peer network, a client-server network, a cloud computing environment, etc. Any of the computing devices described herein may also include some type of computer system. Such computer systems may then include network interfaces to other devices within a LAN, an intranet, an extranet, and/or the Internet (see, eg, network(s) 120). A computer system may also operate in the capacity of a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment. can.

FIG. 1 also depicts an example portion of an example base station 102. As shown in FIG. Base station 102 may be communicatively coupled to network(s) 120, as shown in FIGS. 1 and 2. Base station 102 includes at least a bus 104, a controller 106 (eg, a CPU or a specialized ASIC or FPGA), and a network interface 108. Base station 102 also includes multiple memory modules (see, eg, memory modules 110a and 110b). Base station 102 may also include a data storage system (not shown) and other components (not shown) that may be part of the base station. Other components of base station 102 not shown may include portions of a cellular base station. A cellular base station for purposes of this disclosure may be considered a cellular-enabled mobile device site where antennas and electronic communication equipment are located. The location may be on a radio tower, tower, or other erected structure. Such structures can create cells (or adjacent cells) within a cellular network. The erected structure can support an antenna and one or more sets of transceivers, digital signal processors, control electronics, a GPS receiver for timing, primary and backup power supplies, and shelter.

Each memory module (see, e.g., memory modules 110a and 110b) of base station 102 and other base stations described herein includes a dedicated controller (see, e.g., dedicated controller 114), a plurality of memory chips (e.g., , memory chips 112a and 112b), and a memory bus (see, eg, memory bus 118) that connects the dedicated controller to the plurality of memory chips. Each memory module may also include a network interface (see, eg, network interface 116). In embodiments where the memory module has a network interface, a memory bus (see, eg, memory bus 118) may connect the network interface and dedicated controller to multiple memory chips.

As shown in FIG. 1, the memory module 110a includes a dedicated controller 114, a plurality of memory chips including memory chips 112a and 112b, a network interface 116, and a memory bus 118 connecting the dedicated controller, the plurality of memory chips, and the network interface. including. Also, as shown, network interface 116 is represented by a dashed box indicating that modules with network interfaces are optional. In such embodiments that include a network interface, the memory modules can bypass communicating with external devices via network interface 108 because each memory module has its own network interface. In embodiments where the memory module does not have a network interface, the base station's network interface (see, eg, network interface 108) can be used to communicate with external devices. Such external devices are devices external to base station 102.

In some embodiments, base station 102 is, includes, or is part of a cellular base station, as described above. The cellular base station or base station 102 may be configured to receive and/or initiate shadow computations of the main computations that it performs on behalf of mobile devices (eg, see computing devices 122a-122c). The main computation may include computational tasks, and the shadow computation may be at least a portion or derivative of the main computation. The cellular base station or base station 102 may also be configured to perform shadow calculations. In some embodiments, a dedicated controller (see, e.g., dedicated controller 114) may be configured to receive and/or initiate shadow calculations of the main calculations it performs for the mobile device, and may be configured to can be configured to run.

The cellular base station or base station 102 may also be configured to transmit output data of the performed shadow calculations to the mobile device or to other devices. In some embodiments, a dedicated controller (e.g., see dedicated controller 114) has a network interface (e.g., see network interface 108 or network interface 116) and a communication network (e.g., see network(s) 120). The output data of the performed shadow computation can be configured to transmit to the mobile device or to other devices via the .

The cellular base station or base station 102 may also transmit output data of the performed shadow calculations to other base stations, such as other cellular base stations (see, e.g., base stations 222a, 222b, and 222c). Can be configured. In some embodiments, a dedicated controller (e.g., see dedicated controller 114) has a network interface (e.g., see network interface 108 or network interface 116) and a communication network (e.g., see network(s) 120). may be configured to transmit the output data of the performed shadow calculations to other base stations (eg, see base stations 222a-222c), such as other cellular base stations, via the base station.

In some embodiments, the cellular base station or base station 102 may also be configured to send shadow calculations back to the mobile device. In some embodiments, a dedicated controller (e.g., see dedicated controller 114) has a network interface (e.g., see network interface 108 or network interface 116) and a communication network (e.g., see network(s) 120). can be configured to send shadow calculations back to the mobile device via

In some embodiments, the cellular base station or base station 102 also derives at least one other shadow calculation from the shadow calculation and then sends the other shadow calculation(s) to at least one device other than the base station. can be configured to send. For example, the cellular base station or base station 102 may also derive other shadow calculation(s) from the shadow calculation and then transmit other shadow calculation(s) to the other base station or other cellular base station. It can be configured to: In some embodiments, a dedicated controller (see, e.g., dedicated controller 114) derives other shadow computation(s) from the shadow computation, and then connects the network interface (e.g., network interface 108 or network interface 116) and a communication network (see, e.g., network(s) 120) to at least one device other than the base station.

In some embodiments, when a mobile device is within a threshold distance of another base station or other cellular base stations (see, e.g., base stations 222a-222c), A cellular base station generates less network traffic than the base station or cellular base station and/or when other base stations or other cellular base stations have greater computing power than the base station or cellular base station. Station or base station 102 may also be configured to transmit shadow calculations to other base stations or cellular base stations. In some embodiments, when a mobile device is within a threshold distance of another base station or other cellular base stations (see, e.g., base stations 222a-222c), A dedicated controller when a station generates less network traffic than the base station or cellular base station and/or when other base stations or other cellular base stations have greater computing power than the base station or cellular base station. (see, e.g., dedicated controller 114) communicates with other base stations or The shadow calculation may be configured to send to a cellular base station. In such and other embodiments, other cellular base stations or other base stations (e.g., see base stations 222a-222c) may also be configured to send shadow calculations back to the mobile device. . In some embodiments, other base stations or dedicated controllers of other cellular base stations may be configured to send shadow calculations back to the mobile device via the network interface and communication network.

In some embodiments, sending and receiving shadow calculations may occur entirely within one time period or in divided portions within multiple separate time periods. Also, sending and receiving shadow computations can be done in such a way that after migrating the shadow computation (e.g., migrating the shadow computation from one device to another), the original computation from which the shadow computation was derived no longer exists. may involve a complete migration of computations. When transferring shadow computations in full or in part, the shadow computations can be partitioned by computational tasks. The tasks so divided can then be allocated among base stations or other types of devices or equipment. Also, shadow computations can be derived from shadow computations recombined from different origins, so parts of the computations are performed from more devices to fewer devices. In other words, one or more shadow computations can be consolidated from many devices to fewer devices or base stations. Furthermore, by sending the output of a shadow computation, many other shadow computations may be generated or initiated. And such actions can also merge separate datasets of shadow calculations and other related data, and generate or terminate related shadow calculation(s) when certain criteria are met. do.

As shown in FIG. 1, bus 104 communicatively couples controller 106, network interface 108, and a plurality of memory modules (see, eg, memory modules 110a and 110b). Bus 104 may also communicatively couple such portions to other portions of the base station, such as data storage systems and other components. The base station 102 includes at least a controller 106 and - read only memory (ROM), flash memory, dynamic random access memory (DRAM) (such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), static random access memory ( (See memory modules 110a and 110b). The computer system may also include a data storage system, not shown, and such portions may communicate with each other via bus 104, which may include multiple buses.

For some embodiments, FIG. 1 includes a block diagram of a base station 102 having a computer system on which embodiments of the present disclosure may operate. In some embodiments, a computer system can include a set of instructions that, when executed, cause a machine to perform at least any one or more of the methods described herein. In such embodiments, the machine connects (e.g., via network interface 108) to other machines within a LAN, intranet, extranet, and/or Internet (see e.g., network(s) 120) network connection). A machine can operate in the function of a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

Base station controller 106 may be or include one or more general purpose processing units, such as a microprocessor, central processing unit, and the like. More particularly, the processing device may include a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a single instruction multiple data (SIMD), It may be a processor implementing multiple instruction multiple data (MIMD), or other instruction sets, or a combination of instruction sets. Controller 106 may also be one or more special purpose processing devices such as an ASIC, programmable logic such as an FPGA, a digital signal processor (DSP), a network processor, and the like. Controller 106 may be configured to execute instructions to perform at least some of the operations and steps described herein.

A data storage system (not shown) of base station 102 includes a machine-readable system having one or more instruction sets or software stored thereon that is capable of implementing any one or more of the methods or functions described herein. storage media (also known as computer-readable media). The data storage system of base station 102 can have execution capabilities, such as it can at least partially execute instructions residing on the data storage system. The instructions may also reside entirely or at least partially within memory (see, e.g., memory modules 110a and 110b) and/or within controller 106 while the computer system executes them. The station's memory and controller also constitute machine-readable storage media. The memory of base station 102 may be or include main memory. The memory of base station 102 can have execution capabilities, such as it can at least partially execute instructions that reside in the memory.

The memory of base station 102 (see, eg, memory modules 110a and 110b) as well as the memory of the computing devices described herein may include various types of memory. For example, such memory can include flash memory having flash memory cells. Also, for example, such memory may include dynamic random access memory (DRAM), which includes DRAM cells. Also, for example, such memory may also include non-volatile random access memory (NVRAM), including NVRAM cells. NVRAM cells may include 3D XPoint memory cells.

Some embodiments may include a system for a base station, such as a system that includes multiple memory modules (see, eg, memory modules 110a and 110b). Such systems may include multiple memory modules, each memory module configured for insertion into a printed circuit board (PCB) of a base station (see, eg, base station 102). And, in such embodiments, each memory module may include multiple memory chips (see, eg, memory chips 112a and 112b) and a dedicated controller (see, eg, dedicated controller 114).

In such embodiments and other embodiments described herein, the dedicated controller is, includes, or is part of a graphics processing unit (GPU) or an artificial intelligence (AI) accelerator. It may be. The dedicated controller can then be coupled to multiple memory chips. In such an example, the dedicated controller may be configured to receive and/or initiate shadow computations of the main computations it performs on behalf of the mobile device, and to perform the shadow computations. The dedicated controller in such instances may also be configured to send output data of the performed shadow calculations to the mobile device. The dedicated controller in such instances may also be configured to transmit output data of the performed shadow calculations to other cellular base stations. The dedicated controller in such instances may also be configured to send shadow calculations to other cellular base stations. The dedicated controller in such an example also controls when the mobile device is within a threshold distance of another cellular base station, when the other cellular base station experiences less network traffic than the cellular base station, and/or The shadow computation may be configured to send to other cellular base stations when the other cellular base stations have greater computing power than the cellular base station. The dedicated controller in such instances may also be configured to send shadow calculations back to the mobile device.

Some embodiments may include a device with multiple memory chips, multiple electrical contacts, and a dedicated controller. and such apparatus includes a network interface configured to communicate input and output data of the dedicated controller through one or more communication networks that bypass the main processor of the computing device on which the apparatus is installed. can include devices. The computing device on which the apparatus is installed may be a computing device of a base station (such as base station 102) or one or more networks (see, e.g., network(s) 120), such as computing devices 122a-122c. ) may be a computing device connected to a base station, such as a base station connected via a base station.

In some embodiments, such a device may include a printed circuit board (PCB) configured for insertion into a memory slot of a motherboard. Also, multiple memory chips can be coupled to the PCB. Also, multiple electrical contacts may be on each side of the PCB. Also, a dedicated controller can be coupled to the PCB. A network interface device can then be coupled to the PCB. In such and other examples, the dedicated controller may include a graphics processing unit (GPU), and/or other types of dedicated controllers, such as an AI accelerator. In such and other examples, the network interface device may include a wireless network interface configured to communicate via one or more wireless networks. The one or more communication networks can then bypass the main data bus of the computing device on which the apparatus is installed.

The apparatus is also configured to connect the plurality of memory chips to at least some of the plurality of electrical contacts to communicate input and output data of the plurality of memory chips to a main processor of the computing device in which the system is installed. The first connection portion may include a first connection portion. The apparatus can also include a second connection configured to connect the plurality of memory ships to the dedicated controller. The network interface device then receives the dedicated controller's input data from the other device and transmits the dedicated controller's output data to the other device via a communication path that bypasses the main processor of the computing device in which the device is installed. The device can include a third connection configured to connect the dedicated controller to the network interface to communicate the .

The apparatus may also include an arbiter configured to resolve conflicts when the main processor attempts to access data in multiple memory chips while the dedicated controller accesses the multiple memory chips. .

Some embodiments may include a system with multiple dual in-line memory modules (DIMMs). Each DIMM of the plurality of DIMMs may include a PCB configured for insertion into a memory slot of an additional PCB that is separate from the plurality of DIMMs. Each DIMM of the plurality of DIMMs may include a plurality of memory chips coupled to a PCB and a plurality of electrical contacts on opposite sides of the PCB. Each DIMM of the plurality of DIMMs may include a dedicated controller coupled to the PCB. and each DIMM of the plurality of DIMMs is coupled to the PCB and configured to communicate via one or more communication networks that bypass the main processor of the computing device in which the system is installed. can include. The computing device on which the system is installed may be a computing device of a base station (such as base station 102) or one or more networks (e.g., see network(s) 120, such as computing devices 122a-122c). ) may be a computing device connected to a base station, such as a base station connected via a base station.

In some embodiments, such a system can include an external controller that is separate from the DIMMs and configured to coordinate calculations with dedicated controllers for the DIMMs. And, in such embodiments, the system can have an additional PCB that is separate from the DIMMs and includes multiple memory slots configured to accept the DIMMs. External controllers can then be coupled to additional PCBs. Also, in such embodiments, the additional PCB may be a motherboard and the external controller may include a central processing unit (CPU).

In such and other examples, the dedicated controller may include a graphics processing unit (GPU), and/or other types of dedicated controllers, such as an AI accelerator. And in such and other examples, the network interface device of each DIMM of the plurality of DIMMs may include a wireless network interface device configured to communicate via a wireless network.

In some embodiments, for each DIMM of the plurality of DIMMs, the DIMM's wireless network interface receives dedicated controller input data and transmits dedicated controller output data to a main processor of the computing device in which the system is installed. and configured to communicate to one or more displays via one or more wireless communication links that bypass the.

Some embodiments may include DIMMs. A DIMM may include a printed circuit board (PCB) configured for insertion into a memory slot of a motherboard. A DIMM may also include multiple memory chips coupled to a PCB and multiple electrical contacts on opposite sides of the PCB. The DIMM may also include a dedicated controller coupled to the PCB. The DIMM also includes a network interface device coupled to the PCB and configured to communicate input and output data of the dedicated controller via one or more communication networks that cause the DIMM to bypass the main processor of the computing device. be able to. The computing device on which the DIMM is installed may be a computing device of a base station (such as base station 102) or one or more networks (e.g., network(s) 120, such as computing devices 122a-122c). A computing device may be a computing device connected to a base station, such as a base station connected via a computer. In such and other embodiments, and when the DIMM is within a mobile device, the DIMM may be a small outline dual in-line memory module (SO-DIMM). Also, in such and other examples, the dedicated controller includes a graphics processing unit (GPU), and/or other types of dedicated controllers, such as an AI accelerator. And in such and other examples, the network interface device may include a wireless network interface configured to communicate via one or more wireless networks.

Further, in such and other examples, the DIMM connects the plurality of memory chips to at least some of the electrical contacts to transmit input and output data of the plurality of memory chips to the computing device in which the system is installed. A first connection configured to communicate with a main processor of the computer. The DIMM can also include a second connection configured to connect the plurality of memory chips to the GPU. The DIMM then receives GPU input data from other devices and transmits GPU output data to other devices via a communication path that bypasses the main processor of the computing device in which the DIMM is installed. A third connection configured to connect the GPU to the network interface device to communicate with the device can be included.

Further, in such and other examples, the one or more communication networks bypass the main data bus of the computing device in which the DIMM is installed.

and the DIMM includes an arbiter configured to resolve conflicts when the main processor attempts to access data in the multiple memory chips while the dedicated controller is accessing the multiple memory chips in the DIMM. be able to.

FIG. 2 illustrates an example system that includes at least computing devices 122a-122c and base station 102 (see, e.g., FIG. 1), and includes a mobile device 200 and base stations 222a, 222b, and 222c (see, e.g., FIG. 2). 1 shows a networked system 100. Networked system 100 may provide shadow computation in accordance with some embodiments of the present disclosure.

At least some of the illustrated components of FIG. 2 may be functionally and/or structurally similar to the illustrated components of FIG. 1. For example, mobile device 200 may have similar features and/or functionality as any one of computing devices 122a-122c. And, for example, each of base stations 222a-222c may have similar features and/or functionality to base station 102.

FIG. 2 also illustrates example portions of an example mobile device 200. Mobile device 200 may be communicatively coupled to network(s) 120, as shown in FIGS. 1 and 2. The mobile device 200 includes at least a bus 206, a controller 208 (such as a CPU), a memory 210, a network interface 212, a data storage system 214, and other components 216 (I/O components such as a GPS component, various types of user interface components, etc.). , and any type of component found in a mobile or computing device, such as sensors and cameras). Other components 216 may include one or more user interfaces (e.g., GUI, auditory user interface, haptic user interface, etc.), displays, different types of sensors, haptic input/output devices, audio input/output devices, and/or visual input/output devices. It may include an output device, additional application-specific memory, one or more additional controllers (eg, a GPU), or any combination thereof. Bus 206 communicatively couples controller 208, memory 210, network interface 212, data storage system 214, and other components 216. The computing device 202 includes at least a controller 208, a memory 210 (e.g., read only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), static random access memory (SRAM), crosspoint or crossbar memory, crossbar memory, etc.), and a data storage system 214 that is connected via a bus 206 (which may include multiple buses). communicate with each other.

Stated another way, FIG. 2 is a block diagram of a mobile device 200 having a computer system on which embodiments of the present disclosure may operate. In some embodiments, a computer system can include a set of instructions that, when executed, cause a machine to perform at least any one or more of the methods described herein. In such embodiments, the machine may be connected to other machines within a LAN, intranet, extranet, and/or the Internet (e.g., network(s) 120) (e.g., via network interface 212). can do. A machine can operate in the function of a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

Controller 208 represents one or more general purpose processing units, such as a microprocessor, central processing unit, or the like. More particularly, the processing device may include a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a single instruction multiple data (SIMD), It may be a processor implementing multiple instruction multiple data (MIMD), or other instruction sets, or a combination of instruction sets. Controller 208 may also be one or more special purpose processing devices such as an ASIC, programmable logic such as an FPGA, a digital signal processor (DSP), a network processor, and the like. Controller 208 is configured to execute instructions to perform the operations and steps described herein. Controller 208 may further include a network interface device, such as, for example, network interface 212, for communicating via one or more communication networks (eg, network(s) 120).

Data storage system 214 includes a machine-readable storage medium (also known as a computer-readable medium) having one or more instruction sets or software stored thereon that embodies any one or more of the methods or functions described herein. known). Data storage system 214 can have execution capabilities, such as it can at least partially execute instructions residing on the data storage system. The instructions may also reside wholly or at least partially within memory 210 and/or controller 208 while the computer system executes them, with memory 210 and controller 208 also comprising machine-readable storage media. do. Memory 210 may be or include main memory of mobile device 200. Memory 210 can have execution capabilities, such as it can at least partially execute instructions that reside in memory.

Networked system 100 includes computing devices (see, e.g., computing devices 122a-122c and mobile device 200), each of which has one or more buses, controllers, memory, network It can include interfaces, storage systems, and other components. Additionally, each of the computing devices shown in FIGS. 1 and 2 may be, for example, a smartphone, a tablet computer, an IoT device, a smart TV, a smart watch, glasses or other smart consumer electronics, an in-vehicle information system, a wearable smart device, It may be, include, or be part of a mobile device, such as a gaming console, a PC, a digital camera, or any combination thereof. As shown, the computing device 304 may be connected to at least a local-to-device network such as Bluetooth, a wide area network (WAN), a local area network (LAN), an intranet, a mobile wireless network such as 4G or 5G, an extranet, Communication network(s) 120 may be connected, including the Internet, and/or any combination thereof.

Each of the computing or mobile devices described herein (such as computing devices 122a-122c and mobile device 200) may include a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant, etc. (PDA), mobile phone, web appliance, server, network router, switch or bridge, or any machine that executes (sequentially or otherwise) a set of instructions that specify the actions to be performed by that machine. machines that can or may be replaced by them.

Also, although a single machine is shown for the mobile device 200 shown in FIG. 2 and the base station 102 shown in FIG. ), the term "machine" also refers to a set (or sets) of instructions, individually or jointly, for performing one or more of the methods or acts described herein. shall be construed to include any collection of machines running . and that each of the illustrated computing devices or mobile devices and computing systems each includes at least a bus and/or a motherboard, one or more controllers (such as one or more CPUs), and temporary data storage. at least one type of network interface, a storage system that may include persistent data storage, and/or any combination thereof. In some multi-device embodiments, one device completes some portions of the methods described herein, and then other devices continue with other steps of the methods described herein. You can send the completed results to other devices via the network.

Although the memory, controller, and data storage portions are each shown as being a single portion in the exemplary embodiment, each portion is a single portion capable of storing instructions and performing their respective operations. or should be construed as including multiple parts. The term "machine-readable storage medium" also refers to any medium that is capable of storing or encoding a set of instructions for execution by a machine and that causes a machine to perform any one or more of the methods of this disclosure. should be construed as including. Accordingly, the term "machine-readable storage medium" shall be construed to include, but not be limited to, solid state memory, optical media, and magnetic media.

3 and 4 depict flowcharts of example operations of methods 300 and 400, respectively, that may be performed by the base stations shown in FIGS. 1 and 2, according to some embodiments of the present disclosure. In some embodiments, the example operations of methods 300 and 400 may be performed by one or more dedicated controllers (see, eg, dedicated controller 114). And, in such embodiments, the sending and receiving operations may be performed over one or more network interfaces (e.g., see network interface 108 or network interface 116) and one or more communication networks (e.g., network(s)). (see 120).

In FIG. 3, method 300 begins at step 302 with receiving and initiating a shadow computation of a main computation to perform on behalf of a mobile device by a base station (such as a cellular base station). Initiating may be performed by one or more dedicated controllers, and receiving may be by one or more dedicated controllers via one or more network interfaces. The main computation may include computational tasks, and the shadow computation may be at least a portion or derivative of the main computation. Shadow computation may also be for common computing devices. The mobile device or other computing device can then send shadow calculations to the base station. In other words, shadow calculations may be received from a mobile device or other computing device.

At step 304, method 300 continues with performing shadow calculations by the base station.

At step 306, method 300 continues with transmitting output data of the performed shadow computation by the base station to the mobile device or to other devices. Some devices can rely on data output produced by shadow computation.

At step 308, method 300 continues with transmitting by the base station to other base stations (such as other cellular base stations) the output data of the performed shadow calculations. In some cases, several base stations may communicate or exchange intermediate outputs to generate shadow computations and computation outputs.

At step 310, method 300 continues with determining whether one or more criteria are met. Determining whether the one or more criteria are met may include determining whether the mobile device is within a threshold distance of another base station, whether the mobile device is within a threshold distance of another base station, or whether the mobile device is within a threshold distance of another base station; This may include determining whether traffic is occurring, determining whether other base stations have greater computing power than the base station, or any combination thereof.

At step 312, method 300 continues with transmitting shadow calculations by the base station to other base stations (such as other cellular base stations) when one or more forwarding criteria are met. For example, at step 312, method 300 can include transmitting a shadow calculation by a base station to another base station when the mobile device is within a threshold distance of the other base station. Also, for example, in step 312, method 300 can include, by a base station, transmitting a shadow calculation to another base station when the other base station generates less network traffic than the base station. Also, for example, in step 312, method 300 can include, by the base station, transmitting the shadow computation to another base station when the other base station has greater computational capability than the base station. A base station may also retain shadow calculations when they are sent or forwarded to other base stations.

At step 314a, method 300 continues sending shadow calculations back to the mobile device by the base station. Since the shadow calculation was not forwarded to other base stations via step 312, the base station sends the shadow calculation back to the mobile device.

At step 314b, method 300 continues sending shadow calculations back to the mobile device by other base stations. Since the shadow calculation was transferred to the other base station via step 312, the other base station sends the shadow calculation back to the mobile device. Once the shadow calculations are sent or forwarded to other base stations, the base station may also retain the shadow calculations and return the shadow calculations to the mobile device.

As shown in FIG. 4, method 400 includes all the steps of method 300 and further includes steps 402, 404, 406, 408a, and 408b.

Method 400 begins at step 302 with receiving and initiating a shadow computation of a main computation to perform on behalf of a mobile device by a base station (such as a cellular base station). The method 400 can then continue with performing shadow calculations by the base station at step 304. Then, after step 304, method 400 branches. The method may continue with the remainder of the steps of method 300, including steps 306, 308, 310, 312, 314a, and 314b, and/or with additional steps 402, 404, 406, 408a, and 408b. be able to.

At step 402, method 400 continues to derive other shadow calculations from the shadow calculation by the base station.

At step 404, method 400 continues with determining whether one or more transfer criteria are met. Determining whether the one or more criteria are met may include determining whether the mobile device is within a threshold distance of another base station, whether the mobile device is within a threshold distance of another base station, or whether the mobile device is within a threshold distance of another base station; This may include determining whether traffic is occurring, determining whether other base stations have greater computing power than the base station, or any combination thereof.

At step 406, method 400 continues with transmitting other derived shadow calculations by the base station to other base stations (such as other cellular base stations) once the one or more forwarding criteria are met. . For example, in step 406, the method 400 includes transmitting by the base station the other derived shadow calculation to the other base station when the mobile device is within a threshold distance of the other base station. Can be done. Also, for example, in step 406, the method 400 may include transmitting other shadow calculations derived by the base station to other base stations when the other base station experiences less network traffic than the base station. can be included. Also, for example, in step 406, the method 400 includes transmitting, by the base station, other derived shadow calculations to the other base station when the other base station has greater computing power than the base station. be able to. The base station may also retain other derived shadow calculations if they are transmitted or forwarded to other base stations.

At step 408a, method 400 continues sending other derived shadow calculations back to the mobile device by the base station. Since the derived other shadow calculations were not transferred to other base stations via step 406, the base station sends the derived other shadow calculations back to the mobile device.

At step 408b, method 400 continues sending back other shadow calculations derived by other base stations to the mobile device. Since the derived other shadow calculations were transferred to the other base station via step 406, the base station sends the derived other shadow calculations back to the mobile device. When the other derived shadow calculations are sent or forwarded to other base stations, the base station may also retain the other derived shadow calculations and return the other derived shadow calculations to the mobile device. You can also do it.

In some embodiments, the steps of methods 300 and/or 400 are sequential, such that each step can be performed independently by monitoring input data, performing operations, and outputting data to subsequent steps. Please understand that it can be implemented as a process. Also, the steps can be implemented as a discrete event process, such that each step can be triggered by an event that causes it to be triggered and to produce a particular output. It is also to be understood that each of FIGS. 3 and 4 represents a minimal method within a possibly larger method of a more complex system than that partially presented in FIGS. 1 and 2.

In some embodiments, a non-transitory computer-readable storage medium tangibly encoded with computer-executable instructions (see, e.g., memory modules 110a and 110b) is stored in a processor associated with a computing device (e.g., When executed by dedicated controller 114), methods may be performed, such as methods including any one or more of the operations described herein.

5 and 6 illustrate example memory modules 502 and 602, respectively, according to some embodiments of the present disclosure. Either memory module 502 or 602 may be, include, or be part of a device and/or system.

FIG. 5 shows a memory module 502 having multiple memory chips (see, eg, memory chips 504a, 504b, and 504c). Memory module 502 also has at least one controller (see, eg, controllers 506a and 506b). As shown, different embodiments of memory module 502 may have one controller (eg, controller 506a), two controllers (eg, controllers 506a and 506b), or more than two controllers. It should be understood that the dashed boxes represent optional components. It should also be appreciated that embodiments of memory module 502 may have two or more than two memory chips.

The memory described herein, such as the memory of a memory module, may include various types of memory. For example, such memory can include flash memory having flash memory cells. Also, for example, such memory may include dynamic random access memory (DRAM), which includes DRAM cells. Also, for example, such memory may also include non-volatile random access memory (NVRAM), including NVRAM cells. NVRAM cells may include 3D XPoint memory cells.

Memory module 502 is also shown having at least one interface device (see, eg, interface devices 508a and 508b). As shown, different embodiments of memory module 502 may have one interface device (eg, interface device 508a), two interface devices (eg, interface devices 508a and 508b), or more than two interface devices. Can be done. And, as mentioned above, it should be understood that the dashed boxes represent optional components. At least one interface device (see, eg, interface devices 508a and 508b) may be configured to communicate input and output data for memory module 502. Input/output data may bypass at least one processor (e.g., the main processor) of the system in which the memory module 502 is installed (e.g., through the installations 8a and 518b where the memory module 502 is installed). interfaces 508a and 508b that bypass at least one processor 512 of the system being configured. In some embodiments, as shown in FIG. (See interfaces 508a and 508b, which are connected to other devices 514 of the system and bypass, via connections 518a and 518b, the bus 516 (which may include multiple buses) of the system in which the memory module is installed. . It should be understood that the dashed connections represent optional connections.

Memory module 502 also includes a plurality of memory chips (e.g., see memory chips 504a, 504b, and 504c), controller(s) (e.g., see controllers 506a and 506b), and interface device(s) (e.g., , interface devices 508a and 508b)) are shown having a bus 510 (which may include multiple buses). Bus 510 may be part of the bus of the system in which the memory module is installed (see, e.g., bus 516), and the bus connects memory module 502 to the rest of the system in which it is installed. . Bus 510 may be separate from bus 516 in some embodiments, and may be separate from bus 516 in other embodiments, as indicated by the dashed line portion of bus 510 that connects the memory modules to bus 516 and the rest of the system. It may be connected to bus 516. It should be understood that the dashed connections represent optional connections. One or more of the controllers of memory module 502 (see, e.g., controllers 506a and 506b) communicate data via bus 510 and connections that bypass bus 516 (see, e.g., connections 518a and 518b). Mediation is possible.

Interface devices and other interface devices referred to herein may include one or more network interface devices, one or more links, one or more buses, one or more ports, one or more peer-to-peer links, or any combination thereof.

In some embodiments, memory module 502 may implement a global shared context. Generally, a global shared context includes multiple instances of memory modules 502 or 602 that communicate with each other via their interface devices. A global shared context can be beneficial for graphics processing and graphics applications because large amounts of memory are available and graphics processing can be improved by processing data close to memory. In such and other embodiments, the interface device(s) (see, e.g., interface devices 508a and 508b) communicate with at least one of the memory modules installed in the system in which the communicating memory module is installed. can be configured to communicate input and output data to two other instances.

In some embodiments, memory module 502 or other memory modules described herein, controller 506a or other controllers described herein, interface device 508a or other controllers described herein, The interface device, memory chips 504a, 504b, and 504c or other memory chips described herein, or any combination thereof, may be used in a system-on-package (SoP), such as a system-on-chip (SoC), an intervening chiplet system, etc. ), or may be part of a dissimilar die stack, etc. All of these embodiments represent tightly integrated IP blocks and chips that do not necessarily include PCBs for coupling with each other and with the rest of the system. Embodiments that include or are part of an SoC, or other embodiments, include one or more GPUs, or one or more other types of specialized processors, and/or one or more PIM units. can be included. Embodiments that include or are part of an SoC, or other embodiments, include a memory controller, a display sink (e.g., HDMI or DisplayPort), a wireless interface or network radio, an AI engine or accelerator, It may include or include processors connected thereto, such as scalar processors, vector processors, CPU cores, and the like.

Although not shown in FIG. 5, memory module 502 can also include multiple electrical contacts. Memory module 502 may also include a PCB configured for insertion into a memory slot of a motherboard. In such embodiments, multiple memory chips (see, eg, memory chips 504a, 504b, and 504c) may be coupled to the PCB, and multiple electrical contacts may be on either side of the PCB. Additionally, controller(s) (see, e.g., controllers 506a and 506b) may be coupled to the PCB, and interface device(s) (see, e.g., interface devices 508a and 508b) may be coupled to the PCB. be able to.

In some embodiments, the controller(s) (see, eg, controllers 506a and 506b) may be, include, or be part of at least one dedicated controller. The dedicated controller(s) are, include, or are part of a GPU, AI accelerator, neural processing unit (NPU), other type of dedicated controller, PIM unit, or any combination thereof. It may be.

In some embodiments, the interface device(s) (e.g., interface devices 508a and 508b) may include at least one wireless interface device that communicates at least partially wirelessly, or may include optical communication between chips. It may also include on-chip optical interconnects that provide Other parts of the interface device(s) can communicate via wires. The interface device(s) may also be a hybrid interface device with multiple functions and/or channels and channel types. The interface device(s) may be, include, or be part of a network interface device (such as a wireless network interface device). The interface device(s) may include at least one wireless interface device, and/or the wired link may include one or more wired and/or wireless networks, peer-to-peer links, ports, buses, etc. can be configured to communicate.

In some embodiments, the memory module 502 connects the plurality of memory chips (e.g., memory chips 504a, 504b, and 504c) to at least some of the plurality of electrical contacts to provide input/output of the plurality of memory chips. A first connection configured to communicate data to a processor of a computing device (such as a main processor of the computing device) in which memory module 502 is installed can be included. Memory module 502 can also include a second connection configured to connect the plurality of memory chips to controller(s) (see, eg, controllers 506a and 506b). Memory module 502 also includes one or more third connections configured to connect controller(s) to interface device(s) (see, e.g., interface devices 508a and 508b). as a result, the interface device(s) receive input data for the controller(s) from other devices via a communication path that bypasses the processor of the computing device in which the memory module 502 is installed. and communicate the output data of the controller(s) to other devices.

FIG. 6 shows a memory module 602 that is somewhat similar to memory module 502. However, memory module 602 is shown with at least one arbiter (see, eg, arbiters 604a and 604b). FIG. 6 shows a memory module 602 having a plurality of memory chips (eg, see memory chips 504a, 504b, and 504c) similar to the chips shown in FIG. Memory module 602 also has at least one controller similar to the at least one controller shown in FIG. 5 (see, eg, controllers 506a and 506b). As also shown in FIG. 6, different embodiments of memory module 502 can have one controller (e.g., controller 506a), two controllers (e.g., controllers 506a and 506b), or more than two controllers. . It should be understood that the dashed boxes represent optional components. It should also be appreciated that embodiments of memory module 602 may have two or more than two memory chips.

Also shown in FIG. 6, memory module 602 is illustrated with at least one interface device similar to the at least one interface device shown in FIG. 5 (see, e.g., interface devices 508a and 508b). . As shown, different embodiments of memory module 602 may have one interface device (eg, interface device 508a), two interface devices (eg, interface devices 508a and 508b), or more than two interface devices. Can be done. As mentioned above, it should be understood that the dashed boxes represent optional components. Interface device(s) (see, eg, interface devices 508a and 508b) may be configured to communicate input and output data of memory module 602. Input/output data may bypass the processor (eg, main processor) of the system in which memory module 602 is installed. In some embodiments, input/output data bypasses the data bus (such as the main data bus) of the system in which memory module 602 is installed.

Further, as described above and shown in FIG. 6, memory module 602 includes at least one arbiter (eg, arbiters 604a and 604b). The at least one arbiter is configured to determine whether a processor of the hosting computing device has multiple memory chips (e.g., It may be configured to resolve conflicts when attempting to access data on chips 504a and 504b). As shown, different embodiments of memory module 602 can have one arbiter (eg, arbiter 604a), two arbiters (eg, 604a and 604b), or more than two arbiters. And, as mentioned above, it should be understood that the dashed boxes and connections represent optional components.

In some embodiments, the arbiter is such that each controller has one arbiter for arbitrating access to the memory chips among all devices accessing these chips and external devices (main processor and system). may be part of the controller. In other embodiments, the arbiter connects the memory chips so that each arbiter can queue memory requests to each chip in order of processing and resolve conflicts associated with requests to the same address within the memory chip. may be part of. Also, in some embodiments, one or more of the arbiters for memory module 202 (see, e.g., arbiters 604a and 604b) bypass bus 510 and bus 516 of the system in which memory module 602 is installed. Data communicated over the connections (eg, see connections 518a and 518b) can be arbitrated.

As described above and shown in FIGS. 5 and 6, memory module 502 and memory module 602 communicate input and output data to a plurality of memory chips, at least one controller (e.g., at least one dedicated controller), and memory modules. at least one interface device configured to. Input and output data bypasses the processor of the computing device in which the memory module 502 or 602 is installed. The interface device(s) may then be configured to communicate input/output data to at least one other memory module of the computing device (not shown in FIGS. 5 and 6). In some embodiments, input/output data, or portions thereof, are communicated through and processed by the main processor (such as to register the state of memory modules).

The interface device(s) of the memory module 502 or 602 includes at least one network interface device that can be configured to communicate input/output data of the controller(s) via one or more communication networks. can be included. The controller(s) may include a GPU, an AI accelerator, an NPU, other types of dedicated controllers, a PIM unit, or any combination thereof. At least one interface device of memory module 502 or 602 may include at least one wireless interface device configured to communicate at least partially wirelessly via one or more wireless communication networks. , may include intra-chip optical interconnects that provide optical communications between the chips, and one or more wireless communication networks or intra-chip optical interconnects of the computing device in which the memory module 502 or 602 is installed. The data bus (such as the main data bus) can be bypassed. In some embodiments, wireless communication may occur between multiple memory modules installed in the system. For example, a wireless receiver can enable data communication between modules aligned-in-space (such as DIMMs installed on a PC board). This can increase the speed of such communication. Specifically, in some embodiments, terahertz wireless communications (THz) can enable speeds of 100 Gb/s. Accordingly, in such instances, THz radiation within the chip or module may support large amounts of data exchange between the memory modules disclosed herein.

And, as specifically shown in FIG. 6, the memory module 602 is configured to operate on a processor of a computing device having the memory module while the controller(s) of the memory module accesses the memory chips of the memory module. includes an arbiter configured to resolve conflicts when the memory chips attempt to access data in multiple memory chips.

7 and 8 illustrate example memory modules 702 and 802, respectively, according to some embodiments of the present disclosure. FIG. 8 depicts a memory module system 802 that is somewhat similar to memory module system 702 illustrated in FIG. However, memory module system 802 is shown with at least one arbiter (see, eg, arbiters 804a and 804b). At least one arbiter shown as being included in the memory module system 802 is configured to control a processor of a computing device having or hosting the memory module system 802 while at least one controller in the memory module system is accessing a memory chip. is configured to resolve conflicts when the memory module system attempts to access data on one or more memory chips of the memory module system.

Both illustrated memory module systems 702 and 802 include multiple memory modules (see, eg, memory modules 704a, 704b, and 704c). Each of the memory modules includes a plurality of memory chips. Each memory module of the plurality of memory modules (see, eg, memory modules 704a, 704b, and 704c) may be memory module 502 or memory module 602. Memory module systems 702 and 802 also each include at least one external controller (see, eg, external controllers 706a and 706b) and at least one interface device (see, eg, interface devices 708a and 708b).

Memory module systems 702 and 802 each include a plurality of memory modules (see, e.g., memory modules 704a, 704b, and 704c), at least one external controller (see, e.g., external controllers 706a and 706b), and at least one Illustrated with a bus 710 (which may include multiple buses) connecting interface devices (see, eg, interface devices 708a and 708b).

Memory module systems 702 and 802 are each shown having at least one interface device (see, eg, interface devices 708a and 708b). As shown, different embodiments of memory modules 702 and 802 may include one interface device (eg, interface device 708a), two interface devices (eg, interface devices 708a and 708b), or more than two interface devices. can have And, as mentioned above, it should be understood that the dashed boxes represent optional components. At least one interface device (see, eg, interface devices 708a and 708b) may be configured to communicate input and output data for each of memory module systems 702 and 802. Input/output data may bypass the processor (e.g., main processor) of each system in which one of memory module systems 702 and 802 is installed (e.g., if one of memory module systems 702 and 802 is installed) interfaces 708a and 708b that are connected to other devices 714 of the system and bypass at least one processor 712 of the system via connections 718a and 718b). In some embodiments, as shown in FIG. 7, input/output data bypasses the data bus (such as the main data bus) of the system in which one of the memory module systems 702 and 802 is installed (e.g., the other of the system). (See interfaces 708a and 708b, which are connected to device 714 and bypass the system's bus 716 (which may include multiple buses) via connections 718a and 718b. It should be understood that the dashed connections represent optional components.

Bus 710 may also be part of a bus (see, e.g., bus 716) of a system in which one of memory module systems 702 and 802 is installed; and connect it to the rest of the system where it is installed. Bus 710 may be separate from bus 716 in some embodiments and may be separate from bus 716 in other embodiments, as illustrated by the dashed line portion of bus 710 that connects the memory module system to bus 716 and the rest of the system. may be connected to bus 716. It should be understood that the dashed connections represent optional connections. One or more of the controllers of memory module systems 702 and 802 (see, e.g., controllers 706a and 706b) communicate via bus 710 and connections that bypass bus 716 (see, e.g., connections 718a and 718b). data can be reconciled.

As shown, the external controller(s) (see, e.g., external controllers 706a and 706b) connect the plurality of memory modules (see, e.g., memory modules 704a, 704b, and 704c) of each of memory module systems 702 and 802. ). In some embodiments of memory module systems 702 and 802, external controller(s) may be configured to coordinate calculations by the controllers of multiple memory modules (e.g., controllers 506a and 506b and memory module 502, 602, and 704a-704c). The external controller(s) may also be configured to coordinate communications by the multiple memory module interface devices (e.g., see interface devices 508a and 508b and memory modules 502, 602, and 704a-704c). Can be done.

Also, as shown, the interface device(s) (see, e.g., interface devices 708a and 708c) are connected to the plurality of memory modules (e.g., memory modules 704a, 704b, and 704c) of each of memory module systems 702 and 802. ). At least one interface device of memory module systems 702 and 802 (see, e.g., interface devices 708a and 708b) may include at least one wireless interface device that communicates at least partially wirelessly, or may include an optical It may also include on-chip optical interconnects that provide communications. Other portions of the interface device(s) of memory module systems 702 and 802 may communicate via wires. At least one interface device of memory module systems 702 and 802 may also be a hybrid interface device with multiple functions and/or channels and channel types. The interface device(s) of memory module systems 702 and 802 may be, include, or be part of a network interface device (such as a wireless network interface device). The interface device(s) of memory module systems 702 and 802 may include at least one wireless interface device, and/or the wired link may include one or more wired and/or wireless networks, peer-to-peer links, Can be configured to communicate via ports, buses, etc.

Also, the multiple memory modules (see, eg, memory modules 704a, 704b, and 704c) may be multiple different types of memory structures. For example, the plurality of memory modules may include one or more DIMMs, one or more SO-DIMMs, one or more RDIMMs, one or more mini-RDIMMs, one or more socketed memory stacks, multiple socket systems on one or more packages, or other types of PoPs for memory, one or more of different types of memory structures or modules, or any combination thereof; may be or include parts.

Additionally, each memory module described herein may be a different type of memory structure. For example, the memory modules described herein are or are DIMMs, SO-DIMMs, RDIMMs, mini-RDIMMs, socketed memory stacks, or other types of PoPs for socketed systems or memory on packages. may be part of or include.

For example, in some embodiments of memory module system 702 or 802, the system may include multiple DIMMs. Each DIMM of the plurality of DIMMs may then include a PCB configured for insertion into a memory slot of an additional PCB that is separate from the plurality of DIMMs. Each DIMM of the plurality of DIMMs also includes a plurality of memory chips coupled to a PCB, a plurality of electrical contacts on opposite sides of the PCB, at least one controller (such as at least one dedicated controller) coupled to the PCB, and a DIMM. at least one interface device configured to communicate input/output data of the computer. The input/output data bypasses the DIMM and at least one processor of the computing device on which the system is installed. And, in such embodiments of systems 702 and 802 with DIMMs, the interface device(s) may be configured to communicate input/output data to at least one other of the plurality of DIMMs.

Also, in such embodiments of systems 702 and 802 with DIMMs, the external controller may be separate from the DIMMs and configured to coordinate calculations by the dedicated controller of the DIMMs. The external controller may also be configured to coordinate communications by interface devices of multiple DIMMs. And, in such embodiments, the additional PCB may include multiple memory slots that are separate from and configured to accept multiple DIMMs. Also, the external controller can be coupled to an additional PCB, which can be a motherboard, and the external controller can include other types of processors, such as a central processing unit (CPU) or a dedicated controller. Can be done.

In some embodiments, at least one controller for each DIMM of the plurality of DIMMs may be a dedicated controller. For example, the at least one controller may be, be part of, or include a GPU, an AI accelerator, an NPU, other types of dedicated controllers, a PIM unit, or any combination thereof. .

In some embodiments, the DIMM interface device(s) of the plurality of DIMMs may include wireless interface devices configured to communicate at least partially wirelessly, or may include optical communications between chips. It may also include on-chip optical interconnects provided. and, in such an example, for each DIMM of the plurality of DIMMs, the DIMM's wireless interface device receives input data of at least one controller and the computing device hosting the system 702 or 802 in which the system is installed. The output data of the controller(s) may be configured to communicate to one or more user interfaces via one or more wireless communication links that bypass the processor of the controller(s). The one or more user interfaces may include a tactile UI (touch), a visual UI (field of view), such as a GUI, an auditory UI (sound), an olfactory UI (smell), an equilibrium UI (balance), and a gustatory UI (taste), or It may include one or more of any type of user interface (UI), including any combination thereof.

In some embodiments, DIMMs may communicate with each other via one or more high speed wireless interfaces. Because the DIMMs may be installed, aligned, and close to each other, high-speed wireless interfaces with close transmitters can be used to transmit data between the DIMMs. Also, wires can connect the DIMMs through a side of each DIMM other than the side that connects the DIMM to the PCB when inserted into the memory slot.

FIG. 9 illustrates an example networked system 900 including at least computing devices 902, 922a, 922b, 922c, and 922d, according to some embodiments of the present disclosure. FIG. 9 also illustrates an example portion of an example computing device 902 that is part of a networked system 900. 9 further illustrates such computing devices as IoT devices, mobile devices, communication network devices, and equipment (e.g., see base station 930), appliances (e.g., see appliance 940), and vehicles (e.g., , vehicle 950).

Computing device 902 and other computing devices (e.g., see computing devices 922a, 922b, 922c, and 922d) of networked system 900 are communicatively coupled to one or more communication networks 920. be able to. The computing device 902 includes at least a bus 906, a controller 908 (such as a CPU), a first memory 910, a network interface 912, a data storage system 914, and other components 916 (such as a GPS component, various types of user interface components, etc.). /O component, and may be any type of component found in a mobile device or computing device, such as sensors and cameras), and a second memory 918 (memory module 502 or 602 or memory module system 702 or 802). may include). Other components 916 may include one or more user interfaces (e.g., GUI, auditory user interface, haptic user interface, etc.), displays, different types of sensors, tactile input/output devices, audio input/output devices, and/or visual input/output devices. It may include an output device, additional application-specific memory, one or more additional controllers (eg, a GPU), or any combination thereof. Bus 906 communicatively couples controller 908 , first memory 910 , network interface 912 , data storage system 914 , and other components 916 , and in some embodiments connects such components to second memory 912 . can be combined with As mentioned above, it should be understood that the dashed boxes and connections represent optional components.

Computing device 902 includes at least a controller 908, a first memory 910, and a second memory 918 (e.g., read only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM), or Rambus dynamic random access memory (RDRAM), static random access memory (SRAM), crosspoint or crossbar memory, crossbar memory, etc.), and a data storage system 914, which includes a bus 906 (multiplex communicate with each other via a network (which may include a bus). In some embodiments, second memory 518 may not communicate via bus 506.

Stated another way, FIG. 9 includes a block diagram of a computing device 902 having a computer system on which embodiments of the present disclosure may operate. In some embodiments, a computer system can include a set of instructions that, when executed, cause a machine to perform at least any one or more of the methods described herein. In such embodiments, the machine may be connected to other machines within a LAN, intranet, extranet, and/or the Internet (e.g., network(s) 920) (e.g., via network interface 912). can do. A machine can operate in the function of a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

Controller 908 represents one or more general purpose processing devices such as a microprocessor, central processing unit, etc. More particularly, the processing device may include a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a single instruction multiple data (SIMD), It may be a processor implementing multiple instruction multiple data (MIMD), or other instruction sets, or a combination of instruction sets. Controller 908 may also be one or more special purpose processing devices such as an ASIC, programmable logic such as an FPGA, a digital signal processor (DSP), a network processor, and the like. Controller 908 is configured to execute instructions to perform the operations and steps described herein. Controller 908 may further include a network interface device, such as a network interface 912, for communicating via one or more communication networks (such as network(s) 920).

Data storage system 914 includes a machine-readable storage medium (also known as a computer-readable medium) having one or more instruction sets or software stored thereon that embodies any one or more of the methods or functions described herein. known). Data storage system 914 can have execution capabilities, such as it can at least partially execute instructions residing on the data storage system. The instructions may also reside completely or at least partially within at least one of the first memory 910 and the second memory 918 and/or within the controller 908 while the computer system executes them. At least one of first memory 910 and second memory 918 and controller 908 also constitute a machine-readable storage medium. First memory 910 may be or include main memory of computing device 902. First memory 910 and second memory 918 can have execution capabilities, such as they can at least partially execute instructions that reside in the memory.

As described above, networked system 900 includes computing devices, each of which may include one or more buses, controllers, memory, network interfaces, storage systems, and other components. can. Additionally, each of the computing devices shown in FIG. 9 and described herein may include, for example, a smartphone, a tablet computer, an IoT device, a smart television, a smart watch, eyeglasses or other smart consumer electronics, an in-vehicle information It may include or be part of a mobile device, such as a system, a wearable smart device, a gaming console, a PC, a digital camera, or any combination thereof. As indicated, the computing device may be connected to at least a local-to-device network such as Bluetooth, a wide area network (WAN), a local area network (LAN), an intranet, a mobile wireless network such as 4G or 5G, an extranet, the Internet. , and/or any combination thereof. In some embodiments, as indicated by dashed line connection 919, second memory 918 is connected to at least one network such that it can communicate separately with other devices via communication network(s) 920. Can contain an interface. For example, a memory module or memory module system of second memory 918 (see, e.g., memory modules 502 and 602 and memory module systems 702 and 802) may be configured such that such components communicate via communication network(s) 920. It can have its own network interface so that it can communicate separately with other devices.

Each of the computing devices described herein may include a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), mobile phone, web appliance, server, network router, switch or A bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying the actions to be performed by that machine, may be or be replaced by it.

Also, although a single machine is illustrated with respect to device 902 shown in FIG. shall be construed to include any collection of machines that execute a set (or sets) of instructions at a time. and each of the illustrated computing devices and computing systems may each include at least a bus and/or motherboard, one or more controllers (such as one or more CPUs), and temporary data storage. It can include memory, at least one type of network interface, a storage system that can include persistent data storage, and/or any combination thereof. In some multi-device embodiments, one device completes some portions of the methods described herein, and then other devices continue with other steps of the methods described herein. You may be able to send completed results to other devices via the network.

Although the memory, controller, and data storage portions are each shown as being a single portion in the example embodiments, each portion may include a single portion or multiple portions capable of storing instructions and performing their corresponding operations. It should be interpreted as including. The term "machine-readable storage medium" also refers to any medium that is capable of storing or encoding a set of instructions for execution by a machine and that causes a machine to perform any one or more of the methods of this disclosure. should be construed as including. Accordingly, the term "machine-readable storage medium" shall be construed to include, but not be limited to, solid state memory, optical media, and magnetic media.

Some portions of the preceding detailed description are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the methods used by those skilled in the data processing arts to most effectively convey the substance of their work to those skilled in the art. An algorithm is here, and generally, considered to be a self-consistent sequence of operations that leads to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

It should be recognized, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure provides a method for manipulating data represented as physical (electronic) quantities within the registers and memory of a computer system, and for manipulating data represented as physical (electronic) quantities within the memory or registers of a computer system or other such information storage systems. can refer to the operations and processes of a computer system, or similar electronic computing device, that convert data into data.

The present disclosure also relates to apparatus for performing the operations herein. The apparatus may be specially configured for the intended use or may include a general purpose computer that can be selectively activated or reconfigured by a computer program stored on the computer. Such computer programs may be stored on any type of disk, such as floppy disks, optical disks, CD-ROMs, and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical The computer readable storage medium may be stored on a computer readable storage medium such as a card or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems may be used programmatically in accordance with the teachings herein, or it may prove advantageous to construct more specialized equipment to perform the methods. The structure of a variety of these systems appears as described in the following description. Additionally, this disclosure is not described with respect to any particular programming language. It should be understood that a variety of programming languages may be used to implement the teachings of this disclosure as described herein.

The present disclosure is presented as a computer program product or software that may include a machine-readable medium having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes in accordance with the present disclosure. be able to. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (eg, a computer). In some embodiments, the machine-readable (e.g., computer-readable) medium includes read-only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory components, etc. machine (e.g., computer) readable storage media;

In the foregoing specification, embodiments of the disclosure have been described with reference to specific exemplary embodiments thereof. It will be apparent that various modifications may be made without departing from the broader spirit and scope of the embodiments of the disclosure as set forth in the claims below. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims (18)

A method,
initiating, at a cellular base station, a shadow calculation of a main calculation to perform on behalf of a mobile device, the main calculation comprising a calculation task, and the shadow calculation being at least a part or derivative of the main calculation; , said starting;
performing the shadow computation by the cellular base station ;
sending the shadow calculation back to the mobile device by the cellular base station;
The method described above. 2. The method of claim 1, comprising transmitting output data of the performed shadow computation by the cellular base station to the mobile device or to another device. 2. The method of claim 1, comprising transmitting output data of the performed shadow computation by the cellular base station to other cellular base stations. 2. The method of claim 1, comprising transmitting the shadow calculation by the cellular base station to other cellular base stations. 5. The method of claim 4, comprising transmitting the shadow calculation by the cellular base station to the other cellular base station when the mobile device is within a threshold distance of the other cellular base station. . 5. The method of claim 4, comprising transmitting the shadow calculation by the cellular base station to the other cellular base station when the other cellular base station generates less network traffic than the cellular base station. Method. 5. The method of claim 4, comprising transmitting the shadow computation by the cellular base station to the other cellular base station when the other cellular base station has greater computing power than the cellular base station. . 5. The method of claim 4, comprising sending the shadow calculation back to the mobile device by the other cellular base station. deriving at least one other shadow calculation from the shadow calculation by the cellular base station;
and transmitting the at least one other shadow calculation by the cellular base station to at least one device other than the base station. 10. The method of claim 9 , comprising transmitting the at least one other shadow calculation by the cellular base station to other cellular base stations. A system for a base station,
a plurality of memory modules, each memory module configured for insertion into a printed circuit board (PCB), each memory module comprising:
multiple memory chips,
at least one graphics processing unit (GPU) coupled to the plurality of memory chips;
initiating a shadow computation of a main computation to perform for a mobile device, wherein the main computation includes a computation task, and the shadow computation is at least a portion or derivative of the main computation; and,
performing the shadow calculation ;
sending the shadow calculation back to the mobile device; and
the plurality of memory modules, the at least one graphics processing unit (GPU) configured to perform the following steps. 12. The system of claim 11 , wherein the at least one GPU is configured to send output data of the performed shadow computation to the mobile device. 12. The system of claim 11 , wherein the at least one GPU is configured to transmit output data of the performed shadow computation to other cellular base stations. 12. The system of claim 11 , wherein the at least one GPU is configured to send the shadow calculations to other cellular base stations. 15. The at least one GPU is configured to send the shadow calculation to the other cellular base station when the mobile device is within a threshold distance of the other cellular base station. System described. The at least one GPU is configured to send the shadow calculation to the other cellular base station when the other cellular base station generates less network traffic than the other cellular base station. The system according to item 14 . 15. The at least one GPU is configured to send the shadow computation to the other cellular base station when the other cellular base station has greater computing power than the cellular base station. System described. A system for a base station,
a plurality of memory modules, each memory module configured for insertion into a printed circuit board (PCB), each memory module comprising:
multiple memory chips,
at least one artificial intelligence (AI) accelerator coupled to the plurality of memory chips;
Receiving a shadow computation of a main computation to perform on behalf of a mobile device, wherein the main computation includes a computation task, and the shadow computation is at least a portion or derivative of the main computation. and,
performing the shadow calculation ;
sending the shadow calculation back to the mobile device; and
the at least one artificial intelligence (AI) accelerator configured to perform the following steps: the plurality of memory modules;

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