JP7380406B2 - Real-time arithmetic processing unit - Google Patents

Description

The present invention relates to a real-time arithmetic processing device.

Conventionally, microcomputers that have been widely used are mainly configured using a CPU, memory, and peripheral circuits. BACKGROUND ART Conventionally, developers have been able to implement various types of processing by implementing desired processing contents in a memory as software, and having a microcomputer execute the software stored in the memory. With this method, the processing can be changed relatively easily by updating the software, ensuring flexibility.

In the case of a conventional general microcomputer, software such as an application, an OS (operating system), and an interrupt handler is implemented in a ROM, and a jump address of an interrupt handler to which a jump is made at the time of an interrupt is encoded in machine code. At this time, the CPU configured in the microcomputer reads out the instruction code in the ROM pointed to by the instruction address bus via the instruction data bus based on the program counter, and stores it in the instruction register in the CPU. The instruction decoder section in the CPU replaces the instruction code stored in the instruction register with various control signals to control general-purpose registers in the CPU, ALU (Arithmetic Logic Unit), RAM, and other peripheral functions. I have to.

As described in Patent Document 1, a CPU multi-core technology has been proposed and provides a method for improving processing performance. However, since the configuration described in Patent Document 1 employs a multi-core configuration, the circuit size conversely increases.

Patent No. 5453825

An object of the present disclosure is to provide a real-time arithmetic processing device that can quickly respond to arithmetic event interrupts while suppressing an increase in circuit scale as much as possible.

According to the first aspect of the invention, the operating system processing section (3) and the arithmetic processing section (6) are configured independently in terms of hardware within the same IC chip. The operating system processing section (3) and the arithmetic processing section (6) can now process independently.

Here, when a calculation event is issued from the outside, the operating system processing unit (3) determines the execution order based on the time axis and priority, issues an execution command to the task related to the calculation event, and manages the tasks. is specialized in. Further, the arithmetic processing section (6) is specialized in executing arithmetic processing according to execution instructions from the operating system processing section (3).

The invention according to claim 1 also includes a message list (4) that stores a start address and an end address associated with a task, and an arithmetic instruction table (5) that stores an arithmetic instruction set.

The arithmetic processing unit includes a program counter block (31) and an arithmetic instruction decoder (32), and upon receiving an instruction to execute a task related to the arithmetic event from the operating system processing unit (3), the arithmetic processing unit receives the start address associated with the task and the arithmetic instruction decoder (32). The end address is received from the message list (4), and arithmetic processing is executed by referring to the arithmetic instruction set in the arithmetic instruction table (5) at the address indicated by the counter value of the program counter (41) from the start address to the end address.

Therefore, the operating system processing unit (3) and the arithmetic processing unit (6) can divide the processing content for each hardware configuration and perform parallel processing. will be able to respond quickly.

In addition, as an interface between the operating system processing unit (3) and the arithmetic processing unit (6), it serves as an interface between the non-execution state (ST1, ST3, ST4) and the execution state (ST2, ST5) of the arithmetic task. A task tray (25) is provided that allows predetermined transitions to be recognized by both the operating system processing unit (3) and the arithmetic processing unit (6).

According to the first aspect of the invention , the task tray allows both the operating system processing section and the arithmetic processing section to recognize a predetermined transition between the non-execution state and the execution state of the arithmetic task. Therefore, the operating system processing unit and the calculation processing unit can recognize the transition between the non-execution state and the execution state of the calculation task in the task tray, and can handshake the non-execution state/execution state of the calculation task with each other.

Hardware configuration diagram of a real-time arithmetic processing device according to the first embodiment Diagram schematically explaining the hardware configuration of the FPUOS functional block State transition diagram in task tray state Electrical configuration diagram schematically explaining the interface structure between the FPUOS functional block and the program counter block Timing chart part 1 explaining the flow of calculation task processing Timing chart part 2 explaining the flow of calculation task processing Timing chart part 3 explaining the flow of calculation task processing Hardware configuration diagram of a real-time arithmetic processing device according to the second embodiment Timing chart schematically showing changes in watchdog timer count value

Hereinafter, some embodiments will be described with reference to the drawings. In the following description, components having the same or similar functions as those described in each embodiment will be denoted by the same or similar symbols, and the description of the second embodiment and subsequent embodiments will be omitted as necessary.

(First embodiment)
Explanatory diagrams of the first embodiment are shown in FIGS. 1 to 7. First, with reference to FIG. 1, the overall hardware configuration of the real-time arithmetic processing device 1 will be described. The real-time arithmetic processing device 1 includes an FPUOS functional block 3 (hereinafter abbreviated as FPUOS3: equivalent to an operating system processing unit), a message list 4, an arithmetic instruction table 5, a WORKER 6 (equivalent to an arithmetic processing unit), and a group of FPU first argument general-purpose registers 7. , the FPU second argument general-purpose register group 8, and the FPU 9 (corresponding to a floating point arithmetic processing unit) are configured within the same ASIC, that is, within the IC chip. Note that a watchdog timer 2 (see FIG. 8) for monitoring the hardware configuration is also provided, but this will be explained in a second embodiment below.

When the real-time arithmetic processing device 1 receives an arithmetic event from an external higher-level scheduler 10, it executes floating-point arithmetic processing according to a binary arithmetic instruction preset in the arithmetic instruction table 5.

The message list 4 stores a task ID, which is an identification code (ID) of a task related to a calculation event, and a start address and an end address associated with the task ID in a list outside the FPUOS 3 (Fig. (See also 2). When the FPUOS 3 specifies a task ID (task ID specification S8 in FIG. 1), it returns the start address and end address corresponding to the specified task ID as the selection result S9 of the message list 4.

Further, in the arithmetic instruction table 5 shown in FIG. 1, arithmetic instruction sets are developed corresponding to the arithmetic instruction table addresses. When the WORKER 6 specifies the arithmetic instruction table address S10 from the program counter block 31 to the arithmetic instruction table 5, the arithmetic instruction set corresponding to the arithmetic instruction table address S10 is returned as an arithmetic instruction set selection result S11.

The FPUOS3 is a block that implements the operating system functions related to the FPU9 using a hardware block in the ASIC. When the external scheduler 10 issues a calculation event, the FPUOS 3 receives the calculation event from the scheduler 10.

The FPUOS 3 determines the execution order of tasks related to calculation events based on the time axis and priority. The FPUOS 3 reads out the calculation start address and the calculation end address from the message list 4 in association with the task ID assigned to the task, and instructs the WORKER 6 to execute the task. See task execution command S5 shown in FIG. Note that the WORKER 6 receives the task execution command S5, and when the execution of the task is completed, returns it as a task completion S6.

Further, the FPUOS 3 is a functional block specialized for instructing the execution of tasks as described above and for managing the tasks being executed by the WORKER 6. The FPUOS 3 functions as an operating system processing unit. Further, the WORKER 6 is a functional block specialized for executing arithmetic processing according to an execution command from the FPUOS 3.

Next, a configuration example of the FPUOS 3 will be described with reference to FIG. 2. The FPUOS 3 includes a power-on reset 21 (POR), an OS state machine 22, a message tray 23, a message queue 24, and a task tray 25, and also includes interfaces 26 to 29 with the message list 4.

The message tray 23 can store n pairs of task ID and priority parameters as task messages MSG, and has a storage area for parameters equal to the number of messages stored in the tray. The task ID indicates the identification number of the task message MSG assigned in the order of input time. The task ID is an identification number that can be expressed using a smaller amount of information than the start address and end address stored in the message list 4. A priority is set for each task message MSG.

The number of messages stored in the tray indicates the total number of task messages MSG stored in the message tray 23. The task message MSG is transferred to the message queue 24 according to the number of messages stored in the tray.
As for the transfer method, each time the task ID and priority parameters are stored in the message tray 23, the FPUOS 3 may perform time-sharing transfer in which the number of messages stored in the tray is incremented, or it may be transferred in parallel in one cycle. It's okay. Further, when the task message MSG is transferred from the message tray 23 to the message queue 24, the FPUOS 3 counts down the number of messages stored in the tray.

The message queue 24 is configured to be able to store n pairs of task messages MSG with parameter combinations of priority, task ID, and status. The task tray 25 has a storage area for parameters such as the task suspension flag, the task tray state TTRAY_ST, the normal start address NTT_STA_ADDR and normal end address NTT_STP_ADDR of the normal task tray NTASK_TRAY, and the priority start address PTT_STA_ADDR and priority end address PTT_STP_ADDR of the priority task tray PTASK_TRAY. has been done. The task tray 25 is provided as an interface between the FPUOS 3 and the WORKER 6, and each parameter secured in the task tray 25 is made recognizable (readable) from both the FPUOS 3 side and the WORKER 6 side.

The task suspension flag is a flag that is set by the FPUOS 3 to indicate that the task is suspended, and is a flag that can be recognized by both the FPUOS 3 and the WORKER 6. The task suspension flag is a flag used during the suspension handshake period (t17 to t18 in FIG. 6) for suspending the calculation task, and the WORKER 6 is not given the authority to set or clear the task suspension flag. First, it is given to the FPUOS3 side.

Further, the task tray state TTRAY_ST represents either a non-execution state representing a state in which the WORKER 6 is not executing a task, or an execution state representing a state in which the WORKER 6 is executing a task.

Specifically, as illustrated in FIG. 3, the task tray state TTRAY_ST includes "task empty state ST1," "normal task execution state ST2," "normal task completed state ST3," "normal task suspended state ST4," and "priority task state ST4." task execution state ST5".

Among these, in the task empty state ST1, the normal task completed state ST3, and the normal task suspended state ST4, the WORKER 6 is in a task non-execution state in which it is not executing any task, and in the normal task execution state ST2 and the normal task suspended state. In state ST4, the WORKER 6 is in a task execution state in which it is executing some task.

The write access right for the task tray state TTRAY_ST is given to both the FPUOS 3 and the WORKER 6, and the task tray state TTRAY_ST is set to be writable and rewritable from both the FPUOS 3 and the WORKER 6.

However, the write access right for the task tray state TTRAY_ST is set to avoid conflict between the FPUOS 3 and the WORKER 6. The write access right for the task tray state TTRAY_ST is on the FPUOS 3 side in the task non-execution state, and on the WORKER 6 side in the task execution state.

The FPUOS 3 is a hardware block related to operating system calculations that executes processing in an event-driven manner, and receives the occurrence of calculation events from the scheduler 10, which is an external upper block that manages calculation events, via the interface 12 (see Figure 1). and accept it.

The FPUOS 3 receives the task message MSG related to the calculation event by writing the task ID, priority, and number of messages stored in the tray in the message tray 23 shown in FIG.

The OS state machine 22 is configured in hardware so that after the power-on reset 21 is released after the power is turned on, the OS state machine 22 cyclically transitions between the following four states as a basic operation. The four states are the Send message (hereinafter abbreviated as Send) state, the Peek message (hereinafter abbreviated as Peek) state, the Dispatch message (hereinafter abbreviated as Disp) state, and the Post processing (hereinafter abbreviated as Post) state. .

The basic flow of normal task processing executed by the WORKER 6 in response to cyclic state transitions by the OS state machine 22 will be described below.
<Send status>
When the OS state machine 22 transitions to the Send state, it transfers the task message MSG received from the outside into the message tray 23 to the message queue 24. At this time, if the message queue 24 is empty, the task messages MSG are stored in order from the head of the message queue 24. Furthermore, if another task message MSG already exists in the message queue 24, the task message MSG is written in chronological order to the number next to the already stored task ID. The message queue 24 has such a first-in, first-out queue structure.

<Peek state>
When the OS state machine 22 finishes transferring the message from the message tray 23 to the message queue 24, it transitions to the Peek state. In the Peek state, the OS state machine 22 determines whether to activate or not, and selects a task message MSG to be activated from the message queue 24.

When the OS state machine 22 determines that there is no task message MSG in the message queue 24 in the Peek state, the OS state machine 22 skips the process and determines that the task message MSG will not be activated.

Conversely, when the task message MSG is stored in the message queue 24, the OS state machine 22 stores the priority parameter, the state parameter, and the queue number of the message queue 24 in the Peek state. The task message MSG to be activated is selected based on and. Even if the priority is the same, the smaller the queue number, the more preferentially the task message MSG is selected.

The priority parameter indicates a parameter indicating multiple levels of priority including low priority and high priority. In this embodiment, an example will be described in which the priority is set to two levels, low priority and high priority, but it may be set to three or more levels. The state parameter indicates the state of the message queue 24, and includes a preparation state (hereinafter referred to as Ready state), an initial state or startup state (hereinafter referred to as Peek state), an execution state (hereinafter referred to as Run state), a standby state (hereinafter referred to as Wait state), and an end state. (hereinafter referred to as Nothing state). States other than the Run state indicate a non-execution state in which the task message MSG is not being executed on the WORKER 6 side.

Normally, the OS state machine 22 selects the task message MSG of the message queue 24 that is in the Ready state, and transitions the state of the selected message queue 24 from the Ready state to the Peek state. The OS state machine 22 selects a task message MSG to be activated by selecting a task ID.

<Disp status>
When the OS state machine 22 finishes selecting the task message MSG to be activated, it transits to the Disp state, transfers the task message MSG selected in the Peek state to the task tray 25, and instructs the WORKER 6 to execute the task message MSG.

In the Disp state, the FPUOS 3 searches the message list 4 for a task ID whose state parameter in the message queue 24 corresponds to the Peek state, and searches the start address and end address associated with the matched task ID. Determine the address.

Then, the OS state machine 22 stores the start address/end address determined in the message list 4 via the interface 27 in the normal start address NTT_STA_ADDR/normal end address NTT_STP_ADDR of the normal task tray NTASK_TRAY in the task tray 25, respectively. do.

The OS state machine 22 then transitions the state of the message queue 24 from the Peek state to the Run state, and transitions the task tray state TTRAY_ST to the "normal task execution state ST2." The WORKER 6 receives the task execution command S5 by polling the task tray state TTRAY_ST.

<Post status>
When the FPUOS 3 finishes issuing the task execution command S5 to the WORKER 6, the OS state machine 22 transitions to the Post state. In the Post state, the FPUOS 3 organizes the message queue 24 as post-processing. Specifically, the FPUOS 3 empties the message queue 24 if there is a task message MSG in the Nothing state in the message queue 24.

On the other hand, while the WORKER 6 is executing an arithmetic task, the task message MSG stored in the message queue 24 never enters the Nothing state. When the WORKER 6 is executing an arithmetic task, the OS state machine 22 passes through the Post state, returns to the Send state, and undergoes a cyclic state transition.

When the WORKER 6 finishes executing the calculation task, the WORKER 6 transitions the task tray state TTRAY_ST to the "normal task completion state ST3". The OS state machine 22 transits to the Disp state, and transitions the state of the message queue 24 being executed from the Run state to the Nothing state. The OS state machine 22 transitions to the Post state. If there is a message queue 24 in the Nothing state in the Post state, the OS state machine 22 empties the message queue 24.

<Explanation of technical significance of using task ID>
Usually, the start address/end address stored in the message list 4 is expressed in multiple bits such as 2^n bits, for example 16 bits or 32 bits. When an address number becomes a relatively large value, an unnecessarily large number of hardware storage units such as registers are required to associate this address address with other information and store it. The scale of the hardware circuit tends to increase.

However, in this embodiment, the OS state machine 22 uses the task ID instead of handling data using the start address/end address itself. The task ID can be expressed with about 1 or 2 bits, and can be expressed with at least an amount of information smaller than the address address of the start address/end address. Therefore, the storage capacity required for the hardware storage section of the message tray 23 and the message queue 24 can be reduced, and the circuit scale of the message tray 23 and the message queue 24 can be suppressed.

<Explanation of the technical significance of using the bank switching interface 28>
In the above configuration, an example was given in which the task ID is about 1 bit or 2 bits, but if the number of types of task ID increases, the amount of information in the task ID increases, and in this case, the amount of information in the message tray 23 and message queue 24 increases. This may lead to an increase in the hardware circuit scale.

In such a case, as shown in FIG. It is desirable to provide a bank information holding area for switching banks of information in list 4. This allows the external scheduler 10 to bank-switch the relationship between the task ID associated with the message list 4 and the start address/end address.

Bank switching information is stored in the bank information holding area of message list 4. The bank switching information is based on a small amount of information, for example, about 1 bit, and the relationship between the task ID and the start address/end address can be changed significantly with a small amount of information. Therefore, by providing a bank switching interface 28 for externally switching banks, the amount of task ID information to be stored can be reduced, and as a result, the hardware circuits configuring the message tray 23 and message queue 24 can be reduced in size. can be converted into

<Detailed explanation of WORKER6>
As illustrated in FIG. 1, the WORKER 6 includes a program counter block 31, an arithmetic instruction decoder 32, and a selector 33. The FPUOS 3 and the WORKER 6 are configured independently in the ASIC in terms of hardware.

The WORKER 6 receives the start address and end address (normal start address NTT_STA_ADDR/normal end address NTT_STP_ADDR, or priority start address PTT_STA_ADDR/priority end address) of the message list 4 and calculation instruction table 5 linked to the task message MSG related to the calculation event from the FPUOS 3. PTT_STP_ADDR), the program counter block 31 is directly controlled. The details of the interface structure between the FPUOS 3 and the program counter block 31 will be described later.

When the WORKER 6 receives an execution command related to an arithmetic task from the FPUOS 3, the WORKER 6 uses the arithmetic instruction decoder 32 to read the arithmetic instruction table 5 from the start address to the end address of the message list 4 that is set in advance in association with the execution instruction of the arithmetic task. Refer to the arithmetic instruction set inside.

The WORKER 6 decomposes the arithmetic instruction set referenced by the arithmetic instruction decoder 32 into an FPU arithmetic instruction S17, argument selection S27 to S28, and FPU first argument general-purpose register group 7, FPU second argument general-purpose register group 8, and Output to FPU9.

The FPU first argument general-purpose register group 7 is composed of a set of registers capable of storing a plurality of arguments, and a register selection selector (none of which is shown) connected to the rear stage of the register set. The register selection selector is also connected to input the output S15 of the selector 33.

The FPU second argument general-purpose register group 8 also includes a set of registers capable of storing a plurality of arguments, and a register selection selector (none of which is shown) connected to the rear stage of the register set. The register selection selector is also connected to input the output S16 of the selector 33.

The selector 33 described above is connected to be able to input external data S13 from the external memory 11. The arithmetic instruction decoder 32 can specify the input external data S13 by specifying the address of the external memory 11 using the external address signal S12. Further, the selector 33 is connected so as to be able to input the floating point calculation result by the FPU 9, the stored value of the FPU first argument general-purpose register group 7, and the stored value of the FPU second argument general-purpose register group 8.

The arithmetic instruction decoder 32 selects the input source and output destination of the selector 33 based on the input arithmetic instruction set of the arithmetic instruction table 5. The selector 33 distributes the above-mentioned input value to the FPU first argument general-purpose register group 7 as an output S15 as the FPU first argument general-purpose register input selection result based on the operation instruction decoder selection S29 inputted from the operation instruction decoder 32. , the output S16 is distributed to the FPU second argument general-purpose register group 8 as the FPU second argument general-purpose register input selection result.

As a result, any register in the FPU first argument general-purpose register group 7 or any register in the FPU second argument general-purpose register group 8 may contain the external data S13 in the external memory 11 or the floating-point operation result by the FPU 9. can be held.

The arithmetic instruction decoder 32 can output the stored value stored in any register of the FPU first argument general-purpose register group 7 to the FPU 9 based on the argument selection S27, or output the output S15 of the selector 33 directly to the FPU 9.

The arithmetic instruction decoder 32 can output the stored value stored in any register of the FPU second argument general-purpose register group 8 to the FPU 9 based on the argument selection S28, or output the output S16 of the selector 33 directly to the FPU 9.

The FPU 9 can use the output arguments of the FPU first argument general-purpose register group 7 and the FPU second argument general-purpose register group 8 to perform operations such as four arithmetic operations, comparisons, and type conversions specified by the FPU operation instruction S17. , which allows floating point arithmetic processing to be performed. The FPU 9 outputs the floating point calculation result as an FPU calculation result S14. The FPU 9 can execute floating point arithmetic tasks using a wide variety of input data as arguments.

The WORKER 6 sequentially executes binary operation processing while updating the program counter 41 (see FIG. 4) of the program counter block 31 for each operation, and when the end address is reached, the WORKER 6 outputs a task completion notification to the FPUOS 3. This allows a series of floating point arithmetic tasks to be completed.

<<Configuration and basic operation of program counter block 31>>
The configuration and basic operation of the program counter block 31 will be explained below with reference to FIG. The program counter block 31 includes a program counter 41 , a match comparison section 42 , a transition detection section 43 , an interruption determination section 44 , a start address selector 45 , and an end address selector 46 .

The start address selector 45 selects either the normal start address NTT_STA_ADDR of the normal task tray NTASK_TRAY or the priority start address PTT_STA_ADDR of the priority task tray PTASK_TRAY based on the state stored in the task tray state TTRAY_ST, and sets the program counter 41 to either one. Outputs the starting address of.

The end address selector 46 selects either the normal end address NTT_STP_ADDR of the normal task tray NTASK_TRAY or the priority end address PTT_STP_ADDR of the priority task tray PTASK_TRAY based on the state stored in the task tray state TTRAY_ST, and causes the match comparison unit 42 to select either one. Output the end address.

The transition detection unit 43 detects that the task tray state TTRAY_ST has transitioned from the "normal task empty state ST1" to the "normal task execution state ST2" and from the "normal task suspended state ST4" to the "priority task execution state ST5". The load command S33 is detected and outputted to the program counter 41 at these timings.

The program counter 41 loads a start address through the start address selector 45 by inputting the load command S33, starts counting sequentially from the start address, outputs the counted address counter value to the match comparison unit 42, and also outputs the operation command The counted address counter value is outputted to table 5 as arithmetic instruction table address S10. Thereby, the arithmetic instruction decoder 32 can decode the arithmetic instruction by referring to the arithmetic instruction set selection result S11 corresponding to the arithmetic instruction table address S10.

On the other hand, the match comparison unit 42 determines whether the address counter value of the program counter 41 matches the end address selected by the end address selector 46, and when outputting the end address match signal S32, changes the task tray state TTRAY_ST. Transition the state of.

At this time, as illustrated in FIG. 3, if the task tray state TTRAY_ST is the "normal task execution state ST2", the task tray state TTRAY_ST transitions to the "normal task completion state ST3" by the instruction from the match comparison unit 42. Further, if the task tray state TTRAY_ST is the "priority task execution state ST5", the task tray state TTRAY_ST transitions to the "normal task suspension state ST4" by a command from the match comparison unit 42.

Furthermore, the interruption determination unit 44 determines whether to continue or interrupt the currently executing task based on the set/reset state of the task interruption flag. The interruption determination unit 44 checks the operation instruction set selection result S11 output from the operation instruction table 5 after the timing when the task interruption flag is set.

Further, the interruption determination unit 44 determines an interruption address based on the confirmed arithmetic instruction set, and after the address counter value of the program counter 41 reaches the interruption address, saves the interruption address to a storage area that normally stores the start address NTT_STA_ADDR. let The storage area in which the interruption address is saved is not limited to the storage area for the normal start address NTT_STA_ADDR; for example, a separate register may be provided inside the program counter block 31 to save the interruption address.

Then, the interruption determination unit 44 outputs WORKER interruption completion S31 and causes the task tray state TTRAY_ST of the task tray 25 to transition from the "normal task execution state ST2" to the "normal task interruption state ST4."

The transition detection unit 43 triggers and outputs the restart load signal S30 when the task tray state TTRAY_ST transitions from the "normal task suspended state ST4" to the "normal task execution state ST2." The transition detection unit 43 causes the program counter 41 to reload the interruption address that was saved in the storage area where the normal start address NTT_STA_ADDR is stored at the time of interruption by the trigger output of the restart load signal S30.

Then, the arithmetic instruction decoder 32 resumes decoding the arithmetic instruction code related to the normal task indicated by the count value of the program counter 41, and the FPU 9 resumes execution of the arithmetic processing related to the normal task. The subsequent flow is the same as described above.

Next, the overhead reduction effect of FPUOS3 will be explained together with a comparative example.
<Explanation of comparative example>
In conventional microcontrollers, when an interrupt occurs while an application is not being processed, it jumps to the interrupt vector, jumps to interrupt handler processing, and at the beginning of interrupt handler processing, registers such as general-purpose registers, status registers, and the program counter of the jump source, etc. A context switch is performed at the time of an interrupt to save information for returning to the point of interruption.

After that, the interrupt handler selects a task according to each interrupt as its main process, sends a message to the OS about the selected task, and returns to the source of interruption by performing a context switch upon return as post-processing of the interrupt handler. . Thereafter, a message is received within the OS and an application task is started.

When the system executes an application task, it performs a context switch at the start of the application to save information to return to the startup source, and then executes the main processing of the application task.

When an interrupt occurs during the execution of a high-priority task, a jump is made to the interrupt handler processing as described above, a context switch is performed at the time of the interrupt, and as the main processing of the interrupt handler, tasks are selected according to various interrupts, and the OS It sends a message to the selected task, performs a context switch on return as post-processing of the interrupt handler, and returns to the source of interruption.

A typical microcomputer is structured such that when an interrupt occurs, application task processing is interrupted for the overhead time of context switching at the time of the interrupt and return, and the interrupt handler processing time. Therefore, the task processing of the application is interrupted when an interrupt occurs, resulting in a decrease in the speed of task processing.

<Explanation of operation of this embodiment>
In contrast, in this embodiment, the FPUOS 3 and the WORKER 6 are configured independently in terms of hardware. Therefore, the application task can be processed without interrupting the execution task, and the overhead time of the context switch at the time of interrupt and return can be reduced.

A detailed explanation of this processing operation will be given below. Figure 5 shows a case where a low-priority (equivalent to second priority) arithmetic event occurs while WORKER6 is executing a high-priority (equivalent to first priority) arithmetic task. It shows.

First, when a high-priority calculation event occurs while the WORKER 6 is waiting to execute a calculation task, the FPUOS 3 associates the task ID and priority in the message tray 23 with the OS state machine 22. Stores task message MSG1. Here, the high priority task message MSG is defined as task message MSG1.

The storage timing t1 of the task message MSG1 shown in FIG. 5 is assumed to be after the Send message state (hereinafter abbreviated as Send state) of the OS state machine 22. In this case, the OS state machine 22 transitions from Peek message state (hereinafter abbreviated as Peek state), Dispatch message state (hereinafter abbreviated as Disp state), and Post processing state (hereinafter abbreviated as Post state) to the next state after transition. At timing t2 in the Send state, the task message MSG1 is transferred from the first tray No. 1 of the message tray 23 to the message queue MQ1, and the first tray No. 1 of the message tray 23 is cleaned to an empty state.

The OS state machine 22 transitions the state of the message queue MQ1 from Ready to the next state, Peek state, at timing t2, and determines the activation task. The OS state machine 22 selects the task message MSG1 to be activated from the message queue 24 in the Peek state. Here, the explanation will be given assuming that task message MSG1 is selected. The OS state machine 22 transits to the Disp state at timing t3, and starts the task message MSG1 selected in the Peek state and waiting to be started.

At timing t4, the OS state machine 22 transitions the state of the task message MSG1 related to the message queue MQ1 from the Peek state to the Run state, and also changes the start address and end address of the operation instruction table 5 of the task ID linked to the task message MSG1. Search for the address in message list 4.

Then, the OS state machine 22 reads the start address and end address via the interface 27, stores them in the normal start address NTT_STA_ADDR and normal end address NTT_STP_ADDR of the normal task tray NTASK_TRAY in the task tray 25 of the FPUOS 3, and sets the task tray state TTRAY_ST to " A transition is made from the "normal task empty state ST1" to the "normal task execution state ST2."

On the WORKER 6 side, when the task tray state TTRAY_ST transitions from "normal task empty state ST1" to "normal task execution state ST2", the contents of the operation from the normal start address NTT_STA_ADDR to the normal end address NTT_STP_ADDR are read from the operation instruction table 5. Meanwhile, floating-point binary operations are sequentially processed using the FPU 9, the FPU first argument general-purpose register group 7, and the FPU second argument general-purpose register group 8.

When a low-priority calculation event occurs at timing t5 while the WORKER 6 is executing a high-priority calculation task, a low-priority task message MSG2 is stored in the first tray No. 1 of the message tray 23 in the FPUOS 3. . Here, the low-priority task message MSG is designated as task message MSG2.

After that, even if the OS state machine 22 is placed in the Send state, the message queue MQ1 is not in the empty state. Therefore, the OS state machine 22 transfers the task message MSG2 to the message queue MQ2 at timing t6, and also cleans the first tray No. 1 of the message tray 23 to an empty state. Subsequently, when the OS state machine 22 enters the Peek state, it tries to select a startup task, but since a high-priority calculation task is already being executed, it does nothing in the Peek state and shifts to the Disp state.

At this time, on the FPUOS3 side, since the task tray state TTRAY_ST is maintained in the normal task execution state ST2, it can be understood that the task message MSG being executed on the WORKER6 side is the task message MSG1.

Furthermore, the FPUOS 3 is configured by hardware independent of the WORKER 6. Therefore, even if a low-priority calculation event occurs while WORKER 6 is executing a high-priority calculation task, WORKER 6 suspends execution of the high-priority calculation task after timing t5. High-priority computational tasks can be processed intensively without any problems.

When the WORKER 6 is executing a high-priority calculation task that has the highest priority, the FPUOS 3 prevents the low-priority calculation task from being sent to the WORKER 6 as an execution command. The calculation task can be processed at the fastest speed without interrupting the priority calculation task.

Next, the effect of suppressing processing overhead time by the FPUOS 3 will be explained using other execution examples. In the following, as illustrated in Figure 6, while a calculation task with a low priority (equivalent to the 3rd priority) lower than the highest priority is being executed, a calculation task with a higher priority (equivalent to the 4th priority) is executed. An overview of the operation will be explained using an example of the behavior when a calculation event occurs.

When the scheduler 10 issues a low-priority calculation event while the WORKER 6 is waiting in an unprocessed state, a message containing the task ID and priority of the task to be executed in the low-priority calculation event is sent. It is stored in the tray 23.

As shown in FIG. 6, the storage timing t11 of the task message MSG1 related to a low-priority calculation event in the message tray 23 has passed the Send state of the OS state machine 22. Therefore, the OS state machine 22 transfers the task message MSG1 from the message tray 23 to the message queue MQ1 at the end timing of the next Send state after transitioning through the Peek state, Disp state, and Post state, and also transfers the task message MSG1 from the message tray 23 to the message queue MQ1. The first tray No. 23 is cleaned to an empty state.

The OS state machine 22 transitions the state of the message queue MQ1 from Ready to the next state, Peek state, at timing t12, and determines the activation task. The OS state machine 22 selects an activation task from the message queue 24 in the Peek state. The OS state machine 22 transits to the Disp state at timing t13, and starts the task selected in the Peek state and waiting to be started.

The OS state machine 22 transitions the state of the task message MSG1 of the message queue MQ1 from the Peek state to the Run state at timing t14, and also changes the start address and end address of the operation instruction table 5 linked to the task ID of the message queue MQ1. search for.

Then, the OS state machine 22 reads the start address and end address via the interface 27, stores them in the normal start address NTT_STA_ADDR and the normal end address NTT_STP_ADDR of the normal task tray NTASK_TRAY of the task tray 25 of the FPUOS 3, and sets the task tray state TTRAY_ST to "normal task". A transition is made from the "empty state ST1" to the "normal task execution state ST2."

On the WORKER 6 side, when the task tray state TTRAY_ST transitions from "normal task empty state ST1" to "normal task execution state ST2", the contents of the operation from the normal start address NTT_STA_ADDR to the normal end address NTT_STP_ADDR are read from the operation instruction table 5. Meanwhile, floating-point binary operations are sequentially processed using the FPU 9, the FPU first argument general-purpose register group 7, and the FPU second argument general-purpose register group 8.

<Outline of operation of program counter block 31>
When the OS state machine 22 is in the Disp state, the program counter block 31 shown in FIG. 4 loads the normal start address NTT_STA_ADDR into the program counter 41 at the timing when the transition detection unit 43 outputs the load command S33.

At this loading timing, the task tray state TTRAY_ST is set to the "normal task execution state ST2." Therefore, the start address selector 45 selects the storage area of the normal start address NTT_STA_ADDR, and loads the normal start address NTT_STA_ADDR into the program counter 41. On the other hand, the end address selector 46 selects the normal end address NTT_STP_ADDR stored in the normal task tray NTASK_TRAY, and causes the match comparison unit 42 to input the normal end address NTT_STP_ADDR.

The arithmetic instruction decoder 32 specifies the address pointed to by the program counter 41 in the arithmetic instruction table 5 and decodes the arithmetic instruction code. The program counter 41 sequentially decodes the arithmetic instruction codes while referring to the arithmetic instruction table 5 by advancing the count in accordance with the clock input, and the FPU 9 executes the arithmetic instructions up to the normal end address NTT_STP_ADDR.

<Issue a high-priority calculation event while a low-priority calculation event is being executed>
On the other hand, when the WORKER 6 generates a high-priority calculation event at timing t15 while executing a low-priority calculation task after timing t14, the FPUOS 3 lowers the task related to the high-priority calculation event. An execution command is given to the WORKER 6 with priority over the task related to the priority calculation event.

At this time, the external scheduler 10 stores the high priority task message MSG2 in the first tray No.1 of the message tray 23. Thereafter, when the OS state machine 22 enters the Send state, since the message queue MQ1 is not empty, it transfers the task message MSG2 to the message queue MQ2 at timing t16, and cleans the message tray 23 to an empty state.

Subsequently, when the OS state machine 22 enters the Peek state, it tries to select the task message MSG to be activated, but since the WORKER 6 is in the state of executing the low priority task message MSG1, the message queue MQ2 changes to the Ready state. The FPUOS 3 sets the task suspension flag when the state of the OS state machine 22 is in the Peek state.

By setting the task suspension flag, the FPUOS 3 instructs the WORKER 6 to suspend the low-priority task message MSG1 being executed, and performs a handshake to suspend the low-priority task message MSG1. The OS state machine 22, which has been cyclically transitioning, is held in the Disp state during the interrupted handshake period t17 to t18.

<Calculation execution using WORKER6>
After timing t17 when the FPUOS 3 sets the task suspension flag, the WORKER 6 recognizes the task suspension flag. The WORKER 6 refers to the arithmetic instruction table 5 and confirms the arithmetic instruction set selection result S11. Then, at timing t18, the WORKER 6 determines the interruption address at a well-defined timing that allows temporary interruption of the arithmetic instruction, completes the processing interruption, and saves the determined interruption address. At this time, the WORKER 6 saves the interruption address to the storage area of the task tray 25 for the normal start address NTT_STA_ADDR.

Further, the interruption determination unit 44 transitions the task tray state TTRAY_ST from the "normal task execution state ST2" to the "normal task interruption state ST4" via WORKER interruption completion S31.

On the FPUOS 3 side, the FPUOS 3 waits for a response from the WORKER 6, which operates independently of the FPUOS 3, to interrupt the arithmetic processing. The FPUOS 3 determines that the WORKER 6 has interrupted the calculation execution when the task tray state TTRAY_ST has transitioned from the "normal task execution state ST2" to the "normal task suspension state ST4."

At timing t18, the FPUOS3 transitions the state of the message queue MQ1 from the Run state to the Wait state, restarts the cyclic transition from the Disp state, and transitions to the Post state.

During the interrupted handshake period t17-t18 between the FPUOS3 and the WORKER6, the OS state machine 22 remains in the Disp state. Since the OS state machine 22 does not cyclically change the state and remains in the Disp state, the FPUOS 3 can immediately respond to an interruption response related to the execution of a calculation task by the WORKER 6. This makes it possible to suppress an increase in task interruption overhead time.

Thereafter, when the OS state machine 22 resumes cyclic state transition and transitions to the Peek state, the FPUOS 3 clears the task suspension flag at timing t19.

Further, the OS state machine 22 changes the state of the message queue MQ2 in which the high-priority task message MSG2 is stored from the Ready state to the Peek state, makes it wait for task activation, and then changes it to the Disp state.

Normally, the OS state machine 22 stores the start address and end address of the message list 4 in the task tray 25 in the Disp state. However, in the current state, the task tray state TTRAY_ST is the "normal task interruption state ST4", so the interruption address remains in the normal task tray NTASK_TRAY.

The FPUOS 3 searches the message list 4 for the start address/end address of the operation instruction table 5 of the task ID associated with the Peek state of the message queue 24, and sends the searched start address/end address via the interface 27. and read it out.

The FPUOS3 stores the read start address/end address in the storage area of the priority start address PTT_STA_ADDR and priority end address PTT_STP_ADDR of the priority task tray PTASK_TRAY at timing t20, and changes the task tray state TTRAY_ST from the "normal task suspended state ST4" to the "priority task tray state ST4". "Task execution state ST5". The OS state machine 22 maintains the Disp state and polls for the task tray state TTRAY_ST to return to the "normal task suspension state ST4."

<Task execution using WORKER6>
On the WORKER 6 side, when the task tray state TTRAY_ST transitions to the "priority task execution state ST5", the start address selector 45 selects the priority start address PTT_STA_ADDR, and the end address selector 46 selects the priority end address PTT_STP_ADDR.

The transition detection unit 43 has a function of outputting a load command S33 when the task tray state TTRAY_ST transitions from the "normal task suspension state ST4" to the "priority task execution state ST5", and by the trigger output of this load command S33. Load the priority start address PTT_STA_ADDR into the program counter 41.

At this loading time, the task tray state TTRAY_ST has transitioned to the "priority task execution state ST5." Since the start address selector 45 selects the priority start address PTT_STA_ADDR, the program counter 41 loads the priority start address PTT_STA_ADDR. Thereafter, the arithmetic instruction decoder 32 decodes the arithmetic instruction code in the arithmetic instruction table 5 pointed to by the program counter 41.

Therefore, upon transition to the "priority task execution state ST5", the WORKER 6, while referring to the operation instruction table 5, determines the operation contents according to the addresses from the priority start address PTT_STA_ADDR to the priority end address PTT_STP_ADDR, Using the general-purpose register group 7 and the FPU second argument general-purpose register group 8, floating-point binary operations are sequentially processed. This allows high-priority calculation tasks to be activated with minimal latency.

When the high-priority calculation task is executed up to the priority end address PTT_STP_ADDR, the program counter 41 matches the priority end address PTT_STP_ADDR, and the match comparison unit 42 becomes active. The match comparison unit 42 causes the task tray state TTRAY_ST to transition from the "priority task execution state ST5" to the "normal task suspension state ST4" by outputting the end address match signal S32.

FIG. 7 is a timing chart following FIG. 6. When the WORKER 6 completes execution from the priority start address PTT_STA_ADDR to the priority end address PTT_STP_ADDR, it transitions the task tray state TTRAY_ST from the "priority task execution state ST5" to the "normal task suspension state ST4" at timing t21 in FIG.

On the other hand, the OS state machine 22 remains in the Disp state at least while the WORKER 6 is executing a high priority calculation task. Therefore, by confirming that the task tray state TTRAY_ST has transitioned to the "normal task suspension state ST4", it is possible to immediately know that the WORKER 6 has finished executing the high priority calculation task.

After confirming that the task tray state TTRAY_ST has transitioned to the "normal task suspension state ST4," the OS state machine 22 transitions the state of the message queue MQ2 from the Run state to the Nothing state. The OS state machine 22 restarts the cyclic transition and transitions to the Post state.

The FPUOS 3 limits the function of transitioning the message queue MQ2 from the Run state to the Nothing state to any fixed state of the OS state machine 22, here the Disp state.

Furthermore, if the OS state machine 22 continues the cyclic transition without waiting in the Disp state and the WORKER 6 completes task processing at a timing other than the Disp state, it is necessary to wait for the cyclic transition until the next Disp state. This results in poor real-time responsiveness.

In this embodiment, since the OS state machine 22 remains in the Disp state while the WORKER 6 is executing the high-priority calculation task, the FPUOS 3 determines the timing when the WORKER 6 finishes processing the high-priority calculation task. This state transition can be accepted at t21 and can be dealt with immediately.

In this way, while the WORKER 6 is executing a high-priority arithmetic task, the state of the OS state machine 22 is maintained in the Disp state, so when the WORKER 6 completes execution of the high-priority arithmetic task, the OS state machine 22 22 can immediately recognize that WORKER 6 has completed execution. As a result, the OS state machine 22 can respond immediately, and an increase in task completion overhead time can be suppressed.

Thereafter, when the OS state machine 22 restarts the cyclic transition and transits to the Peek state again, at timing t23, the OS state machine 22 transitions the suspended state of the message queue MQ1 from the Wait state to the Peek state. This causes the OS state machine 22 to make a cyclic transition to the Disp state after entering the task activation wait state. The OS state machine 22 transitions the state of the message queue MQ1 from the Peek state to the Run state in the Disp state at timing t23.

Normally, when the OS state machine 22 transitions to the Disp state, it stores the start address and end address from the message list 4 in the normal task tray NTASK_TRAY, but at timing t23, the task tray state TTRAY_ST is the "normal task suspended state ST4". , an interruption address is stored in the normal start address NTT_STA_ADDR of the task tray 25.

Therefore, the OS state machine 22 skips the address search process in the message list 4, transitions the task tray state TTRAY_ST from the "normal task suspension state ST4" to the "normal task execution state ST2", and the OS state machine 22 makes a cyclic transition. resume.

When the task tray state TTRAY_ST of the task tray 25 transitions from the "normal task suspended state ST4" to the "normal task execution state ST2," the transition detection unit 43 on the WORKER 6 side changes from the "normal task suspended state ST4" to the "normal task execution state ST2'' is detected, and a restart load signal S30 is output at this timing.

When the restart load signal S30 is triggered, the interruption address saved at the time of interruption is loaded into the program counter 41. At the time of restart loading, the task tray state TTRAY_ST is the "normal task execution state ST2." Therefore, the start address selector 45 selects the normal start address NTT_STA_ADDR, and loads the interruption address saved in the storage area of the normal start address NTT_STA_ADDR into the program counter 41. When the interrupt address is loaded into the program counter 41, the operation instruction codes in the operation instruction table 5 are sequentially executed starting from the interruption address.

On the other hand, since the end address selector 46 also selects the normal end address NTT_STP_ADDR, the arithmetic instruction decoder 32 reads the arithmetic instruction table 5 indicated by the program counter 41 and sequentially executes them up to the normal end address NTT_STP_ADDR.

When the match comparison unit 42 determines that the address value indicated by the program counter 41 matches the normal end address NTT_STP_ADDR, it transitions the task tray state TTRAY_ST from the "normal task execution state ST2" to the "normal task completion state ST3." This allows the low-priority arithmetic task processing to be restarted and completed.

After timing t24, the WORKER 6 reads the operation contents according to the execution address from the interruption address to the normal end address NTT_STP_ADDR from the operation instruction table 5, and reads the contents of the operation according to the execution address from the interruption address to the normal end address NTT_STP_ADDR, and sends the contents to the FPU 9, the FPU first argument general-purpose register group 7, and the FPU second argument general-purpose register group. 8 can be used to sequentially process binary floating-point operations.

While the WORKER 6 is executing a high-priority arithmetic task, the OS state machine 22 is held in the Disp state, so when the WORKER 6 completes executing the high-priority arithmetic task, the OS state machine 22 is executed by the WORKER 6. You can immediately recognize that it has been completed. As a result, the OS state machine 22 can respond immediately, and an increase in task completion overhead time can be suppressed.

<Comparative example>
Multitasking OSs that are currently popular are not suitable for high-speed calculations because they generate processing overhead, taking into consideration that context switches and the like occur when tasks of multiple processes collide.

<Summary of this embodiment>
In this embodiment, the FPUOS 3 and the WORKER 6 are configured separately and independently in terms of hardware. Therefore, the application task can be processed without interrupting the high-priority execution task, and the overhead time of the context switch at the time of interrupt and return can be reduced.
In addition, when the WORKER 6 is executing a high-priority arithmetic task that has the highest priority, the FPUOS 3 prevents the low-priority arithmetic task from being transferred to the WORKER 6 as an execution command. The arithmetic task can be processed at the fastest speed without interrupting the high-priority arithmetic task.
In addition, in this embodiment, during the interrupted handshake period t17 to t18 between the FPUOS 3 and the WORKER 6, the OS state machine 22 is kept in the Disp state while the message queue MQ1 related to the low priority calculation task is kept in the Run state. remains in place. Since the OS state machine 22 does not cyclically change the state and remains in the Disp state and maintains the message queue 24 in the Run state, the FPUOS 3 responds to the interruption response related to the execution of the calculation task by the WORKER 6. The message queue 24 can be immediately changed to the Wait state, allowing immediate response. This makes it possible to suppress an increase in task interruption overhead time.

Furthermore, in this embodiment, during the period t20 to t21 from when the WORKER 6 starts executing the task message MSG2 related to the high-priority calculation task to when the task tray state TTRAY_ST transitions to the "normal task suspension state ST4", The FPUOS3 executes state control in which the OS state machine 22 remains in the Disp state while maintaining the message queue MQ2 associated with the high priority task message MSG2 in the Run state. Therefore, when the WORKER 6 completes execution of a high-priority arithmetic task, the OS state machine 22 can immediately recognize that the WORKER 6 has completed execution. As a result, the OS state machine 22 can respond immediately, and an increase in task completion overhead time can be suppressed.

(Third embodiment)
Additional explanatory diagrams of the third embodiment are shown in FIGS. 8 and 9. When conventional microcontrollers perform both OS processing and application processing sequentially using a single piece of hardware, it is possible to determine whether a deadlock has occurred by monitoring whether the OS periodically transitions to a predetermined state. can. In this case, if one watchdog timer is provided, it can be determined whether a deadlock has occurred.

However, in the configuration of the first embodiment described above, since the FPUOS 3 and the WORKER 6 are configured independently in terms of hardware, even if only one watchdog timer is provided, one of the hardware configurations (for example, FPUOS 3 ) can be monitored, but the other hardware configuration (for example, WORKER 6) cannot be monitored.

Therefore, as shown in FIG. 8, the watchdog timer 2 for operation monitoring includes an FPUOS monitoring watchdog timer 2a (corresponding to an operating system processing monitoring WDT) for monitoring the operation of the FPUOS 3, and an operation monitoring watchdog timer 2a for monitoring the operation of the WORKER 6. It is desirable to independently provide a WORKER monitoring watchdog timer 2b (corresponding to an arithmetic processing monitoring WDT) to monitor the FPUOS 3 and WORKER 6, respectively. As a result, the operations of the hardware configuration of the FPUOS 3 and the hardware configuration of the WORKER 6 can be independently monitored.

The FPUOS monitoring watchdog timer 2a (hereinafter referred to as FPUOS monitoring WDT 2a) is constituted by a free-run counter, and counts the count value in free-run. Every time the OS state machine 22 cyclically transitions from the Send state to the Post state, the FPUOS monitoring WDT 2a clears the count value.

When the OS state machine 22 deadlocks and the count value of the FPUOS monitoring WDT 2a exceeds the FPUOS monitoring WDT threshold, the FPUOS monitoring WDT 2a outputs a WDT error to the outside.

On the other hand, the WORKER monitoring WDT 2b is constituted by a free run counter, and free runs are counted in the "normal task execution state ST2". The WORKER monitoring WDT 2b is cleared when the task tray state TTRAY_ST of the FPUOS 3 becomes other than the "normal task execution state ST2". When the count value of the WORKER monitoring WDT 2b exceeds a predetermined WORKER monitoring WDT threshold, the WORKER monitoring WDT 2b outputs a WDT error.

In FIG. 9, a solid line indicates a case where the WORKER 6 normally ends the calculation task from the "normal task execution state ST2" indicating that the WORKER 6 is executing the normal calculation task. Furthermore, a broken line indicates a case where the WORKER 6 abnormally terminates the calculation task from the "normal task execution state ST2".

In the solid line case shown in FIG. 9 in which the "normal task execution state ST2" ends normally, the WORKER 6 continues to operate normally without going out of control. At this time, the WORKER 6 and the FPU 9 complete the calculation task from the normal start address NTT_STA_ADDR to the normal end address NTT_STP_ADDR. Then, the program counter block 31 in the WORKER 6 rewrites the task tray state TTRAY_ST from the "normal task execution state ST2" to the "normal task completion state ST3." At this time, the watchdog timer 2 clears the WORKER monitoring WDT 2b at timing t31. Therefore, no WDT error is output.

However, if the process does not end normally in the "normal task execution state ST2", the task tray state TTRAY_ST continues to be held as the "normal task execution state ST2", so that the count value of the WORKER monitoring WDT 2b will eventually exceed the WORKER monitoring WDT threshold. Then, the watchdog timer 2 outputs a WDT error at timing t32. Thereby, deadlock of the WORKER 6 can be avoided, and runaway of the WORKER 6 can be monitored.

Note that the FPUOS monitoring WDT threshold is determined from timing t17 when the FPUOS 3 sets the task suspension flag in the task tray 25 to timing t18 when the WORKER 6 side transitions the task tray state TTRAY_ST to the "normal task suspension state ST4" in which the calculation task is suspended. It is desirable to set a threshold value that can count at least a time exceeding time T1 (see FIG. 6). That is, it is desirable to set the FPUOS monitoring WDT threshold to a threshold that can count a time equal to or longer than the time T1 plus a predetermined first margin time (first condition).

Moreover, the FPUOS monitoring WDT threshold is set to a threshold that can count the time that exceeds at least the time T2 (see FIGS. 6 and 7) from when the WORKER 6 starts executing a high-priority calculation task to when the execution is completed. This is desirable. That is, it is desirable that the FPUOS monitoring WDT threshold is set to a value that can count the time obtained by adding a predetermined second margin time to time T2 (second condition). The FPUOS monitoring WDT threshold value is preferably a threshold value that satisfies both the first condition and the second condition described above.

According to this embodiment, the watchdog timer 2 has a function of monitoring the FPUOS 3 and the WORKER 6, so that the FPUOS 3 and the WORKER 6 can be independently monitored. In addition to being able to monitor the operation of the FPUOS 3, deadlock and runaway of the WORKER 6 can be monitored and abnormalities can be detected.

(Other embodiments)
The present invention is not limited to the above-mentioned embodiment, and for example, the following modifications or expansions are possible.
Floating point operations are not limited to single precision, double precision, etc. Furthermore, although the embodiment has been described with reference to floating point arithmetic processing, the present invention is not limited to this, and may be applied to, for example, fixed point arithmetic processing.

The configurations and functions of the plurality of embodiments described above may be combined. A mode in which a part of the above embodiment is omitted as long as the problem can be solved can also be regarded as an embodiment. In addition, all conceivable aspects can be regarded as embodiments as long as they do not deviate from the essence of the invention specified by the words written in the claims.

Although the present invention has been described based on the embodiments described above, it is understood that the present invention is not limited to the embodiments or structures. The present invention also includes various modifications and equivalent modifications. In addition, various combinations and configurations, as well as other combinations and configurations that include one, more, or fewer elements, fall within the scope and spirit of the present invention.

In the drawing, 1 is a real-time arithmetic processing unit, 3 is an FPUOS (operating system processing unit), 4 is a message list, 5 is an arithmetic instruction table, 6 is a WORKER (arithmetic processing unit), 25 is a task tray, TTRAY_ST is a task tray state, 31 32 is a program counter block, 32 is an arithmetic instruction decoder, and 41 is a program counter.

Claims (4)

When a calculation event is issued from the outside, an operating system processing unit (3 )and,
an arithmetic processing unit (6) specialized for executing arithmetic processing according to execution instructions of the operating system processing unit (3);
Each is configured independently on the hardware within the same IC chip,
a message list (4) that stores a start address and an end address associated with the task;
an arithmetic instruction table (5) that stores an arithmetic instruction set;
The arithmetic processing unit includes a program counter (41) and an arithmetic instruction decoder (32), and upon receiving an instruction to execute the task related to the arithmetic event from the operating system processing unit (3), the arithmetic processing unit executes the execution command associated with the task. Receive the start address and the end address from the message list (4), and refer to the arithmetic instruction set of the arithmetic instruction table (5) at the address indicated by the counter value of the program counter (41) from the start address to the end address. It performs arithmetic processing by
As an interface between the operating system processing unit (3) and the arithmetic processing unit (6),
A predetermined transition between the non-execution state (ST1, ST3, ST4) and the execution state (ST2, ST5) of the task is determined from the operating system processing unit (3) and the arithmetic processing unit (6). A real-time arithmetic processing device equipped with a task tray (25) that allows both to be recognized . The task tray includes a storage area for a task tray state (TTRAY_ST) that can be written by both the operating system processing unit (3) and the arithmetic processing unit,
The write access right for the task tray state is set to avoid conflict between the operating system processing unit (3) and the arithmetic processing unit (6),
When the task is not executed by the arithmetic processing unit, access rights are granted to the operating system processing unit (3),
The real-time arithmetic processing device according to claim 1 , wherein when the task is executed by the arithmetic processing unit, access rights are granted to the arithmetic processing unit. While the arithmetic processing unit (6) is executing the task with the first priority, which is the highest priority, the operating system processing unit (3) performs an operation on a task with a second priority lower than the first priority. If an event occurs,
3. The real-time arithmetic processing device according to claim 2, wherein said operating system processing section does not transfer said task of said second priority to said arithmetic processing section as an execution command. While the arithmetic processing unit (6) is executing the task with a third priority lower than the highest priority, the operating system processing unit (3) is executed with a task related to a fourth priority higher than the third priority. When a calculation event occurs,
3. The real-time arithmetic processing device according to claim 2, wherein the operating system processing section instructs the arithmetic processing section to execute the task of the fourth priority over the third priority.

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