JP7361192B2 - ハードウェア・アクセラレータとインターフェースするための方法 - Google Patents

ハードウェア・アクセラレータとインターフェースするための方法 Download PDF

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JP7361192B2
JP7361192B2 JP2022500757A JP2022500757A JP7361192B2 JP 7361192 B2 JP7361192 B2 JP 7361192B2 JP 2022500757 A JP2022500757 A JP 2022500757A JP 2022500757 A JP2022500757 A JP 2022500757A JP 7361192 B2 JP7361192 B2 JP 7361192B2
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ピヴェトー、クリストフ
イオアンノウ、ニコラス
クラウチェック、イゴール
ガロ-ブルドー、マニュエル レ
セバスティアン、アブ
エレフセリウー、エヴァンゲロス、スタブロス
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    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
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    • G06F17/10Complex mathematical operations
    • G06F17/16Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
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    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
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    • G06F9/46Multiprogramming arrangements
    • G06F9/50Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
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    • G06F9/46Multiprogramming arrangements
    • G06F9/48Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806Task transfer initiation or dispatching
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    • G06F9/4881Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • GPHYSICS
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    • G06N3/02Neural networks
    • G06N3/06Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065Analogue means
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
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    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/08Learning methods
    • G06N3/084Backpropagation, e.g. using gradient descent
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00Indexing scheme relating to G06F9/00
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JP2022500757A 2019-07-15 2020-06-30 ハードウェア・アクセラレータとインターフェースするための方法 Active JP7361192B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16/511,689 US11250107B2 (en) 2019-07-15 2019-07-15 Method for interfacing with hardware accelerators
US16/511,689 2019-07-15
PCT/EP2020/068377 WO2021008868A1 (en) 2019-07-15 2020-06-30 A method for interfacing with hardware accelerators

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JP2022541144A5 JP2022541144A5 (https=) 2022-11-18
JP7361192B2 true JP7361192B2 (ja) 2023-10-13

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CN115904696A (zh) * 2021-09-30 2023-04-04 想象技术有限公司 用于配置具有可配置流水线的神经网络加速器的方法和设备
TR2021020689A2 (tr) * 2021-12-22 2023-07-21 Havelsan Hava Elektronik Sanayi Ve Ticaret Anonim Sirketi Gömülü ve bütünleşi̇k si̇stemlerde paralel yapay si̇ni̇r ağlari i̇le topluluk öğrenmesi̇
US20240161222A1 (en) * 2022-11-16 2024-05-16 Nvidia Corporation Application programming interface to indicate image-to-column transformation
US12455900B1 (en) 2023-03-07 2025-10-28 QEngine LLC Method for executing a query in a multi-dimensional data space using vectorization and a related system
KR102740239B1 (ko) * 2023-03-24 2024-12-10 한국과학기술원 다중 신경망 가속을 위한 확장가능 벡터-어레이 이종 가속기 구조 및 스케쥴링 기법

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JP2022541144A (ja) 2022-09-22
WO2021008868A1 (en) 2021-01-21
US20210019362A1 (en) 2021-01-21
US11250107B2 (en) 2022-02-15
EP3999957A1 (en) 2022-05-25
CN114127689B (zh) 2025-06-06
CN114127689A (zh) 2022-03-01
EP3999957B1 (en) 2025-09-24

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