JP7358797B2 - Semiconductor device and its manufacturing method, and semiconductor module - Google Patents

Description

The present invention relates to a semiconductor device, a method of manufacturing the same, and a semiconductor module, and particularly relates to a technique effective when applied to a semiconductor device, a method of manufacturing the same, and a semiconductor module having a switching element and a rectifying element in the same package.

Silicon carbide (SiC) is attracting attention as a next-generation power semiconductor material. SiC has a band gap of 3.25 eV for 4H-SiC, which is about three times larger than the 1.12 eV of silicon (Si) used so far, and an electrolytic strength of 2 to 4 mV/1, which is nearly an order of magnitude higher than that of Si. cm, and has superior material properties compared to Si. To date, devices using SiC (for example, rectifier devices such as diodes, switching devices such as transistors and thyristors, etc.) have been prototyped, and power semiconductor modules equipped with these have been manufactured.

Power semiconductor modules are usually made by reflow-processing and soldering an insulating substrate to a base member with high heat dissipation properties, and at the same time connecting semiconductor elements to the insulating substrate by soldering and wiring the elements using wire bonding to ensure insulation. A gel-sealed structure is used for this purpose. However, in order to take advantage of the high performance of SiC, module structures that further improve power density have been proposed. As such a module, there is a structure (full mold structure) in which wiring is performed using a printed wiring board and pins instead of wire bonding, and the entire module is sealed with resin (see Patent Documents 1 and 2). It is also possible to configure a circuit by combining a plurality of modules having such a structure.

On the other hand, it is known that a large number of several types of dislocations exist in a SiC substrate used when manufacturing a SiC element. When a device containing certain types of dislocations is operated, the dislocations may grow into stacking faults due to recombination of electron-hole pairs (see Non-Patent Document 1). Since the occurrence of stacking faults adversely affects device characteristics and increases the conduction loss of the power semiconductor module, it is desirable that stacking faults do not occur.
One possible way to solve this problem is to fabricate a silicon carbide substrate free of dislocations. Although various techniques have been proposed to improve the quality of silicon carbide wafers (see Patent Document 3), complete elimination of dislocations has not yet been achieved.

Another possible solution is to perform a screening test by applying a current to the semiconductor element (see Patent Document 4). In screening tests, devices with no characteristic changes before and after the application of current are judged to be good. However, in order to screen for current deterioration phenomena, it is necessary to apply a large current of several hundred A/ ^cm2 and a long period of time of several minutes or more. is necessary. Applying large currents is difficult in normal chip testing. This is because the chip temperature tends to become high due to problems such as large heat generation due to contact resistance, large thermal resistance on the back surface that makes cooling difficult, and large variations in thermal resistance due to the effects of unevenness on the back surface.

Here, performing a screening test in which a large current is applied to the chip as a countermeasure against current deterioration in the built-in diode of a SiC element, particularly a SiC-MOSFET, makes cooling difficult and increases equipment cost and takt time. If screening tests could be conducted in a module state with lower thermal resistance, these costs could be reduced, but in the currently mainstream power semiconductor module in which SiC-MOSFETs and SiC-SBDs are connected in parallel, If an attempt is made to apply a current to the drain, the current will be shunted to the SBD, making it impossible to perform a MOSFET screening test. This affects the reliability of the semiconductor device and the semiconductor module including the same, so there is room for improvement from the viewpoint of reliability.
Therefore, the inventors of the present invention focused their attention on printed wiring boards and created the present invention.

In addition to the above-mentioned prior art documents related to the present invention, the following may be mentioned.
Patent Document 5 discloses that an output terminal MO to which first and second MOS transistors Q1 and Q2 are connected and an output terminal DO to which first and second Schottky barrier diodes D1 and D2 are connected are separated. The technology has been disclosed.
Patent Documents 4 and 6-8 disclose chip-level screening techniques.
Patent Document 9 discloses screening at a temperature of MOSFET of 50° C. or more and 145° C. or less.
Patent Document 10 discloses that an arbitrary position where the first metal layer 5g2 for the gate of the printed circuit board 5 and the second metal layer 5s2 for the source are adjacent to each other is exposed from the insulating resin 6, and the exposed first metal layer 5g2 is exposed from the insulating resin 6. A technique is disclosed in which the capacitor 10 is electrically and mechanically connected between the capacitor 5g2 and the second metal layer 5s2.

WO2011/083737 Japanese Patent Application Publication No. 2014-090016 Japanese Patent Application Publication No. 2015-002207 Japanese Patent Application Publication No. 2016-011862 Japanese Patent Application Publication No. 2017-130520 WO2014-097448 JP2017-212317A Japanese Patent Application Publication No. 2018-205251 Japanese Patent Application Publication No. 2018-205250 WO2014-185050

Journal of Applied Physics 99,011101(2006)

SUMMARY OF THE INVENTION In view of the above-mentioned problems, it is an object of the present invention to provide a technique that can improve the reliability of a semiconductor device and a semiconductor module equipped with the same.

A semiconductor device according to one embodiment of the present invention includes an insulated circuit board having an insulating plate and a conductive plate, a transistor chip installed on the insulated circuit board and having a first main electrode and a second main electrode, and an insulated circuit board. a diode chip installed on top, having an anode electrode and a cathode electrode, the cathode electrode of which is electrically connected to the first main electrode of the transistor chip; and a diode chip that is electrically connected to the second main electrode of the transistor chip. A wiring board having a first conductor and a second conductor electrically connected to the anode electrode of the diode chip, and disposed on the transistor chip and diode chip side of the insulated circuit board at a distance from the insulated circuit board. A semiconductor device comprising: a connecting member for electrically connecting a first conductor and a second conductor on a surface of a wiring board;

Further, a method for manufacturing a semiconductor device according to one embodiment of the present invention includes an insulated circuit board having an insulating plate and a conductive plate, and a transistor installed on the insulated circuit board 10 and having a first main electrode and a second main electrode. a diode chip installed on an insulated circuit board and having an anode electrode and a cathode electrode, the cathode electrode of which is electrically connected to a first main electrode of the transistor chip; a first conductor electrically connected to the anode electrode of the diode chip; and a second conductor electrically connected to the anode electrode of the diode chip; A method of manufacturing a semiconductor device comprising: a wiring board arranged in a manner that the transistor chip is screened by passing a current between the second main electrode and the first main electrode of the transistor chip; and, after conducting a screening test, electrically connecting the first conductor and the second conductor with a conductive member on the surface of the wiring board.

Further, a semiconductor module according to one embodiment of the present invention is a semiconductor module having a plurality of semiconductor devices installed on a main surface of a base member, wherein the plurality of semiconductor devices is an insulated circuit board having an insulating plate and a conductive plate. a transistor chip installed on the insulated circuit board 10 and having a first main electrode and a second main electrode; and a transistor chip installed on the insulated circuit board and having an anode electrode and a cathode electrode, the cathode being the transistor chip. a diode chip electrically connected to a first main electrode of the transistor chip, a first conductor electrically connected to a second main electrode of the transistor chip, and a second conductor electrically connected to an anode electrode of the diode chip. A wiring board having a conductor and disposed on the transistor chip and diode chip side of the insulated circuit board at a distance from the insulated circuit board, and a first conductor and a second conductor on the surface of the wiring board. A connection member for electrical connection is provided.

According to the present invention, it is possible to improve the reliability of a semiconductor device and a semiconductor module including the same.

1 is an equivalent circuit diagram showing an example of a semiconductor device according to a first embodiment of the present invention. FIG. 1 is a schematic plan view showing an example of a semiconductor device according to a first embodiment of the present invention. FIG. 3 is a schematic plan view showing an example of a plane pattern of a first conductor and a second conductor of a wiring board in the semiconductor device according to the first embodiment of the present invention. 1 is a schematic plan view showing an example of a chip arrangement in a semiconductor device according to a first embodiment of the present invention; FIG. A schematic cross-sectional view showing an example of the internal structure of the semiconductor device according to the first embodiment of the present invention ((a) is a schematic cross-sectional view showing the cross-sectional structure taken along the line II-II in FIG. 2, (b) is a schematic cross-sectional view showing the cross-sectional structure taken along the line III-III. 1 is a process flow diagram for explaining a method for manufacturing a semiconductor device according to a first embodiment of the present invention. FIG. 1 is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to a first embodiment of the present invention. 1 is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to a first embodiment of the present invention. 1 is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to a first embodiment of the present invention. FIG. 3 is a schematic cross-sectional view showing a first modification of the semiconductor device according to the first embodiment of the present invention. FIG. 7 is a schematic cross-sectional view showing a second modification of the semiconductor device according to the first embodiment of the present invention. FIG. 7 is a diagram showing an example of a semiconductor module according to a second embodiment of the present invention ((a) is a schematic cross-sectional view, and (b) is a schematic cross-sectional view in which a part of (a) is enlarged). FIG. 7 is a diagram for explaining a method for manufacturing a semiconductor module according to a second embodiment of the present invention ((a) is a schematic cross-sectional view, and (b) is a schematic cross-sectional view in which a part of (a) is enlarged). FIG. 7 is a diagram for explaining a method for manufacturing a semiconductor module according to a second embodiment of the present invention ((a) is a schematic cross-sectional view, and (b) is a schematic cross-sectional view in which a part of (a) is enlarged). FIG. 7 is a diagram for explaining a method for manufacturing a semiconductor module according to a second embodiment of the present invention ((a) is a schematic cross-sectional view, and (b) is a schematic cross-sectional view in which a part of (a) is enlarged).

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
In addition, in all the figures for explaining the embodiments of the invention, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.
Furthermore, each drawing is schematic and may differ from the actual drawing. Furthermore, the following embodiments are intended to exemplify devices and methods for embodying the technical idea of the present invention, and the configuration is not limited to the following. That is, the technical idea of the present invention can be modified in various ways within the technical scope described in the claims.
In addition, in the following embodiments, in three directions that are orthogonal to each other in space, a first direction and a second direction that are orthogonal to each other in the same plane are respectively referred to as an X direction and a Y direction, and the first direction and A third direction perpendicular to each of the second directions is defined as a Z direction.

(First embodiment)
In the first embodiment, a case will be described in which the present invention is applied to a one-element package type (1-in-1 type) semiconductor device equipped with a set of switching elements and a rectifying element. Further, in the first embodiment, the first main electrode of the transistor chip is assumed to be a drain electrode, and the second main electrode is assumed to be a source electrode.

As shown in FIG. 1, the semiconductor device 1 according to the first embodiment of the present invention includes a switching element Tr and a rectifying element Di connected in parallel and inversely to the switching element Tr. A cathode electrode K of the rectifying element Di is electrically connected to a drain electrode D serving as a first main electrode of the switching element Tr. An anode electrode A of the rectifying element Di is electrically connected to a source electrode S as a second main electrode of the switching element Tr via a bridge plate 30 as a connecting member. In the switching element Tr, a drain electrode D is electrically connected to a first main circuit terminal 7a (see FIG. 2), which will be described later, and a source electrode S is electrically connected to a second main circuit terminal 7b (see FIG. 2), which will be described later. The control electrode G is electrically connected to a control terminal 7c (see FIG. 2), which will be described later. The auxiliary electrode Sa is an auxiliary electrode for detecting the voltage on the source electrode S side, and is electrically connected to an auxiliary terminal 7d (see FIG. 2), which will be described later.

The switching element Tr has a configuration in which a plurality of transistor chips 2 shown in FIG. 4 are connected in parallel. Further, the rectifying element Di also has a configuration in which a plurality of diode chips 3 shown in FIG. 4 are connected in parallel. As the switching element Tr, a vertical semiconductor element with an insulated gate structure such as a MIS transistor or an IGBT, in which the main current flows in the depth direction of the transistor chip, is suitable. As the rectifying element Di, a vertical semiconductor element such as a fast recovery diode (FRD) or a Schottky barrier diode (SBD) is suitable. Hereinafter, the switching element Tr is a vertical MISFET with an insulated gate structure mainly composed of a semiconductor substrate made of silicon carbide (SiC), and the rectifying element Di is an SBD mainly composed of a semiconductor substrate made of SiC. I will explain.

Note that the MIS transistor forming the transistor chip is a concept that includes MISFET, MISSIT, and the like. In contrast to MOS transistors that use a silicon oxide (SiO ₂ ) film as the gate insulating film, "MIS transistors" are a more comprehensive insulated gate type transistor that uses an insulating film other than SiO ₂ film as the gate insulating film. means. Silicon oxynitride (SiON) film, strontium oxide (SrO) film, silicon nitride (Si ₃ N ₄ ) film, and aluminum oxide (Al ₂ O ₃ ) film can also be used for the gate insulating film of MIS transistors. be. Alternatively, a magnesium oxide (MgO) film, a yttrium oxide (Y ₂ O ₃ ) film, a hafnium oxide (HfO ₂ ) film, a zirconium oxide (ZrO ₂ ) film, a tantalum oxide (Ta ₂ O ₅ ) film, A bismuth oxide (Bi ₂ O ₃ ) film may also be used. Furthermore, it is also possible to select some of these single layer films and use a composite film in which a plurality of them are laminated. In addition to SiC, other semiconductor materials such as silicon (Si), gallium nitride (GaN), diamond, or aluminum nitride (AlN) can be used as the semiconductor material.

Next, a specific configuration of the semiconductor device 1 according to the first embodiment of the present invention will be described.
As shown in FIGS. 2 to 5, the semiconductor device 1 according to the first embodiment of the present invention includes a transistor chip 2, a diode chip 3, first to fourth conductive posts 5a, 5b, 5c, and 5d. It includes a first main circuit terminal 7a and a second main circuit terminal 7b, a control terminal 7c and an auxiliary terminal 7d, an insulated circuit board 10, and a wiring board 20. Further, the semiconductor device 1 includes the transistor chip 2, the diode chip 3, the first to fourth conductive posts 5a to 5d, the first main circuit terminal 7a, the second main circuit terminal 7b, the control terminal 7c, the auxiliary terminal 7d, A resin sealing body 8 is provided as a sealing body for sealing an insulated circuit board 10, a wiring board 20, and the like. The semiconductor device 1 also includes a metal bridge plate 30 on the main surface of the wiring board 20 as a connecting member that electrically connects the first conductor 22a and the second conductor 22b of the wiring board 20. ing.

As shown in FIGS. 2 and 5, the resin sealing bodies 8 have a rectangular shape, for example, a rectangle, when viewed from above, and are located on opposite sides of each other in the longitudinal direction, which is the X direction (first direction). It has two short sides 8a and 8b, and two long sides 8c and 8d located opposite to each other in the short direction, which is the Y direction (second direction) orthogonal to the X direction. The resin sealing body 8 is made of, for example, an epoxy-based thermosetting insulating resin.
Each of the first main circuit terminal 7a, the second main circuit terminal 7b, the control terminal 7c, and the auxiliary terminal 7d is made of a conductive pin, and is sealed with a resin sealing body 8 except for a part; It protrudes to the outside of the body 8. That is, each of the first main circuit terminal 7a, the second main circuit terminal 7b, the control terminal 7c, and the auxiliary terminal 7d is connected to the inside and outside of the resin sealing body 8 in the Z direction (thickness direction) perpendicular to the X direction and the Y direction. It extends over .

The first main circuit terminal 7a is arranged at the center of the resin encapsulant 8 on the one short side 8a side, and the second main circuit terminal 7b is arranged at the center of the resin encapsulant 8 on the other short side 8b side. has been done. The control terminal 7c is arranged at the center of the resin sealing body 8 on the one long side 8c side, and the auxiliary terminal 7d is arranged at the center of the resin sealing body 8 on the other long side 8d side. In the first embodiment, although the number is not limited to this, for example, two each of the first and second main circuit terminals 7a and 7b, and one each of the control terminal 7c and the auxiliary terminal 7d are provided.

As shown in FIG. 4 and FIGS. 5(a) and 5(b), the insulated circuit board 10 includes an insulating plate 11, a conductive plate 12 fixed to the main surface of the insulating plate 11, and a conductive plate 12 fixed to the main surface of the insulating plate 11. has a metal plate 13 fixed to the opposite back surface. In the first embodiment, the conductive plate 12 includes a first conductive plate 12a and a second conductive plate 12b that are insulated and separated from each other. The insulated circuit board 10 is, for example, a direct copper bonding (DCB) board in which copper is eutectically bonded to the surface of a ceramic substrate, an AMB board in which metal is placed on the surface of a ceramic substrate by an active metal brazing (AMB) method, or the like. It is possible to adopt As the material of the ceramic substrate, silicon nitride (Si ₃ N ₄ ), aluminum nitride (AlN), alumina (Al ₂ O ₃ ), etc. can be used, for example.

The insulating plate 11 has a rectangular shape when viewed from above, for example, a rectangle, and has two short sides corresponding to the two short sides 8a and 8b and the two long sides 8c and 8d of the resin sealing body 8. It has two long sides. The first conductive plate 12a has a rectangular shape when viewed from above, for example, a substantially square solid pattern. The first conductive plate 12a is arranged such that the directions of the four sides match the directions of the four sides of the insulating substrate, so that one of the two short sides of the insulating plate 11 (resin-sealed 8). The second conductive plate 12b has a rectangular shape when viewed from above, for example, a rectangular solid pattern. The second conductive plate 12b is arranged so that its longitudinal direction coincides with the Y direction on the other short side of the two short sides of the insulating plate 11 (on the other short side 8b side of the resin sealing body 8). It is located in The first conductive plate 12a and the second conductive plate 12b are formed so that the first conductive plate 12a has an area several times larger than that of the first conductive plate 12a, and are separated and insulated from each other.
The back surface of the insulated circuit board 10 , that is, the metal plate 13 is exposed from the back surface of the resin sealing body 8 on the opposite side to the main surface.

As shown in FIG. 4 and FIGS. 5(a) and 5(b), the transistor chip 2 has, for example, a second main electrode on one surface (main surface) of two surfaces located opposite to each other. It has a source electrode 2s, and has a drain electrode 2d as a first main electrode on the other surface (back surface). Further, the transistor chip 2 has a gate electrode 2g as a control electrode on one surface. The diode chip 3 has, for example, an anode electrode 3a on one surface (main surface) of two surfaces located opposite to each other, and a cathode electrode 3k on the other surface (back surface).
For example, two diode chips 3 are arranged on the center line in the longitudinal direction (X direction) of the insulated circuit board 10 at a predetermined interval. For example, four transistor chips 2 are arranged at predetermined intervals on both sides of the array of diode chips 3. The four transistor chips 2 are connected in parallel to form a switching element Tr. Further, the two diode chips 3 are connected in parallel to form a rectifying element Di.

As shown in FIGS. 5A and 5B, the transistor chip 2 has a drain electrode 2d connected to the first conductive plate 12a of the insulated circuit board 10 with a bonding material such as solder 15 interposed between the drain electrode 2d and the electrically and mechanically It is connected. Further, as shown in FIG. 5A, in the diode chip 3, similarly to the transistor chip 2, the cathode electrode 3k is electrically connected to the first conductive plate 12a of the insulated circuit board 10 with a bonding material such as solder 15 interposed therebetween. physically and mechanically connected. That is, the drain electrode 2d of the transistor chip 2 and the cathode electrode 3k of the diode chip 3 are electrically connected to each other via the first conductive plate 12a and the solder 15.

As shown in FIG. 3 and FIGS. 5(a) and 5(b), the wiring board 20 is spaced apart from the insulated circuit board 10 on the main surface side (transistor chip 2 and diode chip 3 side) of the insulated circuit board 10. It is located. The wiring board 20 is a normal printed wiring board, and has, for example, a two-layer wiring structure, although it is not limited thereto. Specifically, the wiring board 20 includes an insulating plate 21, a first conductor 22a and a second conductor 22b provided on the first wiring layer on the main surface of the insulating plate 21, and a main surface of the insulating plate 21. has a gate wiring 23a (see FIG. 5(b)), an auxiliary source line (not shown), etc. provided in the second wiring layer on the opposite back surface.

The first conductor 22a has a substantially C-shape when viewed from above, and includes two first portions _22a1 extending in the X direction and spaced apart from each other in the Y direction, and extending in the X direction. The second portion 22a ₂ is integrally connected to one end side of the two first portions 22a ₁ . The second conductor 22b extends in the X direction and is arranged between the two first portions 22a ₁ and 22a ₁ of the first conductor 22a. The first conductor 22a and the second conductor 22b are individually separated and insulated from each other.

As shown in FIGS. 3, 4, 5(a) and 5(b), one end of the first conductive post 5a is electrically and mechanically bonded to the source electrode 2s of the transistor chip 2 using a bonding material such as solder 16. The other end thereof passes through the wiring board 20 and is electrically and mechanically connected to the first conductor 22a. That is, the first conductive post 5a rises from the source electrode 2s of the transistor chip 2 toward the wiring board 20, penetrates the wiring board 20, and is connected to the first conductor 22a of the wiring board 20.

The second conductive post 5b has one end electrically and mechanically connected to the second conductive plate 12b of the insulated circuit board 10 using a bonding material such as solder 16, and the other end penetrates through the wiring board 20 and is connected to the first conductive plate 12b of the insulated circuit board 10. 22a electrically and mechanically connected. That is, the second conductive post 5b rises from the second conductive plate 12b of the insulated circuit board 10 toward the wiring board 20, penetrates the wiring board 20, and is connected to the first conductor 22a of the wiring board 20.

One end of the third conductive post 5c is electrically and mechanically connected to the anode electrode 3a of the diode chip 3 using a bonding material such as solder 16, and the other end penetrates through the wiring board 20 and is electrically connected to the second conductor 22b. physically and mechanically connected. That is, the third conductive post 5c rises from the anode electrode 3a of the diode chip 3 toward the wiring board 20, penetrates the wiring board 20, and is connected to the second conductor 22b of the wiring board 20.

The fourth conductive post 5d is electrically and mechanically connected to the gate electrode 2g of the transistor chip 2 using a bonding material such as solder 16, and the other end thereof is electrically and mechanically connected to the gate wiring 23a of the wiring board 20. ing. That is, the fourth conductive post 5d rises from the gate electrode 2g of the transistor chip 2 toward the wiring board 20, and is connected to the gate wiring 23a of the wiring board 20.

As shown in FIGS. 2 to 5(b) and (b), the other end of the first main circuit terminal 7a is electrically and mechanically bonded to the first conductive plate 12a of the insulated circuit board 10 by using a bonding material such as solder 16. The intermediate portion passes through the through hole of the wiring board 20, and the other end protrudes from the main surface of the resin sealing body 8. The second main circuit terminal 7b has one end electrically and mechanically connected to the second conductive plate 12b of the insulated circuit board 10 using a bonding material such as solder 16, and an intermediate portion passing through a through hole of the wiring board 20. The other end side protrudes from the main surface of the resin sealing body 8 .

That is, the first main circuit terminal 7a is electrically connected to the drain electrode 2d of the transistor chip 2 and the cathode electrode 3k of the diode chip 3 via the solder 16, the first conductive plate 12a of the insulated circuit board 10, and the solder 16, respectively. has been done. The source electrode 2s of the transistor chip 2 includes the solder 16, the first conductive post 5a, the first conductor 22a of the wiring board 20, the second conductive post 5b, the solder 16, the second conductive plate 12b of the insulated circuit board 10, and It is electrically connected to the second main circuit terminal 7b via solder 16. Further, the anode electrode 3a of the diode chip 3 is electrically connected to the second conductor 22b of the wiring board 20 via the solder 16 and the third conductive post 5c.

The control terminal 7c has one end that penetrates the wiring board 20 and is electrically and mechanically connected to the gate wiring 23a (see FIG. 5(b)) of the wiring board 20, and the other end that penetrates the wiring board 20 and is electrically and mechanically connected to the main surface of the resin encapsulant 8. stands out from That is, the control terminal 7c is electrically connected to the gate electrode 2g of the transistor chip 2 via the gate wiring 23a of the wiring board 20, the fourth conductive post 5d, and the solder 16.
Although not shown in detail, one end of the auxiliary terminal 7d passes through the wiring board 20 and is electrically and mechanically connected to the auxiliary source line of the wiring board 20, and the other end is connected to the main surface of the resin sealing body 8. stands out from The auxiliary source wiring is electrically connected to the first conductor 22a.

As shown in FIGS. 2 and 5(a), the resin sealing body 8 exposes a portion of each of the first conductor 22a and the second conductor 22b of the wiring board 20 on its main surface (upper surface). It has an opening 9. The openings 9 are provided at two locations, for example, although the openings 9 are not limited thereto. The openings 9 are arranged at predetermined intervals in the Y direction perpendicular to the arrangement direction of the transistor chips 2 and the arrangement direction (X direction) of the diode chips 3, and span the first conductor 22a and the second conductor 22b. placed in position. Further, the opening 9 is arranged between four chips including the two transistor chips 2 and the two diode chips 3 when viewed in plan toward the main surface of the resin sealing body 8.

The bridge plate 30 is electrically and mechanically connected to a portion of each of the first conductor 22a and the second conductor 22b through the opening 9 using a bonding material such as solder 31. That is, each of the first conductor 22a and the second conductor 22b is electrically connected to each other by the connection of the bridge plate 30, but is insulated from each other except for the conduction by the bridge plate 30.
After conducting a screening test in the manufacturing process of the semiconductor device 1, the bridge plate 30 is formed by applying solder 31 to a portion of each of the first conductor 22a and the second conductor 22b through the opening 9 of the resin sealing body 8. electrically and mechanically connected. That is, in the screening test, since the first conductor 22a and the second conductor 22b are separated, the switching element Tr and the rectifying element Di (transistor chip 2 and diode chip 3) are separated on the circuit. The bridge plate 30 is made of, for example, copper as a metal material that has excellent conductivity and wettability with solder.

Next, a method for manufacturing the semiconductor device 1 according to the first embodiment of the present invention will be described using FIGS. 7 to 9 while referring to the flowchart shown in FIG.
First, in the substrate stack forming step S1 of FIG. 6, the transistor chip 2, the diode chip 3, the first to fourth conductive posts 5a to 5d, the first and second main circuit terminals 7a and 7b, the control terminal 7c, and the auxiliary terminal 7d, a board stack 25 is formed using the insulated circuit board 10, the wiring board 20, and the like.
Specifically, first, the other ends of the first to fourth conductive posts 5a to 5d, the control terminal 7c, and the auxiliary terminal 7d are electrically and mechanically connected to predetermined positions of the wiring board 20 prepared in advance. Connect to.

Next, as shown in FIG. 7A, in the insulated circuit board 10, a solder paste material 15a, for example, is applied as a bonding material to the chip mounting area of the first conductive plate 12a. Then, as shown in FIG. 7A, the transistor chip 2 and the diode chip 3 are placed on the chip mounting area of the first conductive plate 12a with the solder paste material 15a interposed therebetween. The transistor chip 2 and the diode chip 3 are arranged so that their back surfaces (drain electrode 2d, cathode electrode 3k) are on the solder paste material 15a side. As shown in FIG. 7A, in the insulated circuit board 10, a bonding material such as solder paste is applied to each of the terminal connection area of the first conductive plate 12a, the terminal connection area of the second conductive plate 12b, and the post connection area. At the same time, the solder paste material 16a is also applied to the source electrode 2s and gate electrode 2g of the transistor chip 2, and the anode electrode 3a of the diode chip 3.

Next, as shown in FIG. 7(b), the wiring board 20 is placed on the insulated circuit board 10 so that the first to fourth conductive posts 5a to 5d are on the insulated circuit board 10 side. In this step, the wiring board 20 is supported by the insulated circuit board 10 while being spaced apart from the insulated circuit board 10 by the first to fourth conductive posts 5a to 5d. Further, one end side of the first conductive post 5a is placed on the source electrode 2s of the transistor chip 2 via a solder paste material 16a, and one end side of the second conductive post 5b is placed on the second conductive plate 12b of the insulated circuit board 10. One end of the third conductive post 5c is placed on the anode electrode 3a of the diode chip 3 with the solder paste material 16a interposed therebetween. Although not shown in FIG. 7(b), referring to FIG. 5(b), one end side of the fourth conductive post 5d is placed on the gate electrode 2g of the transistor chip 2 via the solder paste material 16a. be done.

Next, the first main circuit terminal 7a and the second main circuit terminal 7b are inserted into predetermined through holes of the wiring board 20 and held vertically. In this process, as shown in FIG. 7(b), the first main circuit terminal 7a has one end placed on the first conductive plate 12a of the insulated circuit board 10 with a solder paste material 16a interposed therebetween, and the second main circuit terminal 7a One end of the terminal 7b is placed on the second conductive plate 12b of the insulated circuit board 10 via a solder paste material 16a.

Next, by performing reflow treatment in this state, the drain electrode 2d of the transistor chip 2 and the cathode electrode 3k of the diode chip 3 are attached to the first conductive plate 12a of the insulated circuit board 10, as shown in FIG. 8(a). They are electrically and mechanically connected by solder 15, respectively. Further, one end side of the first main circuit terminal 7a is electrically and mechanically connected to the first conductive plate 12a of the insulated circuit board 10 by solder 16, and one end side of the second main circuit terminal 7b and the second conductive post 5b are connected electrically and mechanically to the first conductive plate 12a of the insulated circuit board 10. One end side is electrically and mechanically connected to the second conductive plate 12b of the insulated circuit board 10 by solder 16, respectively. Further, one end side of the first conductive post 5a is electrically and mechanically connected to the source electrode 2s of the transistor chip 2, and one end side of the third conductive post 5c is connected to the anode electrode 3a of the diode chip 3 by solder 16, respectively. Furthermore, although not shown in FIG. 8A, referring to FIG. 5B, one end side of the fourth conductive post 5d is electrically and mechanically connected to the gate electrode 2g of the transistor chip 2 by the solder 16. Connected. As a result, a substrate stack 25 is formed. Furthermore, a transistor chip 2 and a diode chip 3 are installed on the first conductive plate 12a of the insulated circuit board 10, respectively.

Next, a resin sealing step S2 shown in FIG. 6 is performed. Specifically, after the substrate laminate 25 is placed in a cavity of a mold, for example, a thermosetting epoxy resin is injected into the cavity. As a result, as shown in FIG. 8(b), the transistor chip 2, the diode chip 3, the first to fourth conductive posts 5a to 5d, the first and second main circuit terminals 7a and 7b, and the control terminal 7c Then, a resin sealing body 8 is formed that seals the board stack 25 including the auxiliary terminal 7d, the insulated circuit board 10, and the wiring board 20. In this step, by providing a recess in the wall surface of the cavity of the molding die, the other end sides of each of the first and second main circuit terminals 7a, 7b, control terminal 7c, and auxiliary terminal 7d are sealed with resin. It can be made to protrude outside from the main surface of 8. Conversely, by providing a convex portion on the wall surface of the cavity of the molding die, the opening 9 where a portion of each of the first and second conductors 22a and 22b of the wiring board 20 is exposed is sealed with resin. It can be formed into a body 8. In this first embodiment, two openings 9 are formed in the resin sealing body 8. In addition, by sealing the metal plate 13 of the insulated circuit board 10 in pressure contact with the wall surface of the cavity of the molding die, the metal plate 13 of the insulated circuit board 10 can be The plate 13 can be exposed.

In this step, since the first conductor 22a and the second conductor 22b of the wiring board 20 are electrically separated, the switching element Tr and the rectifying element Di are separated after the resin sealing body 8 is formed. However, the transistor chip 2 and the diode chip 3 are separated in terms of circuitry.

Next, in a primary on-resistance measuring step S3 shown in FIG. 6, the on-resistance of the switching element Tr in which four transistor chips 2 are connected in parallel is measured.
Next, a screening test step S4 shown in FIG. 6 is performed. In this screening test step S4, as shown in FIG. 9(a), the positive terminal (+) of the power supply 26 is connected to the second main circuit terminal 7b, the negative terminal (-) is connected to the first main circuit terminal 7a, and each transistor For example, a current of 100 A/cm ² is applied to the built-in diode (between the source region and the drain region) of the chip 2 for 15 minutes. In this case, if a chip with an active area of about 5 mm ² is used as the transistor chip 2, a current of 5 A is required per chip. In this first embodiment, since four transistor chips 2 are mounted, a current of 20 A is applied. At this time, since the transistor chip 2 generates heat, the back side (metal plate 13) of the insulated circuit board 10 is cooled with a chiller.

In this step, since the switching element Tr and the rectifying element Di (transistor chip 2 and diode chip 3) are separated in the circuit, when current is applied from the second main circuit terminal 7b to the first main circuit terminal 7a in this state, Since only the built-in diode (between the source region and the drain region) of each transistor chip 2 is energized, a screening test of each transistor chip 2 is possible. Since each transistor chip 2 is mounted on the insulated circuit board 10, it has high heat dissipation and can apply a large current compared to the case of a single chip. Further, after the screening test is performed, the bridge plate 30 is electrically and mechanically connected to a portion of each of the first and second conductors 22a and 22b through the opening 9 of the resin sealing body 8 using solder 31. Accordingly, it is possible to reversely connect the rectifying element Di to the switching element Tr.

Next, after the screening test step S4 is completed, in a secondary on-resistance measurement step S5 shown in FIG. 6, the on-resistance of the switching element Tr in which four transistor chips 2 are connected in parallel is measured in the same way as the primary one.
Next, in the selection step S6 of FIG. 6, the primary on-resistance value measured in the primary on-resistance measurement step S3 and the secondary on-resistance value measured in the secondary on-resistance measurement step S5 are compared. The switching element Tr whose secondary on-resistance value has increased from the primary on-resistance value by more than a predetermined standard is determined to be a defective product as a stacking fault has occurred inside the transistor chip 2, and the secondary on-resistance value A switching element Tr whose primary resistance value falls within a predetermined standard is determined to be a good product, and is selected as a good or bad product.

Next, the conductor connection step S7 shown in FIG. 6 is performed on the semiconductor devices in the manufacturing process (semi-finished products) that have been selected as non-defective products. Specifically, as shown in FIG. 9(b), the first conductor 22a and the second conductor 22b of the wiring board 20 are formed on the main surface of the wiring board 20 through the opening 9 of the resin sealing body 8. Apply solder paste material to a portion of each. Then, a bridge plate 30 is placed on a portion of each of the first conductor 22a and the second conductor 22b via a solder paste material so as to straddle the separation region between each portion. Then, by performing a reflow treatment in this state and melting the solder paste material, the bridge plate 30 is electrically and mechanically connected to a portion of each of the first conductor 22a and the second conductor 22b by the solder 31. . Since the connection of the bridge plate 30 with the solder 31 is performed after the resin sealing body 8 is formed, the solder 31 should be used so that a temperature hierarchy is formed with the solders 15 and 16 specified at the time of forming the board laminate 25. In addition, it is preferable to select a material having a lower melting point than the solders 15 and 16. When solder with a Sn-Sb composition is used as the solder 15 and 16 for forming the substrate laminate 25, for example, solder with a Sn-Sb-Ag composition may be used as the solder 31 for connecting the bridge plate 30. It is possible to construct a temperature hierarchy of the solder used in the process.

In this step, the switching element Tr and the rectifying element Di (transistor chip 2 and diode chip 3) are connected in parallel and in reverse.
Thereafter, the semiconductor device 1 according to the first embodiment is almost completed by performing various tests and marking steps on the semiconductor device in the manufacturing process that has been selected as a good product.

As explained above, in the semiconductor device 1 of the first embodiment, in the manufacturing process, before the first conductor 22a and the second conductor 22b of the wiring board 20 are connected by the bridge plate 30, the switching element Tr is Since the rectifying element Di is separated in the circuit, each transistor chip 2 can be subjected to a screening test. Further, after the screening test is performed, by connecting the first conductor 22a and the second conductor 22b of the wiring board 20 with the bridge plate 30, it is possible to reversely connect the rectifying element Di to the switching element Tr. . Therefore, even in the case of the semiconductor device 1 in which the switching element Tr and the rectifying element Di are connected in parallel and reversely, the screening test can be performed, so that the reliability of the semiconductor device 1 can be improved.

Further, according to the method for manufacturing the semiconductor device 1 according to the first embodiment, a highly reliable semiconductor device 1 can be provided.
The semiconductor device 1 according to the first embodiment also includes a first conductor 22a electrically connected to the source electrode 2s of the transistor chip 2, and a second conductor 22a electrically connected to the anode electrode 3a of the diode chip 3. Since the conductor 22b is electrically connected to the bridge plate 30 on the main surface of the wiring board 20, the wiring of the conductive path electrically connects the source electrode 2s of the transistor chip 2 and the anode electrode 3a of the diode chip 3. The length can be shortened and the inductance can be reduced.
In addition, the semiconductor device 1 according to the first embodiment has a connection between the first conductor 22a and the second conductor 22b by the bridge plate 30, which is projected as a connection between the first conductor 22a and the second conductor 22b. Since this is performed between four chips, the distances between these four chips and the bridge plate 30 can be made equal.

(Modified example of the first embodiment)
(First modification)
In the first embodiment described above, the wiring board 20 in which the first and second conductors 22a and 22b were provided on one side of the insulating plate 21 was described. However, the present invention is not limited to the wiring board 20 of the first embodiment. For example, as shown in FIG. 10, the present invention can also be applied to a wiring board 20A in which first and second conductors 22a and 22b are provided on both sides of an insulating plate 21, respectively. In this case, the insertion bridge member 32 as a connecting member is inserted into the through hole 21a provided in the insulating plate 21 of the wiring board 20A to connect the first conductor 22a and the second conductor 22b on both sides of the insulating plate 21. Preferably, they are electrically connected. Further, it is preferable that the insertion bridge member 32 has a T-shaped cross section along the insertion direction.

(Second modification)
Moreover, in the above-described first embodiment, a case has been described in which the bridge plate 30 is used as a connecting member that electrically connects the first conductor 22a and the second conductor 22b. However, the present invention is not limited to the bridge plate 30 of the first embodiment or the insertion bridge member 32 of the first modification. For example, solder itself may be used as the connection member, and as shown in FIG. 11, the first conductor 22a and the second conductor 22b may be directly electrically and mechanically connected with the solder 31.
Note that in the first embodiment and the modified example described above, a one-element package (1 in 1) type semiconductor device has been described, but the present invention is not limited to a one-element package (1 in 1) type semiconductor device. That is, the present invention can also be applied to a two-element package (2in1) type semiconductor device equipped with two sets of switching elements and rectifying elements.

(Second embodiment)
In this first embodiment, a case will be described in which the present invention is applied to a semiconductor module.
As shown in FIGS. 12(a) and 12(b), a semiconductor module 40 according to a second embodiment of the present invention includes a semiconductor device 1 according to the above-described first embodiment, a first semiconductor device 1A and a second semiconductor device. It is provided as 1B. Furthermore, the semiconductor module 40 according to the second embodiment includes a base member 41 on which the first and second semiconductor devices 1A and 1B are installed, and a base member 41 with the first and second semiconductor devices on the main surface. It includes a frame-shaped case 43 installed so as to surround 1A and 1B. Further, the semiconductor module 40 according to the second embodiment includes a first bus bar 45 electrically and mechanically connected to the first main circuit terminal 7a of each of the first and second semiconductor devices 1A and 1B; and a second bus bar 46 electrically and mechanically connected to the second main circuit terminal 7b of each of the first and second semiconductor devices 1A and 1B. The semiconductor module 40 according to the second embodiment also includes a gel-like sealing resin that seals the first and second semiconductor devices 1A and 1B installed on the main surface of the base member 41 inside the case 43. It is equipped with 47.

The first and second semiconductor devices 1A and 1B are installed on the main surface of the base member 41 with, for example, solder 42 interposed between each metal plate 13 and the base member 41 as a bonding material.
The connection form of the first bus bar 25 and the second bus 26 can be changed depending on the specifications of the product. In the semiconductor module 40 according to the second embodiment, for example, main circuit terminals of the first and second semiconductor devices 1A and 1B having the same function (first main circuit terminals 7a and second main circuit terminals 7b) are connected in parallel by first and second bus bars 45 and 46 to achieve a large current capacity.

Here, in the above-described first embodiment, a case has been described in which the first conductor 22a and the second conductor 22b are electrically connected by the bridge plate 30 after the screening test in the manufacturing process of the semiconductor device 1. In contrast, in the second embodiment, in the manufacturing process of the semiconductor module 40, the first conductive material is The body 22a and the second conductor 22b are electrically connected by a bridge plate 30. A method for manufacturing the semiconductor module 40 according to this embodiment will be described below with reference to FIGS. 12 to 15.

First, first and second semiconductor devices 1A and 1B are prepared. The first and second semiconductor devices 1A and 1B basically have the same configuration as the first semiconductor device 1, but with reference to FIG. 13, the first conductor 22a and the second conductor 22b are The connection by the bridge plate 30 is not implemented, and the switching element Tr and the rectifying element Di (the transistor chip 2 and the diode chip 3) are separated in terms of the circuit. However, the screening test has already been conducted in the manufacturing process of the first and second semiconductor devices 1A and 1B.

Next, as shown in FIGS. 13(a) and 13(b), a bonding material such as solder is applied between the main surface of the base member 41 and the metal plate 13 of each of the first and second semiconductor devices 1A and 1B. The first and second semiconductor devices 1A and 1B are placed on the main surface of the base member 41 with the material 42a interposed therebetween.
Next, as shown in FIGS. 13A and 13B, in each of the first and second semiconductor devices 1A and 1B, the first conductor 22a of the wiring board 20 is passed through the opening 9 of the resin sealing body 8. For example, a solder paste material 31a is applied as a bonding material to a portion of each of the second conductors 22b. Then, as shown in FIGS. 14(a) and 14(b), a solder paste material is applied to a portion of each of the first conductor 22a and the second conductor 22b so as to straddle the separation region between the portions of the second conductor 22b. A bridge plate 30 is placed via 31a.

Next, by performing a reflow treatment in this state to melt the solder paste material 42a and the solder paste material 31a, the first The second semiconductor devices 1A and 1B are fixed with solder 42, and the bridge plate 30 is electrically and mechanically connected to a portion of each of the first conductor 22a and the second conductor 22b with solder 31. Here, as the solder 31 and the solder 42, materials with a melting point lower than that of the solders 15 and 16 are selected so that a temperature hierarchy is formed with the solders 15 and 16 specified at the time of forming the board stack 25. is preferred. When using Sn-Sb-based solder as the solders 15 and 16 for forming the substrate laminate 25, for example, by using Sn-Sb-Ag-based solder for the solder 31 and solder 42, the amount of solder used can be reduced. It is possible to construct temperature hierarchies.
In this step, the switching element Tr and the rectifying element Di (transistor chip 2 and diode chip 3) are connected in parallel and in reverse.

Thereafter, the first bus bar 45 is connected to the first main circuit terminal 7a of each of the first and second semiconductor devices 1A, 1B, and the second bus bar 45 is connected to the second main circuit terminal 7b of each of the first and second semiconductor devices 1A, 1B. The bus bar 46 is connected, and then a frame-shaped case 43 is bonded to the main surface of the base member 41 so as to surround the first and second semiconductor devices 1A and 1B. Thereafter, a silicone gel sealing resin 47 is injected into the inside of the case 43 to seal the first and second semiconductor devices 1A and 1B with the resin. This sealing resin 47 can fill the openings 9 provided in the resin seals 8 of each of the first and second semiconductor devices 1A and 1B. As a result, the semiconductor module 40 shown in FIG. 12 is almost completed.

As described above, since the semiconductor module 40 according to the second embodiment uses the first and second semiconductor devices in which the switching element and the rectifying element can be connected in parallel and reversely after the screening test, this semiconductor module 40, it is possible to improve reliability.
Further, according to the method of manufacturing the semiconductor module 40 according to the second embodiment, the first conductive material is Since the body 22a and the second conductor 22b are electrically connected by the bridge plate 30, an increase in the number of manufacturing steps can be suppressed, and a highly reliable semiconductor module can be provided at low cost.

Further, according to the method of manufacturing the semiconductor module 40 according to the second embodiment, the resin sealing of each of the first and second semiconductor devices is performed using the sealing resin that seals the first and second semiconductor devices. Since the opening provided in the stopper can be embedded, there is no need to increase the number of steps for embedding the opening. As a result, insulation can be maintained at low cost in the final module form.
Although the second embodiment describes a semiconductor module including two semiconductor devices, the present invention can also be applied to a semiconductor module including three or more semiconductor devices.

1... Semiconductor device 2... Transistor chip 2d... Drain electrode 2g... Gate electrode 2s... Source electrode 3... Diode chip 3a... Anode electrode 3k... Cathode electrode 5a... First conductive post 5b... Second conductive post 5c... Third conductive post 7a...First main circuit terminal (source main circuit terminal)
7b...Second main circuit terminal (drain main circuit terminal)
7c...Control terminal 7d...Auxiliary terminal 8...Resin sealing body (sealing body)
8a, 8b... Short side 8c, 8d... Long side 9... Opening 10... Insulated circuit board 11... Insulating plate 12... Conductive plate 12a... First conductive plate 12b... Second conductive plate 13... Metal plate 15, 16... Solder 15a, 16a...Solder paste material 20...Wiring board 21...Insulating plate 22a...First conductor 22a ₁ ...First portion 22a ₂ ...Second portion 22b...Second conductor 23a...Gate wiring 25...Substrate laminate 26... Power supply 30... Bridge plate 31... Solder 32... Insertion bridge member 40... Semiconductor module 41... Base member 42... Solder 43... Case 45... First bus bar 46... Second bus bar 47... Sealing resin

Claims (6)

an insulated circuit board having an insulating plate and a conductive plate;
a transistor chip installed on the insulated circuit board and having a first main electrode and a second main electrode;
a diode chip installed on the insulated circuit board, having an anode electrode and a cathode electrode, and the cathode electrode being electrically connected to the first main electrode of the transistor chip;
a first conductor electrically connected to the second main electrode of the transistor chip; and a second conductor electrically connected to the anode electrode of the diode chip; A semiconductor device comprising: a wiring board disposed on a side of the transistor chip and the diode chip at a distance from the insulating circuit board;
A connecting member electrically and mechanically connected to each of the first conductor and the second conductor by a bonding material is provided on the surface of the wiring board opposite to the insulated circuit board side. A semiconductor device characterized by: 2. The semiconductor device according to claim 1, wherein each of the first and second conductors is insulated and isolated from each other except for conduction through the connection member. a first main circuit terminal electrically connected to the first main electrode of the transistor chip and the cathode electrode of the diode chip;
a second main circuit terminal electrically connected to the first conductor;
a sealing body that seals the insulated circuit board, the transistor chip, the diode chip, and the first and second main circuit terminals except for a portion of each of the first and second main circuit terminals; Prepare,
The sealing body has an opening that exposes a portion of each of the first and second conductors,
3. The semiconductor device according to claim 1, wherein the connection member is connected to each of the first and second conductors through the opening. The conductive plate of the insulated circuit board includes a first conductive plate electrically connected to the first main circuit terminal, the first main electrode of the transistor chip, and the cathode electrode of the diode chip; 4. The semiconductor device according to claim 3, further comprising a main circuit terminal and a second conductive plate electrically connected to the first conductor. an insulated circuit board having an insulating plate and a conductive plate;
a transistor chip installed on the insulated circuit board 10 and having a first main electrode and a second main electrode;
a diode chip installed on the insulated circuit board, having an anode electrode and a cathode electrode, and the cathode electrode being electrically connected to the first main electrode of the transistor chip;
a first conductor electrically connected to the second main electrode of the transistor chip; and a second conductor electrically connected to the anode electrode of the diode chip; A method for manufacturing a semiconductor device, comprising: a wiring board disposed on a side of the transistor chip and the diode chip at a distance from the insulating circuit board;
conducting a screening test of the transistor chip by passing a current between the second main electrode and the first main electrode of the transistor chip;
After conducting the screening test, a conductive member is electrically and mechanically attached to each of the first conductor and the second conductor on the surface of the wiring board opposite to the insulated circuit board side using a bonding material. a step of connecting to the
A method for manufacturing a semiconductor device, comprising : A semiconductor module having a plurality of semiconductor devices installed on a main surface of a base member,
The plurality of semiconductor devices are
an insulated circuit board having an insulating plate and a conductive plate;
a transistor chip installed on the insulated circuit board 10 and having a first main electrode and a second main electrode;
a diode chip installed on the insulated circuit board, having an anode electrode and a cathode electrode, and the cathode electrode being electrically connected to the first main electrode of the transistor chip;
a first conductor electrically connected to the second main electrode of the transistor chip; and a second conductor electrically connected to the anode electrode of the diode chip; a wiring board placed on the side of the transistor chip and the diode chip and spaced apart from the insulated circuit board;
A connecting member electrically and mechanically connected to each of the first conductor and the second conductor by a bonding material on the surface of the wiring board opposite to the insulated circuit board side. A semiconductor module characterized by:

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