JP7331440B2 - Semiconductor switching element drive circuit and multi-level power converter - Google Patents

Description

The present invention relates to semiconductor switching element drive circuits and multilevel power converters.

Patent Document 1 discloses a multi-level power converter that switches an input voltage supplied from a load driving power supply using a semiconductor switching element and outputs a predetermined output voltage.

In recent years, compound semiconductor switching elements (for example, GaN devices, SiC devices, etc.) that enable high-speed switching, large-current driving, and high withstand voltage have been developed as semiconductor switching elements used in electric power converters. Off-type semiconductor switching elements are being used.

This normally-off type semiconductor switching element has a lower threshold voltage than an ordinary semiconductor switching element mainly composed of silicon. Therefore, it is necessary to apply a negative voltage to the control terminal in order to reliably control the semiconductor switching element to the cutoff state.
That is, in order to perform switching control of a semiconductor switching element with a low threshold voltage, it is necessary to generate a negative voltage as well as a positive voltage as a driving voltage.

JP 2009-177951 A

Therefore, in the multi-level power converter described in Patent Literature 1, a new power supply needs to be added in order to generate a negative voltage. As a result, the size of the device increases and the cost increases.

SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances, and its object is to generate a negative voltage without adding a new power supply when driving a semiconductor switching element of a multilevel power converter. .

(1) One aspect of the present invention is a semiconductor switching element drive circuit for driving n (n is an integer equal to or greater than 4) semiconductor switching elements provided in a multilevel power converter, wherein each of the semiconductor switching elements each of the drive circuits includes a first capacitor for generating a positive voltage for making the semiconductor switching element conductive, and a first end connected to the first capacitor. a second capacitor connected to the first end of and charging power discharged from the second capacitor in a charged state to generate a negative voltage for turning off the semiconductor switching element. and a first end of the first capacitor and a control terminal of the semiconductor switching element are connected to apply the positive voltage to the control terminal of the semiconductor switching element to perform the semiconductor switching. The negative voltage is applied to the control terminal of the semiconductor switching element by connecting the first end of the third capacitor and the control terminal to a conduction drive circuit that brings the element into conduction. A semiconductor switching element drive circuit, comprising: a circuit for breaking the switching element into a cut-off state.

(2) In the semiconductor switching element drive circuit of (1) above, the third capacitor has a first end connected to a second end of the second capacitor, and the third capacitor in a charged state. a charging circuit for charging the third capacitor by connecting the first end of the second capacitor and the second end of the third capacitor.

(3) In the semiconductor switching element drive circuit of (2) above, the charging circuit may charge the third capacitor via the conducting semiconductor switching element.

(4) The semiconductor switching element drive circuit according to any one of (1) to (3) above, further comprising a positive control power source, wherein the plurality of drive circuits are first to n-th drive circuits. a first end of the first capacitor provided in the m-th (m is an integer of 1 or more and less than n) drive circuit, and the (m+1)-th drive circuit provided in the The first end of the first capacitor is connected via a diode, and the first end of the first capacitor provided in the first drive circuit is connected to the control power supply. It may be connected to the positive terminal.

(5) A multi-level power converter comprising the semiconductor switching element drive circuit according to any one of (1) to (4) above, and n semiconductor switching elements driven by the semiconductor switching element drive circuit. .

As described above, according to the present invention, a negative voltage can be generated without adding a new power supply when driving semiconductor switching elements of a multilevel power converter.

1 is a schematic configuration diagram of a multilevel power converter A according to this embodiment; FIG. 2 is a circuit diagram of a semiconductor switching element drive circuit 6 according to this embodiment; FIG. 4 is a waveform diagram of output voltage V and output current I of multilevel power converter A in this embodiment. FIG. It is a figure which shows the operation pattern (1) which concerns on this embodiment. It is a figure which shows the operation pattern (2) which concerns on this embodiment. It is a figure which shows the operation pattern (3) which concerns on this embodiment. It is a figure which shows the operation pattern (4) which concerns on this embodiment. It is a figure which shows the 1st operation mode which concerns on this embodiment. It is a figure which shows the 2nd operation mode which concerns on this embodiment. It is a figure which shows the 3rd operation mode which concerns on this embodiment. It is a figure which shows the 4th operation mode which concerns on this embodiment. It is a figure which shows the 5th operation mode which concerns on this embodiment. 4 is an explanatory diagram showing the flow of operation of the semiconductor switching element drive circuit 6 in the first state according to the embodiment; FIG. FIG. 7 is an explanatory diagram showing the flow of operation of the semiconductor switching element drive circuit 6 in the second state according to the embodiment; FIG. 11 is an explanatory diagram showing the flow of operation of the semiconductor switching element drive circuit 6 in the third state according to the embodiment; FIG. 11 is an explanatory diagram showing the flow of operation of the semiconductor switching element drive circuit 6 in the fourth state according to the embodiment;

A multi-level power converter A including a semiconductor switching element drive circuit according to this embodiment will be described below.

The multilevel power converter A according to this embodiment is a multilevel inverter that outputs voltages of three levels. However, the multilevel power converter A is not limited to this, and may be a multilevel inverter or a multilevel converter that outputs three or more levels of voltage.
The multi-level power converter A of this embodiment is a three-level NPC (Neutral Point Clamped) inverter of a diode clamp system. However, without being limited to this, the multi-level power converter A may be of a flying capacitor type.

The configuration of the multilevel power converter A according to this embodiment will be described below with reference to FIG. FIG. 1 is a schematic configuration diagram of a multilevel power converter A according to this embodiment.

As shown in FIG. 1, a first input terminal P, a second input terminal N, a third input terminal NP, an output terminal OUT, n (n is an integer equal to or greater than 4) switching elements SW, a capacitor C1, A capacitor C2, a diode D1, a diode D2, a control signal generator 5, and a semiconductor switching element drive circuit 6 are provided.

The first input terminal P is connected to the positive terminal of the first DC power supply 100 . The first DC power supply 100 is a supply source of power supplied from the power converter A to a load such as a motor.
A second input terminal N is connected to the negative terminal of the first DC power supply 100 .
A third input terminal NP is connected to an intermediate potential point of the first DC power supply 100 . However, it is not limited to this, and the third input terminal NP may be connected to the ground.

The output terminal OUT is a terminal for outputting three levels of voltage. The output terminal OUT is connected to the load.

Between the first input terminal P and the second input terminal N, n switching elements SW are connected in series. In addition, in this embodiment, since the multilevel power converter A is a multilevel inverter that outputs voltages of three levels, n=4. That is, when the number of levels of the output voltage is K (integer of 3 or more), n=2K-2.

The n switching elements SW according to this embodiment include switching elements SW1 to SW4.
The switching elements SW1 to SW4 are connected in series between the first input terminal P and the second input terminal N. As shown in FIG. Each of the switching elements SW1 to SW4 is a semiconductor switching element that is turned on or off based on the gate voltage supplied from the semiconductor switching element driving circuit 6. FIG. As a result, the multilevel power converter A converts the input voltage supplied from the first DC power supply 100 into a voltage of a desired level and outputs the voltage to the load.

For example, the switching elements SW1 to SW4 are wide-gap semiconductor switching elements such as MOSFET (metal-oxide-semiconductor field-effect transistor), IGBT (Insulated Gate Bipolar Transistor), SiC (silicon carbide), GaN (gallium nitride), and the like. etc. In this embodiment, the switching elements SW1 to SW4 are n-type MOSFETs.

A drain terminal of the switching element SW1 is connected to a source terminal of the switching element SW2. A source terminal of the switching element SW1 is connected to the second input terminal N. A gate terminal of the switching element SW1 is connected to the semiconductor switching element drive circuit 6 .

A drain terminal of the switching element SW2 is connected to a source terminal of the switching element SW3. A source terminal of the switching element SW3 and a drain terminal of the switching element SW2 are connected to the output terminal OUT.
A source terminal of the switching element SW2 is connected to a drain terminal of the switching element SW1. A gate terminal of the switching element SW2 is connected to the semiconductor switching element drive circuit 6 .

A drain terminal of the switching element SW3 is connected to a source terminal of the switching element SW4. A source terminal of the switching element SW3 is connected to a drain terminal of the switching element SW2. A gate terminal of the switching element SW3 is connected to the semiconductor switching element drive circuit 6 .

A drain terminal of the switching element SW4 is connected to the first input terminal P. As shown in FIG. A source terminal of the switching element SW4 is connected to a drain terminal of the switching element SW3. A gate terminal of the switching element SW4 is connected to the semiconductor switching element drive circuit 6 .

The capacitor C1 has a first end connected to the first input terminal P and a second end connected to the third input terminal NP.
The capacitor C2 has a first end connected to the second end of the capacitor C1 and the third input terminal NP, and a second end connected to the second input terminal N.

The diode D1 has an anode connected to the third input terminal NP and a cathode connected to the source terminal of the switching element SW4 and the drain terminal of the switching element SW3.
The diode D2 has a cathode connected to the third input terminal NP and an anode connected to the source terminal of the switching element SW2 and the drain terminal of the switching element SW1.

The control signal generator 5 is connected to the semiconductor switching element drive circuit 6 . The control signal generator 5 outputs a control signal to the semiconductor switching element drive circuit 6 to instruct generation of the gate voltage. A control signal is, for example, a PWM (pulse width modulation) signal.

Based on the control signal output from the control signal generator 5, the semiconductor switching element drive circuit 6 controls each of the switching elements SW1 to SW4 to turn on or off. The semiconductor switching element drive circuit 6 outputs a gate voltage to each gate terminal of the switching elements SW1 to SW4 based on the output voltage from the second DC power supply 7 which is a single power supply.

A specific configuration of the semiconductor switching element drive circuit 6 according to this embodiment will be described below with reference to FIG. FIG. 2 is a circuit diagram of the semiconductor switching element drive circuit 6 according to this embodiment.

As shown in FIG. 2 , the semiconductor switching element drive circuit 6 includes a second DC power supply 7 and a plurality of drive circuits 8 .

The second DC power supply 7 is a positive control power supply. For example, the second DC power supply 7 may be a power supply for driving the switching elements SW1 to SW4, or may be a power supply for driving other devices (not shown). The output voltage of the second DC power supply 7 is the output voltage VDD.

The plurality of drive circuits 8 includes m-th drive circuit to (m+1)-th drive circuit. In addition, m is an integer greater than or equal to 1 and less than n. In this embodiment, since n=4, the multiple drive circuits 8 include a first drive circuit 8a, a second drive circuit 8b, a third drive circuit 8c and a fourth drive circuit 8d.

The first drive circuit 8a is provided corresponding to the switching element SW1. The first drive circuit 8a controls ON/OFF of the switching element SW1 based on the output voltage VDD from the second DC power supply 7 . Specifically, in order to sufficiently turn on the switching element SW1, the first drive circuit 8a generates a positive voltage to be applied to the gate terminal of the switching element SW1 as a gate voltage, and applies the generated positive voltage to the gate of the switching element SW1. Apply to terminal. Further, in order to sufficiently turn off (cut off) the switching element SW1, the first drive circuit 8a generates a negative voltage to be applied to the gate terminal of the switching element SW1 as a gate voltage, and applies the generated negative voltage to the switching element SW1. applied to the gate terminal of

The second drive circuit 8b is provided corresponding to the switching element SW2. The second drive circuit 8b controls ON/OFF of the switching element SW2 based on the output voltage VDD from the second DC power supply 7. FIG. Specifically, in order to sufficiently turn on the switching element SW2, the second drive circuit 8b generates a positive voltage to be applied to the gate terminal of the switching element SW2 as a gate voltage, and applies the generated positive voltage to the gate of the switching element SW2. Apply to terminal. Further, in order to sufficiently turn off (cut off) the switching element SW2, the second drive circuit 8b generates a negative voltage to be applied to the gate terminal of the switching element SW2 as a gate voltage, and applies the generated negative voltage to the switching element SW2. applied to the gate terminal of

A third drive circuit 8c is provided corresponding to the switching element SW3. The third drive circuit 8c controls ON/OFF of the switching element SW3 based on the output voltage VDD from the second DC power supply 7. FIG. Specifically, in order to sufficiently turn on the switching element SW3, the third drive circuit 8c generates a positive voltage to be applied to the gate terminal of the switching element SW3 as a gate voltage, and applies the generated positive voltage to the gate of the switching element SW3. Apply to terminal. Further, the third drive circuit 8c generates, as a gate voltage, a negative voltage to be applied to the gate terminal of the switching element SW3 in order to sufficiently turn off (cut off state) the switching element SW3, and applies the generated negative voltage to the switching element SW3. applied to the gate terminal of

A fourth drive circuit 8d is provided corresponding to the switching element SW4. The fourth drive circuit 8 d controls ON or OFF of the switching element SW4 based on the output voltage VDD from the second DC power supply 7 . Specifically, in order to sufficiently turn on the switching element SW4, the fourth drive circuit 8d generates a positive voltage to be applied to the gate terminal of the switching element SW4 as a gate voltage, and applies the generated positive voltage to the gate of the switching element SW4. Apply to terminal. Further, the fourth drive circuit 8d generates a negative voltage to be applied to the gate terminal of the switching element SW4 as a gate voltage in order to sufficiently turn off (cut off state) the switching element SW4, and applies the generated negative voltage to the switching element SW4. applied to the gate terminal of

The configurations of the first drive circuit 8a to the fourth drive circuit 8d according to this embodiment will be specifically described below. Components having similar functions are denoted by the same reference numerals, and description thereof may be omitted. However, for the purpose of distinguishing each component of the first drive circuit 8a to the fourth drive circuit 8d, the suffix "a" is attached to the end of each component of the first drive circuit 8a. The suffix "b" is added to the end of each component of the drive circuit 8b of No. 2, the suffix "c" is added to the end of the reference of each component of the third drive circuit 8c, and the fourth The suffix "d" may be attached to the end of the reference numerals of the components of the drive circuit 8d in some cases.

First, the configuration of the first drive circuit 8a according to this embodiment will be described.

The first drive circuit 8a includes a positive power supply capacitor 9a (first capacitor), a negative power supply buffer capacitor 10a (second capacitor), a backflow prevention diode 11a, a limiting resistor 12a, a charge/discharge control section 13a, a rectifier diode 14a, voltage limiting diode 15a, negative power supply capacitor 16a (third capacitor), and limiting resistor 17a.

The positive power supply capacitor 9a has a first end connected to the positive terminal of the second DC power supply 7 and a second end connected to the negative terminal of the second DC power supply 7 and the source terminal of the switching element SW1. It is

The negative power supply buffer capacitor 10a has a first end connected to the first end of the positive power supply capacitor 9a and the positive terminal of the second DC power supply 7, and a second end connected to the rectifying diode 14a. It is connected to the cathode and the anode of the voltage limiting diode 15a.
The backflow prevention diode 11a has an anode connected to the first terminal of the negative power buffer capacitor 10a and a cathode connected to the drain terminal of the switching element SW1 via the limiting resistor 12a.

The limiting resistor 12a has a first end connected to the cathode of the backflow prevention diode 11a and a second end connected to the drain terminal of the switching element SW1.
Based on the control signal output from the control signal generator 5, the charge/discharge controller 13a controls charging and discharging of the positive power supply capacitor 9a, the negative power supply buffer capacitor 10a, and the negative power supply capacitor 16a. The configuration of the charge/discharge control unit 13a will be specifically described below.

The charge/discharge control unit 13a includes a switching element 20a (drive circuit for conduction) and a switching element 21a (drive circuit for interruption).
The switching element 20a supplies a conduction drive signal to the gate terminal of the switching element SW1. The conduction drive signal is a signal that turns on the switching element 20a, and is, for example, a positive gate voltage. For example, the switching element 20a is an NPN IGBT.

The switching element 21a supplies a cut-off drive signal to the gate terminal of the switching element SW1. The cut-off drive signal is a signal that turns off the switching element 20a, and is, for example, a negative gate voltage. For example, the switching element 21a is a PNP IGBT.
In the present embodiment, the charge/discharge control unit 13a is a push-pull circuit using the switching element 20a and the switching element 21a, but is not limited to this, and is a control circuit that controls on or off of the switching element SW1. There is no particular limitation, if any.

The collector terminal of the switching element 20a is connected to the first end of the positive power supply capacitor 9a and the first end of the negative power supply buffer capacitor 10a. The emitter terminal of the switching element 20a is connected to the emitter terminal of the switching element 21a. A base terminal of the switching element 20a and a base terminal of the switching element 21a are connected to the control signal generator 5. FIG. A connection point between the emitter terminal of the switching element 20a and the emitter terminal of the switching element 21a is connected to the gate terminal of the switching element SW1 via the limiting resistor 17a. A collector terminal of the switching element 21a is connected to a first end of the negative power supply capacitor 16a.

The rectifying diode 14a has an anode connected to the first end of the negative power supply capacitor 16a and a cathode connected to the second end of the negative power supply buffer capacitor 10a.

The voltage limiting diode 15a is connected in parallel with the negative power supply capacitor 16a. For example, the voltage limiting diode 15a has an anode connected to the second end of the negative power supply buffer capacitor 10a and a cathode connected to the second end of the positive power supply capacitor 9a. The voltage limiting diode 15a limits the voltage across the negative power supply capacitor 16a to a predetermined voltage. The predetermined voltage corresponds to a negative gate voltage applied to the gate terminal of the switching element SW1. Therefore, it is set based on the gate voltage when the switching element SW1 is turned off and the withstand voltage of the gate terminal of the switching element SW1. In this embodiment, the voltage limiting diode 15a is a so-called Zener diode, and the breakdown voltage of the Zener diode corresponds to the predetermined voltage.

The negative power supply capacitor 16a has a first end connected to the anode of the rectifying diode 14a and the collector terminal of the switching element 21a, and a second end connected to the second end of the positive power supply capacitor 9a and the second end of the positive power supply capacitor 9a. is connected to the negative electrode terminal of the DC power supply 7 of . A second end of the negative power supply capacitor 16a is connected to the source terminal of the switching element SW1.

The limiting resistor 17a has a first end connected to the emitter terminal of the switching element 20a and the emitter terminal of the switching element 21a, and a second end connected to the gate terminal of the switching element SW1.

Next, the configuration of the second drive circuit 8b according to this embodiment will be described.

The second drive circuit 8b includes a positive power supply capacitor 9b (first capacitor), a negative power supply buffer capacitor 10b (second capacitor), a backflow prevention diode 11b, a limiting resistor 12b, a charge/discharge control section 13b, a rectifier diode 14b, voltage limiting diode 15b, negative power supply capacitor 16b (third capacitor), limiting resistor 17b, limiting resistor 18b, and backflow prevention diode 19b.

The positive power supply capacitor 9b has a first end connected to the cathode of the backflow prevention diode 19b and a second end connected to the source terminal of the switching element SW2.

The negative power supply buffer capacitor 10b has a first end connected to the first end of the positive power supply capacitor 9b and the cathode of the reverse current prevention diode 19b, and a second end connected to the cathode of the rectification diode 14b and the cathode of the reverse current prevention diode 19b. It is connected to the anode of the voltage limiting diode 15b.
The backflow prevention diode 11b has an anode connected to the first terminal of the negative power supply buffer capacitor 10b and a cathode connected to the drain terminal of the switching element SW2 via the limiting resistor 12b.

The limiting resistor 12b has a first end connected to the cathode of the backflow prevention diode 11b and a second end connected to the drain terminal of the switching element SW2.
The charge/discharge control section 13b controls charge/discharge of the positive power supply capacitor 9b, the negative power supply buffer capacitor 10b, and the negative power supply capacitor 16b based on the control signal output from the control signal generation section 5. FIG. The configuration of the charge/discharge control unit 13b will be specifically described below.

The charge/discharge control unit 13b includes a switching element 20b (drive circuit for conduction) and a switching element 21b (drive circuit for interruption).
The switching element 20b supplies a conduction drive signal to the gate terminal of the switching element SW2. For example, the switching element 20b is an NPN IGBT.

The switching element 21b supplies a cut-off drive signal to the gate terminal of the switching element SW2. For example, the switching element 21b is a PNP IGBT.
In the present embodiment, the charge/discharge control unit 13b is a push-pull circuit using the switching element 20b and the switching element 21b, but is not limited to this, and is a control circuit that controls on or off of the switching element SW2. There is no particular limitation, if any.

The collector terminal of the switching element 20b is connected to the first end of the positive power supply capacitor 9b and the first end of the negative power supply buffer capacitor 10b. The emitter terminal of the switching element 20b is connected to the emitter terminal of the switching element 21b. A base terminal of the switching element 20b and a base terminal of the switching element 21b are connected to the control signal generator 5. FIG. A connection point between the emitter terminal of the switching element 20b and the emitter terminal of the switching element 21b is connected to the gate terminal of the switching element SW2 via the limiting resistor 17b. A collector terminal of the switching element 21b is connected to a first end of the negative power supply capacitor 16b.

The rectifying diode 14b has an anode connected to the first end of the negative power supply capacitor 16b and a cathode connected to the second end of the negative power supply buffer capacitor 10b.

The voltage limiting diode 15b is connected in parallel with the negative power supply capacitor 16b. For example, the voltage limiting diode 15b has an anode connected to the second end of the negative power supply buffer capacitor 10b and a cathode connected to the second end of the positive power supply capacitor 9b. The voltage limiting diode 15b limits the voltage across the negative power supply capacitor 16b to a predetermined voltage. The predetermined voltage corresponds to a negative gate voltage applied to the gate terminal of the switching element SW2. Therefore, it is set based on the gate voltage when the switching element SW2 is turned off and the withstand voltage of the gate terminal of the switching element SW2. In this embodiment, the voltage limiting diode 15b is a so-called Zener diode, and the breakdown voltage of the Zener diode corresponds to the predetermined voltage.

The negative power supply capacitor 16b has a first end connected to the anode of the rectifying diode 14b and the collector terminal of the switching element 21b, and a second end connected to the second end of the positive power supply capacitor 9b. ing. A second end of the negative power supply capacitor 16b is connected to the source terminal of the switching element SW2.

The limiting resistor 17b has a first end connected to the emitter terminal of the switching element 20b and the emitter terminal of the switching element 21b, and a second end connected to the gate terminal of the switching element SW2.

The limiting resistor 18b has a first end connected to the positive terminal of the second DC power supply 7 and a second end connected to the anode of the backflow prevention diode 19b.
The backflow prevention diode 19b has an anode connected to the positive terminal of the second DC power supply 7 via a limiting resistor 18b, and a cathode connected to the first end of the positive power supply capacitor 9b and the first end of the negative power supply buffer capacitor 10b. 1 end.

Next, the configuration of the third drive circuit 8c according to this embodiment will be described.

The third drive circuit 8c includes a positive power supply capacitor 9c (first capacitor), a negative power supply buffer capacitor 10c (second capacitor), a backflow prevention diode 11c, a limiting resistor 12c, and a charge/discharge control section 13c (second capacitor). 3), a rectifying diode 14c, a voltage limiting diode 15c, a negative power supply capacitor 16c, a limiting resistor 17c, a limiting resistor 18c, and a backflow prevention diode 19c.

The positive power supply capacitor 9c has a first end connected to the cathode of the backflow prevention diode 19c and a second end connected to the source terminal of the switching element SW3.

The negative power supply buffer capacitor 10c has a first end connected to the first end of the positive power supply capacitor 9c and the cathode of the backflow prevention diode 19c, and a second end connected to the cathode of the rectifier diode 14c and the cathode of the reverse current prevention diode 19c. It is connected to the anode of the voltage limiting diode 15c.
The backflow prevention diode 11c has an anode connected to the first terminal of the negative power supply buffer capacitor 10c and a cathode connected to the drain terminal of the switching element SW3 via the limiting resistor 12c.

The limiting resistor 12c has a first end connected to the cathode of the backflow prevention diode 11c and a second end connected to the drain terminal of the switching element SW3.
Based on the control signal output from the control signal generator 5, the charge/discharge controller 13c controls the charge/discharge of the positive power supply capacitor 9c, the negative power supply buffer capacitor 10c, and the negative power supply capacitor 16c. The configuration of the charge/discharge control unit 13c will be specifically described below.

The charge/discharge control unit 13c includes a switching element 20c (drive circuit for conduction) and a switching element 21c (drive circuit for interruption).
The switching element 20c supplies a conduction drive signal to the gate terminal of the switching element SW3. For example, the switching element 20c is an NPN IGCT.

The switching element 21c supplies a cutoff drive signal to the gate terminal of the switching element SW3. For example, the switching element 21c is a PNP-type IGCT.
In this embodiment, the charge/discharge control unit 13c is a push-pull circuit using the switching element 20c and the switching element 21c. There is no particular limitation, if any.

The collector terminal of the switching element 20c is connected to the first end of the positive power supply capacitor 9c and the first end of the negative power supply buffer capacitor 10c. The emitter terminal of the switching element 20c is connected to the emitter terminal of the switching element 21c. A base terminal of the switching element 20c and a base terminal of the switching element 21c are connected to the control signal generator 5. FIG. A connection point between the emitter terminal of the switching element 20c and the emitter terminal of the switching element 21c is connected to the gate terminal of the switching element SW3 via the limiting resistor 17c. A collector terminal of the switching element 21c is connected to a first end of the negative power supply capacitor 16c.

The rectifying diode 14c has an anode connected to the first end of the negative power supply capacitor 16c and a cathode connected to the second end of the negative power supply buffer capacitor 10c.

The voltage limiting diode 15c is connected in parallel with the negative power supply capacitor 16c. For example, the voltage limiting diode 15c has an anode connected to the second end of the negative power supply buffer capacitor 10c and a cathode connected to the second end of the positive power supply capacitor 9c. The voltage limiting diode 15c limits the voltage across the negative power supply capacitor 16c to a predetermined voltage. The predetermined voltage corresponds to a negative gate voltage applied to the gate terminal of the switching element SW3. Therefore, it is set based on the gate voltage when the switching element SW3 is turned off and the withstand voltage of the gate terminal of the switching element SW3. In this embodiment, the voltage limiting diode 15c is a so-called Zener diode, and the breakdown voltage of the Zener diode corresponds to the predetermined voltage.

The negative power supply capacitor 16c has a first end connected to the anode of the rectifying diode 14c and the collector terminal of the switching element 21c, and a second end connected to the second end of the positive power supply capacitor 9c. ing. A second end of the negative power supply capacitor 16c is connected to the source terminal of the switching element SW3.

The limiting resistor 17c has a first end connected to the emitter terminal of the switching element 20c and the emitter terminal of the switching element 21c, and a second end connected to the gate terminal of the switching element SW3.

The limiting resistor 18c has a first end connected to the cathode of the backflow prevention diode 19b and a second end connected to the anode of the backflow prevention diode 19c.
The backflow prevention diode 19c has an anode connected to the cathode of the backflow prevention diode 19b via the limiting resistor 18c, and a cathode connected to the first end of the positive power supply capacitor 9c and the first end of the negative power supply buffer capacitor 10c. connected to the ends.

Next, the configuration of the fourth drive circuit 8d according to this embodiment will be described.

The fourth drive circuit 8d includes a positive power supply capacitor 9d (first capacitor), a negative power supply buffer capacitor 10d (second capacitor), a backflow prevention diode 11d, a limiting resistor 12d, a charge/discharge control section 13d, a rectifier diode 14d, voltage limiting diode 15d, negative power supply capacitor 16d (third capacitor), limiting resistor 17d, limiting resistor 18d, and backflow prevention diode 19d.

The positive power supply capacitor 9d has a first end connected to the cathode of the backflow prevention diode 19d and a second end connected to the source terminal of the switching element SW4.

The negative power supply buffer capacitor 10d has a first end connected to the first end of the positive power supply capacitor 9d and the cathode of the backflow prevention diode 19d, and a second end connected to the cathode of the rectification diode 14d and the cathode of the reverse current prevention diode 19d. It is connected to the anode of the voltage limiting diode 15d.
The backflow prevention diode 11d has an anode connected to the first terminal of the negative power buffer capacitor 10d and a cathode connected to the drain terminal of the switching element SW4 via the limiting resistor 12d.

The limiting resistor 12d has a first end connected to the cathode of the backflow prevention diode 11d and a second end connected to the drain terminal of the switching element SW4.
Based on the control signal output from the control signal generator 5, the charge/discharge controller 13d controls charging and discharging of the positive power supply capacitor 9d, the negative power supply buffer capacitor 10d, and the negative power supply capacitor 16d. The configuration of the charge/discharge control unit 13d will be specifically described below.

The charge/discharge control unit 13d includes a switching element 20d (drive circuit for conduction) and a switching element 21d (drive circuit for interruption).
The switching element 20d supplies a conduction drive signal to the gate terminal of the switching element SW4. For example, the switching element 20d is an NPN IGCT.

The switching element 21d supplies a cut-off drive signal to the gate terminal of the switching element SW4. For example, the switching element 21d is a PNP-type IGCT.
In the present embodiment, the charge/discharge control unit 13d is a push-pull circuit using the switching element 20d and the switching element 21d, but is not limited to this, and is a control circuit that controls on or off of the switching element SW4. There is no particular limitation, if any.

The collector terminal of the switching element 20d is connected to the first end of the positive power supply capacitor 9d and the first end of the negative power supply buffer capacitor 10d. The emitter terminal of the switching element 20d is connected to the emitter terminal of the switching element 21d. A base terminal of the switching element 20d and a base terminal of the switching element 21d are connected to the control signal generator 5. FIG. A connection point between the emitter terminal of the switching element 20d and the emitter terminal of the switching element 21d is connected to the gate terminal of the switching element SW4 via the limiting resistor 17d. A collector terminal of the switching element 21d is connected to a first end of the negative power supply capacitor 16d.

The rectifying diode 14d has an anode connected to the first end of the negative power supply capacitor 16d and a cathode connected to the second end of the negative power supply buffer capacitor 10d.

The voltage limiting diode 15d is connected in parallel with the negative power supply capacitor 16d. For example, the voltage limiting diode 15d has an anode connected to the second end of the negative power supply buffer capacitor 10d and a cathode connected to the second end of the positive power supply capacitor 9d. The voltage limiting diode 15d limits the voltage across the negative power supply capacitor 16d to a predetermined voltage. The predetermined voltage corresponds to a negative gate voltage applied to the gate terminal of the switching element SW4. Therefore, it is set based on the gate voltage when the switching element SW4 is turned off and the withstand voltage of the gate terminal of the switching element SW4. In this embodiment, the voltage limiting diode 15d is a so-called Zener diode, and the breakdown voltage of the Zener diode corresponds to the predetermined voltage.

The negative power supply capacitor 16d has a first end connected to the anode of the rectifying diode 14d and the collector terminal of the switching element 21d, and a second end connected to the second end of the positive power supply capacitor 9d. ing. A second end of the negative power supply capacitor 16d is connected to the source terminal of the switching element SW4.

The limiting resistor 17d has a first end connected to the emitter terminal of the switching element 20d and the emitter terminal of the switching element 21d, and a second end connected to the gate terminal of the switching element SW4.

The limiting resistor 18d has a first end connected to the cathode of the backflow prevention diode 19c and a second end connected to the anode of the backflow prevention diode 19d.
The backflow prevention diode 19d has an anode connected to the cathode of the backflow prevention diode 19c via a limiting resistor 18d, and a cathode connected to the first end of the positive power supply capacitor 9d and the first end of the negative power supply buffer capacitor 10d. connected to the ends.

The operation of the multilevel power converter A in this embodiment will be described below with reference to FIGS. 3 to 7. FIG. FIG. 3 is a waveform diagram of the output voltage V and the output current I of the multilevel power converter A in this embodiment.

The semiconductor switching element drive circuit 6 of the multilevel power converter A turns on or off the switching elements SW1 to SW4 in accordance with a plurality of preset operation patterns (1) to (4), thereby generating a sine current from the output terminal OUT. Perform normal operation to output waves. A plurality of operation patterns (1) to (4) are determined from the positive/negative relationship between the output voltage V and the output current I, as shown in FIG. Operation patterns (1) to (4) represent switching operations of the switching elements SW1 to SW4.

Specifically, the operation pattern (1) is an operation pattern in which the first state and the second state are alternately repeated, as shown in FIG. In the first state, as shown in FIG. 4A, the switching element S1 and the switching element SW2 are in the OFF state, and the switching element S3 and the switching element SW4 are in the ON state. In the second state, as shown in FIG. 4B, the switching element S1 and the switching element SW4 are in the OFF state, and the switching element S2 and the switching element SW3 are in the ON state.
The operation pattern (1) is an operation pattern performed when both the output voltage V and the output current I are positive (V>0, I>0).

Operation pattern (2) is an operation pattern in which the third state and the fourth state are alternately repeated, as shown in FIG. In the third state, as shown in FIG. 5A, the switching element S3 and the switching element SW4 are in the OFF state, and the switching element S1 and the switching element SW2 are in the ON state. In the fourth state, as shown in FIG. 5B, the switching element S1 and the switching element SW4 are in the OFF state, and the switching element S2 and the switching element SW3 are in the ON state.
The operation pattern (2) is an operation pattern performed when the output voltage V is negative and the output current I is positive (V<0, I>0).

Operation pattern (3) is an operation pattern in which the fifth state and the sixth state are alternately repeated, as shown in FIG. In the fifth state, as shown in FIG. 6A, the switching element S3 and the switching element SW4 are in the OFF state, and the switching element S1 and the switching element SW2 are in the ON state. In the sixth state, as shown in FIG. 6B, the switching element S1 and the switching element SW4 are in the OFF state, and the switching element S2 and the switching element SW3 are in the ON state.
The operation pattern (3) is an operation pattern performed when both the output voltage V and the output current I are negative (V<0, I<0).

Operation pattern (4) is an operation pattern in which the seventh state and the eighth state are alternately repeated, as shown in FIG. In the seventh state, as shown in FIG. 7A, the switching element S1 and the switching element SW4 are in the OFF state, and the switching element S2 and the switching element SW3 are in the ON state. In the eighth state, as shown in FIG. 7B, the switching element S1 and the switching element SW2 are in the OFF state, and the switching element S3 and the switching element SW4 are in the ON state.
The operation pattern (4) is an operation pattern performed when the output voltage V is positive and the output current I is negative (V>0, I<0).

Thus, the semiconductor switching element drive circuit 6 selects one of the operation patterns (1) to (4) based on the positive/negative relationship between the output voltage V and the output current I, and selects the selected operation pattern. By controlling the switching operations of the switching elements SW1 to SW4 in accordance with , a normal operation for outputting a sine wave from the output terminal OUT is executed. However, the semiconductor switching element drive circuit 6 needs to perform the charging operation in advance before performing the normal operation. The charging operation is an operation of charging the positive power supply capacitors 9b to 9d and the negative power supply buffer capacitors 10b to 10d. The positive power supply capacitor 9a and the negative power supply buffer capacitor 10a are always charged regardless of the switching operations of the switching elements SW1 to SW4.
The charging operation according to this embodiment will be described below with reference to FIGS. 8 to 12. FIG.

The semiconductor switching element driving circuit 6 performs charging operation by controlling the switching elements SW1 to SW4 to be on or off. Semiconductor switching element drive circuit 6 executes a charging operation by executing a plurality of operations among the first to fifth operation modes.

<First Operation Mode>
In the first operation mode, as shown in FIG. 8, the semiconductor switching element drive circuit 6 controls the switching element SW1 to be on and the switching elements SW2 to SW4 to be off. In the first mode, the current from the second DC power supply 7 passes through the first charging circuit W1 consisting of the limiting resistor 18b, the reverse current prevention diode 19b, the positive power supply capacitor 9b, and the switching element SW1. As a result, the positive power supply capacitor 9b is charged. The current from the second DC power supply 7 passes through a second charging circuit W2 consisting of a limiting resistor 18b, a backflow preventing diode 19b, a negative power buffer capacitor 10b, a voltage limiting diode 15b, and a switching element SW1. As a result, the negative power supply buffer capacitor 10b is charged. Therefore, in the first operation mode, the positive power supply capacitor 9b and the negative power supply buffer capacitor 10b are charged from the second DC power supply 7 by turning on the switching element SW1.

<Second Operation Mode>
In the second operation mode, as shown in FIG. 9, the semiconductor switching element drive circuit 6 controls the switching elements SW1 and SW2 to be on and the switching elements SW3 and SW4 to be off. Therefore, since the first charging circuit W1 and the second charging circuit W2 are formed, charges are charged from the second DC power supply 7 to the positive power supply capacitor 9b and the negative power supply buffer capacitor 10b.
Furthermore, in the second operation mode, since the switching element SW2 is in the ON state, the current from the second DC power supply 7 is limited to the limiting resistor 18b, the backflow preventing diode 19b, the limiting resistor 18c, the backflow preventing diode 19c, It passes through a third charging circuit W3 comprising a positive power supply capacitor 9c, a switching element SW2, and a switching element SW1. As a result, the positive power supply capacitor 9c is charged. Also, the current from the second DC power supply 7 flows through a limiting resistor 18b, a backflow preventing diode 19b, a limiting resistor 18c, a backflow preventing diode 19c, a negative power supply buffer capacitor 10c, a voltage limiting diode 15c, a switching element SW2, a It passes through a fourth charging circuit W4 comprising a switching element SW1. As a result, the negative power supply buffer capacitor 10c is charged.

<Third Operation Mode>
As shown in FIG. 10, the third operation mode is a mode in which the semiconductor switching element drive circuit 6 controls the switching element SW2 to be on and the switching elements SW1, SW3 and SW4 to be off. The third operation mode is an operation mode executed in a state where the positive power supply capacitor 9b is charged, and only the switching element SW2 is controlled to be turned on, so that the positive power supply capacitor 9b is charged. The positive power supply capacitor 9c and the negative power supply buffer capacitor 10c are charged. The state in which the positive power supply capacitor 9b is charged is, for example, a state in which the positive power supply capacitor 9b is charged to the same potential as the potential (VDD) of the positive terminal of the second DC power supply 7 .
Specifically, the current from the positive power supply capacitor 9b passes through a fifth charging circuit W5 consisting of a limiting resistor 18c, a backflow prevention diode 19c, a positive power supply capacitor 9c, and a switching element SW2. As a result, the positive power supply capacitor 9c is charged. The current from the positive power supply capacitor 9b passes through a sixth charging circuit W6 consisting of a limiting resistor 18c, a backflow prevention diode 19c, a negative power supply buffer capacitor 10c, a voltage limiting diode 15c, and a switching element SW2. As a result, the negative power supply buffer capacitor 10c is charged.

<Fourth Operation Mode>
In the fourth operation mode, as shown in FIG. 11, the semiconductor switching element drive circuit 6 controls the switching elements SW2 and SW3 to be on and the switching elements SW1 and SW4 to be off. The fourth operation mode is an operation mode executed in a state where the positive power supply capacitor 9b is charged, and the switching elements SW2 and SW3 are controlled to be in the ON state, so that the positive power supply capacitor 9b is charged. are charged to positive power supply capacitors 9c and 9d and negative power supply buffer capacitors 10c and 10d.
Specifically, since the fifth charging circuit W5 and the sixth charging circuit W6 are formed, the positive power supply capacitor 9c and the negative power supply buffer capacitor 10c are charged.
Furthermore, since the switching element SW3 is in the ON state, the current from the positive power supply capacitor 9b flows through the limiting resistor 18c, the backflow prevention diode 19c, the limiting resistor 18d, the backflow prevention diode 19d, the positive power supply capacitor 9d, and the switching element. SW3 and a seventh charging circuit W7 comprising a switching element SW2. As a result, the positive power supply capacitor 9d is charged. Also, the current from the positive power supply capacitor 9b flows through a limiting resistor 18c, a backflow preventing diode 19c, a limiting resistor 18d, a backflow preventing diode 19d, a negative power supply buffer capacitor 10d, a voltage limiting diode 15d, a switching element SW3, and a switching element SW3. It passes through an eighth charging circuit W8 consisting of element SW2. As a result, the negative power supply buffer capacitor 10d is charged.

<Fifth Operation Mode>
As shown in FIG. 12, the fifth operation mode is a mode in which the semiconductor switching element drive circuit 6 controls the switching element SW3 to the ON state and controls the switching elements SW1, SW2 and SW4 to the OFF state. The fifth operation mode is an operation mode executed in a state where the positive power supply capacitor 9c is charged, and only the switching element SW3 is controlled to be turned on, so that the positive power supply capacitor 9c is charged. The positive power supply capacitor 99d and the negative power supply buffer capacitor 10d are charged. The state in which the positive power supply capacitor 9c is charged is, for example, a state in which the positive power supply capacitor 9c is charged to the same potential as the potential (VDD) of the positive terminal of the second DC power supply 7 .
Specifically, since the switching element SW3 is in the ON state, the current from the positive power supply capacitor 9c flows through the ninth charging current formed by the limiting resistor 18d, the reverse current prevention diode 19d, the positive power supply capacitor 9d, and the switching element SW3. through circuit W9. As a result, the positive power supply capacitor 9d is charged. The current from the positive power supply capacitor 9c passes through a tenth charging circuit W10 consisting of a limiting resistor 18d, a backflow prevention diode 19d, a negative power supply buffer capacitor 10d, a voltage limiting diode 15d, and a switching element SW3. As a result, the negative power supply buffer capacitor 10d is charged.

In this manner, for example, the semiconductor switching element drive circuit 6 performs the charging operation by switching the operation modes in order of the first operation mode, the second operation mode, and the fourth operation mode before executing the normal operation. Execute. As a result, the semiconductor switching element drive circuit 6 can charge the positive power supply capacitors 9b to 9d and the negative power supply buffer capacitors 10b to 10d. However, the charging operation only needs to charge the positive power supply capacitors 9b to 9d and the negative power supply buffer capacitors 10b to 10d. Not limited to action. For example, the charging operation may be an operation of switching in the order of the second operation mode and the fourth operation mode, or an operation of switching in the order of the first operation mode, the second operation mode and the fifth operation mode. There may be.

The normal operation of the multilevel power converter A in this embodiment will be specifically described below with reference to FIGS. 13 to 16. FIG. First, the case of operation pattern (1) will be described.

<First state>
FIG. 13 is an explanatory diagram showing the flow of operation of the semiconductor switching element drive circuit 6 in the first state according to this embodiment.

As shown in FIG. 13, the charge/discharge control unit 13a controls the switching element 21a to be in the ON state, thereby conducting the first end of the negative power supply capacitor 16a and the gate terminal of the switching element SW1. As a result, the electric charge charged in the negative power supply capacitor 16a passes through the input capacitance 200a of the switching element SW1, the switching element 21a, and returns to the negative power supply capacitor 16a. In this case, since the electric charge charged in the input capacitor 200a is discharged, the switching element SW1 is turned off from on. In other words, the negative charge charged in the negative power supply capacitor 16a passes through the switching element 21a, the input capacitor 200a, and the path returning to the second end of the negative power supply capacitor 16a. Therefore, by supplying negative charges from the first end of the negative power supply capacitor 16a to the gate terminal of the switching element b2, a negative gate voltage is applied to the gate terminal of the switching element SW1. As a result, the switching element SW1 is turned off.

Similarly, as shown in FIG. 13, since the switching element 21b is turned on, the charge/discharge control section 13b conducts the first end of the negative power supply capacitor 16b and the gate terminal of the switching element SW2. As a result, the charge charged in the negative power supply capacitor 16b passes through the input capacitance 200b of the switching element SW2, the switching element 21b, and returns to the negative power supply capacitor 16b. In this case, the electric charge stored in the input capacitor 200b is discharged, so that the switching element SW2 is turned off from on. In other words, the negative charge charged in the negative power supply capacitor 16b passes through the switching element 21b, the input capacitor 200b, and the path returning to the second end of the negative power supply capacitor 16b. Therefore, by supplying negative charges from the first end of the negative power supply capacitor 16b to the gate terminal of the switching element SW2, a negative gate voltage is applied to the gate terminal of the switching element SW2. As a result, the switching element SW2 is turned off.

The charge/discharge control unit 13c controls the switching element 20c to be on and the switching element 21c to be off. As a result, the electric charge charged in the positive power supply capacitor 9c passes through the switching element 20c and the input capacitance 200c of the switching element SW3, and returns to the second end of the positive power supply capacitor 9c. Therefore, the input capacitor 200c starts charging with the charge discharged from the positive power supply capacitor 9c. After that, when the input capacitor 200c is charged with a certain amount of charge, the switching element SW3 shifts from the off state to the on state.

When the switching element SW3 is turned on, the charge stored in the negative power supply buffer capacitor 10c is discharged. Therefore, the charge stored in the negative power supply buffer capacitor 10c passes through the backflow prevention diode 11c, the limiting resistor 12c, the switching element SW3, the negative power supply capacitor 16c, the rectifying diode 14c, and the negative power supply buffer capacitor 10c. through a path returning to the second end of the . Therefore, the negative power supply capacitor 16c is charged with the charges discharged from the negative power supply buffer capacitor 10c. That is, the second end of the negative power supply capacitor 16c is charged with positive charges, and the first end of the negative power supply capacitor 16c is charged with negative charges. In other words, in the first state, the negative power supply capacitor 16c is charged by connecting the first end of the charged negative power supply buffer capacitor 10c to the second end of the negative power supply capacitor 16c. An eleventh charging circuit W11 is formed. The eleventh charging circuit W11 charges the negative power supply capacitor 16c through the conducting switching element SW3. In the first state of the present embodiment, the eleventh charging circuit W11 includes the negative power supply buffer capacitor 10c, the reverse current prevention diode 11c, the limiting resistor 12c, the switching element SW3, the negative power supply capacitor 16c, and the rectifying diode. 14c.

The charge/discharge control unit 13d controls the switching element 20d to be on and the switching element 21d to be off. As a result, the electric charge charged in the positive power supply capacitor 9d passes through the switching element 20d and the input capacitance 200d of the switching element SW4, and returns to the second end of the positive power supply capacitor 9d. Therefore, the input capacitor 200d starts charging with the charge discharged from the positive power supply capacitor 9d. After that, when the input capacitor 200d is charged with a certain amount of charge, the switching element SW4 shifts from the off state to the on state.

When the switching element SW4 is turned on, the charge stored in the negative power supply buffer capacitor 10d is discharged. Therefore, the electric charge stored in the negative power supply buffer capacitor 10d passes through the backflow prevention diode 11d, the limiting resistor 12d, the switching element SW4, the negative power supply capacitor 16d, and the rectifying diode 14d, and is transferred to the negative power supply buffer capacitor 10d. through a path returning to the second end of the . Therefore, the negative power supply capacitor 16d is charged with the charges discharged from the negative power supply buffer capacitor 10d. That is, the second end of the negative power supply capacitor 16d is charged with positive charges, and the first end of the negative power supply capacitor 16d is charged with negative charges. In other words, in the first state, the negative power supply capacitor 16d is charged by connecting the first end of the charged negative power supply buffer capacitor 10d and the second end of the negative power supply capacitor 16d. A twelfth charging circuit W12 is formed to allow the The twelfth charging circuit W12 charges the negative power supply capacitor 16d via the conducting switching element SW4. In the first state of the present embodiment, the twelfth charging circuit W12 includes the negative power buffer capacitor 10d, the reverse current prevention diode 11d, the limiting resistor 12d, the switching element SW4, the negative power capacitor 16d, and the rectifying diode. 14d.

<Second state>
FIG. 14 is an explanatory diagram showing the operation flow of the semiconductor switching element drive circuit 6 in the second state according to this embodiment.
As shown in FIG. 14, the charge/discharge control unit 13a controls the switching element 21a to be in an ON state to connect the first end of the negative power supply capacitor 16a and the gate terminal of the switching element SW1. As a result, negative charges are supplied from the first end of the negative power supply capacitor 16a to the gate terminal of the switching element SW1, and a negative gate voltage is applied to the gate terminal of the switching element SW1. Therefore, the switching element SW1 is turned off.

The charge/discharge control unit 13d controls the switching element 21d to be turned off and the switching element 21d to be turned on. Therefore, the first end of the negative power supply capacitor 16d and the gate terminal of the switching element SW4 are electrically connected. As a result, the charge charged in the negative power supply capacitor 16d passes through the input capacitance 200d of the switching element SW4, the switching element 21d, and returns to the negative power supply capacitor 16d. In this case, since the electric charge charged in the input capacitor 200d is discharged, the switching element SW4 shifts from the ON state to the OFF state. In other words, the negative charge charged in the negative power supply capacitor 16d passes through the switching element 21d, the input capacitor 200d, and the path returning to the second end of the negative power supply capacitor 16d. Therefore, by supplying negative charges from the first end of the negative power supply capacitor 16d to the gate terminal of the switching element SW4, a negative gate voltage is applied to the gate terminal of the switching element SW4. As a result, the switching element SW4 is turned off.

The charge/discharge control unit 13b controls the switching element 20b to the ON state and controls the switching element 21b to the OFF state. As a result, the charge charged in the positive power supply capacitor 9b passes through the switching element 20b, the input capacitance 200b of the switching element SW2, and returns to the second end of the positive power supply capacitor 9b. Therefore, the input capacitor 200b starts charging with the charge discharged from the positive power supply capacitor 9b. After that, when the input capacitor 200b is charged with a certain amount of charge, the switching element SW2 changes from the off state to the on state.

When the switching element SW2 is turned on, the charge stored in the negative power supply buffer capacitor 10b is discharged. Therefore, the electric charge charged in the negative power supply buffer capacitor 10b passes through the backflow prevention diode 11b, the limiting resistor 12b, the switching element SW2, the negative power supply capacitor 16b, the rectifying diode 14b, and the negative power supply buffer capacitor 10b. through a path returning to the second end of the . Therefore, the negative power supply capacitor 16b is charged with the charges discharged from the negative power supply buffer capacitor 10b. That is, the second end of the negative power supply capacitor 16b is charged with positive charges, and the first end of the negative power supply capacitor 16b is charged with negative charges. In other words, in the second state, the negative power supply capacitor 16b is charged by connecting the first end of the charged negative power supply buffer capacitor 10b to the second end of the negative power supply capacitor 16b. A thirteenth charging circuit W13 is formed. The thirteenth charging circuit W13 charges the negative power supply capacitor 16b via the conducting switching element SW2. In the second state of the present embodiment, the thirteenth charging circuit W13 includes the negative power supply buffer capacitor 10b, the reverse current prevention diode 11b, the limiting resistor 12b, the switching element SW2, the negative power supply capacitor 16b, and the rectifying diode. 14b.

As in the first state, the charge/discharge control unit 13c controls the switching element 20c to the ON state and controls the switching element 21c to the OFF state. As a result, the switching element SW3 is controlled to be in the ON state.

Next, the case of operation pattern (2) according to this embodiment will be described.
<Third state>
FIG. 15 is an explanatory diagram showing the operation flow of the semiconductor switching element drive circuit 6 in the third state according to this embodiment.

As shown in FIG. 15, the charge/discharge control unit 13a controls the switching element 20a to be on and the switching element 21a to be off. As a result, the electric charge charged in the positive power supply capacitor 9a passes through the switching element 20a and the input capacitance 200a of the switching element SW1, and returns to the second end of the positive power supply capacitor 9a. Therefore, the input capacitor 200a starts charging with the charge discharged from the positive power supply capacitor 9a. After that, when the input capacitor 200a is charged with a certain amount of charge, the switching element SW1 changes from the off state to the on state.

When the switching element SW1 is turned on, the charge stored in the negative power supply buffer capacitor 10a is discharged. Therefore, the electric charge charged in the negative power supply buffer capacitor 10a passes through the backflow prevention diode 11a, the limiting resistor 12a, the switching element SW1, the negative power supply capacitor 16a, the rectifying diode 14a, and the negative power supply buffer capacitor 10a. through a path returning to the second end of the . Therefore, the negative power supply capacitor 16a is charged with the charges discharged from the negative power supply buffer capacitor 10a. That is, the second end of the negative power supply capacitor 16a is charged with positive charges, and the first end of the negative power supply capacitor 16a is charged with negative charges. In other words, in the third state, the negative power supply capacitor 16a is charged by connecting the first end of the charged negative power supply buffer capacitor 10a and the second end of the negative power supply capacitor 16a. A 14th charging circuit W14 is formed. The fourteenth charging circuit W14 charges the negative power supply capacitor 16a via the conducting switching element SW1. In the third state of the present embodiment, the fourteenth charging circuit W14 includes the negative power supply buffer capacitor 10a, the reverse current prevention diode 11a, the limiting resistor 12a, the switching element SW1, the negative power supply capacitor 16a, and the rectifying diode. 14a.

Similarly, as shown in FIG. 15, the charge/discharge control unit 13b controls the switching element 20b to the ON state and controls the switching element 21b to the OFF state. As a result, the charge charged in the positive power supply capacitor 9b passes through the switching element 20b, the input capacitance 200b of the switching element SW2, and returns to the second end of the positive power supply capacitor 9b. Therefore, the input capacitor 200b starts charging with the charge discharged from the positive power supply capacitor 9b. After that, when the input capacitor 200b is charged with a certain amount of charge, the switching element SW2 changes from the off state to the on state.

When the switching element SW2 is turned on, the thirteenth charging circuit W13 is formed, so that the negative power supply buffer capacitor 10b is discharged. Therefore, the electric charge charged in the negative power supply buffer capacitor 10b passes through the backflow prevention diode 11b, the limiting resistor 12b, the switching element SW2, the negative power supply capacitor 16b, the rectifying diode 14b, and the negative power supply buffer capacitor 10b. through a path returning to the second end of the . Therefore, the negative power supply capacitor 16b is charged with the charges discharged from the negative power supply buffer capacitor 10b.

The charge/discharge control unit 13c controls the switching element 20c to be turned off and the switching element 21c to be turned on. Therefore, the first end of the negative power supply capacitor 16c and the gate terminal of the switching element SW3 are electrically connected. As a result, the charge charged in the negative power supply capacitor 16c passes through the input capacitance 200c of the switching element SW3, the switching element 21c, and returns to the negative power supply capacitor 16c. In this case, since the electric charge charged in the input capacitor 200c is discharged, the switching element SW3 shifts from the ON state to the OFF state. In other words, the negative charge charged in the negative power supply capacitor 16c passes through the switching element 21c, the input capacitor 200c, and the path returning to the second end of the negative power supply capacitor 16c. Therefore, by supplying negative charges from the first end of the negative power supply capacitor 16c to the gate terminal of the switching element SW3, a negative gate voltage is applied to the gate terminal of the switching element SW3. As a result, the switching element SW3 is turned off.

The charge/discharge control unit 13d controls the switching element 21d to be turned off and the switching element 21d to be turned on. Therefore, the first end of the negative power supply capacitor 16d and the gate terminal of the switching element SW4 are electrically connected. As a result, the charge charged in the negative power supply capacitor 16d passes through the input capacitance 200d of the switching element SW4, the switching element 21d, and returns to the negative power supply capacitor 16d. In this case, since the electric charge charged in the input capacitor 200d is discharged, the switching element SW4 shifts from the ON state to the OFF state. In other words, the negative charge charged in the negative power supply capacitor 16d passes through the switching element 21d, the input capacitor 200d, and the path returning to the second end of the negative power supply capacitor 16d. Therefore, by supplying negative charges from the first end of the negative power supply capacitor 16d to the gate terminal of the switching element SW4, a negative gate voltage is applied to the gate terminal of the switching element SW4. As a result, the switching element SW4 is turned off.

<Fourth state>
FIG. 16 is an explanatory diagram showing the operation flow of the semiconductor switching element drive circuit 6 in the fourth state according to this embodiment.

As shown in FIG. 16, the charge/discharge control unit 13a controls the switching element 20a to be turned off and the switching element 21a to be turned on. Therefore, the first end of the negative power supply capacitor 16a and the gate terminal of the switching element SW1 are electrically connected. As a result, the electric charge charged in the negative power supply capacitor 16a passes through the input capacitance 200a of the switching element SW1, the switching element 21a, and returns to the negative power supply capacitor 16a. In this case, since the electric charge charged in the input capacitor 200a is discharged, the switching element SW1 shifts from the ON state to the OFF state. In other words, the negative charge charged in the negative power supply capacitor 16a passes through the switching element 21a, the input capacitor 200a, and the path returning to the second end of the negative power supply capacitor 16a. Therefore, by supplying negative charges from the first end of the negative power supply capacitor 16a to the gate terminal of the switching element SW1, a negative gate voltage is applied to the gate terminal of the switching element SW1. As a result, the switching element SW1 is turned off.

As in the third state, the charge/discharge control unit 13b controls the switching element 20b to the ON state and controls the switching element 21b to the OFF state. As a result, the switching element SW2 is controlled to be in the ON state.

The charge/discharge control unit 13c controls the switching element 20c to be on and the switching element 21c to be off. As a result, the electric charge charged in the positive power supply capacitor 9c passes through the switching element 20c and the input capacitance 200c of the switching element SW3, and returns to the second end of the positive power supply capacitor 9c. Therefore, the input capacitor 200c starts charging with the charge discharged from the positive power supply capacitor 9c. After that, when the input capacitor 200c is charged with a certain amount of charge, the switching element SW3 shifts from the off state to the on state.

When the switching element SW3 transitions to the ON state, the eleventh charging circuit W11 is formed, so that the charge charged in the negative power supply buffer capacitor 10c is discharged. Therefore, the charge stored in the negative power supply buffer capacitor 10c passes through the backflow prevention diode 11c, the limiting resistor 12c, the switching element SW3, the negative power supply capacitor 16c, the rectifying diode 14c, and the negative power supply buffer capacitor 10c. through a path returning to the second end of the . Therefore, the negative power supply capacitor 16c is charged with the charges discharged from the negative power supply buffer capacitor 10c.

As in the fourth state, the charge/discharge control unit 13d controls the switching element 20d to be turned off and the switching element 21d to be turned on. As a result, the switching element SW4 is controlled to be turned off.

Since the operation of the semiconductor switching element drive circuit 6 in the operation pattern (3) is the same as that in the operation pattern (2), the explanation is omitted. Since the operation of the semiconductor switching element drive circuit 6 in the operation pattern (4) is the same as that in the operation pattern (1), the explanation is omitted.

Further, in the operation pattern (1) and the operation pattern (2), for convenience of explanation, the charging of the positive power supply capacitor 9 and the negative power supply buffer capacitor 10 in each drive circuit 8 is omitted. When at least one of the first charging circuit W1 to the tenth charging circuit W10 is formed, the positive power supply capacitor 9 and the negative power supply buffer capacitor 10 are charged.

As described above, the semiconductor switching element drive circuit 6 drives a plurality of semiconductor switching elements SW1-SW4 of the multilevel power converter. The semiconductor switching element driving circuit 6 includes a plurality of driving circuits 8 (first driving circuit 8a to fourth driving circuit 8d) provided for each of the semiconductor switching elements SW1 to SW4. Each drive circuit 8 includes a positive power supply capacitor 9 , a negative power supply buffer capacitor 10 , a negative power supply capacitor 16 , a switching element 20 and a switching element 21 .
A positive power supply capacitor 9 generates a positive voltage for turning on the semiconductor switching element SW. The negative power supply buffer capacitor 10 has a first end connected to the first end of the positive power supply capacitor 9 . The negative power supply capacitor 16 generates a negative voltage for turning off the semiconductor switching element SW by charging the power discharged from the charged negative power supply buffer capacitor 10 . The switching element 20 applies a positive voltage to the control terminal of the semiconductor switching element SW by connecting the first end of the positive power supply capacitor 9 and the control terminal of the semiconductor switching element SW to turn on the semiconductor switching element SW. state. The switching element 21 connects the first end of the negative power supply capacitor 16 and the control terminal of the semiconductor switching element SW to apply a negative voltage to the control terminal of the semiconductor switching element SW to cut off the semiconductor switching element SW. state.

Thereby, the semiconductor switching element driving circuit 6 can generate a negative voltage without adding a new power supply when driving the semiconductor switching element SW of the multilevel power converter.

Although the embodiment of the present invention has been described in detail with reference to the drawings, the specific configuration is not limited to this embodiment, and design and the like are included within the scope of the gist of the present invention.

A Multi-level power converter SW1 to SW4 Switching element (semiconductor switching element)
9a to 9d Positive power supply capacitor (first capacitor)
10a to 10d Negative power supply buffer capacitor (second capacitor)
16a to 16d Negative power supply capacitor (third capacitor)
20a to 20d switching elements (driving circuits for conduction)
21a to 21d switching element (breaking drive circuit)
7 Second DC power supply (control power supply)

Claims (3)

A semiconductor switching element drive circuit for driving n (n is an integer of 4 or more) semiconductor switching elements provided in a multilevel power converter,
A plurality of drive circuits provided for each of the semiconductor switching elements,
Each drive circuit is
a first capacitor for generating a positive voltage for turning on the semiconductor switching element;
a second capacitor having a first end connected to the first end of the first capacitor;
a third capacitor that generates a negative voltage for turning off the semiconductor switching element by charging electric power discharged from the charged second capacitor;
By connecting the first end of the first capacitor and the control terminal of the semiconductor switching element, the positive voltage is applied to the control terminal of the semiconductor switching element to turn on the semiconductor switching element. a universal drive circuit;
a cut-off drive circuit for connecting the first end of the third capacitor and the control terminal to apply the negative voltage to the control terminal of the semiconductor switching element to set the semiconductor switching element in a cut-off state; , and
the third capacitor has a first end connected to a second end of the second capacitor via a rectifying diode ;
a charging circuit for charging the third capacitor by connecting a first end of the second capacitor in a charged state and a second end of the third capacitor;
A semiconductor switching element driving circuit, wherein the charging circuit charges the third capacitor via the conductive semiconductor switching element. It also has a positive control power supply,
The plurality of drive circuits comprises first to n-th drive circuits,
a first end of the first capacitor provided in the m-th (m is an integer equal to or more than n and less than n) drive circuit, and the first capacitor provided in the (m+1)-th drive circuit connected through a diode to the first end of the capacitor;
2. The semiconductor switching element according to claim 1, wherein a first end of said first capacitor provided in said first drive circuit is connected to a positive terminal of said power supply for control. drive circuit. A semiconductor switching element drive circuit according to claim 1 or 2;
n semiconductor switching elements driven by the semiconductor switching element drive circuit;
A multi-level power converter, comprising:

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