JP7328747B2 - Ceramic electronic component and its manufacturing method - Google Patents

Description

TECHNICAL FIELD The present invention relates to a ceramic electronic component and a manufacturing method thereof.

There are various types of ceramic electronic components mounted on wiring boards. Among them, a laminated ceramic capacitor has a structure in which ceramic dielectric layers and internal electrode layers are alternately laminated, and can realize a compact capacitor with a large capacity. A multilayer ceramic capacitor is formed by, for example, printing a conductive pattern on a ceramic green sheet by screen printing, printing a dielectric paste on the green sheet around the conductive pattern by screen printing, and firing it. be done.

By the way, it is known that the conductive pattern described above has a bulge at the peripheral portion during printing, and the thickness of the peripheral portion increases (Patent Document 1). Such a phenomenon is also called a saddle phenomenon. In addition, it is also known that misalignment during printing of the dielectric paste as described above causes the dielectric paste to run over the conductive pattern, degrading the flatness of the dielectric layer after firing ( Patent document 2).

JP 2006-335045 A JP-A-2000-311831

Variation in the thickness of each layer may reduce the reliability of the multilayer ceramic capacitor.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a ceramic electronic component capable of improving reliability and a method of manufacturing the same.

A ceramic electronic component according to the present invention comprises a laminated chip in which a plurality of internal electrode layers are laminated via a dielectric layer containing ceramic as a main component, and at least half or more of the plurality of internal electrode layers. and slits, and the positions of the slits in different layers are uniform within a range of 5 μm when viewed from above.

In the above ceramic electronic component, each of the plurality of internal electrode layers has a rectangular shape when viewed from above, long sides of each of the plurality of internal electrode layers are aligned when viewed from above, and The slit may be formed by

In the above ceramic electronic component, the slits may be formed so as not to divide the internal electrode layers.

In the above ceramic electronic component, the internal electrode layer may be divided into a plurality of electrode pieces by the slits, and may further have an external electrode connected to each of the electrode pieces.

In the above ceramic electronic component, a second imaginary line extending in the transverse direction is positioned below a first imaginary line extending in the transverse direction of the laminated chip from the center of the upper surface of the laminated chip. , the distance between two points at which the second imaginary line intersects the upper surface of the laminated chip is the width of the internal electrode layer in the lateral direction. It may be greater than or equal to the width.

A method for manufacturing a ceramic electronic component according to the present invention includes a step of forming a conductive pattern on the surface of a green sheet containing ceramic as a main component by a printing method, and alternately laminating a plurality of the green sheets and the conductive pattern. forming a laminate; pressing the laminate to press each of the green sheets and the conductive patterns; and firing the laminate to form the green sheets into dielectric layers. and forming a slit in the conductive pattern in the step of forming at least half or more of the plurality of conductive patterns included in the laminate in the step of forming the conductive pattern as an internal electrode layer. characterized by

The method for manufacturing a ceramic electronic component may further include the step of forming a pattern containing the ceramic on the green sheet around the conductive pattern.

In the method for manufacturing a ceramic electronic component, in the step of forming the conductive pattern, the conductive pattern is formed into a rectangle when viewed from above, and the slits are formed along the long sides of the rectangle to form the laminate. In the step of forming, long sides of the plurality of conductive patterns may be aligned when viewed from above.

In the method for manufacturing a ceramic electronic component, in the step of forming the conductive pattern, the slits may be formed so as not to divide the conductive pattern.

According to the present invention, the reliability of ceramic electronic components can be improved.

(a) to (c) are cross-sectional views (part 1) of a multilayer ceramic capacitor used in the investigation during manufacture. (a) and (b) are cross-sectional views (part 2) of a multilayer ceramic capacitor used in the investigation during manufacture. (a) and (b) are exploded perspective views of a laminated ceramic capacitor used in the investigation during manufacture. FIG. 4 is a top view of a conductive pattern of a laminated ceramic capacitor used for investigation; FIG. 4 is a cross-sectional view of a sheet in the case where the reverse pattern and the conductive pattern are misaligned in the multilayer ceramic capacitor used for the investigation; 1(a) to 1(c) are cross-sectional views (part 1) of a laminated ceramic capacitor according to the present embodiment during manufacture. (a) and (b) are cross-sectional views (part 2) of the laminated ceramic capacitor according to the present embodiment during manufacture. FIG. 2 is an exploded perspective view of the laminated ceramic capacitor according to the present embodiment, which is in the middle of manufacturing; FIG. 4 is a top view of a carrier film when manufacturing the multilayer ceramic capacitor according to the present embodiment; (a) is a top view of a screen printing plate used when printing internal electrode layers in this embodiment, and (b) is a cross-sectional view taken along line IV-IV of (a). FIG. 8B is a cross-sectional view taken along the line VI-VI of FIG. 8B; 3 is a perspective view showing the arrangement of internal electrode layers in the multilayer ceramic capacitor according to the embodiment; FIG. (a) is an enlarged cross-sectional view when a reverse pattern runs over the conductive pattern due to positional deviation in this embodiment, and (b) is an enlarged cross-sectional view when pressure is applied in this state. FIG. 4 is a schematic cross-sectional view of a laminated chip used in the investigation; FIG. 10 is a top view of a seat according to a first modified example of the present embodiment; FIG. 10 is a top view of a screen plate used in a first modified example of the present embodiment; (a) is a top view of a first screen plate used in the first modified example of the present embodiment, and (b) is a top view of a second screen plate used in the first modified example of the present embodiment. It is a diagram. FIG. 10 is a top view of an internal electrode layer obtained by cutting the conductive pattern according to the first modified example of the present embodiment along the cutting line and then firing the cut conductive pattern. FIG. 4 is a perspective view showing the arrangement of internal electrode layers in a multilayer ceramic capacitor according to a first modified example of the present embodiment; FIG. 4 is a cross-sectional view of a laminated ceramic capacitor according to a first modified example of the present embodiment; (a) is a top view of a sheet according to a second modification of the present embodiment, and (b) is a sheet obtained by cutting a conductive pattern according to the second modification of the present embodiment along a cutting line and baking the sheet. 2 is a top view of an internal electrode layer obtained by . FIG. 9 is a perspective view showing the arrangement of internal electrode layers in a multilayer ceramic capacitor according to a second modification of the embodiment; FIG. 5 is a cross-sectional view of a laminated ceramic capacitor according to a second modified example of the present embodiment; FIG. 11 is a perspective view showing the arrangement of internal electrode layers in a multilayer ceramic capacitor according to a third modification of the embodiment;

Prior to the description of this embodiment, the matters investigated by the inventors of the present application will be described.

FIGS. 1(a) to 1(c) and FIGS. 2(a) and (b) are cross-sectional views of the multilayer ceramic capacitor used in the investigation during manufacturing, and FIGS. 3(a) and 3(b) are exploded It is a perspective view.

First, as shown in FIG. 1(a), dielectric slurry is applied on a resin carrier film 1 by a die coater and dried to form a green sheet 2a. Then, a conductive paste is printed as the conductive pattern 3 on the green sheet 2a by screen printing. The material of the conductive paste is not particularly limited, but in this example, a conductive paste obtained by kneading nickel powder, dielectric powder, binder and solvent is used. At this time, a convex portion 3a is formed on the peripheral edge of the conductive pattern 3 due to the saddle phenomenon.

FIG. 4 is a top view of the conductive pattern 3. FIG. Note that FIG. 1(a) described above corresponds to a cross-sectional view taken along line II in FIG. As shown in FIG. 4, the conductive pattern 3 is rectangular in top view.

Subsequently, as shown in FIG. 1B, a reverse pattern 2b is formed on the green sheet 2a around the conductive pattern 3 by screen printing, and the step between the green sheet 2a and the conductive pattern 3 is formed by the reverse pattern 2b. fill in. For example, the main component of the reverse pattern 2b is the same material as the main component of the green sheet 2a. Thereafter, as shown in FIG. 1(c), the green sheet 2a is peeled off from the carrier film 1 to obtain a patterned sheet 4. Next, as shown in FIG.

Next, as shown in FIG. 2(a), a plurality of pattern forming sheets 4 are laminated, and cover sheets 6 are placed on the bottom layer and the top layer, so that the green sheets 2a and the conductive patterns 3 are alternately arranged. A laminated body 5 is formed by laminating a plurality of layers. For example, the main component of the cover sheet 6 is the same material as the main component of the green sheet 2a.

In this state, each of the plurality of pattern forming sheets 4 is pressure-bonded by applying pressure to the laminate 5 from above and below. At this time, since excessive pressure is applied to the convex portion 3a formed by the saddle phenomenon, the film thickness of the green sheets 2a above and below the convex portion 3a is reduced, and the green sheet 2a around the convex portion 3a is excessively compressed. stress will be added.

Subsequently, as shown in FIG. 2B, the laminate 5 is cut into a plurality of laminated chips 8. Next, as shown in FIG. By heating the laminated chip 8 , each green sheet 2 a is fired to form the dielectric layer 11 and the conductive pattern 3 is fired to form the internal electrode layer 7 .

FIG. 3(a) is an exploded perspective view of the laminated chip 8 after firing. The sectional views of FIGS. 1 and 2 correspond to the sectional views taken along the line II-II of FIG. 3(a). As shown in FIG. 3(a), the laminated chip 8 is substantially rectangular parallelepiped and has end faces 8a and 8b facing each other. Next, as shown in FIG. 3(b), a pair of external electrodes 9a and 9b are formed by applying a conductive paste to each of the end surfaces 8a and 8b and baking it.

With the above, the basic structure of the multilayer ceramic capacitor 10 according to this example is completed.

According to the manufacturing method of the laminated ceramic capacitor 10 described above, as shown in FIG. excessive pressure will be applied to As a result, the film thickness of the green sheet 2a around the convex portion 3a is reduced, and the reliability of the multilayer ceramic capacitor 10 is reduced.

Further, when the reverse pattern 2b is formed around the conductive pattern 3 in the step of FIG. 1(c), the reverse pattern 2b and the conductive pattern 3 may be misaligned. FIG. 5 is a sectional view of the sheet 4 when the reverse pattern 2b and the conductive pattern 3 are misaligned. In the example of FIG. 5, the reverse pattern 2b runs over the convex portion 3a due to positional deviation. In this case, when the laminated body 5 is pressed in the step of FIG. 2A, excessive pressure is applied to the reverse pattern 2b on the convex portion 3a, further reducing the reliability of the laminated ceramic capacitor 10. .

The present embodiment capable of improving the reliability of the multilayer ceramic capacitor will be described below.

(this embodiment)
In this embodiment, a laminated ceramic capacitor is manufactured as a ceramic electronic component as follows.

6(a) to (c), and FIGS. 7(a) and (b) are cross-sectional views of the multilayer ceramic capacitor according to the present embodiment during manufacturing, and FIGS. It is an exploded perspective view.

First, as shown in FIG. 6A, dielectric slurry is applied on a resin carrier film 21 by a die coater and dried to form a green sheet 22a having a thickness of about 4 μm. The dielectric slurry is a slurry containing a ceramic dielectric as a main component, and is obtained by, for example, kneading PVB (polyvinyl butyral) as a binder with dielectric powder and a solvent. Ethyl cellulose may be used as the binder instead of PVB.

A ceramic material having a perovskite structure represented by the general formula _ABO3 can be used as the dielectric powder material. Examples of such ceramic materials include BaTiO ₃ (barium titanate), CaZrO ₃ (calcium zirconate), CaTiO ₃ (calcium titanate), and SrTiO ₃ (strontium titanate). A ceramic material having a perovskite structure represented by ABO _3-α deviating from the stoichiometric composition may be used as the dielectric powder material. Furthermore, Ba _1-x-y Ca _x Sr _y Ti _1-z Zr ₂ O ₃ (0≦x≦1, 0≦y≦1, 0≦z≦1) having a perovskite structure is used as a dielectric powder material. may be adopted.

Then, a conductive paste is printed as the conductive pattern 23 on the green sheet 22a by screen printing so that the thickness after firing is about 0.6 μm to 1.5 μm. As the conductive paste, for example, a paste obtained by kneading nickel powder, dielectric powder, binder, and solvent is used. Among them, the binder includes, for example, PVB and ethyl cellulose. Metal powder such as copper or tin may be used instead of nickel powder. Further, metal powders of noble metals such as platinum, palladium, silver and gold, and alloys thereof may be used in place of the nickel powder.

Furthermore, in this embodiment, the slit G penetrating the conductive pattern 23 is formed in the portion near the edge 23a of the conductive pattern 23 by appropriately selecting the shape of the screen printing plate used in the screen printing. Although the width of the slit G is not particularly limited, it is, for example, about 0.5 μm to 30 μm. Although the conductive pattern 23 is formed by screen printing in this example, the conductive pattern 23 may be formed by gravure printing. After that, the solvent is removed from the conductive pattern 23 by drying the conductive pattern 23 . When the conductive pattern 23 is formed by the printing method in this way, the convex portion 23c is formed on the conductive pattern 23 beside the slit G due to the saddle phenomenon described above.

FIG. 9 is a top view of the carrier film 21 after this step, and FIG. 6(a) corresponds to a cross-sectional view taken along line III--III in FIG. As shown in FIG. 9, the conductive pattern 23 has a rectangular shape in which the length in the longitudinal direction X is longer than the length in the lateral direction Y, and slits G are formed along the long sides 23d. Each conductive pattern 23 is cut along a cutting line D parallel to the lateral direction Y when cutting later. A cutting line D is set to bisect the conductive pattern 23 . The planar size of the conductive pattern 23 before cutting is not particularly limited. For example, the long side 23d has a length of 0.45 mm to 11 mm, and the short side 23k has a length of 0.06 mm to 3.7 mm.

10(a) is a top view of a screen printing plate used when printing the conductive pattern 23, and FIG. 10(b) is a cross-sectional view taken along line IV-IV of FIG. 10(a). . As shown in FIGS. 10(a) and 10(b), this screen printing plate 50 has a mesh portion 51 and an emulsion portion 52. FIG. Among them, the mesh portion 51 is a portion through which the conductive paste passes, and is formed by weaving fibrous thin metal wires. The emulsion portion 52 is a portion to be masked with the conductive paste, and has a planar shape corresponding to the slit G described above.

Subsequently, as shown in FIG. 6B, a reverse pattern 22b is formed on the green sheet 22a around the conductive pattern 23 by screen printing so as to have a thickness similar to that of the conductive pattern 23, for example, a thickness of 0 after firing. .6 μm to 1.5 μm. In the screen printing, the dielectric paste of the same material as the dielectric slurry used when forming the green sheet 22a is printed as the reverse pattern 22b. The reverse pattern 22b may be formed by gravure printing instead of screen printing.

Thereafter, as shown in FIG. 6(c), the green sheet 22a is peeled off from the carrier film 21 to obtain a patterned sheet 24. Next, as shown in FIG. In the pattern-formed sheet 24, since the reverse pattern 22b is formed around the conductive pattern 23, the step between the green sheet 22a and the conductive pattern 23 is filled with the reverse pattern 22b, and the pattern-formed sheet 24 has good flatness. Become.

Next, as shown in FIG. 7(a), 200 to 500 layers of pattern forming sheets 24 are laminated with the long sides 23d of the plurality of conductive patterns 23 aligned in plan view. At the same time, by disposing cover sheets 26 on the bottom layer and the top layer, a laminate 25 is formed by alternately stacking a plurality of green sheets 22a and conductive patterns 23 . For example, the main component of the cover sheet 26 is the same material as the main component of the green sheet 22a.

Then, while heating the laminate 25 to a temperature of about 50° C. to 300° C., pressure of about 10 MPa to 500 MPa is applied from above and below to press the green sheets 22a and the conductive patterns 23 together.

At this time, since the slits G are formed in the conductive pattern 23 in the present embodiment, the protrusions 23c are deformed by the pressure during pressurization as indicated by the arrow A and escape to the slits G, and the green around the protrusions 23c is deformed. Excessive pressure applied to the seat 22a is suppressed.

In particular, when the long sides 23d of the plurality of conductive patterns 23 are aligned as in this example, the convex portions 23c of the conductive patterns 23 are positioned so as to be vertically connected, so that high pressure is applied between the convex portions 23c. . Therefore, by forming the slits G along the long side 23d as shown in FIG. 9, each convex portion 23c can more easily escape to the slit G during pressurization, and the stress applied to the green sheet 22a around the convex portions 23c can be reduced. easier to relax.

Subsequently, as shown in FIG. 7B, the laminate 25 is cut to cut out a plurality of laminated chips 28 . After that, the laminated chip 28 is heated to a temperature of about 200° C. to 1000° C. to remove the binder contained in the laminated chip 28 . Then, the laminated chip 28 is heated at a temperature of about 1100° C. to 1400° C. for about 10 minutes to 2 hours in a reducing atmosphere with an oxygen partial pressure of 10 ⁻⁵ to 10 ⁻⁸ atm. As a result, each green sheet 22 a is fired to become the dielectric layer 31 , and the conductive pattern 23 is fired to become the internal electrode layer 27 .

FIG. 8(a) is an exploded perspective view of the laminated chip 28. FIG. The sectional views of FIGS. 6 and 7 described above correspond to the sectional views taken along the line VV in FIG. 8(a). As shown in FIG. 8(a), the laminated chip 28 is substantially rectangular parallelepiped and has end faces 28a and 28b facing each other.

Next, as shown in FIG. 8(b), a pair of external electrodes 29a and 29b are formed by applying a conductive paste to each of the end surfaces 28a and 28b and baking it. After that, a plating layer is formed by laminating a nickel layer and a tin layer in this order on the surfaces of the external electrodes 29a and 29b to complete the basic structure of the laminated ceramic capacitor 30 according to the present embodiment.

In this example, the external electrodes 29a and 29b are formed after firing the laminated chip 28, but the order of steps is not limited to this. For example, a conductive paste may be applied to positions corresponding to the external electrodes 29a and 29b of the laminated chip 28 before firing, and fired at the same time.

The size of the laminated ceramic capacitor 30 is, for example, length 0.25 mm, width 0.125 mm, and height 0.125 mm, or length 0.4 mm, width 0.2 mm, height 0.2 mm, or length 0.6 mm, 0.3 mm wide and 0.3 mm high; or 1.0 mm long, 0.5 mm wide and 0.5 mm high; or 3.2 mm long, 1.6 mm wide and 0.5 mm high. 1.6 mm in height, or 4.5 mm in length, 3.2 mm in width and 2.5 mm in height, but are not limited to these sizes.

FIG. 11 is a cross-sectional view taken along line VI-VI in FIG. 8(b). As shown in FIG. 11, in this multilayer ceramic capacitor 30, each internal electrode layer 27 is connected to one of the external electrodes 29a and 29b every other layer, and the internal electrode layers 27 adjacent above and below form a plurality of capacitors. is formed.

12 is a perspective view showing the arrangement of the internal electrode layers 27 in the laminated ceramic capacitor 30. As shown in FIG. Note that elements other than the internal electrode layers 27 are omitted in FIG. 11 in order to make it easier to see the positional relationship between the internal electrode layers 27 .

As shown in FIG. 12, the internal electrode layers 27 are stacked alternately along the longitudinal direction X of each. Further, when the length of the internal electrode layers 27 along the longitudinal direction X is L, the vertically adjacent internal electrode layers 27 are stacked alternately so as to be shifted from each other by a length of L/5 to L/10. be. Further, slits G are formed to penetrate each internal electrode layer 27 . Moreover, the slit G is formed so as not to divide each internal electrode 27 . Note that the slit G does not divide the internal electrode layer 27 means that the internal electrode layer 27 is not divided into a plurality of pieces by the slit G, and the portion connecting any two points in the internal electrode layer 27 is the internal electrode layer. 27 is said to exist.
Moreover, the length a of the slit G after firing is a value of about 80% to 96% of the length L of the internal electrode layer 27, for example, 0.2 mm to 3.6 mm. On the other hand, the width b of the slit G after firing is about 0.2% to 8.0% of the width W of the internal electrode layer 27, for example, 0.5 μm to 30 μm.
In the multilayer ceramic capacitor 30 manufactured according to this embodiment, the positions of the slits G in different layers are aligned within 5 μm in each of the longitudinal direction X and the lateral direction Y when viewed from above.

According to the present embodiment described above, slits G are formed in the conductive pattern 23 as shown in FIG. Therefore, when the laminated body 25 is pressed in the process of FIG. 7A, the convex portion 23c is deformed and escapes to the slit G, and excessive pressure is applied to the green sheet 22a around the convex portion 23c. Suppressed. As a result, problems such as thinning of the green sheet 22a around the convex portion 23c can be avoided, and the reliability of the multilayer ceramic capacitor 30 can be improved.
In addition, in the configuration using the bottomed grooves instead of the slits G, the space for the projections 23c to escape when the laminate 25 is pressurized is reduced, resulting in the inconvenience that the projections 23c cannot be sufficiently absorbed. By using the slit G passing through the conductive pattern 23 as in the embodiment, the protrusion 23c can be sufficiently absorbed.

Moreover, in this embodiment, as shown in FIG. 12, the internal electrode layers 27 are not separated by the slits G and are maintained as one sheet. Therefore, formation of unnecessary capacitors in the internal electrode layers 27 can be prevented, and a multilayer ceramic capacitor having a capacitance close to the designed value can be obtained.

In addition, in this embodiment, the reverse pattern 22b is formed by screen printing in the process of FIG.6(c). Therefore, the reverse pattern 22b may run over the conductive pattern 23 due to misalignment during printing. FIG. 13(a) is an enlarged sectional view in that case. In the example of FIG. 13( a ), the edge of the reverse pattern 22 b runs over the conductive pattern 23 .

FIG. 13(b) is an enlarged sectional view of the pattern sheet 24 when pressure is applied in the process of FIG. 7(a) in this state. As shown in FIG. 13(b), the convex portion 23c is deformed as indicated by the arrow A due to the pressure and escapes to the slit G. to escape to the slit G. Therefore, it is possible to prevent excessive pressure from being applied to the reverse pattern 22b during pressurization, and the reliability of the multilayer ceramic capacitor 10 can be improved.

Further, in the present embodiment, as shown in FIG. 6C, by forming the reverse pattern 22b around the conductive pattern 23, the flatness of the pattern-formed sheet 4 is improved. As a result, the projection 23c escapes into the slit G, and the flatness of the upper surface of the laminated chip 28 formed by laminating the pattern forming sheets 4 is improved.

The inventor of the present application investigated how much the flatness of the laminated chip 28 is improved in this embodiment.

FIG. 14 is a schematic cross-sectional view of the laminated chip 28 used in the investigation. In this investigation, a first imaginary line _L1 extending in the transverse direction Y of the laminated chip 28 from the center C of the upper surface 28c was drawn in order to ensure the flatness of the upper surface 28c of the laminated chip 28. FIG. Then, a second imaginary line _L2 extending in the lateral direction Y with an interval Δ of 1% of the thickness T of the laminated chip 28 is drawn below the first imaginary line _L1 . Also, the distance between two points P and Q where the second imaginary line _L2 intersects the upper surface 28c of the laminated chip 28 is d.

In this case, in this embodiment, the distance d is equal to or greater than the width W of the internal electrode layers 27 in the lateral direction Y (d≧W). On the other hand, the distance d was narrower than the width W in the laminated chip 28 in which the reverse pattern 22b and the slit G were not formed. From this, it was confirmed that the formation of the reverse pattern 22b and the slit G is effective in improving the flatness of the upper surface 28c of the laminated chip 28. FIG.

When the flatness of the upper surface 28c is improved in this way, the upper surface 28c is in close contact with the surface of the wiring board when the multilayer ceramic capacitor 30 is mounted on the wiring board with the upper surface 28c facing down. can be stably implemented.

Next, a modified example of this embodiment will be described.

(First modification)
FIG. 15 is a top view of the pattern forming sheet 24 according to the first modified example. As shown in FIG. 15, in this modification, when forming the pattern forming sheet 24, the slits G are formed in a frame shape along the four sides of the rectangular conductive pattern 23. As shown in FIG. Also, the conductive pattern 23 is cut along the cutting line D at the time of cutting.

The conductive pattern 23 is formed by screen printing as described above. FIG. 16 is a top view of a screen plate used in the screen printing. As shown in FIG. 16, the emulsion portion 52 of the screen plate 55 has a frame-like planar shape corresponding to the slit G. As shown in FIG. A mesh portion 51 is provided in the inner and outer regions of the frame-shaped emulsion portion 52, and the conductive paste passes through the mesh portion 51 to form a planar conductive pattern 23 as shown in FIG. It is formed.

Instead of using one screen plate 55 as described above, two screen plates may be used to form the conductive pattern 23 as follows. 17(a) is a top view of the first screen plate 61, and FIG. 17(b) is a top view of the second screen plate 62. FIG.

Of these, the first screen plate 61 has a rectangular mesh portion 51 corresponding to an area inside the slit G (see FIG. 15) in top view, and an area outside the mesh portion 51 An emulsion section 52 is provided. In addition, the second screen plate 62 has a frame-shaped mesh portion 51 corresponding to an area outside the slit G (see FIG. 15) in a top view. A portion 52 is provided.

When using these screen plates 61 and 62, for example, the first screen plate 61 is first used to print the conductive paste on the region inside the slit G. As shown in FIG. After that, by printing the conductive paste on the area outside the slit G using the second screen plate 62, the conductive pattern 23 having a planar shape as shown in FIG. 15 can be formed.
By forming the conductive pattern 23 in two steps in this way, it is possible to optimize the amount of paste, viscosity, etc. in each printing, and the width of the slit G is smaller than in the case of forming the conductive pattern 23 in one step. can be narrowed.

FIG. 18 is a top view of the internal electrode layer 27 obtained by cutting the conductive pattern 23 along the cutting line D and baking it. The internal electrode layer 27 is divided by slits G into a plurality of electrode pieces 27e and 27f. These electrode pieces 27e and 27f have edges 27g and 27h corresponding to the cutting line D described above. In this modification, these edge portions 27g and 27h are connected to the external electrode 29a (see FIG. 8(b)) and the external electrode 29b. Moreover, the slit G is formed along each of the long side 27d and the short side 27k of the internal electrode layer 27 .

FIG. 19 is a perspective view showing the arrangement of internal electrode layers 27 in a laminated ceramic capacitor 30 according to this modification. In FIG. 19, elements other than the internal electrode layers 27 are omitted in order to make the positional relationship between the internal electrode layers 27 easier to see. This also applies to FIGS. 22 and 24, which will be described later. Similarly to the example of FIG. 12, also in this modified example, the respective internal electrode layers 27 are alternately laminated so as to be shifted from each other by the length of L/5.
Note that the length a of the slit G after firing in this modified example is about 90% to 96% of the length L of the internal electrode layer 27, for example, 0.2 mm to 3.6 mm. On the other hand, the width b of the slit G after firing is about 0.2% to 8.0% of the width W of the internal electrode layer 27, for example, 0.5 μm to 30 μm.

FIG. 20 is a cross-sectional view of the laminated ceramic capacitor 30 according to this modification, and corresponds to the cross-sectional view taken along line VII-VII in FIG. As described above, in this modified example, the internal electrode layer 27 is divided into the electrode pieces 27e and 27f by the slits G, and each of them is connected to the external electrode 29a and the external electrode 29b. Therefore, the potential of each of the electrode strips 27e and 27f can be maintained at the same level, and formation of unnecessary capacitors by the electrode strips 27e and 27f can be prevented.

Also in this modified example described above, by forming the slits G in the conductive pattern 23, the protrusions generated in the conductive pattern 23 due to the saddle phenomenon can escape to the slits G, and the reliability of the multilayer ceramic capacitor 30 can be improved. can.

Moreover, in this modification, the slits G are formed along not only the long sides 27d of the internal electrode layers 27 but also the short sides 27k. As a result, the projections generated in the vicinity of the short side 27k due to the saddle effect can also escape to the slit G. As shown in FIG.

(Second modification)
FIG. 21(a) is a top view of a pattern forming sheet 24 according to a second modified example. As shown in FIG. 21( a ), in this modification, slits G are formed along the short sides 23 k of the rectangular conductive pattern 23 when forming the pattern forming sheet 24 . The slit G is not formed in the portion along the long side 23d of the conductive pattern 23. As shown in FIG.
When the conductive pattern 23 is formed by gravure printing, the saddle phenomenon may occur strongly on the side of the short side 23k, but the saddle phenomenon can be effectively prevented by forming the slit G along the short side 23k. Moreover, since the slits G are not formed along the long side 23d, it is possible to prevent the slits G from reducing the opposing areas of the internal electrode layers 27. FIG.

FIG. 21(b) is a top view of the internal electrode layer 27 obtained by cutting the conductive pattern 23 along the cutting line D and baking it. As shown in FIG. 21(b), the internal electrode layers 27 are not divided by the slits G, and the internal electrode layers 27 are in a continuous state.

FIG. 22 is a perspective view showing the arrangement of internal electrode layers 27 in a laminated ceramic capacitor 30 according to this modification. 12 and 19, also in this modified example, the internal electrode layers 27 are alternately laminated so as to be shifted from each other by the length of L/5. Further, in this modified example, the internal electrode layers 27 are laminated while alternately exchanging the positions of the slits G. As shown in FIG.
In addition, the length a of the slit G after firing in this modified example is a value of about 80% to 96% of the width W of the internal electrode layer 27, for example, 0.04 mm to 2.8 mm. On the other hand, the width b of the slit G after firing is about 0.1% to 3.1% of the length L of the internal electrode layer 27, for example, 0.5 μm to 30 μm.

FIG. 23 is a cross-sectional view of the laminated ceramic capacitor 30 according to this modification, and corresponds to the cross-sectional view taken along line VIII-VIII in FIG. As shown in FIG. 23, by laminating the internal electrode layers 27 while alternately exchanging the positions of the slits G, the slits G appear every other layer in the partial region R of the cross section of the multilayer ceramic capacitor 30. .
As a result, it is possible to suppress the saddle effect while suppressing the decrease in the facing area between the internal electrode layers 27 due to the slit G.

Also in this modified example described above, the reliability of the laminated ceramic capacitor 30 can be improved by forming the slits G in the internal electrode layers 27 in the same manner as in the first modified example.

(Third modification)
FIG. 24 is a perspective view showing the arrangement of internal electrode layers 27 in a laminated ceramic capacitor 30 according to this modification. As shown in FIG. 24, in this modification, the internal electrode layers 27 in which the slits G are not formed and the internal electrode layers 27 in which the slits G are formed are alternately laminated. Thus, even if the slits G are formed in only half of the plurality of internal electrode layers 27 and the slits G are not formed in the remaining internal electrode layers 27, it is possible to expect an improvement in reliability due to the slits G to some extent. can.

A laminated ceramic capacitor according to this embodiment was produced and its characteristics were investigated.
(Example 1)

2000 multilayer ceramic capacitors 30 having internal electrode layers 27 having the shape shown in FIG. A load test was performed.

The thickness of the conductive pattern 23 was set to 1.0 μm, and the width of the slit G was set to 20 μm. The number of layers of the conductive pattern 23 was 474, the thickness of the green sheet 22a was 2.7 μm, and the thickness of the reverse pattern 22b was 0.9 μm. As a result of the high-temperature load test, it was found that the failure rate was reduced to 1/10 in this embodiment as compared with the case where the slit G was not formed.
(Example 2)

According to the first modification, 2000 laminated ceramic capacitors 30 having internal electrode layers 27 having the shape shown in FIG. A high temperature load test was performed under the condition of 38V.

The thickness of the conductive pattern 23 was set to 1.0 μm, and the width of the slit G was set to 20 μm. The number of layers of the conductive pattern 23 was 474, the thickness of the green sheet 22a was 2.7 μm, and the thickness of the reverse pattern 22b was 0.9 μm. As a result of the high-temperature load test, it was found that the failure rate was reduced to 1/15 of the case where the slit G was not formed in this embodiment.
(Example 3)

According to the second modification, 2000 laminated ceramic capacitors 30 having internal electrode layers 27 having the shape shown in FIG. A high temperature load test was performed under the condition of 38V.

The thickness of the conductive pattern 23 was set to 1.0 μm, and the width of the slit G was set to 20 μm. The number of layers of the conductive pattern 23 was 474, the thickness of the green sheet 22a was 2.7 μm, and the thickness of the reverse pattern 22b was 0.9 μm. As a result of the high-temperature load test, it was found that the failure rate was reduced to 1/3 of the case where the slit G was not formed in this embodiment.

As mentioned above, although this embodiment was described in detail, this embodiment is not limited above. For example, in the above description, a laminated ceramic capacitor was manufactured as a ceramic electronic component, but a varistor, a thermistor, or the like may be manufactured as a ceramic electronic component.

1 Carrier film 2a Green sheet 2b Reverse pattern 3 Conductive pattern 3a Projection 4 Pattern forming sheet 5 Laminated body 6 Cover sheet 7 Internal electrode layer 8 Laminated chip 8a End surface 8b End surface 9a External electrode 9b External electrode 10 Multilayer ceramic capacitor 11 Dielectric layer 21 Carrier film 22a Green sheet 22b Reverse pattern 23 Conductive pattern 23a Edge 23c Projection 23d Long side 24 Pattern forming sheet 25 Laminate 26 Cover sheet 27 Internal electrode layer 27d Long side 27e Electrode piece 27f Electrode piece 27g Edge 27h Edge 27k short side 28 laminated chip 28a end surface 28b end surface 28c upper surface 29a external electrode 29b external electrode 30 laminated ceramic capacitor 31 dielectric layer 50 screen printing plate 51 mesh portion 52 emulsion portion 55 screen plate 61 first screen plate 62 second screen Plate G slit

Claims (4)

A laminated chip formed by alternately laminating a plurality of dielectric layers containing ceramic as a main component and a plurality of internal electrode layers, wherein the plurality of laminated internal electrode layers are alternately led out to two different end surfaces. and,
an external electrode formed on each of the two end faces;
a plurality of slits provided in at least half or more of the plurality of internal electrode layers and extending in a direction in which the two end faces face each other ;
In a top view, the positions of the plurality of slits in different layers are aligned within a range of 5 μm,
The plurality of slits extend to the external electrodes to which the internal electrode layers having the slits are connected so as not to increase in width , and the other external electrode side is not exposed on the surface of the laminated chip, and A ceramic electronic component , wherein the slits are connected to each other on the other external electrode side by means of slits substantially perpendicular to the extending direction of the plurality of slits. Under the first virtual line extending in the width direction of the laminated chip from the center of the upper surface of the laminated chip, a second virtual line extending in the width direction is drawn from the first virtual line to the thickness of the laminated chip. that the distance between two points where the second imaginary line intersects the upper surface of the laminated chip is equal to or greater than the width of the internal electrode layer in the lateral direction when drawn at intervals of 1% of 2. The ceramic electronic component according to claim 1. A green sheet containing ceramic as a main component and a conductive pattern formed on the surface of the green sheet by a printing method are alternately laminated to form a laminate before firing, and the laminate is pressurized to obtain the above-described a step of crimping each of the green sheets and the conductive patterns to alternately expose the stacked conductive patterns on two different end faces of the laminate;
forming external electrodes on the two end surfaces during or after firing the laminate,
In the step of forming at least half or more of the plurality of conductive patterns included in the laminate, a plurality of slits extending in a direction in which the two end faces face each other are formed in the conductive pattern, and the plurality of slits are formed in the conductive pattern. extends to one of the two end faces without increasing its width, is not exposed on the surface of the other end face on the other end face side, and the plurality of slits extends on the other end face side A method of manufacturing a ceramic electronic component, characterized by forming a slit connecting the plurality of slits in a direction substantially perpendicular to the direction of the ceramic electronic component. 4. The method of manufacturing a ceramic electronic component according to claim 3 , further comprising the step of forming a pattern containing said ceramic on said green sheet around said conductive pattern.

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