JP7327269B2 - Gate drives and compound gate drives - Google Patents

Description

The present invention relates to gate drives and composite gate drives.

In a power converter in which gate-driven switching elements are connected in series between power supply terminals, it is necessary to control gate drive so as to avoid short-circuiting of upper and lower arms. In addition, it is required to be able to protect the elements of the opposing arm in the event of an abnormality. For this reason, conventionally, a high voltage IC is provided as a gate drive device so as to avoid short-circuiting of the upper and lower arms in principle by transmitting gate voltage information of one of the upper and lower arms to the other arm. There is

However, this configuration uses a high withstand voltage IC capable of coping with the high voltage applied between the upper and lower arms, resulting in high cost. For this reason, in order to avoid using a high-voltage IC, there is a gate drive device that transmits gate voltage information between upper and lower arms using insulated communication.

However, in the conventional devices, the information transmitted to the opposed arm is only ON/OFF information of the switch, so there is a possibility that the element of the opposed arm cannot be protected when an abnormality occurs.

Japanese Patent Application Laid-Open No. 2002-272131 Japanese Patent No. 5585514 Japanese Patent No. 5776658

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above circumstances, and its object is to provide a gate drive device and a composite gate drive device capable of avoiding short-circuiting of upper and lower arms at low cost and protecting switching elements of opposing arms when an abnormality occurs. is to provide

The gate drive device according to claim 1 is a gate drive device that drives one switching element among a plurality of gate-driven switching elements connected in series, and comprises an on-drive circuit that turns on the switching element. (21), an off-drive circuit (22) for off-driving the switching element, and a drive signal generation circuit (26) for outputting a gate drive signal by calculating a logical product of a drive command signal and a drive permission signal received from the outside. a first insulating communication circuit (27) for outputting the gate drive signal output by the drive signal generation circuit in an electrically isolated state; and a gate state signal for detecting the gate voltage of the switching element and outputting a gate state signal. an abnormality detection circuit (24) for detecting an abnormal state of the switching element and outputting an abnormality detection signal; drive and control the on-drive circuit and the off-drive circuit based on the state signal output from the gate monitoring circuit and the abnormality detection signal output from the abnormality detection circuit to output the drive permission signal. A control circuit (20) and a second isolation communication circuit (28) for outputting the drive enable signal output from the control circuit to the outside in an electrically isolated state are provided.

By adopting the above configuration, for example, in the case where each of two gate-driven switching elements connected in series is provided for gate driving, the control circuit can control the gate voltage supplied via the first insulating communication circuit. It drives and controls the ON drive circuit and the OFF drive circuit based on the drive signal. At this time, if a drive permission signal is not input from another gate drive device, the off operation is performed regardless of the drive command signal. Therefore, drive control is performed so as to avoid short-circuiting of the upper and lower arms and to protect the switching element when an abnormality occurs. It can be performed.

In addition, the control circuit performs control corresponding to the abnormality detection signal from the abnormality detection circuit according to the state signal input from the gate monitoring circuit and the abnormality detection signal from the abnormality detection circuit for the switching element that the control circuit is driving. , to transmit a drive enable signal to another gate driver through the second isolated communication circuit. As a result, in a gate drive device that drives other switching elements, drive control can be performed so as to protect the switching elements when an abnormality occurs while avoiding short-circuiting of the upper and lower arms.

Electrical configuration diagram showing the first embodiment Action explanatory diagram 1 Timing chart 1 Action explanatory diagram 2 Timing chart 2 Electrical configuration diagram showing the second embodiment Timing chart Electrical configuration diagram of the current detection circuit Effect explanatory diagram of differential current determination Electrical configuration diagram showing the third embodiment Explanation of terminal names and functions on the control side Explanatory diagram of terminal names and functions on the drive side Logic circuit node name and explanatory diagram Electrical block diagram of ON drive circuit, OFF drive circuit and related parts Timing chart Explanatory diagram of constant voltage drive system Timing chart Explanatory diagram of low-current drive method Timing chart Electrical block diagram of the parts related to soft-break and short-circuit overcurrent detection Timing chart Electrical configuration diagram of the part related to gate monitoring operation and half-on suppression operation Timing chart Electrical configuration diagram of the part related to power element overheat protection operation Timing chart Electrical configuration diagram of the part related to temperature monitor operation Timing chart Electrical configuration diagram of the part related to IC overheat protection operation Timing chart Electrical configuration diagram of the part related to the 5V power supply circuit Timing chart Electrical configuration diagram of the part related to the UVLO circuit Timing chart Electrical configuration diagram of isolated communication circuit Timing chart Electrical configuration diagram showing the fourth embodiment Timing chart Electrical configuration diagram showing the fifth embodiment

(First embodiment)
A first embodiment of the present invention will be described below with reference to FIGS. 1 to 3. FIG. In this embodiment, two IGBTs (Insulated Gate Bipolar Transistors) 1 and 2 as switching elements connected in series between power supply terminals are gate-driven, and a load is supplied from a commonly connected node. It is applied to the configuration that energizes the

In each of the two IGBTs 1 and 2, the high side IGBT 1 is gate driven by the gate driving device 10A, and the low side IGBT 2 is gate driven by the gate driving device 10B. Also, the two IGBTs 1 and 2 are provided with sense emitters, respectively, and current detection resistors 1a and 2a are connected between the sense emitters and the emitters.

Since the two gate drive devices 10A and 10B have the same configuration, the configuration of the gate drive device 10A will be described below as a representative. Further, the constituent elements of the gate driving device 10A are denoted by numerals with a appended to them, and the equivalent constituents of the gate driving device 10B are denoted by numerals appended with b.

The gate drive device 10A includes a logic circuit 20a, an ON drive circuit 21a, an OFF drive circuit 22a, a gate monitoring circuit 23a, a current detection circuit 24a, a power element overheat protection circuit 25a, an AND circuit 26a, a first insulation communication circuit 27a and a second It has an insulated communication circuit 28a. The gate drive device 10A also has a terminal MINa, a terminal GENINa, a terminal GENOUTa, a terminal MPa, a terminal MNa, a terminal GINa, a terminal SOCa, and a terminal TAINa as input/output terminals.

One of two input terminals of the AND circuit 26a receives a gate drive signal from the outside through the terminal MINa, and the other terminal GENINa receives a signal from the other gate drive device 10B side. The AND circuit 26a outputs a high-level signal to the logic circuit 20a through the first insulating communication circuit 27a when the signals input from the two input terminals are both high-level. The AND circuit 26a functions as a drive signal generation circuit.

When the input signal from the AND circuit 26a becomes high level, the logic circuit 20a stops driving the off drive circuit 22a, and then gives the on drive signal from the on drive circuit 21a to the gate of the IGBT 1 via the terminal MPa to turn it on. drive. Further, when the input signal from the AND circuit 26a becomes low level, the logic circuit 20a stops driving the ON drive circuit 21a, and then gives the OFF drive signal to the gate of the IGBT 1 from the OFF drive circuit 22a through the terminal MNa. drive off. The logic circuit 20a functions as a control circuit.

The gate monitoring circuit 23a receives the gate voltage of the IGBT 1 from the terminal GIN and determines whether the gate voltage is normal. When there is an abnormality in the gate voltage, the gate monitoring circuit 23a detects an abnormal state and outputs an abnormality detection signal to the logic circuit 20a.

The current detection circuit 24a takes in the terminal voltage of the current detection resistor 1a connected to the sense emitter of the IGBT 1 through the terminal SOC, detects the current value of the IGBT 1, and detects an abnormal state such as a short circuit. When the current value of the IGBT 1 is abnormal, the current detection circuit 24a detects an abnormal state and outputs an abnormality detection signal to the logic circuit 20a. The current detection circuit 24a is one of the abnormality detection circuits.

The power element overheat protection circuit 25a inputs the forward voltage of the temperature-sensitive diode 30a through the terminal TAINa with a constant current flowing through the temperature-sensitive diode 30a arranged near the IGBT 1, and detects the value of the forward voltage. The temperature of IGBT1 is detected. When the detected temperature is abnormal, the power element overheat protection circuit 25a detects an abnormal state and outputs an abnormality detection signal to the logic circuit 20a. Although two temperature sensitive diodes 30a are shown in series here, one or three or more may be provided.

When an abnormality detection signal is input from any one of the gate monitoring circuit 23a, the current detection circuit 24a, and the power element overheat protection circuit 25a, the logic circuit 20a transmits the input abnormality detection signal through the second insulation communication circuit 28a. is output from the terminal GENOUTa to the other gate driving device 10B side.

The gate drive device 10B has the same configuration as the gate drive device 10A described above except that the suffix is changed from a to b. .

Between the gate driving devices 10A and 10B, terminals GENINa and GENOUTb are connected by a communication line L1, terminals GENINb and GENOUTa are connected by a communication line L2, and terminals GENOUTb and a are connected. to the other terminals GENINa and b.

Next, the operation of the above configuration will be described with reference to FIGS. 2 to 5 as well.
First, normal operation will be described with reference to FIGS. 2 and 3. FIG. In FIG. 2, the thick line indicates the output path of the signal that gives the timing when the high-side IGBT 1 and the low-side IGBT 2 alternately turn on and off. FIG. 3 also shows the states of the signals of the respective parts of the gate driving devices 10A and 10B.

The state of FIG. 3 shows a state in which the two IGBTs 1 and 2 continuously repeat the ON/OFF operation. First, a state in which a drive signal for turning on the IGBT 1 is input at time t0 will be described. The drive signal is input through the terminal MINa so as to alternately repeat ON/OFF at a predetermined cycle. Here, for example, at time t0, the gate driving device 10A receives a high-level signal MINa for turning on, and at the same time t0, a low-level signal MINb for turning off is inputted to the gate driving device 10B. Thereafter, at time t3, both signals MINa,b are inverted.

In the state immediately before time t0, IGBT1 is in the off state and IGBT2 is in the on state. First, the on-drive signal from the on-drive circuit 21b of the gate drive device 10B is stopped, and the off-drive signal is output from the off-drive circuit 22b through the terminal MNb, and the IGBT 2 in the on state is off-driven. As a result, the gate voltage of the IGBT 2 drops, and when it drops to the threshold voltage Vth at time t1, the gate monitoring circuit 23b detects this and a detection signal is input to the logic circuit 20b.

The logic circuit 20b outputs the detection signal as a high-level signal from the terminal GENOUTb to the communication line L1 via the second isolation circuit 28b. At this time, the logic circuit 20b outputs an off-driving signal to the off-driving circuit 22b to discharge the gate charge of the IGBT 2 from the terminal MNb, reduce the gate voltage to 0, and maintain the off state.

On the other hand, in the gate drive device 10A, when a high-level signal is input from the communication line L1 to the terminal GENINa, the AND circuit 26a calculates the result of operation with the high-level drive signal input from the terminal MINa. , outputs a high-level ANDa signal to the logic circuit 20a through the first insulating communication circuit 27a.

The logic circuit 20a receives this signal and outputs a signal for driving the IGBT 1 to the ON state from the terminal MPa to the ON drive circuit 21a. As a result, the gate voltage of the IGBT 1 gradually increases. The gate voltage of the IGBT 1 at this time is input to the gate monitoring circuit 23a through the terminal GINa.

When the gate voltage of the IGBT 1 rises and reaches the threshold voltage Vth at time t2, the gate monitoring circuit 23a detects the ON state and outputs a low-level detection signal to the logic circuit 20a. The logic circuit 20a receives this and outputs a low-level detection signal from the terminal GENOUTa via the second insulation communication circuit 28a. As a result, a low-level detection signal is input from the terminal GENINb to the AND circuit 26b on the gate drive device 10B side. The input from the terminal MINb of the AND circuit 26b is also a low-level drive signal.

As a result, after the gate drive device 10B detects that the IGBT 2 is turned off from the on state at the time t0, and reliably turned off at the time t1 after the dead time has passed, the gate drive device 10A turns the IGBT 1 off. driven on.

After that, at time t3, the gate driving device 10A receives a low-level driving signal through the terminal MINa, and the gate driving device 10B receives a high-level driving signal through the terminal MINb. A low-level signal is output to the logic circuit 20a regardless of the signal level from. As a result, the logic circuit 20a stops the ON drive signal from the ON drive circuit 21a, the OFF drive signal is output from the OFF drive circuit 22a via the terminal MNa, and the IGBT 1 in the ON state is turned OFF. As a result, the gate voltage of the IGBT 1 drops, and when it drops to the threshold voltage Vth at time t4, the gate monitoring circuit 23a detects this and a detection signal is input to the logic circuit 20a.

The logic circuit 20a outputs the detection signal as a high-level signal from the terminal GENOUTa to the communication line L2 via the second isolation circuit 28a. At this time, the logic circuit 20a also outputs an off drive signal to the off drive circuit 22a to discharge the gate charge of the IGBT 1 from the terminal MNa, reduce the gate voltage to 0, and maintain the off state.

On the other hand, in the gate drive device 10B, when a high level signal is input from the communication line L1 to the terminal GENINb, the AND circuit 26b calculates the result of the operation with the high level drive signal input from the terminal MINb. , a high-level signal is output to the logic circuit 20b through the first insulating communication circuit 27b.

The logic circuit 20b receives this signal and outputs a signal for driving the IGBT 2 to the ON state from the terminal MPb to the ON drive circuit 21b. As a result, the gate voltage of the IGBT 2 gradually increases. The gate voltage of the IGBT 2 at this time is input to the gate monitoring circuit 23b via the terminal GINb.

When the gate voltage of the IGBT 2 rises and reaches the threshold voltage Vth at time t5, the gate monitoring circuit 23b detects the ON state and outputs a low-level detection signal to the logic circuit 20b. The logic circuit 20b receives this and outputs a low-level detection signal from the terminal GENOUTb to the communication line L1 via the second insulation communication circuit 28b. As a result, on the gate drive device 10A side, a low-level detection signal is input to the AND circuit 26a from the communication line L1 via the terminal GENINa. The input from the terminal MINa of the AND circuit 26a is also a low-level drive signal.

As a result, after the gate drive device 10A detects that the IGBT 1 is turned off from the on state at the time t3 and reliably turned off at the time t4 after the dead time has passed, the gate drive device 10B turns the IGBT 2 off. driven on.
Thereafter, the IGBTs 1 and 2 are alternately turned on and off with a dead time in the same manner as described above.

Next, with reference to FIGS. 4 and 5, the operation when the IGBT 1 has a short-circuit failure in the middle will be described.
That is, in a state in which the gate drivers 10A and 10B drive and control the IGBTs 1 and 2 in the same manner as described above, the IGBT 1 turns on at time t2 and then turns off as shown in FIG. Assume that a short-circuit fault occurs at time tx before operation.

In this case, due to the short-circuit failure of the IGBT 1, for example, the gate voltage gradually decreases as shown in FIG.

As a result, the logic circuit 20a maintains a state of outputting a low-level signal from the terminal GENOUTa to the communication line L2 via the second insulating communication circuit 28a in order to indicate the abnormal state. As a result, in the gate drive device 10B, even when an external on-driving drive signal is input to the terminal MINb after time t3, the AND circuit 26b receives the low-level input from the communication line L2 to the terminal GENINb. The output is held off by a signal.

As a result, after time t3, the IGBT 2 is not turned on by the gate driving device 10B and is kept off. Therefore, in this state, the IGBT 2 is not turned on, so that a through current can be prevented from flowing between the power supply and the ground.

In addition, since an isolated communication circuit is provided to perform communication between the gate drivers, malfunction due to a potential difference between the high side and the low side is prevented, and the operations of the IGBTs 1 and 2 are associated with each other. Control can be performed with good timing between 10A and 10B.

According to the first embodiment, for example, when an abnormal state occurs in which the IGBT 1 is short-circuited, the gate drive device 10A of the own arm detects this and turns off the IGBT 1, and the gate drive device of the opposing arm 10B through the second isolated communication circuit 28b, the gate drive device 10B receiving this can turn off the IGBT 2 as well.

Similarly, even if the IGBT 2 is short-circuited contrary to the above, the occurrence of an abnormal state can be similarly transmitted to the gate drive device 10A side, so that short-circuiting of the upper and lower arms can be avoided when an abnormality occurs. can.
In addition, since the drive enable signal can be transmitted to the opposing arm at the off timing of the IGBTs 1 and 2, the dead time control can be reliably executed.
Furthermore, by providing the insulating communication circuits 27 and 28, signal transmission between the upper and lower arms can be realized at low cost.

(Second embodiment)
6 to 9 show the second embodiment, and the differences from the first embodiment will be explained below.

In this embodiment, in addition to the configuration in which the current detection of the IGBTs 1 and 2 by the gate driving devices 10A and 10B detects an abnormal state based only on the absolute value as in the first embodiment, the previous current value in the repeated ON/OFF process is used. Instead of the current detection circuits 24a and 24b, current detection circuits 29a and 29b are provided to detect abnormal changes in the current as compared to the current detection circuits 24a and 24b.

The current detection circuits 29a and 29b receive current values when the IGBTs 1 and 2 are turned on as terminal voltages SOC of the current detection resistors 1a and 2a, respectively. and when the difference exceeds a predetermined threshold, it is determined that the difference is greater than or equal to.

FIG. 7 shows changes in the signals of the gate drivers 10A and 10B when the current of the IGBT 1 sharply increases after time t5. In FIG. 7, for example, from time t0 to t5, the IGBTs 1 and 2 are in a state in which the IGBTs 1 and 2 are alternately controlled to be turned on and off. In this state, for example, the detected currents of the IGBTs 1 and 2 are input as voltage signals from the terminals SOCa and SOCb to the current detection circuits 29a and 29b, respectively.

The voltage signals of the detected currents input to the current detection circuits 29a and 29b gradually increase cycle by cycle, for example V1, V2 and V3. Differences from the previous values are calculated as V2-V1 and V3-V2, and these difference values are equal to or less than the threshold value ΔVth in a normal state.

However, in the case shown in FIG. 7, when IGBT1 is energized at time t5, the voltage signal of the detected current of IGBTR1 has increased not to the level of V2 but to the greatly increased level of Vx. The level of the voltage signal Vx at this time is equal to or lower than the level of the threshold Vth_SC as the first threshold for judging a short circuit, but the difference value Vx−V1 from the previous voltage signal V1 exceeds the threshold ΔVth as the second threshold. Therefore, the current detection circuit 29a determines that this is an abnormal state.

As a result, the current detection circuit 29a outputs an abnormality detection signal to the logic circuit 20a. When receiving the abnormality detection signal, the logic circuit 20a controls to keep the IGBT 1 in the OFF state, and stops outputting a high level signal from the terminal GENOUTa via the insulating communication circuit 28a. As a result, no high-level signal is input to the terminal GENINb on the side of the gate drive device 10B, so that no drive signal is output to the logic circuit 20b even at time t8 when the IGBT 2 is turned on.

Next, specific configurations and operations of the current detection circuits 29a and 29b that perform the above operations will be described with reference to FIGS. 8 and 9. FIG. Since the current detection circuits 29a and 29b have the same configuration, the current detection circuit 29a will be described below as a representative.

As shown in FIG. 8, the current detection circuit 29a includes a comparator 101 that determines an overcurrent with a threshold value Vth_SC that is a determination value, and a difference determination unit 102 that determines a difference value with a threshold value ΔVth that is a difference determination value by the operation described above. Prepare. The non-inverting input terminal of the comparator 101 is connected to the terminal SOC (terminal SOCa, terminal SOCb), and the threshold Vth_SC is input to the inverting input terminal. The comparator 101 outputs the determination result from the output terminal to the logic circuit 20a.

The difference determination unit 102 includes an AD converter 103, a subtraction unit 104, and a comparator 105 for determination. The AD converter 103 takes in the voltage signal of the detected current input from the terminal SOC (terminal SOCa, terminal SOCb), converts it into a digital value, and outputs it. The subtraction unit 104 includes a current value holding unit 106 , a previous value holding unit 107 and a subtraction circuit 108 .

The current value holding unit 106 outputs and holds the digital conversion output input from the AD converter 103 to the subtraction circuit 108 as the current value SH1 obtained in one ON period. In the next ON period, the current value holding unit 106 transfers the current value SH1 as the previous value SH0 to the previous value holding unit 107, and holds the digital conversion output input this time as the new current value SH1.

The subtraction circuit 108 calculates the difference between the current value SH1 and the previous value SH0, and outputs it to the comparator 105 as the voltage difference ΔV of the analog voltage. The comparator 105 outputs a low-level signal when the input voltage difference ΔV is smaller than the threshold voltage ΔVth, and outputs an abnormality detection signal CMP to the logic circuit 20 when it is greater than the threshold voltage ΔVth.
Next, the operation of the above configuration will be described with reference to FIG.

In the gate drive device 10A, when the output signal from the AND circuit 26a, that is, the AND signal of the external drive signal MINa and the input signal GENINa from the gate drive device 10B is applied to the logic circuit 20a, the ON drive circuit 21a, ON/OFF drive control of the IGBT 1 is performed by the OFF drive circuit 22a.

As shown in FIG. 9, the output of the AND circuit becomes a signal that turns on at times t0, t2 and t4 and turns off at times t1, t3 and t5. , voltage signals V1, V2, and V3 corresponding to the detected current of the IGBT 1 are input, and return to zero level at timings t1, t3, and t5 of off-drive.

The voltage signals V 1 , V 2 and V 3 are converted into digital signals D 1 , D 2 and D 3 respectively by the AD converter 103 and output to the subtractor 104 . The digital signals D1 to D3 output by the AD converter 103 are captured by the current value holding unit 106 of the calculation unit 104 at the timing when the output of the AND circuit changes to the low level indicating the OFF operation. The current value holding unit 106 holds the fetched digital signals D1 to D3 and outputs them to the subtraction circuit 104 until the next fetching operation is performed.

On the other hand, the digital signals D1 to D3 fetched into the current value holding unit 106 are outputted to the previous value holding unit 107 at the timing when the output of the AND circuit changes to high level indicating ON operation. Previous value holding unit 106 inputs the input value to subtraction circuit 108 as previous value SH0.

Further, the subtraction circuit 104 subtracts the current value SH1 from the current value SH1 at times t1, t3, and t5 when the updated current value SH1 is input from the current value holding unit 105, that is, at times t1, t3, and t5 when the output of the AND circuit changes to a low level indicating an OFF operation. A difference from the previous value SH0 is calculated and output to the comparator 105 as a difference value ΔV. As a result, the difference value ΔV corresponding to the difference voltage between the voltage signal of the detected current and the previous value of zero is input to the non-inverting input terminal of the comparator 105 .

Now, in the example shown in FIG. 9, when the IGBT 1 is turned on at time t4, the current value has not yet reached the short-circuit current detection threshold Vth_SC, but it is in a state of increasing rapidly. In this case, in the subtraction circuit 104, the current value SH1 of the current value holding unit 106 is taken into the previous value holding unit 107 at time t4, and the current value holding unit 106 stores the current input value of the AD converter 103 as follows: It is captured at time t5, which is the off timing.

At time t5, the difference value ΔV3 between the previous value SH0 in the previous value holding unit 107 and the current value SH1 in the current value holding unit 106 is obtained in the subtraction circuit 108. Since it is larger than the threshold voltage ΔVth, the comparator A differential abnormality detection signal CMP is output from 105 to the logic circuit 20 .

As a result, even if the detected voltage of the emitter current of the IGBT 1 does not exceed the short-circuit detection level in the short-circuit detection circuit 29a, if there is a change exceeding the threshold voltage ΔVth with respect to the previous detection voltage, it is regarded as an abnormal state. can be determined as

Further, when such an abnormal state is detected, the IGBT 1 is turned off by the off-driving circuit 22 or soft cut-off circuit 31, thereby preventing the IGBT 1 from being destroyed.

(Third embodiment)
10 to 35 show the third embodiment, and the differences from the first embodiment will be explained below. In this embodiment, specific detailed configurations and operations of the gate driving devices 10A and 10B shown in the first embodiment are shown. Since the gate driving devices 10A and 10B have the same configuration, the configuration of the gate driving device 10A will be described below. In order to avoid complication, the internal constituent elements are indicated by omitting the suffix a.

FIG. 10 shows the overall electrical configuration of the gate drive device 10A. In this configuration, the ON drive circuit 21 has a drive power supply 21x inside. In addition to the OFF drive circuit 22, a soft cutoff circuit 31 and an OFF hold circuit 32 are provided. In addition to the current detection circuit 24, an overcurrent detection circuit 33 is provided. A temperature monitor circuit 34 is provided in addition to the power element overheat protection circuit 25 .

It also has an IC overheating protection circuit 35 that detects overheating in the gate driving device 10A composed of an IC and protects it. The power supply circuit system includes a 5V power supply circuit 36 and UVLO (Under Voltage Lock Out) circuits 37 and 38 for preventing low voltage malfunction. Further, the second isolated communication circuit 28 comprises three isolated communication circuits 28P, 28Q, 28R. The isolated communication circuits 27 , 28 P, 28 Q, and 28 R have the same configuration, and an isolation element 42 is interposed between the transmitting section 40 and the receiving section 41 . A transformer or the like is used as the insulating element 42, for example.

The specific configuration and function of each circuit will be described below, and each terminal provided in the gate drive device 10A composed of an IC will be described with reference to FIGS. 11 and 12. FIG. A terminal shown in FIG. 11 is provided as a terminal for controlling the gate drive device 10A. These control-side terminals include a control-side power supply VDD terminal, a drive input terminal MIN, an abnormal output terminal FAIL, a temperature monitor output terminal TOUT, a self-arm ON permission input terminal GENIN, and an opposing arm ON permission output terminal GENIN. There are a terminal GENOUT, a control-side ground terminal GND1, and the like.

Further, the terminals shown in FIG. 12 are provided as drive-side terminals for the gate drive device 10A to perform control operation and abnormality detection. These drive terminals include a terminal VCC for receiving power from a power supply VC, a terminal VREF for a 5V power supply, a terminal VFB for a driving power supply, a terminal PMP for on-drive transistor input, a terminal MP for on-drive transistor output, and an off-drive transistor A terminal MN for output, a terminal SCO for soft cutoff that is short circuit protection, a terminal SOUT for holding off output, a terminal GIN for gate monitoring, a terminal SOC for overcurrent and short circuit detection input, and a terminal TAIN for temperature sense input. , and a terminal GND for driving-side ground.

The drive terminals of the gate drive device 10A are connected to the logic circuit 20 via internal drive circuits, detection circuits, and the like. The drive-side terminal and the control-side terminal are kept electrically insulated by the first insulating communication circuit 27 and the second insulating communication circuits 28P, 28Q, and 28R.

FIG. 13 shows node names and functions of terminals A to O of the logic circuit 20. As shown in FIG. These terminals A to O will be briefly described below. A terminal A is a terminal to which an ON/OFF drive signal is input from the AND circuit 26 via the first insulating communication circuit 27 . A terminal B is a terminal for outputting an abnormality detection signal in response to an abnormality in the IGBT 1 (2) or an abnormality in the gate drive device 10A (10B). A terminal C is a terminal for outputting a temperature monitor signal for the IGBT 1 (2).

A terminal D is a terminal for receiving a detection signal of a drop in the VCC power supply from the UVLO circuit 37 . A terminal E is a terminal for outputting a power element ON drive control signal for ON-driving the IGBT 1 to the ON drive circuit 21 . A terminal F is a terminal for outputting a power element off-driving control signal for off-driving the IGBT 1 to the off-driving circuit 22 .

A terminal G is a terminal for outputting a soft cutoff signal for soft cutoff to the soft cutoff circuit 31 after detecting a short circuit of the power element. A terminal H is a terminal for outputting an OFF hold signal for holding the OFF state of the power element to the OFF hold circuit 32 . A terminal I is a terminal for inputting a gate monitoring signal of a gate monitoring circuit 23 that monitors the gate voltage of the IGBT 1, which is a power element.

A terminal J is a terminal for inputting an overcurrent detection signal output when the current of the IGBT 1 detected by the overcurrent detection circuit 33 becomes an overcurrent. A terminal K is a terminal for inputting a short-circuit detection signal output by the current detection circuit 24 when the IGBT 1 is in a short-circuited state. A terminal L is a terminal for inputting a power element overheat protection signal output when the power element overheat protection circuit 25 detects that the temperature of the IGBT 1 is in an overheat state.

A terminal M is a terminal for inputting temperature information of the power element obtained by monitoring the temperature of the IGBT 1 by the temperature monitor circuit 34 as a temperature monitor input signal. A terminal N is a terminal for inputting an IC overheating protection signal output when the IC overheating state is detected by the IC overheating protection circuit 35 . A terminal O is a terminal for outputting ON permission information for the counter arm as a counter arm ON permission signal to the terminal GENOUT via the second insulating communication circuit 28R.

<On drive, off drive operation, and off hold operation>
Next, basic functions of each part will be described. FIG. 14 shows parts related to on/off driving of the IGBT 1, which is a power element. A drive signal for driving the IGBT 1 is input from the AND circuit 26 to the terminal A of the logic circuit 20 via the first insulating communication circuit 27 . The drive signal is a signal obtained by ANDing the drive signal input to the terminal MIN and the self-arm-on permission signal input to the terminal GENIN.

The logic circuit 20 outputs a power element ON drive control signal from the terminal E to the ON drive circuit 21 . The ON drive circuit 21 gives a gate drive output from the terminal MP to the gate of the IGBT 1 via the resistor 5 when the power element ON drive control signal is given. At this time, as will be described later, the on-drive circuit 21 has a constant voltage drive system and a constant current drive system.

The off drive circuit 22 includes a buffer circuit 22x and an n-channel MOS transistor 22y. A power element off drive control signal is input from the terminal F of the logic circuit 20 to the buffer circuit 22x. The MOS transistor 22y has a drain connected from the terminal MN to the gate of the IGBT 1 via the resistor 6, a source connected to the ground, and a gate connected to the output terminal of the buffer circuit 22x.

The gate monitoring circuit 23 includes a comparator 23x, an inverting input terminal to which a reference voltage of an off-holding threshold is input, and a non-inverting input terminal connected to the gate of the IGBT 1 via a terminal GIN. In the gate monitoring circuit 23, the gate voltage Vg of the IGBT 1 is input to the non-inverting input terminal of the comparator 23x. input.

The off hold circuit 32 includes a buffer circuit 32x and an n-channel MOS transistor 32y. The buffer circuit 32 x receives an off hold signal from the terminal H of the logic circuit 20 . The MOS transistor 32y has a drain connected from the terminal SOUT to the gate of the IGBT1, a source connected to the ground, and a gate connected to the output terminal of the buffer circuit 32x. The off-holding circuit 32 is configured to connect the terminal SOUT to the gate of the IGBT 1 with low impedance, and can be directly connected as shown in the figure, or can be connected via a low-impedance resistance element or the like. is also possible.

<On drive operation>
Next, the on-drive operation will be described. As shown in FIG. 15, when the power element ON drive control signal is turned ON at time t0, the ON drive circuit 21 charges the gate of the IGBT 1 to turn it ON. At this time, as described above, the on-drive circuit 21 has a constant voltage drive type as shown in FIGS. 16 and 17 and a constant current drive type as shown in FIGS. In addition, in FIG. 15, the drive signal MIN&GENIN is indicated by negative logic.

This is due to the demand for low loss and miniaturization in inverters such as motor drive devices for EV/EHV vehicles. It is implemented from the relationship of consideration.

In drive technology, in addition to reducing IGBT switching loss, it is necessary to consider the switching surge voltage between the collector and the emitter and the surge voltage of the motor sharing surge that occurs in the motor, but there is a trade-off between switching loss and surge voltage. Since there is a relationship of

Reduction of switching loss is determined by switching speed, and reduction of surge voltage is considered to be reduction of time change di/dt of the current flowing through the switching element and reduction of parasitic inductance.

In the constant voltage drive method, as shown in FIG. 16, the ON drive circuit receives a drive signal from the inverter circuit to which the ON/OFF drive signal is applied from the logic circuit 20 to the gate of the p-channel MOS transistor Tr1 for drive. It is a given configuration. When the MOS transistor Tr1 is turned on, a constant voltage of the power supply voltage VB is applied to the gate of the IGBT from the terminal VOUGT through the resistor Rg.

At this time, as shown in FIG. 16, the current Ig1 flowing into the gate of the IGBT is a value obtained by dividing the potential difference (VB-Vg) obtained by subtracting the gate voltage Vg from the power supply voltage VB by the resistance value. The resistance value is the sum of the on-resistance Ron of the MOS transistor Tr1 and the resistance Rg (Ron+Rg).

As shown in FIG. 17, for example, when the MOS transistor Tr1 is turned on at time t1, the output voltage Vout output from the terminal VOUT rises substantially to the power supply voltage VB. Also, the gate current Ig1 begins to flow rapidly from time t1, but decreases with time as the gate voltage Vg increases. On the other hand, the gate voltage Vg rises from time t1 and remains at the mirror voltage Vm during the mirror period. After that, when the mirror period ends, the gate voltage Vg rises again and reaches near the power supply voltage VB, and the IGBT is turned on.

In the constant-voltage driving method, the switching speed is generally slowed down in order to reduce the time change di/dt of the current, which is dealt with by increasing the gate resistance Rg to lower the gate current Ig. Since variations in gate current Ig are determined by variations in gate resistance Rg and gate voltage Vg, gate current Ig1 is designed in consideration of these variations in order to satisfy surge design.

In addition, in the constant voltage drive method, the driving current decreases as the gate voltage Vg increases during ON driving, so that the collector-emitter voltage Vce becomes less sharp, which may result in increased switching loss.

On the other hand, in the constant current drive method, as shown in FIG. 18, the ON drive circuit includes a MOS transistor Tr1, a differential amplifier OP for driving the MOS transistor Tr1, a shunt resistor Rs, a reference resistor Rref, and a constant current Icc. have a source. The MOS transistor Tr1 is configured such that the power supply voltage VB is supplied via the shunt resistor Rs, and the gate voltage is controlled by the differential amplifier OP so that the potential difference of the shunt resistor Rs is constant.

As a result, the current flowing through the MOS transistor Tr1 becomes constant, so that the IGBT can be driven at a constant current. At this time, the current Ig2 flowing into the gate of the IGBT is equal to the value of the current flowing through the shunt resistor Rs, as shown in FIG. 18. Therefore, the potential difference (VB −VS) divided by the resistance value of the shunt resistor Rs.

As shown in FIG. 19, for example, when the MOS transistor Tr1 is turned on at time t1, a gate current Ig2 flows through the IGBT via the shunt resistor Rs and the MOS transistor Tr1. At this time, as described above, the gate current Ig2 is controlled to be the constant current Igo, and the potential of the terminal VS is kept lowered by the reference voltage Vref.

After that, when the IGBT is turned on by applying a predetermined gate voltage at time t2 after the mirror period, the gate current Ig2 becomes zero and the potential of the terminal VS also becomes substantially the power supply voltage VB.

In the constant-current driving method, the gate current Ig2 can be expressed by the voltage and resistance of the shunt resistor until the gate voltage Vg rises and the voltage across the shunt resistor is reduced. In the case of the constant current drive system, the variation is determined by the shunt resistance and the VS voltage (amplifier variation). Therefore, the constant current drive method is not affected by the gate voltage, so compared to the constant voltage drive method, the constant current drive method can suppress an increase in switching loss due to variations in specifications when designing surges. .

<Off drive operation and off hold operation>
Next, the off-driving operation and the off-holding operation will be described.
The IGBT 1 is turned off by extracting the gate charge of the IGBT 1 by the off drive circuit 22 according to the power element off drive control signal. At this time, in order to prevent the gate voltage from being applied to the IGBT 1 in the OFF state for some reason, the off-holding circuit 32 connects the gate and the emitter with a low impedance, and the gate voltage Vg is held below the threshold. I'm trying to

Between times t0 and t1, the IGBT 1 is turned on by the on-drive circuit 21. At time t1, the on-drive circuit 21 turns off, and the off-drive circuit 22 drives instead. In the off-drive circuit 22, the MOS transistor 22y is turned on, whereby the gate charge of the IGBT 1 is extracted and the gate voltage Vg is lowered.

At this time, the off drive circuit 22 extracts the gate charge of the IGBT 1 via the resistor 6, so the gate voltage Vg decreases at the speed set by the resistor 6. FIG. When the gate voltage Vg becomes equal to or lower than the threshold voltage, the IGBT1 is turned off.

Further, the gate monitoring circuit 23 monitors the gate voltage Vg of the IGBT 1 , and when the gate voltage Vg becomes equal to or lower than the OFF holding threshold, the comparator 23 x detects this and inputs a detection signal to the terminal I of the logic circuit 20 . The logic circuit 20 drives the off holding circuit 32 to hold the off state in response to the detection signal from the gate monitoring circuit 32 .

In this case, when the gate voltage Vg of the IGBT1 is sufficiently lowered to turn off the IGBT1, the off-holding circuit 32 keeps the gate and emitter of the IGBT1 substantially short-circuited by the MOS transistor 32y. As a result, the gate and the emitter of the IGBT 1 are connected with a low impedance, thereby preventing the gate voltage Vg from exceeding the threshold unintentionally due to noise or the like, thereby preventing erroneous ignition. In FIG. 15, at time t2 when the gate voltage Vg reaches the off-holding threshold, the off-holding circuit 32 is driven to hold the gate voltage Vg of the IGBT 1 at approximately 0V.

<Soft cutoff operation and short circuit overcurrent detection operation>
Next, the protection operation of the IGBT 1 by the soft cutoff circuit 31 will be described with reference to FIGS. 20 and 21. FIG. A current detection circuit 24 and an overcurrent detection circuit 33 detect whether or not the current flowing through the IGBT 1 reaches an abnormal level. When an abnormal current flows, that is, when an abnormal state occurs, the IGBT 1 is turned off at a speed different from that during normal turn-off to prevent destruction.

The soft cutoff circuit 31 includes a buffer circuit 31x and an n-channel MOS transistor 31y. A soft cut-off signal is input from the terminal G of the logic circuit 20 to the buffer circuit 31x. The MOS transistor 31y has a drain connected from the terminal SCO to the gate of the IGBT 1 via the resistor 7, a source connected to the ground, and a gate connected to the output terminal of the buffer circuit 31x.

The soft cutoff circuit 31 is configured to be able to shut down the IGBT 1 at a speed different from that during normal off, depending on the resistance value of the resistor 7 connected in series. Further, by turning off the IGBT 1 using the soft cutoff circuit 31, it is possible to prevent the IGBT 1 from breaking down.

The current detection circuit 24 includes a comparator 24x, an inverting input terminal to which a threshold voltage Vth_SC for short-circuit detection is input, and a non-inverting input terminal connected to the sense emitter of the IGBT 1 via a terminal SOC. In the current detection circuit 24, a detection voltage corresponding to the emitter current of the IGBT 1 is input to the non-inverting input terminal of the comparator 24x. Input to the terminal K of the logic circuit 20 .

The overcurrent detection circuit 33 includes a comparator 33x, an inverting input terminal to which a threshold voltage Vth_OC for overcurrent detection is input, and a non-inverting input terminal connected to the sense emitter of the IGBT 1 via a terminal SOC. In the overcurrent detection circuit 33, a detection voltage corresponding to the emitter current of the IGBT 1 is input to the non-inverting input terminal of the comparator 33x. It is input to the terminal J of the logic circuit 20 as a signal.

In FIG. 20, the ON drive circuit 21 shows an example of a circuit configuration using a constant voltage drive system, but it is also possible to apply a circuit configuration using a constant current drive system. It is also possible to employ a configuration that uses both.
Next, the operation when a short-circuit fault occurs and the soft cut-off operation will be described with reference to FIG.

When the drive signal input from the outside switches from OFF to ON at time t0, the ON drive signal is output from the logic circuit 20 to the ON drive circuit 21, and a voltage is applied to the gate of the IGBT1. As a result, the gate voltage Vg of the IGBT1 rises and the IGBT1 is turned on.

At this time, the current flowing through the IGBT 1 is input to the terminal SOC as the terminal voltage of the current detection resistor 1a connected to the sense emitter. When the IGBT 1 has a short-circuit failure, the current of the IGBT 1 does not remain constant at a predetermined level and continues to rise, so the voltage signal input to the terminal SOC also rises.

When the detection voltage input to the terminal SOC exceeds the threshold voltage Vth_SC for short-circuit detection, the current detection circuit 24 outputs a high-level short-circuit detection signal from the comparator 24x to the terminal K of the logic circuit 20 as an abnormal state. be done. Thus, in the logic circuit 20, when a high-level short-circuit detection signal is input at time t2 when the constant filter time Tf has elapsed, occurrence of a short-circuit abnormality is determined.

The logic circuit 20 outputs a soft cutoff signal to the soft cutoff circuit 31 when a short-circuit abnormality occurs. As a result, the soft cutoff circuit 31 turns on the MOS transistor 31 y and performs a soft cutoff operation of discharging the gate charge of the IGBT 1 through the resistor 7 . As a result, when the gate voltage Vg of the IGBT1 decreases, it works to reduce the current of the IGBT1.

Then, at time t3, when the current of the IGBT 1 decreases and the detection voltage input to the terminal SOC becomes equal to or lower than the threshold voltage Vth_SC for short circuit detection, the comparator 24x becomes low level and the short circuit detection signal is turned off. When time t4 has elapsed, the gate voltage Vg of the IGBT1 becomes zero level, the IGBT1 is turned off, and the detected voltage input to the terminal SOC becomes zero.

In the above operation, the overcurrent detection operation by the overcurrent detection circuit 33 is performed in substantially the same manner as the detection operation of the current detection circuit 24 except that the threshold voltage Vth_OC for overcurrent determination is different. The cutoff circuit 31 allows the IGBT 1 to perform a soft cutoff operation. Further, the above-described short-circuit determination threshold and overcurrent determination threshold can be set to different voltages, or can be set to the same voltage.

The short-circuit abnormality determination by the logic circuit 20 is performed by setting the filter time Tf. This is to prevent malfunction due to noise, and the set time of the filter time Tf is set to an appropriate value. Alternatively, other processing operations may be employed without filter time.
In addition, in the logic circuit 20, it is also possible to combine information on the gate voltage Vg as a condition for judging short circuit or overcurrent.

<Gate monitoring operation and half-on suppression operation>
Next, referring to FIGS. 22 and 23, in the off operation of IGBT 1, the half-on state in which the gate voltage Vg continues to be equal to or higher than the threshold voltage for more than a certain period of time is regarded as an abnormal state, and the operation of suppressing this. explain.

FIG. 22 shows circuitry that functions when a half-on condition occurs. Also, FIG. 23 shows the change state of the signal of each part. It is assumed that a high-level drive signal MIN&GENIN indicating OFF drive is input from the AND circuit 26 through the first insulating communication circuit 27 at time t0 from a state before time t0 when the IGBT 1 is ON-driven.

As a result, the logic circuit 20 gives a drive stop signal to the ON drive circuit 21 at time t1, and stops applying the gate voltage to the IGBT1. After that, the logic circuit 20 outputs an off drive signal to the off drive circuit 22 at time t2 after the dead time. As a result, the charge on the gate of the IGBT 1 is discharged through the resistor 6 and the MOS transistor 22 y of the off drive circuit 22 .

At this time, if the IGBT 1 is in a normal state, the gate voltage Vg drops to zero level within a predetermined time as the charge is discharged, as indicated by the dashed line in FIG. , and a low-level gate monitoring signal is output from the gate monitoring circuit 23 to the logic circuit 20 .

However, in the abnormal state where the IGBT 1 does not turn off normally and is in a half-on state, the gate voltage Vg of the IGBT 1 slowly decreases, so the gate monitoring circuit 23 sends a high-level gate monitoring signal to the logic circuit 20. keep outputting. In the logic circuit 20, if the gate monitoring signal remains at high level even at time t3 when the fixed time Tx set for determination has elapsed since time t0 when the drive signal was turned off, A half-on state, which is an abnormal state, is determined.

When the logic circuit 20 determines the half-on state, the logic circuit 20 outputs a drive signal to the off-holding circuit 32 in order to perform low-impedance off-driving. As a result, the off-holding circuit 32 turns on the MOS transistor 32y, connects the gate of the IGBT1 to the ground level through the terminal SOUT, and rapidly lowers the gate voltage Vg to zero level. As a result, a low-level gate monitoring signal is input from the gate monitoring circuit 23, and the OFF state can be recognized.

<Power element overheat protection operation>
Next, referring to FIGS. 24 and 25, the operation of determining the overheating state of the IGBT 1 will be described.

As described above, the power element overheat protection circuit 25 monitors the overheating state of the IGBT 1 to be driven by monitoring the forward voltage Vf of the temperature sensitive diode 30 . The power element overheat protection circuit 25 has a comparator 25x and a constant current circuit 25y.

The comparator 25x has a hysteresis, a threshold voltage Vth_OT for determining overheating is set to the non-inverting input terminal, and an inverting input terminal is connected to the anode of the temperature sensitive diode 30 via the terminal TAIN. The constant current circuit 25y is provided to pass a predetermined current through the temperature sensitive diode 30 when the temperature is detected.

The power element overheat protection circuit 25 supplies a constant current from the constant current circuit 25y to the temperature sensing diode 30 when the temperature is detected, and the comparator 25x inputs the forward voltage of the temperature sensing diode 30 at this time as a temperature detection signal. Two temperature-sensitive diodes 30 connected in series are used here, but the number can be set as appropriate.

Since the forward voltage Vf of the temperature-sensitive diode 30 has characteristics that change according to temperature, the temperature in the vicinity of the IGBT 1 can be detected by measuring the forward voltage while a constant current is flowing. Here, a threshold voltage Vth_OT for power element overheat determination is set to the non-inverting input terminal of the comparator 25x. Due to the hysteresis action of the comparator 25x, the threshold voltage is Vth_OTL when the output is inverted to high level, and the threshold voltage is Vth_OTH, which is larger than Vth_OTL, when the output is inverted to low level.

In the logic circuit 20, when the output of the power element overheat protection circuit 25 is input, a filter 20x for outputting the power element overheat detection signal OT after a certain filter time Tf1, and a filter 20x for a certain filter time Tf2. is provided with a filter 20y for outputting a drive signal to the OFF holding circuit 22 after . Furthermore, an inverter 20z for inverting the output of the filter 20y and outputting it to the ON drive circuit 21 is provided.

As shown in FIG. 25, for example, when the drive signal MIN&GENIN for ON drive is input at time t0, an instruction signal is output to the logic circuit 20, and the IGBT 1 is ON-driven by the ON drive circuit 21 at time t1. As a result, the gate voltage Vg of the IGBT 1 reaches a predetermined level and turns on.

In the normal state where the temperature of the IGBT 1 is low, the forward voltage Vf of the temperature sensitive diode 30 is higher than the threshold voltage Vth_OTL for judging the overheating state, so the output of the comparator 25x is low level. Thereafter, when the IGBT 1 generates heat and the forward voltage Vf of the temperature sensitive diode 30 decreases, and becomes equal to or lower than the threshold voltage Vth_OTL at time t3, it is determined that an abnormal state exists, and the logic circuit outputs a high-level overheat detection signal as an abnormality detection signal. 20.

In the logic circuit 20, the filter 20x outputs the overheat detection signal OT at time t4 after the filter time Tf1 has elapsed. Further, the filter 20y outputs a drive signal to the off drive circuit 22 at time t5 after the filter time Tf2 has elapsed. At the same time, it outputs to the ON drive circuit 21 the drive signal for the OFF operation inverted through the inverter 20z. In practice, the ON drive circuit 21 is controlled to turn OFF first, and the OFF drive circuit 22 turns ON after a dead time.

As a result, the IGBT1 is turned off, and the gate voltage Vg is lowered. When the current becomes zero, the IGBT 1 no longer generates heat and the temperature drops due to heat radiation. After that, when the forward voltage Vf of the temperature sensitive diode 30 becomes equal to or higher than the threshold voltage Vth_OTH at time t6, the comparator 25x outputs a low level signal. to output

As a result, when the temperature of the IGBT 1 reaches an overheated state, this state is detected by the power element overheat protection circuit 25, and the IGBT 1 is turned off by the off drive circuit 22, thereby preventing the IGBT 1 from being destroyed.

<Temperature monitor operation>
Next, the temperature monitor operation will be described with reference to FIGS. 26 and 27. FIG.
The temperature monitor circuit 34 detects the temperature of the IGBT 1 with the temperature sensitive diode 30 and outputs a temperature monitor output TOUT, similarly to the power element overheat protection circuit 25 . The temperature monitor circuit 34 includes a constant current circuit 34x, an AD conversion circuit 34y and a DUTY conversion circuit 34z.

In the temperature monitor circuit 34, when the temperature is detected, a constant current flows from the constant current circuit 34x to the temperature sensing diode 30, and the forward voltage Vf corresponding to the temperature is taken from the terminal TAIN to the AD conversion circuit 34y. The AD conversion circuit 34y converts the captured voltage of the terminal TAIN into a digital value and outputs the digital value to the DUTY conversion circuit 34z.

The DUTY conversion circuit 34z performs DUTY conversion processing in a pattern as shown in FIG. As shown in the figure, the minimum voltage is DUTY 0% and the maximum voltage is DUTY 100%.

Also, in the logic circuit 20, the values DUTY-converted by the DUTY conversion circuit 34z are output as a series of sequences. Here, for example, a signal indicating the start of the temperature transmission sequence is added in the header section T1. The start signal of the temperature transmission sequence is, for example, a combined signal of "HHHHL" as shown in FIG. .

Also, in the data section, the pattern is such that the data is output for m periods, with the period T2 being one. Each cycle T2 is composed of a duty conversion data period Tdd indicating temperature information and an "H" fixed time T3. In the DUTY conversion data period Tdd, DUTY is indicated by periods of "L" and "H".

<IC overheat protection operation>
28 and 29, the overheating detection and protection operation in each circuit in the IC will be described.

Inside the IC constituting the gate drive device 10A (10B), an IC overheat protection circuit 35 capable of effectively protecting from an overheated state is provided corresponding to a plurality of circuits that generate heat.

Specifically, three IC overheat protection circuits 35A to 35C are provided so as to detect the overheat state of the ON drive circuit 21, the OFF drive circuit 22 and the 5V power supply circuit 36 as an abnormal state. The IC overheat protection circuits 35A to 35C have the same configuration. As shown in FIG. 28, the IC overheat protection circuit 35A provided in the ON drive circuit 21 will be described.

The IC overheat protection circuit 35A includes a constant current circuit 35x, a temperature sensitive diode 35y and a comparator 35z. The temperature-sensitive diode 35y is arranged in a portion to be protected from overheating, and a constant current is supplied from the constant-current circuit 35x when the overheating state is determined. Similar to the comparator 25x of the power element overheat protection circuit 25, the comparator 35z has a hysteresis and operates similarly.

While the ON drive circuit 21, the OFF drive circuit 22 and the 5V power supply circuit 36 are operating, the temperatures of the circuit components are detected by the IC overheat protection circuits 35A to 35C and input to the logic circuit 20 as IC overheat detection signals OT1 to OT3. be. The logic circuit 20 is provided with filter circuits 20p, 20q, and 20r to which the input signals of the IC overheat protection circuits 35A to 35C are input, and outputs detection signals when the filter time Tf has elapsed.

As a result, as shown in FIG. 29, when the internal circuit overheats while the ON drive circuit 21 and the OFF drive circuit 22 are operating in accordance with the drive command, the forward voltage Vf of the temperature sensitive diode 35y decreases. , and the comparator 35z detect this as an abnormal state. At time t1, when overheat detection signals OT1 to OT3, which are abnormal detection signals, are output from any of the IC overheat protection circuits 35A to 35C, in the logic circuit 20, the filter time Tf elapses due to the filters 20p, 20q, and 20r. An off command is output at time t2.

As a result, the ON drive circuit 21 and the OFF drive circuit 22 stop operating. After that, the temperature inside the circuit drops as time passes, and when the overheat detection signals OT1 to OT3 are canceled at time t3, the ON drive circuit 21 and the OFF drive circuit 22 follow the drive command again. Return to working state.
By the above operation, the ON drive circuit 21, the OFF drive circuit 22 and the 5V power supply circuit 36 are prevented from being destroyed due to overheating.

<Operation of 5V power supply circuit>
The operation of 5V power supply circuit 36 will now be described with reference to FIGS. 30 and 31. FIG.
The 5V power supply circuit 36 inputs the voltage VCC supplied from the power supply terminal VC from the terminal VCC, internally generates a 5V voltage, and outputs it to an internal circuit or an external circuit.

In FIG. 30, the 5V power supply circuit 36 includes a reference voltage generation circuit 36x, a differential amplifier 36y, and voltage dividing resistors R1 and R2. The reference voltage generating circuit 36x is supplied with power from the power supply terminal VCC, and inputs a reference voltage for generating a 5V power supply to the non-inverting input terminal of the differential amplifier 36y. A voltage dividing resistor R1 is connected between the inverting input terminal and the output terminal of the differential amplifier 36y, and a voltage dividing resistor R2 is connected between the inverting input terminal and the ground.

The differential amplifier 36y controls the output voltage so that the power supply voltage VCC becomes the reference voltage set by the reference voltage generation circuit 36x, that is, 5V. At this time, the voltage divided by the voltage dividing resistors R1 and R2 is fed back to the inverting input terminal of the differential amplifier 36y.
The 5V voltage output generated in this way is supplied to the internal circuitry as well as to the external circuitry via the terminal VREF.

FIG. 31 shows changes in the level of the power supply voltage VCC, which is the power supply on the driving side, and changes in VREF, which is the generated 5V power supply output. When the power supply voltage VCC rises and reaches 5V, the 5V power supply output is fixed at 5V even if the power supply voltage VCC rises further. As a result, a 5V power supply output can be stably supplied without being affected by fluctuations in the power supply voltage VCC.

<Operation of UVLO>
The operation of UVLO circuits 37 and 38 will now be described with reference to FIGS. 32 and 33. FIG.
The UVLO circuits 37 and 38 have a function to stop the operation and protect the internal circuits before an abnormal state occurs when the power supply voltages VCC and VDD of the IC drop below the operating voltage range. 32 will be described because they have the same configuration except that .

The UVLO circuit 37 has a comparator 37x and a filter circuit 37y. The comparator 37x has a hysteresis, an inverting input terminal to which the detection voltage Vt_UVLO is input, and a non-inverting input terminal connected to the power supply terminal VCC.

As shown in FIG. 33, in the period from time t1 to t2 when the power supply voltage VC is equal to or higher than the detection voltage Vt_UVLO, the comparator 37x is in a low level output state, and the UVLO circuit 37 sets the internal IC flag to a low level state. and When the power supply voltage VC drops to the detection voltage Vt_UVLO or less at time t2, the comparator 37x outputs a high-level detection signal. After the filter time tdLFT has passed, the filter circuit 37 y sets the internal IC flag to high level and outputs it to the logic circuit 20 .

The logic circuit 20 stops the operation of the internal circuit when a high-level intra-IC flag is input. This can prevent malfunction caused by a voltage drop in the internal circuit of the IC, that is, the gate drive device 10A (10B).

After that, when the power supply voltage VC returns to the detection voltage Vt_UVLO or higher at time t4, the UVLO circuit 37 starts outputting a low level flag to the in-IC flag logic circuit 20, and the stop state of the internal circuit by the logic circuit 20 is released. and resume operation.

The UVLO circuit 38 also detects a drop in the power supply voltage VD, and when a drop state is detected in the same manner as described above, the logic circuit 20 controls the internal circuit to stop operating.

As described above, by providing the UVLO circuits 37 and 38, it is possible to prevent malfunction inside the IC when the power supply voltages VC and VD are temporarily lowered.

<Insulation communication function>
34 and 35 show the electrical configuration and operation of the first isolated communication circuit 27 and the second isolated communication circuit 28 (28P, 28Q, 28R).

Signal transmission is performed while input and output are electrically insulated. Also, since the insulating communication circuits 27 and 28 (28P, 28Q, 28R) have the same configuration, the first insulating communication circuit 27 will be described as shown in FIG.

The first isolation communication circuit 27 transmits an input signal from the transmission section 40 side to the reception section 41 side via the isolation element 42 with a communication circuit of set "H" and reset "L". The transmitter 40 includes a pulse generation circuit 40x and buffer circuits 40y and 40z. The receiving section 41 includes a latch circuit 41x and buffer circuits 41y and 41z. The isolation element 42 includes transformers 42x and 42y corresponding to high and low, respectively.

The transmission unit 40 outputs pulses from output terminals (INH/INL) corresponding to set (H) and reset (L) according to the toggle of the input signal (IN). The isolation element 42 transmits the signal from the transmission section 40 to the reception section 41 through the transformers 42x and 42y in a state in which direct current is cut off. The receiving unit 41 toggles the output (OUT) when the corresponding terminal (OUTH/OUTL) receives a pulse.
As a result, signal transmission can be performed between the input and output terminals in a state in which a DC component is cut off, and signal transmission can be performed between circuits having different ground levels.

According to such a third embodiment, as a specific configuration of the gate control devices 10A and 10B shown in the first and second embodiments, by providing a configuration as shown in FIG. As information, it is possible to transmit and receive various abnormality detection signals, thereby improving the protection function of the IGBTs 1 and 2 .

In the above configuration, the insulating element 42 may be of a magnetic coupling type using a GMR sensor instead of a magnetic coupling type using a transformer coil, or may be of a capacitive coupling type insulation transmission type using a capacitor. can also be adopted.

(Fourth embodiment)
36 and 37 show a fourth embodiment, and the differences from the first embodiment will be explained below. In this embodiment, on the premise of the configuration of the above-described embodiment, it is configured to further improve the function.

Specifically, it proposes a short-circuit protection technology for IGBTs 1 and 2, which are power elements used in inverters and the like. Basically, the IGBT1 is prevented from being destroyed by detecting the current flowing through the IGBT1, which is a power element, and turning off the IGBT1 at a different speed than when it is normally turned off when a current exceeding the threshold flows. It is something to do.

As a background for providing this embodiment, it can be assumed that the filter time is not changed and set individually for power elements such as IGBTs, and therefore clamping is normally performed when the gate voltage rises. In some cases, it may affect the switching losses of the power elements.

Also, when the gate voltage is detected and handled, the detection delay time in gate voltage detection affects the gate voltage, so if the gate voltage exceeds the detection threshold and the power element is shorted , there is a possibility that the short-circuit energy increases and the power element breaks down.

This embodiment aims to solve the above problems, and solves the point that the filter time cannot be changed for each power element and the point that the gate voltage detection has a detection delay time.

Therefore, firstly, it is possible to reduce the switching loss without depending on the power element. Secondly, although the gate voltage is clamped, the clamping time is set to the detection delay time or more and as short as possible to solve the problem.

As a result, by performing gate voltage clamping, the short-circuit energy of the power element is reduced so as not to destroy the power element. At this time, the gate clamp time is set to be longer than the detection delay time and as short as possible.

In addition, erroneous detection of a short circuit is prevented by gate voltage detection. At this time, the gate voltage detection is set as high as possible without exceeding the clamp voltage.
Next, a specific configuration will be described with reference to FIG.

The gate monitoring circuit 23 determines the gate voltage Vg of the IGBT 1 with the gate detection threshold value Vth by the comparator 23x. The gate detection threshold Vth is set so as to satisfy the following relationship, for example.
Vm<Vth<Vcl
Here, Vm is the mirror voltage of IGBT1, and Vcl is the clamp voltage.

The IGBT 1 is held at the mirror voltage Vm if it enters a mirror period while the gate voltage Vg is rising, and then rises to a predetermined gate voltage. Therefore, the gate detection threshold Vth is set to a value larger than the mirror voltage Vm. Further, after the gate detection threshold value Vth is detected, the gate voltage Vg is set to a voltage lower than the clamp voltage Vcl because the gate voltage Vg is held at the clamp voltage Vcl.

The gate clamp circuit 50 is composed of a differential amplifier 50x and a MOS transistor 50y. The differential amplifier 50x inputs the gate voltage Vg of the IGBT 1 from the terminal SCO to the non-inverting input terminal through the resistor 8, and the MOS transistor so that the gate voltage Vg becomes equal to the clamp voltage Vcl set by the above relationship. 50y is driven and controlled.

The logic circuit 20 includes a clamp filter time generation circuit 20s therein, and upon receiving a detection signal from the gate monitoring circuit 23 via a terminal I, drives the gate clamp circuit 50 when a preset clamp filter time Tf_CL elapses. A drive signal is output so as to
Here, the clamp filter time Tf_CL is set so as to satisfy the following conditions in relation to the gate detection delay time Td.
Td≤Tf_CL

In addition, when a short-circuit state is detected as described above, the IGBT 1 is turned off at a different speed to shut down by driving the soft cutoff circuit 31 that shuts down the IGBT 1 separately from the off drive circuit 22 in the normal state. Avoid destruction.
The operation of the above configuration will be described with reference to FIG. 37 as well.

The logic circuit 20 outputs a drive signal to the ON drive circuit 21 at time t1 according to the drive signal to turn on the IGBT1. As a result, the gate voltage Vg of the IGBT 1 gradually increases, and the emitter current also increases.

Here, when the IGBT 1 is in a short-circuit state, the detected voltage of the emitter current is detected by the current detection circuit 24 from the voltage signal from the terminal SOC, and when it exceeds the short-circuit detection threshold Vth_SC at time t2, the short-circuit detection signal is output to the logic circuit. 20.

Also, since the collector of the IGBT 1 rises, the gate voltage Vg rises due to capacitive coupling. At this time, the gate monitoring circuit 23 outputs a detection signal to the logic circuit 20 when the gate voltage Vg of the IGBT 1 rises and exceeds the gate detection threshold Vth at time t3.

In the logic circuit 20, the clamp filter time generation circuit 20s outputs a driving instruction so that the gate clamp circuit 50 performs a gate clamp operation for the period of the clamp filter time Tf_CL. Thus, the gate clamp circuit 50 clamps the gate voltage Vg of the IGBT 1 so that it does not rise above the clamp voltage Vcl during the clamp filter time Tf_CL from time t3 to time t4, even if the gate voltage Vg rises.

After that, at time t4 when the clamp filter time Tf_CL has elapsed, the logic circuit 20 outputs a drive signal to the soft cutoff circuit 31 to pull out the gate charge of the IGBT 1. switch to the off state.

As a result, even when a power element including any IGBT 1 is used in normal times, the short-circuit energy of the power element can be reduced under the condition that the switching loss of the power element is not affected, and the breakdown of the power element can be prevented.

In the above configuration, the threshold voltages Vth_SC and Vth_OC of the current detection circuit 24 and the overcurrent detection circuit 33 can be set to the same voltage or different voltages.
In addition, in this embodiment, the following items are assumed as invention specifying matters.

As a first specific matter, the clamp filter time Tf_CL is set to start counting from the time when the gate voltage detection threshold value Vth is exceeded, and to be equal to or longer than the gate voltage detection delay time Td.
As a second specific item, the gate voltage detection threshold Vth should be set high within a range not exceeding the gate clamp voltage Vcl.

(Fifth embodiment)
FIG. 38 shows a fifth embodiment, and the differences from the first embodiment will be explained below. This embodiment provides short-circuit protection technology for power devices such as IGBTs 1 used in inverters and the like.

In the gate drive device, even if the current due to the feedback capacitance flows to the gate when the power element to be controlled is overcurrent or short-circuited, it is equipped with a gate potential change circuit that can quickly cut off the overcurrent and short-circuit flowing through the power element. There is a device (Patent No. 5776658).

However, when a gate potential change function is added to an IC constituting a gate drive device, it is necessary to add a gate potential change terminal. In addition, when trying to establish a gate potential change circuit by amplifier feedback, an external resistor/capacitor may be required for phase compensation.

In this embodiment, the input terminal of the clamp circuit 60 for short-circuit clamping and the input terminal of the soft cutoff circuit are provided for the purpose of eliminating such a problem, increasing the number of gate potential changing terminals, and reducing the number of external parts. In that case, it is possible to use both the phase compensation resistor and the OFF resistor for soft shutdown when amplifier feedback is used.
Therefore, in this embodiment, the AC characteristics of the amplifier are designed so that the OFF resistance for soft shutdown and the constant of the phase compensation resistance can be shared.

FIG. 38 shows the electrical configuration. In this configuration, the current flowing through the IGBT 1, which is a power element, is detected, and when a current greater than or equal to the short-circuit detection threshold flows, the IGBT 1 is turned off at a speed different from that of the normal off time, thereby preventing the IGBT 1 from being destroyed. It is intended to prevent

Similar to the configuration of the third embodiment, the gate drive device 10A includes an ON drive circuit 21, an OFF drive circuit 22, a soft cutoff circuit 31, a current detection circuit 24, an overcurrent detection circuit 33, a gate monitoring circuit 23 and a clamp circuit 60. It has The soft cutoff circuit 31 and the clamp circuit 60 receive the gate voltage Vg of the IGBT 1 from the terminal SOUT through the resistor 7 .

An adjusting circuit 61 including the resistor 7 is provided between the resistor 7 connected to the terminal SOUT and the gate of the IGBT1. The adjustment circuit 61 includes a diode 61x and a capacitor 61y in addition to the resistor 7. FIG. The diode 61x has an anode connected to the gate of the IGBT 1, a cathode connected to the resistor 7, and a ground, which is a reference potential, via a capacitor 61y.

The soft cutoff circuit 31 is connected to the gate of the IGBT 1 via a resistor 7 different from the off drive circuit 22, and can shut down the IGBT 1 at a speed different from the off operation by the off drive circuit 22 during normal off. , thereby preventing the IGBT 1 from being destroyed.

In the above configuration, the current flowing through the IGBT 1 is monitored by the short-circuit detection circuit 23 and the overcurrent detection circuit 33, and when a short-circuit state or an overcurrent state occurs, a preset short-circuit detection threshold value or overcurrent detection threshold value is set. After this, after the clamp filter time, the gate charge of the IGBT 1 is pulled out by the soft cutoff circuit 31 to turn off the IGBT 1 .

In addition, for example, if a short circuit with a large change in the collector voltage occurs, such as when the collector is short-circuited to the power supply voltage while the IGBT1 is on, a current flows into the gate through the feedback capacitance between the gate and the collector of the IGBT1, and the gate voltage Vg rises. In such a case, since the soft cutoff circuit 31 described above reduces the gate voltage based on the increase in the sense current, the IGBT 1 may not be turned off quickly.

On the other hand, in the adjustment circuit 61, when the gate rises to Vf or more of the diode 61x, the rise of the gate voltage Vg is suppressed by the capacitor 61y. Therefore, the clamp circuit 60 serves as a short-circuit protection precharge power output that controls the voltage of the capacitor 61y to be equal to the gate voltage Vg when the IGBT 1 is on.

According to such a fifth embodiment, the short-circuit energy of the IGBT 1, which is a power element, can be reduced, thereby preventing the IGBT 1 from breaking down. Further, even if the current from the capacitor 61y flows to the gate of the IGBT1, the overcurrent flowing to the IGBT1 can be cut off quickly.

Furthermore, by adopting the above configuration, the IC-based gate drive device 10A does not need to newly add terminals, and it is possible to reduce the cost by sharing the parts.

In the above configuration, the resistance value of the resistor 7 and the capacitance value of the capacitor 61y of the adjusting circuit 61 do not need to be matched when implementing the soft cutoff by adopting a configuration in which the terminal SOUT is also used. However, from the simulation results of the inventors, we were able to find sufficiently applicable conditions.

(Other embodiments)
The present invention is not limited to the above-described embodiments, and can be applied to various embodiments without departing from the scope of the invention. For example, the following modifications or extensions can be made.
Although the switching element has been described as using an IGBT, it is not limited to this, and may be a MOS transistor or a SICMOS transistor.
The configuration in which the switching elements are connected in series can also be applied to an inverter circuit that configures a multi-phase bridge such as two-phase, three-phase or more phases.

Although the present disclosure has been described with reference to examples, it is understood that the present disclosure is not limited to such examples or structures. The present disclosure also includes various modifications and modifications within the equivalent range. In addition, various combinations and configurations, as well as other combinations and configurations, including single elements, more, or less, are within the scope and spirit of this disclosure.

In the drawings, 1 and 2 are IGBTs (switching elements), 1a and 2a are current detection resistors, 5 to 7 are resistors, 10A and 10B are gate drive devices, 20, 20a and 20b are logic circuits (control circuits), 20x to 20z is a filter circuit, 21, 21a, 21b are ON drive circuits, 21x is a drive power source, 22, 22a, 22b are OFF drive circuits, 23, 23a, 23b are gate monitoring circuits, 24, 24a, 24b, 29, 29a , 29b is a current detection circuit (abnormality detection circuit); 25, 25a, 25b are power element overheat protection circuits; 26, 26a, 26b are AND circuits (drive signal generation circuits); , 28, 28a, 28b, 28P, 28Q, and 28R are second insulated communication circuits, 30a and 30b are temperature-sensitive diodes, 102 is a difference determination unit, 31 is a soft cutoff circuit, 32 is an off-holding circuit, and 33 is an overcurrent detector. 34 is a temperature monitor circuit, 35 is an IC overheat protection circuit, 36 is a 5V power supply circuit, 37 and 38 are UVLO circuits, 50 is a gate clamp circuit, 60 is a clamp circuit, 61 is an adjustment circuit, 61x is a diode, and 61y is a diode. Capacitors L1 and L2 are communication lines.

Claims (8)

A gate drive device for driving one switching element among a plurality of gate-driven switching elements connected in series,
an on-driving circuit (21) for on-driving the switching element;
an off-driving circuit (22) for off-driving the switching element;
a drive signal generation circuit (26) for calculating the logical product of a drive command signal and a drive permission signal received from the outside and outputting a gate drive signal;
a first isolation communication circuit (27) for outputting the gate drive signal output by the drive signal generation circuit in an electrically insulated state;
a gate monitoring circuit (23) for detecting the gate voltage of the switching element and outputting a state signal of the gate;
an anomaly detection circuit (24) for detecting an anomaly state of the switching element and outputting an anomaly detection signal;
driving and controlling the on-driving circuit and the off-driving circuit based on the gate driving signal provided through the first insulating communication circuit, and the state signal output from the gate monitoring circuit and the abnormality detection circuit outputting from the abnormality detection circuit; a control circuit (20) for outputting the drive permission signal based on the input abnormality detection signal;
and a second isolation communication circuit (28) for outputting the drive enable signal output from the control circuit to the outside in an electrically isolated state. 2. The gate drive device according to claim 1, wherein said abnormality detection circuit detects an abnormal current of said switching element. 3. The gate drive device according to claim 2, wherein the abnormality detection circuit detects an abnormal current when the current of the switching element exceeds a first threshold value for determining an abnormal current. 4. The gate drive device according to claim 2, wherein the abnormality detection circuit detects an abnormal current when a difference current value between the current of the switching element and the current at the time of previous driving exceeds a second threshold. 5. The apparatus according to any one of claims 1 to 4, wherein said abnormality detection circuit comprises a temperature detection element for detecting temperature of said switching element, and a detection section for detecting an overheating state of said switching element based on a detection signal of said temperature detection element. A gate drive device according to any one of the preceding claims. A composite gate drive device provided with the gate drive device according to any one of claims 1 to 5 corresponding to each of at least two switching elements used in series connection,
The control circuit is
controlling not to output the drive permission signal to the rest of the plurality of gate drivers when one of the plurality of gate drivers receives an anomaly detection signal from the anomaly detection circuit;
A composite gate drive device in which one of the plurality of gate drive devices does not drive regardless of the drive signal for the switching element when the drive permission signal is not input from the remaining gate drive devices. . A gate drive device for driving a gate drive type switching element,
an on-driving circuit (21) for on-driving the switching element;
an off-driving circuit (22) for off-driving the switching element ;
a current detection circuit (24) for detecting a short circuit state of the switching element;
a gate clamp circuit (50) for clamping a gate voltage to a gate clamp voltage different from that during a steady ON/OFF state for a clamp filter time when the switching element is ON-driven;
A gate driving device comprising a gate monitoring circuit (23) that detects a gate voltage of the switching element and sets a start timing of the clamp filter time when a gate detection voltage lower than the gate clamp voltage is reached. A gate drive device for driving a gate drive type switching element,
an on-driving circuit (21) for on-driving the switching element;
an off-driving circuit (22) for off-driving the switching element;
an overcurrent detection circuit (33) for detecting overcurrent in the switching element;
a soft cutoff circuit (31) that softly cuts off the switching element;
Between the diode (61x) provided between the gate of the switching element and the input terminal to the soft cutoff circuit and forwardly connected from the gate to the input terminal, and between the cathode of the diode and a reference voltage an adjustment circuit (61) comprising a capacitor (61y) connected to and absorbing a current caused by charging or discharging of the feedback capacitor between the gate and the emitter;
and a clamp circuit (60) for clamping the terminal voltage on the positive electrode side of the capacity of the adjustment circuit to a predetermined voltage range through the input terminal to the soft cutoff circuit.

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