JP7324529B2 - Hysteresis comparator and communication circuit - Google Patents

Description

The present invention relates to hysteresis comparators and communication circuits.

The inventor of the present application has proposed an electronic circuit that performs data communication between substrates using capacitive coupling and inductive coupling (together referred to as electromagnetic field coupling) (see Patent Documents 1 and 2, for example). In such electronic circuits, flexible printed circuit boards (FPCs), printed circuit boards (PCBs), modules, and terminals (hereinafter collectively referred to as boards) have couplers. formed.

In Patent Document 1, a signal line is used as a coupler. Two signal lines (a signal line and a feedback signal line) arranged in parallel are formed on each substrate (FIG. 33). The signal line and the feedback signal line are terminated and matched using resistors. The signal line and feedback signal line of one substrate are arranged parallel to and in the same direction as the signal line and feedback signal line of the other substrate. By stacking the substrates, the signal lines are arranged close to each other. Since the signal lines overlap each other and the feedback signal lines overlap each other, wireless communication can be performed by electromagnetic field coupling.

Patent Document 2 discloses a communication device using a signal line as a coupler. In Patent Document 2, since a differential signal is used, a lead transmission line is connected to both ends of one signal line. A positive signal is input to the transmission line from one extraction transmission line, and a negative signal is input to the transmission line from the other extraction transmission line.

Japanese Patent No. 5213087 JP 2014-033432 A

A digital signal is a non-return to zero signal (NRZ signal), and when it passes through an AC coupler such as an electromagnetic field coupler, the DC component is lost and it becomes a small-amplitude pulse signal. The receiver restores this small-amplitude pulse signal to a digital signal using a hysteresis comparator (Patent Document 1, paragraph 0191 and FIG. 30). The hysteresis comparator can change the input threshold, and can improve noise resistance when there is no signal change (that is, when the same digital data continues). A hysteresis of 50 mV or more and 1/3 or less of the signal amplitude is often required.

If a commercially available hysteresis comparator IC (Integrated Circuit) chip is used, it is difficult to speed up data communication. On the other hand, comparators without hysteresis are highly versatile, and high-speed IC chips are commercially available. Moreover, the hysteresis width may be insufficient in commercially available hysteresis comparator IC chips.

Also, if the comparator IC chip is to be applied to a vehicle, the parts must be vehicle-certified. However, relatively few hysteresis comparator IC chips are vehicle-certified. On the other hand, comparators without hysteresis are more versatile, and more and more of them are on the market with automotive qualification. Therefore, comparators with no hysteresis and comparators with a small hysteresis width are readily available and can be constructed at low cost.

The present embodiment has been made in view of the above problems, and even when an IC chip having a comparator without hysteresis or a hysteresis comparator with a small hysteresis width is used, a hysteresis comparator having desired characteristics and communication The purpose is to provide a circuit.

A communication circuit according to the present embodiment includes a substrate, an electromagnetic field coupler provided on the substrate, and a first comparator that compares levels of received signals received by the electromagnetic field coupler, a first IC chip mounted on the substrate; and a second comparator for comparing levels of the received signal. and a feedback loop that positively feeds back the output to the input.

In the above communication circuit, the first IC chip may have a serial/parallel converter arranged after the first comparator.

In the communication circuit described above, a capacitor may be provided in the feedback loop.

In the communication circuit described above, a resistor may be provided in the feedback loop.

A communication circuit according to this embodiment includes a substrate, an electromagnetic field coupler provided on the substrate, and a comparator that compares levels of received signals received by the electromagnetic field coupler. a feedback loop that has a mounted IC chip, a first capacitor provided on the substrate, and positively feeds back the output of the IC chip to the input; and the electromagnetic field coupler and the IC chip. and a second capacitor.

A communication circuit according to this embodiment includes a substrate, an electromagnetic field coupler provided on the substrate, and a comparator that compares levels of received signals received by the electromagnetic field coupler. a mounted IC chip; and a feedback loop having a resistor provided on the substrate and positively feeding back the output of the IC chip to the input.

A hysteresis comparator according to this embodiment includes a substrate and a first comparator for comparing levels of two input signals, a first IC chip mounted on the substrate, and the two input signals. a second IC chip mounted on the substrate; and a feedback loop for positively feeding back the output of the second IC chip to the input.

In the above hysteresis comparator, the first IC chip may have a serial/parallel converter arranged after the first comparator.

In the above hysteresis comparator, a capacitor may be provided in the feedback loop.

In the hysteresis comparator described above, a resistor may be provided in the feedback loop.

According to the present embodiment, it is possible to provide a hysteresis comparator and a communication circuit that can obtain desired characteristics even when using an IC chip having a comparator with no hysteresis or a comparator with a small hysteresis width. can.

2 is a block diagram showing a configuration of a communication circuit according to Embodiment 1; FIG. 2 is a block diagram showing a configuration example of an IC chip in Embodiment 1; FIG. FIG. 4 is a diagram showing a hysteresis width HYS calculated by simulation; FIG. 4 is a diagram showing a hysteresis width HYS calculated by simulation; It is a figure which shows the circuit structure used for simulation. 4 is a waveform diagram showing simulation results in Embodiment 1. FIG. 3 is a block diagram showing a configuration example of an IC chip; FIG. FIG. 8 is a block diagram showing the configuration of a communication circuit according to the second embodiment; FIG. FIG. 10 is a waveform diagram showing simulation results in the second embodiment; FIG. 11 is a block diagram showing the configuration of a communication circuit according to a third embodiment; FIG. 11 is a block diagram showing a configuration example of an IC chip in Embodiment 3; FIG.

Embodiment 1.
Hereinafter, this embodiment will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the hysteresis comparator according to the first embodiment. As shown in FIG. 1, the communication circuit 1 includes a substrate 2, an IC chip 13, a buffer 14, feedback loops 20p and 20n, resistors 21p and 21n, couplers 31p and 31n, and output terminals 41p and 41n. and resistors 51-54. The substrate 2 is provided with couplers 31p and 31n, resistors 51 to 54, an IC chip 13, a buffer 14, and resistors 21p and 21n. The substrate 2 is a wiring substrate on which wiring for connecting each component is formed.

In this embodiment, the signal received by the communication circuit 1 is described as a differential signal. It may be. In the following description, when identifying two components (differential pairs) that transmit differential signals, a subscript of p or n will be used. If there is no particular distinction between the two components that transmit differential signals, p and n will be described without subscripts. For example, the coupler 31 is used when the two couplers 31p and 31n are not identified. Also, the resistors 21p and 21n and the output terminals 41p and 41n are simply described as the resistor 21 and the output terminal 41 when the differential pair is not identified.

The coupler 31 is, for example, the electromagnetic field coupler shown in Patent Documents 1 and 2. The coupler 31 is a transmission line coupler configured by a transmission line on the substrate 2 as shown in FIG. 33 of Patent Document 1 or FIG. 2 of Patent Document 2 or the like. The coupler 31 is provided with a coupler similar to the coupler 31 in a communication circuit (not shown) serving as a communication partner. The coupler 31 can be, for example, transmission lines arranged in parallel so as to couple in an electric field and a magnetic field as a distributed constant system. Alternatively, the coupler 31 can be an overlapping coil (inductive coupler) for magnetic field coupling (inductive coupling) as a lumped constant system. Alternatively, the coupler 31 can be electrodes arranged parallel to each other for electric field coupling (capacitive coupling) as a lumped constant system. Electromagnetic coupling may be coupling using at least one of an electric field and a magnetic field.

The communication circuit 1 performs, for example, half-duplex communication with a communication circuit (not shown) serving as a communication partner. The communication circuit 1 serves as a communication device that transmits and receives data by wireless communication. Specifically, the coupler 31 of the communication circuit 1 is connected in a non-contact manner to the coupler of the communication circuit with which communication is to be performed. The digital signal is a non-return to zero signal (NRZ signal), and when it passes through the coupler 31, the DC component is lost and it becomes a pulse signal with small amplitude. Therefore, the received signals received by the couplers 31p and 31n are small-amplitude pulse signals. Since the configuration of the receiver is one of the technical features of the communication circuit 1 according to the present embodiment, only the configuration of the receiving side will be described, and the configuration of the transmitting side will be omitted. Also, the communication circuit 1 may be a receiving device without a transmitting function.

One end of the coupler 31 p is connected to the resistor 51 and the other end is connected to the non-inverting input terminal of the IC chip 13 . One end of the coupler 31 n is connected to the resistor 52 and the other end is connected to the inverting input terminal of the IC chip 13 . Resistors 51 and 52 are connected between the coupler 31p and the coupler 31n. Resistors 51 and 52 are termination resistors that terminate coupler 31p and coupler 31n.

The IC chip 13 is a semiconductor chip mounted on the substrate 2 . IC chip 13 is a receiver chip that functions as a receiver. Specifically, the IC chip 13 has a semiconductor circuit for restoring a digital signal. The configuration of the IC chip 13 will be described later.

The received signals received by the couplers 31p and 31n are input to the IC chip 13 . The IC chip 13 has a comparator that restores the received data. That is, the comparator restores the digital signal by comparing the levels of the two received signals. The digital signal is 1 when the level of the received signal from the coupler 31p is higher than the level of the received signal from the coupler 31n, and 0 when it is lower. The comparator provided in the IC chip 13 is a comparator without hysteresis characteristics. Alternatively, the comparator provided in the IC chip 13 may be a comparator with a small hysteresis width.

Resistors 53 and 54 are connected between the two input terminals of the IC chip 13 . A node between resistors 53 and 54 is biased at the termination potential Vb. Assuming that the power supply voltage is VDD, Vb=VDD/2, for example. The resistance values of the resistors 51-54 correspond to the characteristic impedance Z0 of the coupler 31 or the transmission line, typically Z0=50Ω.

The output of IC chip 13 is connected to buffer 14 . Therefore, the digital signal restored by the IC chip 13 is input to the buffer 14 . The buffer 14 amplifies the output amplitude of the IC chip 13 to the power supply voltage. The buffer 14 outputs the received signal to output terminals OUTP and OUTN. The output of buffer 14 is used as received data. The IC chip 13 and buffer 14 are assumed to be general-purpose semiconductor chips. That is, the IC chip 13 and the buffer 14 may be commercially available chips. Note that the buffer 14 can be omitted.

Feedback loops 20p and 20n are provided between the input and output of the IC chip 13 . Feedback loops 20p, 20n connect the output of IC chip 13 to the input. This connection is desirably within a distance sufficiently short compared to the wavelengths that are the components of the digital signal.

Feedback loops 20p and 20n are provided with resistors 21p and 21n, respectively. The feedback loops 20p and 20n have wiring on the substrate 2 and a resistor 21. FIG. Resistors 21p and 21n are feedback resistors. In other words, the input and output of the IC chip 13 are connected via the resistor 21 . The resistance values of the resistors 21p and 21n are the same, eg, 300Ω to 3kΩ. The output from IC chip 13 is fed back to the input of IC chip 13 via resistor 21 . Feedback loops 20p and 20n positively feed back the output of the IC chip 13 to the input. The input potentials of the IC chip 13 are VIP and VIN, and the output potentials are VOP and VON.

A circuit configuration of the IC chip 13 and the buffer 14 is shown in FIG. The IC chip 13 has a comparator COM and an inverter INV. The comparator COM compares the levels of the input potentials VIP and VIN of the differential input terminals INP and INN of the IC chip 13 . A two-stage inverter INV is provided at the output stage of the comparator COM. A resistor 56 is provided after the inverter INV. The inverter INV is a CMOS (Complementary Metal-Oxide-Semiconductor) inverter. Also, the buffer 14 has two stages of CMOS inverters.

When a positive differential signal is input to the comparator COM of the IC chip 13, the comparator COM outputs a positive signal with an amplitude close to VDD. This signal adds positive feedback to the input potential through resistor 21 . For example, when the voltage Vb is VDD/2, the current output from the comparator COM is the output impedance Z0 (sum of the impedance of the inverter INV in the output stage of FIG. 2 and the resistor 56), the resistance value R of the resistor 21 , and two parallel-connected termination resistors Z0 (having an equivalent resistance value of Z0/2) to the termination potential Vb (that is, VDD/2). Therefore, a differential voltage v_hys represented by the following equation (1) is added to the input terminal of the comparator COM by positive feedback.

v_hys=(VDD/2)*{(Z0/2)/((Z0/2)+R+Z0)}
=VDD*{1/(6+(4R/Z0))} (1)

For example, if VDD=1.8V, then R=1 kΩ and v_hys=21 mV, and R=0.5 kΩ and V_hys=39 mV. For VDD=±5V and Vb=0V, R is approximately 1.7 kΩ to obtain a hysteresis width of 70 mV.

As a result, the output of the comparator COM is not inverted unless a negative differential signal with a greater amplitude is input to the input terminals INP and INN. In other words, the input threshold of comparator COM has hysteresis. By changing the value of R, the hysteresis width of the input threshold can be adjusted.

3 and 4 show simulation results when VDD=1.8 V and Vb=0.9 V and the resistance values R of the resistors 21p and 21n are changed. 3 and 4 show the hysteresis width HYS when the simulation results are obtained with the circuit configuration shown in FIG. As shown in FIGS. 3 and 4, the hysteresis width HYS can be obtained according to the resistance value R of the resistors 21p and 21n.

FIG. 6 is a simulation result showing the transient response when R=0.5 kΩ. Here, the input potential and the output potential when the received signal received using the coupler 31 is input to the comparator are shown. VI indicates the waveforms of the input potentials VIP and VIN, and VO indicates the waveforms of the output potentials VOP and VON. According to the configuration of this embodiment, the signal component that is positively fed back is added to the input signal of the comparator COM. Therefore, the comparator COM can appropriately compare the levels of the received signals.

In a general hysteresis comparator, the input threshold changes to the opposite polarity of the input signal, but in this embodiment, the signal component of the input signal is added to the same polarity as the input signal as described above. . As a result, the IC chip 13 can obtain an effect (noise immunity) equivalent to that of a hysteresis comparator. The IC chip 13 serving as a receiver compares the received signals from the combiner 31, so that the data can be appropriately restored. The IC chip 13 can appropriately restore data from the small-amplitude pulse signal. Therefore, noise resistance is high, and high-speed data communication is possible.

According to the configuration of this embodiment, it is possible to provide an appropriate hysteresis width even when the IC chip 13 having the comparator COM without hysteresis is used. In other words, resistors 21p and 21n having resistance values corresponding to the required hysteresis width should be placed in the feedback loops 20p and 20n. For example, by changing the resistance value R of a resistor element (chip resistor, lead resistor, etc.) mounted on the substrate 2, a hysteresis comparator having a desired hysteresis width can be realized. Further, the comparator COM is not limited to a comparator without hysteresis, and may be a hysteresis comparator with a small hysteresis width. Even in such a case, the hysteresis width can be widened by providing the resistor 21 in the feedback loop 20 . Therefore, desired hysteresis characteristics can be obtained.

A general-purpose chip can be used as the IC chip 13 . Various IC chips using comparators without hysteresis as receiving circuits are commercially available. Furthermore, such IC chips are also commercially available as chips that have been certified for in-vehicle use, and are readily available. Therefore, even when the easily available IC chip 13 is used as the receiver, the digital signal can be appropriately restored. Therefore, the hysteresis comparator and the receiving circuit can be manufactured with inexpensive commercially available parts. Development and manufacturing of dedicated IC chips are not required, and a low-cost hysteresis comparator and communication circuit can be realized. In addition, the in-vehicle communication circuit can be manufactured at low cost. Even when using the IC chip 13 having a comparator without hysteresis or a comparator with a small hysteresis width, it is possible to realize a hysteresis comparator and a communication circuit 1 capable of obtaining desired characteristics.

In addition, in the case of a single-ended configuration, the coupler 31 is one. A comparator compares the input signal from combiner 31 with a reference voltage. That is, one of the two input signals to the IC chip 13 becomes the received signal from the coupler 31, and the other becomes the reference voltage. The IC chip 13 compares the level of the input signal with the reference voltage and restores the digital signal.

FIG. 7 is a block diagram showing a configuration example of the IC chip 13 as a receiving chip. The IC chip 13 has an equalizer 131 , a receiver circuit 132 , a CDR (clock data recovery) circuit, and an output circuit 134 .

The equalizer 131 is a circuit that adjusts the frequency characteristics of the received signal. For example, the equalizer 131 has a frequency filter for amplifying high frequency components. The receiving circuit 132 has, for example, the hysteresis-free comparator COM shown in FIG. Further, the receiving circuit 132 may have an output stage inverter INV. The receiving circuit 132 restores data by comparing the levels of the two received signals. A CDR (Clock Data Recovery) circuit is a circuit that separates the clock and data of a received signal in which the clock is superimposed on the data. The output circuit 134 has, for example, the two-stage inverter INV shown in FIG.

Even when such an IC chip 13 is used as a receiving chip, the receiving circuit 132 can appropriately restore data from a small-amplitude pulse signal. Therefore, data can be restored using a hysteresis comparator having a desired hysteresis characteristic, enabling high-speed data communication.

Embodiment 2.
This embodiment will be described with reference to FIG. FIG. 8 is a block diagram showing the configuration of the communication circuit 1. As shown in FIG. In this embodiment, feedback loops 20p and 20n are provided with capacitors 22p and 22n. That is, the resistors 21p and 21n in FIG. 2 are replaced with capacitors 22p and 22n, respectively. Furthermore, capacitors 63p and 63n are provided in the transmission line between the coupler 31 and the IC chip 13. FIG. Since the basic configuration other than the capacitors 22p, 22n and the capacitors 63p, 63n is the same as that of the first embodiment, description thereof is omitted.

Capacitors 22p, 22n are placed in feedback loops 20p, 20n, respectively. That is, the input and output of the IC chip 13 are connected via the capacitor 22 .

Capacitors 63 p and 63 n are arranged on the input side of IC chip 13 . That is, the capacitor 63p is arranged between the coupler 31p and the non-inverting input terminal of the IC chip 13. FIG. Capacitor 63 n is arranged between coupler 31 n and the inverting input terminal of IC chip 13 . Capacitors 63p, 63n are provided outside the feedback loops 20p, 20n. The capacitors 63p and 63n transmit the reception signals received by the couplers 31p and 31n to the IC chip 13 . That is, the received signal received by the coupler 31p is input to the non-inverting input terminal of the IC chip 13 via the capacitor 63p. A received signal received by the coupler 31n is input to the inverting input terminal of the IC chip 13 via the capacitor 63n.

In this embodiment, positive feedback by capacitors 22p and 22n is used. That is, the feedback loops 20p and 20n positively feed back the input of the IC chip 13 to the output as in the first embodiment. Therefore, since the communication circuit 1 operates in the same manner as in the first embodiment, the same effects can be obtained.

Let C be the capacitance value of the capacitors 22p and 22n, and C1 be the capacitance value of the capacitors 63p and 63n. Let Vc be the amplitude of the output pulse signal of the coupler 31, and Vfb be the amplitude of the signal positively fed back from the output of the IC chip 13 through the capacitors 22p and 22n. Since electric charge is stored at the input node of the IC chip 13, the input potential Vin of the IC chip 13 is represented by Vc and Vfb as the following equation (2).
C1(Vin-Vc)+C(Vin-Vfb)=0 (2)

Solving equation (2) with Vin yields equation (3).
Vin=Vc/{(1+(C/C1))+Vfb/{(1+(C1/C)) (3)

Therefore, the hysteresis width of the input threshold of the comparator can be adjusted by C1/C. For example, when VDD-=1.8V, C1=1 nF and C=23 pF, v_hys=40 mV. In order to obtain a hysteresis width of 70 mV when VDD is ±5 V and Vb=0 V, C1=1 nF and C=7 pF. Here, the capacitance value C1 is made larger than the capacitance value C. As shown in FIG.

Capacitor 22p and capacitor 22n have the same capacitance value C. As shown in FIG. Capacitor 63p and capacitor 63n have the same capacitance value C1. It is preferable that the capacitance value C1 is larger than the capacitance value C. The ratio (C1/C) between the capacitance value C1 and the capacitance value C is preferably 10-1000. That is, the capacitance value C1 is preferably about 10 to 1000 times the capacitance value C.

In order to determine the input common-mode potential of the comparator, the input of the IC chip 13 is biased to Vb by resistors 53 and 54. FIG. The resistance value r of the resistors 53 and 54 can be determined by the time constant of the charge storage. For example, if you want the time constant to be 1 μsec, r is about 1 kΩ when C1=1 nF.

FIG. 9 is a simulation result showing the transient response when C1=400 pF, C=12 pF, and r=2 kΩ. FIG. 9 shows a waveform diagram when a signal is transmitted at 5 Gps. Here, the waveforms of the input potentials VIP and VON and the output potentials VOP and VON when the received signal received using the coupler 31 is input to the comparator are shown. According to the configuration of this embodiment, the signal component that is positively fed back is added to the input signal of the comparator COM. Therefore, effects similar to those of the first embodiment can be obtained.

Embodiment 3.
Embodiment 3 will be described with reference to FIG. FIG. 10 is a block diagram showing the configuration of the communication circuit 1 according to the third embodiment. In the third embodiment, an IC chip 70 is added to the configuration of the first embodiment. That is, two IC chips 13 and an IC chip 70 are mounted on the substrate 2 . Furthermore, in Embodiment 3, the feedback loops 20p and 20n are provided in the IC chip 70 instead of the IC chip 13. FIG. In this embodiment, by using the IC chip 70, the comparator COM of the IC chip 13 is provided with hysteresis.

A description of the same configuration as in the first embodiment will be omitted as appropriate. For example, the coupler 31 is the same as in the first embodiment. Also, the resistor 57 corresponds to the resistors 51 and 52 and the resistor 58 corresponds to the resistors 53 and 54 . Therefore, description of these configurations is omitted.

Couplers 31 p and 31 n are connected to IC chip 13 . The coupler 31 p is connected to the non-inverting input terminal of the IC chip 13 , and the coupler 31 n is connected to the inverting input terminal of the IC chip 13 . The IC chip 13 has a comparator COM without hysteresis as in the first embodiment. Therefore, the voltage levels of the differential received signals from the couplers 31p and 31n of the IC chip 13 are compared.

A branch node BP is provided between the coupler 31 p and the non-inverting input terminal of the IC chip 13 . A branch node BP is connected to a non-inverting input terminal of the IC chip 70 . A branch node BN is provided between the coupler 31n and the inverting input terminal of the IC chip 13 . A branch node BN is connected to an inverting input terminal of the IC chip 70 . Therefore, the received signals from the couplers 31p and 31n are input to the IC chip 70 . That is, the received signal from coupler 31p is input to IC chip 70 via branch node BP. A received signal from coupler 31n is input to IC chip 70 via branch node BN.

The IC chip 70 has the same configuration as the IC chip 13 in FIG. The IC chip 70 has a comparator COM without hysteresis. Comparator COM of IC chip 70 compares the levels of the two received signals from coupler 31 . The feedback loops 20p and 20n feed back the output of the IC chip 70 to the input. The feedback loop 20p is provided with a resistor 21p, and the feedback loop 20n is provided with a resistor 21n. Therefore, feedback loops 20p and 20n provide positive feedback to the output and input of IC chip 70 through resistors 21p and 21n.

Further, the output of IC chip 70 is connected to the input of IC chip 13 via feedback loops 20p, 20n and branch nodes BP, BN. Therefore, the input signal of the IC chip 13 is added with the signal component that is positively fed back. In this embodiment, the IC chip 70 can be used to give the comparator of the IC chip 13 a hysteresis width. As a result, the IC chip 13 can appropriately restore the digital signal as in the first and second embodiments.

For example, when the IC chip 13 includes a serial-parallel converter (hereinafter referred to as an S/P converter), the output of the comparator COM is serial-parallel converted and then output from the IC chip 13 . In this case, positive feedback cannot be given from the output of the IC chip 13 to the input through the resistors 21p and 21n. In contrast, in this embodiment, a receiver chip having an S/P converter can be used as the IC chip 13 . Even if the IC chip 13 has a serial/parallel converter, the comparator of the IC chip 13 can have hysteresis.

Alternatively, the comparator COM of the IC chip 70 may have a slower data transfer speed than the comparator of the IC chip 13 . Even in such a case, hysteresis can be given to the comparator of IC chip 13 . Alternatively, when the signal propagation delay tpd of the IC chip 13 is slower than the data transfer cycle time of the coupler 31, hysteresis can be appropriately given by using the IC chip 70 with a fast signal propagation delay tpd.

In FIG. 10, the feedback loop 20 is configured using the resistor 21, but the feedback loop may be configured using a capacitor as in the second embodiment. In this case, the IC chip 70 may be provided with the capacitor 22 and the capacitor 63 as shown in FIG.

FIG. 11 is a block diagram showing configurations of the IC chip 13 and the IC chip 70. As shown in FIG. The IC chip 70 has a configuration similar to that of the IC chip 13 in FIG. That is, the equalizer 171, receiver circuit 172, CDR circuit 173, and output circuit 174 of the IC chip 70 are the same as the equalizer 131, receiver circuit 132, CDR circuit 133, and output circuit 134 in FIG. Therefore, the description is omitted. Receive circuit 172 is a comparator without hysteresis as in FIG. IC chip 70 is a receiving chip that does not have an S/P converter.

The IC chip 13 has an S/P converter 135 added to the IC chip 13 of FIG. The receiving circuit 132 is a comparator COM without hysteresis as in FIG. The S/P converter 135 is arranged after the receiving circuit 132 and serial-parallel converts the data restored by the receiving circuit 132 .

For example, the S/P converter 135 has a shift register or the like. The S/P converter 135 sequentially holds data according to the clock signal separated by the CDR circuit 133 and converts it into parallel data. The parallel data converted by the S/P converter 135 is output from the IC chip 13 . Note that FIG. 11 shows only four output terminals OUT1P, OUT1N, OUT2P, and OUT2N because the parallel data is 2 bits for simplification of explanation, but the bit length of the parallel data is 3 bits or more. may be

In this embodiment, the IC chip 13 and the IC chip 70 can be general-purpose semiconductor chips. That is, two IC chips having comparators without hysteresis are prepared and mounted on the substrate 2 . As the IC chip 13 and the IC chip 70, commercially available receiving chips that are easily available can be used, so that the hysteresis comparator and the communication circuit can be realized at low cost. The comparators of the IC chip 13 and the IC chip 70 are not limited to comparators without hysteresis, and may be comparators with a small hysteresis width.

It should be noted that the present invention is not limited to the above embodiments, and can be modified as appropriate without departing from the scope of the invention.

This application claims priority based on Japanese Patent Application No. 2019-82616 filed on April 24, 2019, and the entire disclosure thereof is incorporated herein.

1 communication circuit 2 substrate 13 IC chip 14 buffer 20p feedback loop 20n feedback loop 21p resistor 21n resistor 31p coupler 31n coupler 41p output terminal 41n output terminal 51 resistor 52 resistor 53 resistor 54 resistor 70 IC chip 131 equalizer 132 receiver circuit 133 CDR circuit 134 output circuit 135 S/P converter

Claims (8)

a substrate;
an electromagnetic field coupler provided on the substrate;
a first IC chip mounted on the substrate, the first IC chip having a first comparator for comparing levels of received signals received by the electromagnetic field coupler;
a second IC chip mounted on the substrate, the second IC chip having a second comparator for comparing levels of the received signal;
a feedback loop that positively feeds back the output of the second IC chip to the input. 2. The communication circuit according to claim 1, wherein said first IC chip has a serial/parallel converter located after said first comparator. 3. A communication circuit according to claim 1, wherein a capacitor is provided in said feedback loop. 3. A communication circuit according to claim 1, wherein a resistor is provided in said feedback loop. a substrate;
a first IC chip having a first comparator for comparing levels of two input signals and mounted on the substrate;
a second IC chip mounted on the substrate, the second IC chip having a second comparator for comparing levels of the two input signals;
and a feedback loop that positively feeds back the output of the second IC chip to the input. 6. The hysteresis comparator according to claim 5 , wherein said first IC chip has a serial/parallel converter located after said first comparator. 7. A hysteresis comparator according to claim 5 or 6, wherein a capacitor is provided in said feedback loop. 7. A hysteresis comparator as claimed in claim 5 or 6, wherein a resistor is provided in said feedback loop.

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