JP7299117B2 - power supply - Google Patents

Description

The present invention relates to power supply devices.

For example, Patent Literature 1 describes a power supply device that backs up power supply to a power supply target with an auxiliary power supply when the main power supply fails. The main power supply and the auxiliary power supply are connected in parallel to the power supply object. Power from the main power supply is supplied to the power supply target via the first power supply path. A first switch such as an electromagnetic relay is provided on the first feed path. Also, the power of the auxiliary power supply is supplied to the power supply object via the second power supply path. A second switch, such as a field effect transistor, is provided in the second feed path. The second power supply path is connected to a connection point set on the power supply target side of the first power supply path with respect to the first switch. A controller of a power supply device turns off a first switch provided in a first power supply path and switches off a second power supply when an abnormality of the main power supply is detected based on a current supplied from the main power supply to a power supply target. A second switch provided on the path is turned on.

Japanese Patent Application Laid-Open No. 2008-302825 (Fig. 2)

In the power supply device of Patent Literature 1, there are concerns about the following. For example, when backup is required due to a voltage drop in the main power supply, when the first switch is turned off and the second switch is turned on, the first switch is turned on due to the difference in responsiveness of these switches. A situation can be considered in which the second switch is turned on in the state. At this time, since the electrical resistance on the path from the auxiliary power supply to the main power supply is in a state of being further lowered, there is a risk that a large current will flow from the auxiliary power supply to the main power supply. Therefore, there is concern that it will be difficult to adequately protect the main power supply.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a power supply device capable of switching from a main power supply to an auxiliary power supply at a more appropriate timing.

A power supply device capable of achieving the above object has a signal generating circuit, a first switching circuit, a second switching circuit, a first driving circuit, a second driving circuit, and a delay circuit. The signal generation circuit determines whether the state of power supply from the main power supply to the power supply target is normal or abnormal based on the auxiliary power supply for the main power supply that supplies power to the power supply target and the power supplied to the power supply target. Generates a status signal indicating The first switching circuit opens and closes a first power supply path for supplying power from the main power supply to the power supply target. A second switching circuit is connected to the first power supply path to open and close a second power supply path for supplying power from the auxiliary power supply to the power supply object. The first drive circuit closes the first power supply path through the first switching circuit when the state signal indicates that the power supply state is normal, and closes the first power supply path when the state signal indicates that the power supply state is abnormal. The first feed path is opened through the first switching circuit. The second drive circuit opens the second power supply path through the second switching circuit when the state signal indicates that the power supply state is normal, and opens the second power supply path when the state signal indicates that the power supply state is abnormal. The second feed path is closed through a second switching circuit. The delay circuit is provided on a signal path between the signal generation circuit and the second drive circuit, and delays the state signal indicating an abnormality in the power supply state and outputs the state signal to the second drive circuit.

According to the power supply device described above, when the state signal generated by the signal generation circuit switches from one indicating normality of the state of power supply from the main power supply to the power supply target to one indicating abnormality, the first drive circuit outputs the signal A status signal generated by the generating circuit is provided immediately. On the other hand, the state signal generated by the signal generation circuit is delayed by the delay circuit and supplied to the second drive circuit. Therefore, after the first drive circuit opens the first feed path through the first switching circuit, the second drive circuit closes the second feed path through the second switching circuit. As a result, the power source for the power supply target is switched from the main power source to the auxiliary power source. In addition, since the second power supply path is prevented from being closed while the first power supply path is closed, reverse current flow from the auxiliary power supply to the main power supply is also suppressed. As described above, according to the above power supply device, the power supply for the power supply target can be switched from the main power supply to the auxiliary power supply at a more appropriate timing.

In the power supply device described above, the signal generation circuit may include an analog circuit that generates the state signal based on a comparison result between the voltage of the first power supply path and the first threshold voltage.

According to the above power supply device, the timing of opening and closing the first power supply path and the timing of opening and closing the second power supply path are determined according to the comparison result between the voltage of the first power supply path and the first threshold voltage. is determined. Therefore, when the state signal generated by the signal generating circuit switches from indicating normality of the power supply state from the main power supply to the power supply target to indicating abnormality, the timing of opening the first power supply path can be detected only by the analog circuit. However, it is difficult to delay the timing of closing the second feed path. Therefore, it is preferable to provide a delay circuit in the signal path between the signal generation circuit and the second drive circuit.

In the above power supply device, the signal generating circuit outputs the state signal indicating that the power supply state is normal and the power supply state is abnormal according to the comparison result. It may have a holding circuit that switches between and holds the second state that outputs the state signal indicating that. In this case, the holding circuit switches its own output state from the first state to the second state when the comparison result changes from the state indicating the normality of the power supply state to the state indicating the abnormality, Preferably, the second state is maintained regardless of subsequent changes in the state signal.

According to the above power supply device, the state signal generated by the analog circuit returns to the state indicating normality after changing from the state indicating normality to the state indicating abnormality regarding the state of power supply from the main power supply to the power supply target. In any case, the output state of the holding circuit is held in the second state indicating the previous anomaly. Therefore, immediately after the power supply for the power supply target is switched from the main power supply to the auxiliary power supply, it is suppressed that the auxiliary power supply returns to the main power supply. Therefore, by maintaining the state in which the power supply to the power supply target is switched from the main power supply to the auxiliary power supply, the power supply of the auxiliary power supply to the power supply target is stabilized after the power supply to the power supply target is switched from the main power supply to the auxiliary power supply. supplied.

In the power supply device described above, the delay circuit compares the voltage of the state signal generated by the signal generation circuit with a second threshold voltage, and generates an electrical signal having a voltage level corresponding to the comparison result. A comparison circuit may be provided for outputting the delayed state signal to the second drive circuit.

According to the above power supply device, the state signal generated by the signal generation circuit can be delayed by the propagation delay time of the comparison circuit by passing through the comparison circuit.
In the power supply device described above, the delay circuit may be provided in a stage preceding the comparison circuit, and may have a filter circuit for making the rise or fall of the voltage of the state signal for the comparison circuit more gradual. good.

According to the above power supply device, by adjusting the time constant of the filter circuit, it is possible to adjust the rise time or fall time of the voltage of the state signal for the comparison circuit. Therefore, it is easy to adjust the delay time in the delay circuit.

According to the power supply device of the present invention, it is possible to switch from the main power supply to the auxiliary power supply at a more appropriate timing.

1 is a configuration diagram of a steering device to which a first embodiment of a power supply device is applied; FIG. 1 is a circuit diagram of a first embodiment of a power supply; FIG. 1 is a block diagram of a delay circuit according to a first embodiment; FIG. 4 is a graph showing temporal changes in voltage level when an electrical signal supplied from the output terminal of the latch circuit according to the first embodiment passes through the delay circuit; FIG. 4 is a waveform diagram showing rise timings of electric signals generated by the power supply control circuit in the first embodiment with respect to the first drive circuit and the second drive circuit; FIG. 4 is a timing chart showing the timing at which the FET of the first switching circuit is turned off and the timing at which the FET of the second switching circuit is turned on in the first embodiment; The circuit diagram of 2nd Embodiment of a power supply device. FIG. 10 is a waveform diagram showing the timing of the fall of the electric signal generated by the power supply control circuit in the second embodiment with respect to the first drive circuit and the second drive circuit;

<First embodiment>
A first embodiment in which a power supply device is applied to a steering device will be described below.
As shown in FIG. 1 , the steering device 1 includes a steering mechanism 2 , an assist mechanism 3 , a steering control device 4 and a power supply device 5 .

The steering mechanism 2 has a steering shaft 11 and a turning shaft 12 . A steering wheel 13 is fixed to the first end of the steering shaft 11 . A pinion gear 14 is provided at the second end of the steering shaft 11 . The pinion gear 14 meshes with a rack gear 15 provided on the steering shaft 12 . Rotational motion of the steering shaft 11 is converted into axial reciprocating linear motion of the steered shaft 12 through engagement between the pinion gear 14 and the rack gear 15 . This reciprocating linear motion of the steered shaft 12 is transmitted to the left and right steered wheels 17, 17 via tie rods 16, 16 respectively connected to both ends of the steered shaft 12, whereby the steered wheels 17, 17 are steered. angle is changed.

The assist mechanism 3 has a motor 21 and a speed reducer 22 . A three-phase brushless motor is used as the motor 21 and a worm gear mechanism is used as the reduction gear 22 . A motor 21 is connected to the steering shaft 11 via a reduction gear 22 . The speed reducer 22 reduces the speed of rotation of the motor 21 and transmits the reduced rotational force to the steering shaft 11 . That is, the torque of the motor 21 is transmitted to the steering shaft 11 via the reduction gear 22 as a steering assist force, thereby assisting the driver's steering operation.

The steering control device 4 is connected to a vehicle-mounted main power source 6 via a power source device 5 . A battery, for example, is employed as the main power supply 6 . The steering control device 4 operates by consuming power from the main power source 6 supplied via the power source device 5 . The steering control device 4 controls power supply to the motor 21 according to detection results of various sensors provided in the vehicle. The sensors include, for example, torque sensor 31 and vehicle speed sensor 32 . The torque sensor 31 is provided on the steering shaft 11 and detects the steering torque T. As shown in FIG. A vehicle speed sensor 32 detects a vehicle speed V. FIG. The steering control device 4 calculates a target assist force based on the steering torque T and the vehicle speed V, and supplies electric power to the motor 21 for causing the assist mechanism 3 to generate the target assist force.

<Power supply>
Next, the configuration of the power supply device 5 will be described.
As shown in FIG. 2 , the power supply device 5 includes an auxiliary power supply 40 , a power switching circuit 50 , a voltage detection circuit 60 , a power control circuit 70 , an analog determination circuit 80 and a latch circuit 90 .

The power supply device 5 has a first power supply path L1 for supplying power from the main power supply 6 to the steering control device 4 and a second power supply path L2 for supplying power from the auxiliary power supply 40 to the steering control device 4. have. The second power supply path L2 is connected to the connection point P1 of the first power supply path L1. The power of the auxiliary power supply 40 is supplied to the steering control device 4 via a portion of the second power supply path L2 and the first power supply path L1. As the auxiliary power supply 40, a chargeable/dischargeable power storage device, such as a lithium ion capacitor, is employed.

The power switching circuit 50 has a first switching circuit 51 , a second switching circuit 52 , a first driving circuit 53 and a second driving circuit 54 .
The first switching circuit 51 is provided between the main power supply 6 and the connection point P1 on the first power supply path L1. The first switching circuit 51 has a first FET 55 (field-effect-transistor) and a second FET 56 . The first FET 55 and the second FET 56 are of P-channel type, and are turned on by applying a negative voltage.

A source terminal S of the first FET 55 is connected to the high potential side of the main power supply 6 . A drain terminal D of the first FET 55 is connected to a drain terminal D of the second FET 56 . A source terminal S of the second FET 56 is connected to the steering control device 4 via a first power supply path L1. A gate terminal G of the first FET 55 and a gate terminal G of the second FET 56 are connected to the first drive circuit 53, respectively.

The second switching circuit 52 is provided on the second power feeding path L2. The second switching circuit 52 has a third FET 57 and a fourth FET 58 . The third FET 57 and the fourth FET 58 are N-channel type, and are turned on by applying a positive voltage. A drain terminal D of the third FET 57 is connected to the high potential side of the auxiliary power supply 40 . A source terminal S of the third FET 57 is connected to a source terminal S of the fourth FET 58 . A drain terminal D of the fourth FET 58 is connected to the connection point P1 of the first power supply path L1 via the second power supply path L2. A gate terminal G of the third FET 57 and a gate terminal G of the fourth FET 58 are connected to the second drive circuit 54, respectively.

The power control circuit 70 is a digital circuit that handles digital signals. The power supply control circuit 70 is connected via the voltage detection circuit 60 to the connection point P2 of the first power supply path L1. The connection point P2 is set between the main power supply 6 and the first switching circuit 51 on the first power supply path L1. The power control circuit 70 is also connected to the first drive circuit 53 and the second drive circuit 54 .

The power supply control circuit 70 detects the voltage V2 at the connection point P2 through the voltage detection circuit 60, and detects an abnormality of the main power supply 6 based on the detected voltage V2. The power supply control circuit 70 determines abnormality of the main power supply 6 by comparing the voltage V2 at the connection point P2 and the threshold voltage _Vth1 . The threshold voltage V _th1 is a voltage value that serves as a reference when determining an abnormality such as a voltage drop in the main power supply 6, and is set through experiments or simulations.

The power supply control circuit 70 determines that the main power supply 6 is normal when the voltage V2 at the connection point P2 exceeds the threshold voltage _Vth1 . Further, when the voltage V2 at the connection point P2 does not exceed the threshold voltage _Vth1 for the set time, the power supply control circuit 70 determines that the main power supply 6 has an abnormality. The predetermined period of time is set from the viewpoint of avoiding a temporary drop in voltage V2 caused by noise or the like from being erroneously determined as an abnormality in the main power supply 6 .

Incidentally, the power supply control circuit 70 can control switching of the first switching circuit 51 through the first driving circuit 53 . Also, the power control circuit 70 can control switching of the second switching circuit 52 through the second drive circuit 54 .

The analog decision circuit 80 detects an abnormality in the main power supply 6 separately from the power supply control circuit 70 . The analog decision circuit 80 has a voltage dividing circuit 81 and a comparing circuit 82 .
The voltage dividing circuit 81 has voltage dividing resistors 83 and 84 . These voltage dividing resistors 83 and 84 are connected in series with each other. The end of the voltage dividing resistor 83 opposite to the voltage dividing resistor 84 is connected to the connection point P3 of the first power supply path L1. This connection point P3 is set between the connection point P1 and the steering control device 4 on the first power supply path L1. The end of the voltage dividing resistor 84 opposite to the voltage dividing resistor 83 is connected to the ground. A connection point P4 between the voltage dividing resistors 83 and 84 is connected to the comparison circuit 82 .

The comparison circuit 82 has a comparator 85 and a pull-up resistor 86 . A plus input terminal of the comparator 85 is connected to a connection point P4 between the voltage dividing resistors 83 and 84 in the voltage dividing circuit 81 . Therefore, the voltage V3 at the connection point P3 divided by the voltage dividing circuit 81 is applied to the plus input terminal of the comparator 85 . A negative input terminal of the comparator 85 is set as a reference terminal. The voltage applied to the negative input terminal of comparator 85 is fixed at a predetermined reference voltage. A negative input terminal of the comparator 85 is applied with a threshold voltage _Vth2 as a reference voltage generated by a reference voltage generator (not shown). A positive power supply terminal of the comparator 85 is connected to the reference voltage generator. A negative power supply terminal of the comparator 85 is connected to the ground. An output terminal of the comparator 85 is connected to the latch circuit 90 .

Comparator 85 compares voltage V3 at connection point P3 with threshold voltage _Vth2 , which is a reference voltage, and generates a high-level or low-level control signal SC according to the comparison result. The comparator 85 controls the high level when the voltage V3 at the connection point P3 applied to the positive input terminal is higher than the threshold voltage _Vth2 which is the reference voltage, that is, when the main power supply 6 is normal. Generate a signal SC. The comparator 85 controls the low level when the voltage V3 at the connection point P3 applied to the positive input terminal is smaller than the threshold voltage _Vth2 which is the reference voltage, that is, when the main power supply 6 is abnormal. Generate a signal SC. The control signal SC also functions as a status signal indicating whether the status of the main power supply 6 is normal or abnormal.

A pull-up resistor 86 is provided between the reference voltage generator and the output terminal of the comparator 85 . A pull-up resistor 86 is provided to stabilize the control signal SC output from the output terminal of the comparator 85 .

Latch circuit 90 holds the output state in a reset state or a set state based on two input signals. The latch circuit 90 has a set terminal S and a reset terminal R as input terminals. The latch circuit 90 also has two output terminals Q, ^Q- . A set terminal S is connected to the output terminal of the comparator 85 . A reset terminal R is connected to an output port of the power control circuit 70 . The output terminal Q is connected to the first drive circuit 53 and the second drive circuit 54 respectively. Output terminal ^Q- is not used. However, the relationship between the output terminal Q and the output terminal ^Q- , that is, the logic level is always reversed. The truth table of latch circuit 90 is as shown in Table 1.

ラッチ回路９０は、表１に示される真理値表に従って、セット端子Ｓの論理レベルとリセット端子Ｒの論理レベルとの組み合わせに基づき、出力端子Ｑの出力状態としての論理レベルを保持する。セット端子Ｓの論理レベルおよびリセット端子Ｒの論理レベルの双方がローレベル「０」である場合、出力端子Ｑの論理レベルはローレベル「０」となる。セット端子Ｓの論理レベルがローレベル「０」であって、リセット端子Ｒの論理レベルがハイレベル「１」である場合、出力端子Ｑの論理レベルはハイレベル「１」となる。セット端子Ｓの論理レベルがハイレベル「１」であって、リセット端子Ｒの論理レベルがローレベル「０」である場合、出力端子Ｑの論理レベルはローレベル「０」となる。セット端子Ｓの論理レベルおよびリセット端子Ｒの論理レベルの双方がハイレベル「１」である場合、出力端子Ｑの論理レベルは前回の論理レベルに維持される（Ｎｏ Ｃｈａｎｇｅ）。

Latch circuit 90 holds the logic level as the output state of output terminal Q based on the combination of the logic level of set terminal S and the logic level of reset terminal R according to the truth table shown in Table 1. When both the logic level of the set terminal S and the logic level of the reset terminal R are low level "0", the logic level of the output terminal Q is low level "0". When the logic level of the set terminal S is low level "0" and the logic level of the reset terminal R is high level "1", the logic level of the output terminal Q is high level "1". When the logic level of the set terminal S is high level "1" and the logic level of the reset terminal R is low level "0", the logic level of the output terminal Q is low level "0". When both the logic level of the set terminal S and the logic level of the reset terminal R are high level "1", the logic level of the output terminal Q is maintained at the previous logic level (No Change).

When the logic level of the output terminal of the latch circuit 90 is low, the first drive circuit 53 applies a negative gate voltage Vg1 to the gate terminal G of the first FET 55 and the gate terminal G of the second FET 56, respectively. is applied. Since the first FET 55 and the second FET 56 are turned on, the power of the main power supply 6 is supplied to the steering control device 4 via the first power supply path L1. Further, when the logic level of the output terminal of the latch circuit 90 is low, the second drive circuit 54 applies the gate voltage Vg2 to the gate terminal G of the third FET 57 and the gate terminal G of the fourth FET 58. Do not apply. Since the third FET 57 and the fourth FET 58 are turned off, power from the auxiliary power supply 40 is not supplied to the steering control device 4 . Therefore, when the main power source 6 is normal, the power source for the steering control device 4 is the main power source 6 .

The first drive circuit 53 does not apply the gate voltage Vg1 to the gate terminal G of the first FET 55 and the gate terminal G of the second FET 56 when the logic level of the output terminal of the latch circuit 90 is high. . Since the first FET 55 and the second FET 56 are turned off, power from the main power supply 6 is not supplied to the steering control device 4 . In addition, when the logic level of the output terminal of the latch circuit 90 is high, the second drive circuit 54 has a positive gate for the gate terminal G of the third FET 57 and the gate terminal G of the fourth FET 58 respectively. A voltage Vg2 is applied. Since the third FET 57 and the fourth FET 58 are turned on, the power of the auxiliary power supply 40 is supplied to the steering control device 4 via the second power supply path L2. Therefore, when the main power source 6 is abnormal, the power source for the steering control device 4 is the auxiliary power source 40 .

Note that the analog determination circuit 80 and the latch circuit 90 indicate whether the state of power supply from the main power supply 6 to the steering control device 4 is normal or abnormal based on the power supplied to the steering control device 4 to which power is to be supplied. A signal generation circuit is configured to generate a state signal (here, electrical signal SQ). Also, the latch circuit 90 corresponds to a holding circuit.

<Power supply operation>
Next, the operation of the power supply device 5 will be explained.
Power supply control circuit 70 switches first FET 55 and second FET 56 through first drive circuit 53 when the vehicle power supply is switched from off to on, for example, when an initial check (initial inspection) of the vehicle is performed. While each is turned on, the third FET 57 and the fourth FET 58 are turned off through the second drive circuit 54 . As a result, power from the main power supply 6 is supplied to the steering control device via the first power supply path L1.

When the main power supply 6 is normal, the voltage V2 at the connection point P2 of the first power supply path L1 detected through the voltage detection circuit 60 exceeds the threshold voltage _Vth1 , and the connection point of the first power supply path L1 The voltage V3 of P3 exceeds the threshold voltage V _th2 which is the reference voltage of the comparator 85 .

At this time, the power supply control circuit 70 detects that the voltage V2 at the connection point P2 detected through the voltage detection circuit 60 does not exceed the threshold voltage _Vth1 for a predetermined period of time. judge. The power control circuit 70 also generates a low-level electrical signal SR for the latch circuit 90 . Therefore, the logic level of the reset terminal R of the latch circuit 90 is maintained at the low level "0". Also, since the voltage V3 at the connection point P3 exceeds the threshold voltage _Vth2 , which is the reference voltage of the comparator 85, the comparator 85 generates a high-level control signal SC. Therefore, the logic level of the set terminal S of the latch circuit 90 is maintained at the high level "1". Therefore, the logic level of the output terminal Q of the latch circuit 90 is maintained at the low level "0". The relationship between each terminal of the latch circuit 90 and the logic level is given by the following equation (1).

(S, R, Q) = (1, 0, 0) (1)
After completing the initial check of the vehicle, the power supply control circuit 70 applies a high-level electric signal SR to the reset terminal R of the latch circuit 90 in order to put the latch circuit 90 into a predetermined initial state. As a result, the logic level of the reset terminal R changes from low level "0" to high level "1". In this case, the latch circuit 90 holds the previous output state. Therefore, the logic level of the output terminal Q is maintained at the low level "0". The logic level of each terminal of latch circuit 90 in the initial state is given by the following equation (2).

(S, R, Q) = (1, 1, 0) (2)
As shown in equation (2), the logic level of the output terminal Q of the latch circuit 90 is maintained at the low level "0". Therefore, the first drive circuit 53 turns on the first FET 55 and the second FET 56 respectively. Also, the second drive circuit 54 turns off the third FET 57 and the fourth FET 58, respectively. That is, the power source for the steering control device 4 is switched to the main power source 6 . The power of the main power source 6 is supplied to the steering control device 4 via the first power supply path L1.

Next, the operation of the power supply device 5 when an abnormality occurs in the main power supply 6 will be described.
If, for example, the voltage V3 at the connection point P3 drops to a value lower than the threshold voltage _Vth2 , which is the reference voltage of the comparator 85, due to an abnormality occurring in the main power supply 6, the set terminal S is controlled at a low level. A signal SC is applied. At this time, the logic level of the set terminal S changes from high level "1" to low level "0". Also, the logic level of the output terminal Q changes from low level "0" to high level "1". The logic level of each terminal of the latch circuit 90 at this time is given by the following equation (3).

(S, R, Q) = (0, 1, 1) (3)
As shown in equation (3), the logic level of the output terminal Q of the latch circuit 90 is maintained at the high level "1". Therefore, the first drive circuit 53 turns off the first FET 55 and the second FET 56, respectively, while the second drive circuit 54 turns on the third FET 57 and the fourth FET 58, respectively. That is, the power supply for the steering control device 4 is switched from the main power supply 6 to the auxiliary power supply 40 . The power of the auxiliary power supply 40 is supplied to the steering control device 4 via the second power supply path L2 and the first power supply path L1.

As power is supplied from the auxiliary power supply 40 to the steering control device 4 , the voltage V 3 at the connection point P 3 divided by the voltage dividing circuit 81 is applied to the positive input terminal of the comparator 85 . The voltage V3 at this time shows a normal value based on the voltage of the auxiliary power supply 40. FIG. Therefore, the voltage V3 is higher than the threshold voltage _Vth2 , which is the reference voltage of the comparator 85. FIG. Therefore, the comparator 85 generates a high level control signal SC. Therefore, the logic level of the set terminal S of the latch circuit 90 changes from low level "0" to high level "1". In this case, the latch circuit 90 holds the previous output state. The logic level of each terminal of the latch circuit 90 at this time is given by the following equation (4).

(S, R, Q) = (1, 1, 1) (4)
As shown in equation (4), the logic level of output terminal Q is maintained at the high level "1". Therefore, the first drive circuit 53 keeps the first FET 55 and the second FET 56 off, while the second drive circuit 54 keeps the third FET 57 and the fourth FET 58 on. do. That is, the state in which the power source for the steering control device 4 is switched from the main power source 6 to the auxiliary power source 40 is maintained. Immediately after the power source for the steering control device 4 is switched from the main power source 6 to the auxiliary power source 40, the power source for the steering control device 4 is prevented from returning to the main power source 6 immediately.

By the way, it is possible to omit the latch circuit 90 from the power supply device 5 and employ a configuration in which the switching of the first switching circuit 51 and the switching of the second switching circuit 52 are controlled based on the control signal SC generated by the comparator 85. However, when adopting this configuration, there is concern about the following.

As described above, when the power supply for the steering control device 4 is switched from the main power supply 6 to the auxiliary power supply 40, the comparator 85 generates a high level control signal SC indicating that the main power supply 6 is normal. Based on this control signal SC, the first drive circuit 53 turns on the first FET 55 and the second FET 56 , while the second drive circuit 54 turns off the third FET 57 and the fourth FET 58 . That is, even though the power supply for the steering control device 4 has been switched from the main power source 6 to the auxiliary power source 40 due to the detection of an abnormality in the main power source 6 , the power of the auxiliary power source 40 is supplied to the steering control device 4 . , the power supply for the steering control device 4 may unintentionally return from the auxiliary power supply 40 to the main power supply 6 . In this respect, in the present embodiment, the state of switching to the auxiliary power supply 40 by the latch circuit 90 is maintained.

Next, the operation of the power supply device 5 when the main power supply 6 returns to a normal state while the power supply for the steering control device 4 is switched to the auxiliary power supply 40 will be described.
When the main power supply 6 returns to its normal state, the value of the voltage V3 at the connection point P3 applied to the positive input terminal of the comparator 85 exceeds the threshold voltage _Vth2 , which is the reference voltage of the comparator 85. FIG. At this time, the comparator 85 generates a high level control signal SC. Therefore, the logic level of the set terminal S changes from low level "0" to high level "1". In this case, since the latch circuit 90 holds the previous output state, the logic level of the output terminal Q is maintained at the high level "1". The logic level of each terminal of the latch circuit 90 at this time is given by the following equation (5).

(S, R, Q) = (1, 1, 1) (5)
In addition, the voltage V2 at the connection point P2 detected through the voltage detection circuit 60 exceeds the threshold voltage _Vth1 by restoring the main power supply 6 to its normal state. When the power supply control circuit 70 determines that the main power supply 6 has returned to its normal state, it returns the latch circuit 90 to its initial state. Specifically, it is as follows.

The power control circuit 70 temporarily applies a low-level electrical signal SR to the reset terminal R of the latch circuit 90 . As a result, the logic level of the reset terminal R changes from high level "1" to low level "0", and the logic level of the output terminal Q changes from high level "1" to low level "0". The logic level of each terminal of the latch circuit 90 at this time is given by the following equation (6).

(S, R, Q) = (1, 0, 0) (6)
As shown in equation (6), the logic level of the output terminal Q of the latch circuit 90 is maintained at the low level "0". Therefore, the first drive circuit 53 turns on the first FET 55 and the second FET 56, respectively, while the second drive circuit 54 turns off the third FET 57 and the fourth FET 58, respectively. That is, the power supply for the steering control device 4 is restored from the auxiliary power supply 40 to the main power supply 6 . The power of the main power source 6 is supplied to the steering control device 4 via the first power supply path L1.

Next, the power control circuit 70 applies a high level electric signal SR to the reset terminal R of the latch circuit 90 . As a result, the logic level of the reset terminal R changes from low level "0" to high level "1". In this case, since the latch circuit 90 holds the previous output state, the logic level of the output terminal Q is maintained at the low level "0". That is, the latch circuit 90 returns to its initial state. The logic level of each terminal of the latch circuit 90 at this time is given by the following equation (7).

(S, R, Q) = (1, 1, 0) (7)
As shown in equation (7), the logic level of the output terminal Q of the latch circuit 90 is maintained at the low level "0". Therefore, the power source for the steering control device 4 is kept switched to the main power source 6 .

In the power supply device 5 configured in this manner, the following concerns may arise.
That is, first drive circuit 53 and second drive circuit 54 generate gate voltages Vg1 and Vg2 according to the logic level of output terminal Q of latch circuit 90 . That is, the switching timing of the first switching circuit 51 and the second switching circuit 52 is determined by the logic level of the output terminal Q of the latch circuit 90 . For example, when the voltage V3 at the connection point P3 detected through the voltage detection circuit 60 drops to a value lower than the threshold voltage _Vth2 , which is the reference voltage of the comparator 85, due to an abnormality in the main power supply 6, the latch circuit The logic level of the output terminal Q of 90 changes from low level "0" to high level "1". At this time, due to variations in circuit operations of the first drive circuit 53 and the second drive circuit 54, the first FET 55 and the second FET 56 in the first switching circuit 51 are turned off. There is concern that the third FET 57 and the fourth FET 58 in the switching circuit 52 of No. 2 are turned on. When the third FET 57 and the fourth FET 58 are turned on while the first FET 55 and the second FET 56 are turned on, the electrical resistance on the path from the auxiliary power supply 40 to the main power supply 6 is further reduced. Because of this state, a larger current may flow from the auxiliary power supply 40 to the main power supply 6 . Therefore, there is a concern that proper protection of the main power supply 6 will become difficult.

Therefore, in the present embodiment, the following configuration is adopted as the power supply device 5 in order to eliminate such concern.
The power supply device 5 has a delay circuit 100, as indicated by a two-dot chain line in FIG. The delay circuit 100 is provided on the signal path between the output terminal Q of the latch circuit 90 and the second drive circuit 54 . The delay circuit 100 delays the electric signal SQ from the output terminal Q of the latch circuit 90 and outputs it to the second drive circuit 54 . However, the voltage level of the electric signal SQ corresponds to the logic level of the output terminal Q. FIG.

As shown in FIG. 3, delay circuit 100 has filter circuit 101 and comparison circuit 102 .
As filter circuit 101, for example, a low-pass filter having an RC circuit made up of resistors and capacitors and an operational amplifier is employed. The filter circuit 101 is for making the rise or fall of the voltage VQ of the electrical signal SQ as an output to the comparison circuit 102 in the subsequent stage more gradual. The rise time or fall time of the output voltage of the filter circuit 101 corresponds to the time constant determined by the resistance value of the RC circuit and the capacity of the capacitor.

As shown in the graph of FIG. 4, when the logic level of the output terminal Q of the latch circuit 90 switches from low level "0" to high level "1" (time T1), the output voltage of the filter circuit 101, in other words, The value of the voltage VQ of the electric signal SQ that has passed through the filter circuit 101 gradually increases over time according to the time constant of the filter circuit 101 .

As shown in FIG. 3, the comparison circuit 102 compares the voltage VQ of the electric signal SQ that has passed through the filter circuit 101 with a threshold voltage VQ _th which is a reference voltage, and depending on the result of the comparison, it is at a high level or a low level. to generate an electric signal SQd of . Incidentally, the output of the comparison circuit 102 corresponding to the input is delayed by the propagation delay time, which is the response time for switching between the high level and the low level of the output.

As shown in the graph of FIG. 4, when the value of the voltage VQ of the electrical signal SQ that has passed through the filter circuit 101 exceeds the threshold voltage _VQth (time T2), the comparison circuit 102 delays the high-level electrical signal. is generated as an electrical signal SQd. Further, when the value of the voltage VQ of the electric signal SQ that has passed through the filter circuit 101 does not exceed the threshold voltage _VQth , the comparison circuit 102 generates a low-level electric signal as the delayed electric signal SQd.

From time T1 when the logic level of the output terminal Q of the latch circuit 90 switches from the low level "0" to the high level "1", the value of the voltage VQ of the electric signal SQ that has passed through the filter circuit 101 exceeds the threshold voltage _VQth . The delay time ΔT of the electric signal SQ by the delay circuit 100 is the time up to the time T2. That is, delay time ΔT is determined by the time constant of filter circuit 101 and the value of threshold voltage VQ _th which is the reference voltage of comparator circuit 102 . Therefore, by adjusting the time constant of filter circuit 101 and the value of threshold voltage VQ _th of comparison circuit 102, delay time ΔT can be adjusted.

<Action of delay circuit>
Next, the effect of providing the delay circuit 100 in the power supply device 5 will be described.
For example, when the voltage V3 at the connection point P3 drops to a value lower than the threshold voltage _Vth2 , which is the reference voltage of the comparator 85, due to an abnormality in the main power supply 6, the logic level of the output terminal Q of the latch circuit 90 is changed to It changes from low level "0" to high level "1". Accordingly, a high-level electrical signal SQ is output from the output terminal Q of the latch circuit 90 .

As shown in the waveform diagram of FIG. 5, the first drive circuit 53 is immediately supplied with the high-level electrical signal SQ from the output terminal Q without delay (time T11). When the high-level electric signal SQ is taken in, the first drive circuit 53 assumes that the logic level of the output terminal Q of the latch circuit 90 is high, and the gate terminal G of the first FET 55 and the gate terminal G of the second FET 56 Application of the gate voltage Vg1 to the gate terminal G is stopped. Since the first FET 55 and the second FET 56 are turned off, power from the main power supply 6 is not supplied to the steering control device 4 .

As shown in the waveform diagram of FIG. 5, the second drive circuit 54 is supplied with a high-level electric signal SQd obtained by delaying the high-level electric signal SQ by a delay time ΔT through a delay circuit 100. (Time T12). When the high-level electric signal SQd is taken in, the second drive circuit 54 assumes that the logic level of the output terminal Q of the latch circuit 90 is high, and the gate terminal G of the third FET 57 and the gate terminal G of the fourth FET 58 A positive gate voltage Vg2 is applied to the gate terminals G, respectively. Since the third FET 57 and the fourth FET 58 are turned on, the power of the auxiliary power supply 40 is supplied to the steering control device 4 via the second power supply path L2.

At the timing when the first drive circuit 53 stops applying the gate voltage Vg1 to the first FET 55 and the second FET 56, the second drive circuit 54 applies the gate voltage Vg2 to the third FET 57 and the fourth FET 58. is delayed by the delay time ΔT of the delay circuit 100 . Therefore, as shown in the timing chart of FIG. 6, the timing (time T22) at which the third FET 57 and the fourth FET 58 are turned on with respect to the timing (time T21) at which the first FET 55 and the second FET 56 are turned off. is delayed by the delay time ΔT.

The delay time .DELTA.T takes into account variations in the circuit operations of the first drive circuit 53 and the second drive circuit 54, etc., so that the third FET 57 and the fourth FET 57 are delayed before the first FET 55 and the second FET 56 are turned off. is set based on the viewpoint of avoiding that the FET 58 of is turned on. Therefore, when the power supply for the steering control device 4 is switched from the main power supply 6 to the auxiliary power supply 40 due to an abnormality in the main power supply 6, the third FET 57 and Turning on of the fourth FET 58 is suppressed. Since the first FET 55 and the second FET 56 are already turned off when the third FET 57 and the fourth FET 58 are turned on, no current flows back from the auxiliary power supply 40 to the main power supply 6 . Therefore, it is possible to protect the main power supply 6 .

<Effects of the first embodiment>
Therefore, according to the first embodiment, the following effects can be obtained.
(1) When the power supply for the steering control device 4 is switched from the main power supply 6 to the auxiliary power supply 40, the high level electric signal SQ from the latch circuit 90 is immediately supplied to the first drive circuit 53. On the other hand, the electric signal SQd obtained by delaying the electric signal SQ from the latch circuit 90 by the delay time ΔT by the delay circuit 100 is supplied to the second drive circuit 54 . Therefore, after the first FET 55 and the second FET 56 are turned off, the third FET 57 and the fourth FET 58 are turned on. That is, in a state where the first power supply path L1 between the main power supply 6 and the steering control device 4 to which power is supplied is cut off, the second power supply path L2 between the auxiliary power supply 40 and the steering control device 4 is Connected. Therefore, it is possible to protect the main power supply 6 by suppressing the reverse flow of current from the auxiliary power supply 40 to the main power supply 6 . Thus, according to the power supply device 5, the power supply for the steering control device 4 can be switched from the main power supply 6 to the auxiliary power supply 40 at a more appropriate timing.

(2) Delay time ΔT can be adjusted by adjusting the constant of filter circuit 101 in delay circuit 100 and the value of threshold voltage VQ _th which is the reference voltage of comparison circuit 102 . Therefore, the timing of turning off the first FET 55 and the second FET 56 and the timing of turning on the third FET 57 and the fourth FET 58 can be controlled by adjusting the delay time ΔT.

(3) The delay circuit 100 has a filter circuit 101 . By adjusting the time constant of the filter circuit 101, the rising slope of the voltage level of the electric signal SQ output from the filter circuit 101 to the comparison circuit 102 can be adjusted. Therefore, it is easy to adjust the delay time ΔT of the delay circuit 100 .

(4) The delay circuit 100 has a comparison circuit 102 . The comparison circuit 102 generates a high-level electric signal SQd when the voltage of the electric signal SQ that has passed through the filter circuit 101 exceeds the threshold voltage _VQth , which is the reference voltage. That is, the high-level electrical signal SQ from the latch circuit 90 can be delayed while maintaining its voltage level.

(5) When the power source for the steering control device 4 is switched from the main power source 6 to the auxiliary power source 40, the voltage of the first power supply path L1 returns to the normal value as the power supply from the auxiliary power source 40 to the steering control device 4 starts. Even in this case, the latch circuit 90 maintains the state in which the power supply for the steering control device 4 is switched to the auxiliary power supply 40 . Therefore, immediately after the power source for the steering control device 4 is switched from the main power source 6 to the auxiliary power source 40, it is avoided to return to the main power source 6 immediately. Therefore, the electric power of the auxiliary power supply 40 is stably supplied to the steering control device 4 .

(6) When the power control circuit 70 determines that the main power supply 6 has returned to a normal state, the power control circuit 70 latches the electric signal SR for returning the power supply for the steering control device 4 from the auxiliary power supply 40 to the main power supply 6. 90 to the reset terminal R. The power supply for the steering control device 4 is switched from the auxiliary power supply 40 to the main power supply 6 by inverting the logic level of the output terminal Q of the latch circuit 90 . Since the power supply control circuit 70 appropriately controls the logic level of the output terminal Q of the latch circuit 90 , the power supply for the steering control device 4 can be appropriately restored from the auxiliary power supply 40 to the main power supply 6 . Further, since the power supply control circuit 70 more accurately determines whether the main power supply 6 is restored to the normal state, the reliability of returning the power supply to the steering control device 4 to the main power supply 6 can be ensured.

(7) Unlike a digital circuit, the analog determination circuit 80 directly determines the voltage of the first power supply path L1 to the steering control device 4. Therefore, even if power supply to the steering control device 4 becomes difficult due to, for example, an abnormality in the first switching circuit 51 provided in the first power supply path L1, the steering control device 4 It is possible to switch the power supply for the from the main power supply 6 to the auxiliary power supply 40 .

(8) The analog determination circuit 80 performs determination processing of the voltage V3 without digitizing the voltage V3 at the connection point P3. Therefore, the analog determination circuit 80 can quickly switch the power supply for the steering control device 4 between the main power supply 6 and the auxiliary power supply 40 by the amount that the voltage V3 is not digitized.

<Second Embodiment>
Next, a second embodiment of the power supply device will be described. The present embodiment differs from the first embodiment in that power supply device 5 employs a configuration in which analog determination circuit 80 and latch circuit 90 shown in FIG. 2 are omitted.

As shown in FIG. 7, the power supply device 5 includes a first signal path L3 for supplying electrical signals from the power control circuit 70 to the first drive circuit 53, and a signal path L3 from the power control circuit 70 to the second drive circuit 54. It has a second signal path L4 for providing an electrical signal to. The second signal path L4 is connected to the connection point P5 of the first signal path L3.

A delay circuit 200 is provided in the second signal path L4. Delay circuit 200 has filter circuit 101 and comparison circuit 102, like delay circuit 100 shown in FIG. Delay circuit 200 delays control signal SC, which is an electrical signal generated by power supply control circuit 70 , and outputs the delayed control signal SCd to second drive circuit 54 .

When the voltage V2 at the connection point P2 detected through the voltage detection circuit 60 exceeds the threshold voltage _Vth1 , the power supply control circuit 70 determines that the main power supply 6 is normal. Further, when the voltage V2 at the connection point P2 does not exceed the threshold voltage _Vth1 for the set time, the power supply control circuit 70 determines that the main power supply 6 has an abnormality. The predetermined period of time is set from the viewpoint of avoiding a temporary drop in voltage V2 caused by noise or the like from being erroneously determined as an abnormality in the main power supply 6 .

The power supply control circuit 70 switches the power supply for the steering control device 4 between the main power supply 6 and the auxiliary power supply 40 according to the result of the abnormality determination of the main power supply 6 . The power supply control circuit 70 generates a high-level control signal SC when it is determined that the main power supply 6 is normal. The power supply control circuit 70 generates a low-level control signal SC when it is determined that the main power supply 6 is abnormal.

Unlike the first embodiment, the first drive circuit 53 is configured to operate when a high-level control signal SC is supplied from the power supply control circuit 70 to the gate terminal G of the first FET 55 and the gate terminal of the second FET 56 . A negative gate voltage Vg1 is applied to G respectively. Since the first FET 55 and the second FET 56 are turned on, the power of the main power supply 6 is supplied to the steering control device 4 via the first power supply path L1. Unlike the first embodiment, the second drive circuit 54 is configured such that when a high-level control signal SC is supplied from the power supply control circuit 70, the gate terminal G of the third FET 57 and the gate terminal of the fourth FET 58 Gate voltage Vg2 is not applied to G. Since the third FET 57 and the fourth FET 58 are turned off, power from the auxiliary power supply 40 is not supplied to the steering control device 4 . Therefore, when the main power source 6 is normal, the power source for the steering control device 4 is the main power source 6 .

In addition, unlike the first embodiment, the first drive circuit 53, when a low-level control signal SC is supplied from the power supply control circuit 70, causes the gate terminal G of the first FET 55 and the second FET 56 to The gate voltage Vg1 is not applied to the gate terminal G. Since the first FET 55 and the second FET 56 are turned off, power from the main power supply 6 is not supplied to the steering control device 4 . Unlike the first embodiment, the second drive circuit 54 receives the low-level control signal SC from the power supply control circuit 70, the gate terminal G of the third FET 57 and the gate terminal of the fourth FET 58 A positive gate voltage Vg2 is applied to G respectively. Since the third FET 57 and the fourth FET 58 are turned on, the power of the auxiliary power supply 40 is supplied to the steering control device 4 via the second power supply path L2. Therefore, when the main power source 6 is abnormal, the power source for the steering control device 4 is the auxiliary power source 40 .

The power supply control circuit 70 outputs a status signal (here, Then, it corresponds to a signal generation circuit that generates a control signal SC).

<Action of Second Embodiment>
Next, the operation of the second embodiment will be explained.
The power supply control circuit 70 generates a low-level control signal SC when the voltage V2 at the connection point P2 detected through the voltage detection circuit 60 due to an abnormality in the main power supply 6, for example, falls below the threshold voltage _Vth1 . do.

As shown in the waveform diagram of FIG. 8, the low-level control signal SC generated by the power supply control circuit 70 is immediately supplied to the first drive circuit 53 without delay (time T31). The first drive circuit 53 stops applying the gate voltage Vg1 to the gate terminal G of the first FET 55 and the gate terminal G of the second FET 56 when the low level control signal SC is taken. Since the first FET 55 and the second FET 56 are turned off, power from the main power supply 6 is not supplied to the steering control device 4 .

As shown in the waveform diagram of FIG. 8, the second driving circuit 54 is supplied with a low-level control signal SCd obtained by delaying the low-level control signal SC by a delay time ΔT through a delay circuit 100. (Time T32). The second drive circuit 54 applies a positive gate voltage Vg2 to the gate terminal G of the third FET 57 and the gate terminal G of the fourth FET 58, respectively, when the low level control signal SCd is taken. Since the third FET 57 and the fourth FET 58 are turned on, the power of the auxiliary power supply 40 is supplied to the steering control device 4 via the second power supply path L2.

As shown in the waveform diagram of FIG. 6, the second drive circuit 53 stops applying the gate voltage Vg1 to the first FET 55 and the second FET 56 (time T21). The timing (time T22) at which the circuit 54 applies the gate voltage Vg2 to the third FET 57 and the fourth FET 58 is delayed by the delay time ΔT of the delay circuit 100 . That is, the timing at which the third FET 57 and the fourth FET 58 are turned on is delayed by the delay time ΔT with respect to the timing at which the first FET 55 and the second FET 56 are turned off.

Therefore, when the power supply for the steering control device 4 is switched from the main power supply 6 to the auxiliary power supply 40 due to an abnormality in the main power supply 6, the third FET 57 and Turning on of the fourth FET 58 is suppressed.

<Effects of Second Embodiment>
Therefore, according to the second embodiment, in addition to the effects (1) to (4) of the first embodiment, the following effects can be obtained.

(9) Power supply device 5 employs a configuration in which analog determination circuit 80 and latch circuit 90 shown in FIG. 2 are omitted. Therefore, the configuration of the power supply device 5 can be further simplified.

<Other embodiments>
The first and second embodiments may be modified as follows.
- In the first embodiment, the specific configurations of the voltage dividing circuit 81 and the comparing circuit 82 may be changed as appropriate. For example, a configuration in which pull-up resistor 86 is omitted from comparison circuit 82 may be employed.

- In the first embodiment, a configuration in which the voltage dividing circuit 81 is omitted may be adopted as the analog determination circuit 80 . In this case, the comparator 85 of the comparison circuit 82 is provided with withstand voltage performance to the extent that it can withstand the voltage V3 at the connection point P3 that is not voltage-divided. Also, the threshold voltage Vth2, which is the reference voltage of the comparator 85, is appropriately adjusted according to the voltage applied to the positive input terminal of the comparator 85. FIG.

- In the first embodiment, the connection point P3 to which the voltage dividing resistor 83 of the analog determination circuit 80 is connected is set between the main power supply 6 and the first switching circuit 51 in the first power supply path L1. may In this case, a configuration in which the latch circuit 90 is omitted from the power supply device 5 may be adopted. This is because after the power source for the steering control device 4 is switched from the main power source 6 to the auxiliary power source 40 , the power source for the steering control device 4 is supplemented because the power of the auxiliary power source 40 is supplied to the steering control device 4 . This is because the power supply 40 will not unintentionally return to the main power supply 6 .

- In the first embodiment, the comparison circuit 82 may determine abnormality of the main power supply 6 by comparing the value of the current at the connection point P3 and the threshold current, for example.
- In the first embodiment, the power supply control circuit 70 may have a configuration in which the function of determining abnormality of the main power supply 6 based on the voltage V2 at the connection point P2 detected through the voltage detection circuit 60 is omitted. . In this case, the power supply control circuit 70 can recognize whether the main power supply 6 is normal or abnormal based on the logic level of the output terminal of the latch circuit 90, for example.

- In the first and second embodiments, the first FET 55 and the second FET 56 may be of the N-channel type, and the third FET 57 and the fourth FET 58 of the P-channel type.

• Mechanical switches may be employed as the first and second FETs 55 and 56 and the third and fourth FETs 57 and 58 in the first and second embodiments.

- In the first and second embodiments, the steering device 1 to which the power supply device 5 is applied may be an electric power steering device of the type in which the torque of the motor 21 is applied to the steered shaft 12 . Moreover, the steering device 1 to which the power supply device 5 is applied may be a steer-by-wire type steering device.

- In the first and second embodiments, the power supply target of the power supply device 5 is not limited to the steering control device 4 . The object to which the power supply device 5 supplies power may be a control device for an airbag device or a control device for a brake device. Further, the object to which the power supply device 5 supplies power may be a control device for a drive motor in an automatic guided vehicle or an electric vehicle.

4 Steering control device (to be fed) 5 Power source device 6 Main power source 40 Auxiliary power source 50 Power source switching circuit 51 First switching circuit 52 Second switching circuit 53 Second 1 drive circuit 54 second drive circuit 70 power supply control circuit (signal generation circuit) 80 analog judgment circuit (analog circuit) constituting the signal generation circuit 90 latch circuit (analog circuit) constituting the signal generation circuit holding circuit), 100, 200... delay circuit, L1... first feed path, L2... second feed path, SC... control signal (state signal), SQ... electric signal (state signal).

Claims (4)

an auxiliary power source for a main power source that supplies power to a power supply target;
a signal generation circuit that generates a status signal indicating whether the state of power supply from the main power supply to the power supply target is normal or abnormal based on the power supplied to the power supply target;
a first switching circuit that opens and closes a first power supply path for supplying power from the main power supply to the power supply target;
a second switching circuit that is connected to the first power supply path and opens and closes a second power supply path for supplying power from the auxiliary power supply to the power supply target;
When the state signal indicates that the power supply state is normal, the first power supply path is closed through the first switching circuit, and when the state signal indicates that the power supply state is abnormal, the first power supply path is closed through the first switching circuit. a first drive circuit that opens the first power feed path;
When the state signal indicates that the power supply state is normal, the second power supply path is opened through the second switching circuit, and when the state signal indicates that the power supply state is abnormal, the power supply path is opened through the second switching circuit. a second drive circuit for closing the second feed path;
a delay circuit provided in a signal path between the signal generation circuit and the second drive circuit for delaying the state signal indicating an abnormality in the power supply state and outputting the state signal to the second drive circuit. and
The delay circuit compares the voltage of the state signal generated by the signal generation circuit with a second threshold voltage, and outputs an electric signal having a voltage level corresponding to the comparison result to the delayed state signal. and a comparison circuit for outputting to the second drive circuit . 2. The power supply device according to claim 1, wherein said signal generation circuit has an analog circuit for generating said state signal based on a comparison result between the voltage of said first power supply path and a first threshold voltage. The signal generating circuit outputs a first state signal indicating that the power supply state is normal and the state signal indicating that the power supply state is abnormal according to the comparison result. having a holding circuit that switches between and holds the output second state;
The holding circuit switches its own output state from the first state to the second state when the comparison result changes from a state indicating normality of the power supply state to a state indicating abnormality of the power supply state, and thereafter switches the output state from the first state to the second state. 3. The power supply device according to claim 2, wherein said second state is maintained regardless of changes in the state signal. Claims 1 to 3 , wherein said delay circuit is provided in the preceding stage of said comparison circuit and has a filter circuit for slowing the rise or fall of the voltage of said state signal for said comparison circuit. The power supply device according to any one of .

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