JP7297147B2 - Semiconductor power module and power converter - Google Patents

Description

The present disclosure relates to semiconductor power modules and power converters.

In recent years, application of wide bandgap semiconductors such as SiC (Silicon Carbide) and GaN (Gallium Nitride) to power converters has been promoted. A power conversion device using these may increase the switching speed or carrier frequency by ten times or more compared to Si (silicon). While higher carrier frequencies allow passive components to be smaller, they also lead to a significant increase in noise levels.

2. Description of the Related Art It is known that in a power conversion device configured using a semiconductor power module, the switching operation of semiconductor elements, potential fluctuations in a motor driven by the power conversion device, and the like are sources of noise. Since such noise causes malfunction of various electronic devices, noise is suppressed by inserting a noise filter.

For example, Japanese Patent Laying-Open No. 2013-99001 (Patent Document 1) describes a switching element device capable of suppressing noise by improving imbalance between parasitic inductance and capacitance on the positive electrode bus bar side and the negative electrode bus bar side. ing.

Japanese Unexamined Patent Application Publication No. 2013-99001

In the switching element device disclosed in Japanese Patent Laying-Open No. 2013-99001 (Patent Document 1), the conductors arranged between the positive electrode bus bar and the negative electrode bus bar are arranged with a space therebetween. Therefore, the capacitance generated between each bus bar and the conductor is smaller than the capacitance generated between the positive electrode or the negative electrode and the heat radiation conductor within the semiconductor power module. Therefore, there is a problem that the noise suppressing effect is smaller than that of the noise countermeasures taken inside the module, and the size of the semiconductor power module is increased when the same effect is obtained.

An object of the present disclosure is to disclose a small-sized semiconductor power module and a power conversion device capable of obtaining a noise suppression effect in order to solve the above problems.

The present disclosure relates to semiconductor power modules. A semiconductor power module includes a grounded heat dissipation conductor, an insulating layer formed on the heat dissipation conductor, a positive electrode plate and a negative electrode plate provided on the insulating layer, and a positive electrode plate and a negative electrode plate, respectively. an upper arm semiconductor element arranged on the positive electrode plate and connected to the positive electrode plate and the positive electrode; a lower arm semiconductor element arranged on the negative electrode plate; and a lower arm semiconductor A first connection conductor for connecting the negative electrode of the element and the negative electrode plate, and a second connection conductor for connecting the positive electrode of the lower arm semiconductor element and the negative electrode of the upper arm semiconductor element are provided. Lp indicates the effective inductance in the current path from the positive electrode terminal to the positive electrode of the upper arm semiconductor element, and Ln indicates the effective inductance in the current path from the negative electrode terminal to the negative electrode of the lower arm semiconductor element via the negative electrode plate and the first connection conductor. where 0.9 < (Lp*Cp)/(Ln*Cn)<1/0.9.

The semiconductor power module and the power converter disclosed in the present disclosure improve the imbalance between the effective inductance and the capacitance inside the semiconductor power module on the positive terminal side and the negative terminal side, and cancel out the noise current flowing into the heat dissipation conductor. Therefore, the noise current flowing out to the outside can be suppressed.

1 is a schematic cross-sectional view showing the configuration of a semiconductor power module according to Embodiment 1; FIG. FIG. 2 is a bird's-eye view of the semiconductor power module of FIG. 1; 3 is a circuit diagram in which a diode is adopted as an upper arm semiconductor element 7; FIG. 2 is a circuit diagram that employs a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) as an upper arm semiconductor element 7. FIG. It is a half-bridge circuit to show the noise reduction effect of the semiconductor power module of the first embodiment. FIG. 4 is a waveform diagram showing a turn-on operation under the condition that parasitic inductance and capacitance are Lp=10 nH, Ln=10 nH, Cp=50 pF, and Cn=50 pF; FIG. 4 is a waveform diagram showing a turn-on operation under the conditions that parasitic inductance and capacitance are Lp=5 nH, Ln=10 nH, Cp=50 pF, and Cn=50 pF; FIG. 4 is a waveform diagram showing a turn-on operation under the conditions that the parasitic inductance and capacitance are Lp=5 nH, Ln=10 nH, Cp=50 pF, and Cn=25 pF; FIG. 4 is a waveform diagram showing a turn-on operation under the conditions that the parasitic inductance and capacitance are Lp=5 nH, Ln=10 nH, Cp=100 pF, and Cn=50 pF; FIG. 10 is a diagram showing and comparing noise levels when Lp is changed; It is a trapezoidal wave for explaining the frequency spectrum. 4 is a log-log graph showing an envelope function Envelope(f) and a boundary function Bounds(f) with respect to frequency f. 4 is a graph showing boundary functions Bounds(f) for two types of trapezoidal waves; FIG. 3 is a schematic cross-sectional view showing a specific first configuration example of a lower arm semiconductor element 8; FIG. 5 is a schematic cross-sectional view showing a second specific configuration example of a lower arm semiconductor element 8; FIG. 11 is a schematic cross-sectional view showing a third specific configuration example of a lower arm semiconductor element 8; FIG. 11 is a schematic cross-sectional view showing a fourth specific configuration example of a lower arm semiconductor element 8; It is a structural example of the semiconductor power module before adjusting the ratio of (Lp×Cp) and (Ln×Cn). It is a figure which shows the 1st structural example which increases Lp. It is a figure which shows the 2nd structural example which increases Lp. FIG. 11 is a diagram showing a third configuration example for increasing Lp; FIG. 11 is a diagram showing a fourth configuration example for increasing Lp; FIG. 11 is a diagram showing a fifth configuration example for increasing Lp; FIG. 11 is a diagram showing a sixth configuration example for increasing Lp; FIG. 12 is a diagram showing a seventh configuration example for increasing Lp; FIG. 20 is a diagram showing an eighth configuration example for reducing Ln; FIG. 22 is a diagram showing a ninth configuration example for reducing Cn; FIG. 22 is a diagram showing a tenth configuration example for increasing Cp; FIG. 21 is a diagram showing an eleventh configuration example in which Cn is decreased and Cp is increased; A twelfth configuration example in which Cn is decreased and Cp is increased is shown. FIG. 11 is a circuit diagram showing the configuration of a semiconductor power module according to Embodiment 5; FIG. 10 is a diagram comparing noise levels when capacitance Cac is changed under the conditions of Lp=Ln=10 nH and Cp=Cn=50 pF; FIG. 5 is a diagram comparing noise levels when Cac is varied under the conditions of Lp=9 nH, Ln=10 nH, and Cp=Cn=50 pF. BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram which shows the structure of the power conversion system to which the power converter device of this Embodiment is applied.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated in principle.

Embodiment 1.
A semiconductor power module according to the first embodiment will be described below with reference to FIGS. 1 to 9. FIG.

FIG. 1 is a schematic cross-sectional view showing the configuration of a semiconductor power module according to Embodiment 1. FIG. 2 is a bird's-eye view of the semiconductor power module of FIG. 1. FIG.

1 and 2, a semiconductor power module 1 includes a heat dissipation conductor 2, an insulating layer 3, a positive electrode plate 4, a negative electrode plate 5, a positive electrode terminal 41, a negative electrode terminal 51, an upper arm semiconductor It comprises an element 7 , a lower arm semiconductor element 8 , a connection conductor 11 , a connection conductor 12 , a connection conductor 13 and a sealing material 15 . However, in FIG. 2, the sealing member 15 is omitted for easy understanding.

The insulating layer 3 is formed on the heat radiation conductor 2 . A positive electrode plate 4 and a negative electrode plate 5 are provided on the insulating layer 3 . The positive electrode terminal 41 and the negative electrode terminal 51 are electrically connected to the positive electrode plate 4 and the negative electrode plate 5, respectively. The upper arm semiconductor element 7 is arranged on the positive electrode plate 4 . The upper arm semiconductor element 7 has a positive electrode 7p formed on the back surface and a negative electrode 7n formed on the front surface. The lower arm semiconductor element 8 has a positive electrode 8p and a negative electrode 8n both formed on its surface. A positive electrode 7 p of the upper arm semiconductor element 7 is electrically connected to the positive electrode plate 4 . A lower arm semiconductor element 8 is arranged on the negative electrode plate 5 . The connection conductor 11 connects the negative electrode 8n of the lower arm semiconductor element 8 and the negative electrode plate 5 . Connection conductor 12 connects negative electrode 7n of upper arm semiconductor element 7 and positive electrode 8p of lower arm semiconductor element 8 . Connection conductor 13 connects input/output terminal 61 and negative electrode 7 n of upper arm semiconductor element 7 . Incidentally, the connection conductor 13 may connect the input/output terminal 61 and the positive electrode 8p of the lower arm semiconductor element 8 .

When the semiconductor element is a diode, the anode corresponds to the negative electrode and the cathode corresponds to the positive electrode. When the semiconductor element is a P-channel MOSFET, the drain corresponds to the negative electrode and the source corresponds to the positive electrode. , the drain corresponds to the positive electrode and the source corresponds to the negative electrode.

The positive electrode plate 4 and the negative electrode plate 5 face the heat radiation conductor 2 with the insulating layer 3 interposed therebetween. Therefore, a capacitance Cp is formed between the positive electrode plate 4 and the heat radiation conductor 2 and a capacitance Cn is formed between the negative electrode plate 5 and the heat radiation conductor 2 .

Parasitic inductance Lp exists in the current path from the positive electrode terminal 41 to the positive electrode 7p of the upper arm semiconductor element 7 via the positive electrode plate 4. , to the negative electrode 8n of the lower arm semiconductor element 8, there is a parasitic inductance Ln.

Since FIG. 1 is a schematic cross-sectional view, the distance in the height direction between the positive electrode terminal 41 and the insulating layer 3 is different from the distance in the height direction between the input/output terminal 61 and the insulating layer 3. These distances may be the same.

Next, the circuit configuration of the semiconductor power module 1 will be described with reference to FIGS. 3 and 4. FIG. FIG. 3 is a circuit diagram employing a diode as the upper arm semiconductor element 7. As shown in FIG. FIG. 4 is a circuit diagram using a MOSFET as the upper arm semiconductor element 7. As shown in FIG.

3 and 4, semiconductor power module 1 includes a grounded heat dissipation conductor 2, a positive terminal 41, a negative terminal 51, an input/output terminal 61, an upper arm semiconductor element 7, and a lower arm. and a semiconductor element 8 . Upper arm semiconductor element 7 is connected between input/output terminal 61 and positive electrode terminal 41 . Lower arm semiconductor element 8 is connected between input/output terminal 61 and negative terminal 51 .

Although not shown here, the upper arm semiconductor element 7 may be an IGBT (Insulated Gate Bipolar Transistor) or the like. Also, the upper arm semiconductor element 7 and the lower arm semiconductor element 8 may be made of a semiconductor such as silicon (Si) or gallium oxide (GaO) in addition to silicon carbide (SiC) and gallium nitride (GaN).

In the circuit diagrams of FIGS. 3 and 4, the current path from the positive terminal 41 to the upper arm semiconductor element 7 has a parasitic inductance Lp, and the current path from the negative terminal 51 to the lower arm semiconductor element 8 has a parasitic inductance Ln. exist. A capacitance Cp is formed between the positive electrode terminal 41 and the heat radiation conductor 2 . A capacitance Cn is formed between the negative terminal 51 and the heat radiation conductor 2 . The heat radiation conductor 2 is directly grounded or grounded through the housing of the power converter for the purpose of preventing electric shock. This connects the capacitances Cp and Cn to the ground potential.

As shown in FIG. 1, the positive electrode plate 4 connected to the upper arm semiconductor element 7 and the negative electrode plate 5 connected to the lower arm semiconductor element 8 are arranged on the heat dissipation conductor 2 via the thin insulating layer 3. . Therefore, a capacitance exists between the upper arm semiconductor element 7 and the lower arm semiconductor element 8 and the heat radiation conductor 2 . When semiconductor power module 1 has an arm series body in which upper arm semiconductor element 7 and lower arm semiconductor element 8 are connected in series, semiconductor power module 1 includes positive terminal 41 , negative terminal 51 , and input/output terminal 61 . . Capacitances Cp and Cn are formed between the respective electrodes and the conductor 2 for heat dissipation. Here, the upper arm semiconductor element 7 is electrically connected between the positive terminal 41 and the input/output terminal 61 , and the lower arm semiconductor element 8 is electrically connected between the input/output terminal 61 and the negative terminal 51 . be.

Here, a case where vertical semiconductor elements are used for the upper arm semiconductor element 7 and the lower arm semiconductor element 8 and a case where horizontal semiconductor elements are used are examined.

A vertical semiconductor device has a negative electrode on the front surface and a positive electrode on the back surface, and the positive electrode is generally connected to the electrode. Therefore, the upper arm semiconductor element is mounted on the positive electrode and the lower arm semiconductor element is mounted on the input/output electrode and electrically connected. In this case, since the semiconductor element is not mounted on the negative electrode and the area is smaller than that of the positive electrode and the input/output electrode, the capacitance formed on the negative electrode also tends to be small.

On the other hand, in the case of a horizontal semiconductor element, the front surface has a positive electrode and a negative electrode, the back surface has no electrode, and the back surface faces the electrode and is connected directly or via an insulator. In the case of direct connection, the potential of the back surface becomes the same as that of the connected electrode. On the other hand, when connecting through an insulator, the potential of the back surface becomes a floating potential. In addition, depending on the structure of the lateral semiconductor element, the back surface may also be provided with an electrode. A horizontal semiconductor element is generally connected directly or via an insulator to an electrode that has the same potential as the negative electrode of the horizontal semiconductor element. Therefore, the upper arm element is mounted on the output electrode and the lower arm element is mounted on the negative electrode. Each electrode and the negative electrode of the horizontal semiconductor element are connected to each other using a conductor such as an aluminum wire so that they have the same potential. That is, the potential of the rear surface of the lateral semiconductor element becomes the same potential as the negative electrode or becomes a floating potential. In such a configuration, the semiconductor element is not mounted on the positive electrode, and the area of the positive electrode becomes smaller than that of the negative electrode and the input/output electrode, so the capacitance formed on the positive electrode tends to become smaller. be.

The heat radiation conductor is grounded directly or through the housing of the power conversion device for the purpose of preventing electric shock. Therefore, when the semiconductor element performs a switching operation, a noise current flows to the outside through the above-described electrostatic capacitance in accordance with the voltage change.

In the input/output electrodes, the voltage of the positive electrode and the voltage of the negative electrode are alternately applied by the switching operation of the semiconductor element, and accompanying this voltage change, a noise current flows to the outside through the capacitance of the input/output electrodes.

In the positive electrode and the negative electrode, noise currents flow through their respective capacitances in accordance with voltage fluctuations caused by parasitic inductance. Normally, the noise current from the positive electrode side and the noise current from the negative electrode side work in the direction of canceling each other out, but due to the imbalance between the parasitic inductance and capacitance on the positive electrode side and the negative electrode side, some of them are not canceled out. flow outside.

In this embodiment, the imbalance between the parasitic inductance and the capacitance as described above is improved, and the noise current flowing out to the outside is reduced.

The current flowing through the capacitance Cp will be described below. First, assuming that the current flowing through the capacitance Cp is Icp, the current Icp can be expressed by the following equation (1) using the voltage Vcp applied across the capacitance.

Assuming that the potential of the positive terminal 41 is constant, the voltage Vcp across the capacitance Cp is a value obtained by subtracting the voltage across the parasitic inductance Lp from the initial voltage _V0 of the capacitance. Therefore, the voltage Vcp across the capacitance Cp can be expressed by the following equation (2) using the current i flowing through the parasitic inductance Lp.

However, in equation (2), the direction of the current flowing from the positive terminal 41 toward the parasitic inductance Lp is assumed to be positive. From the results of equations (1) and (2), the current Icp flowing through the capacitance Cp can be expressed by the following equation (3).

Similarly, assuming that the direction of the current flowing from the negative electrode terminal 51 toward the parasitic inductance Ln is positive, the current Icn flowing through the capacitance Cn can be expressed by the following equation (4).

Normally, the direction of the current is opposite on the negative electrode side and the positive electrode side, so i=I on the positive electrode side and i=−I on the negative electrode side. Furthermore, the following equations (5) and (6) are obtained from Icp+Icn=0, which is the condition that the currents flowing through the capacitance Cp and the capacitance Cn cancel each other out.

In order for this formula to hold, the coefficient should be zero, so (Lp×Cp)=(Ln×Cn) is obtained. That is, when (Lp.times.Cp) and (Ln.times.Cn) are equal, the noise currents are canceled and the noise currents flowing out to the outside can be suppressed.

FIG. 5 shows a half bridge circuit for showing the noise reduction effect of the semiconductor power module of the first embodiment.

5 further includes a DC voltage source 16, a load inductance 17, a drive circuit 18, and a resistor 19 in addition to the circuit configuration of the semiconductor power module 1 shown in FIG. The DC voltage source 16 is connected between the positive terminal 41 and the negative terminal 51 and applies a positive voltage to the positive terminal 41 with reference to the negative terminal 51 . A load inductance 17 is connected between the positive terminal 41 and the input/output terminal 61 . The drive circuit 18 is connected to the control electrode of the lower arm semiconductor element 8 and controls the ON/OFF operation of the lower arm semiconductor element 8 . A resistor 19 is connected between the heat radiation conductor 2 and the ground potential and represents a parasitic resistance in the ground wiring. Incidentally, the resistance value of the resistor 19 was set to 1Ω.

Next, referring to FIGS. 6 to 9, circuit operation when the lower arm semiconductor element 8 is turned on will be described. Turn-on conditions were set to 400V and 10A. Here, the voltage applied between the positive electrode and the negative electrode of the lower arm semiconductor element 8 is indicated by Vds, and the current flowing from the positive electrode to the negative electrode is indicated by Ids. Also, currents flowing through the capacitances Cp and Cn toward the heat radiation conductor 2 are indicated by Icp and Icn, respectively, and current flowing from the heat radiation conductor 2 to the ground potential via the resistor 19 is indicated by Icom.

FIG. 6 is a waveform diagram showing the turn-on operation under the conditions that the parasitic inductance and capacitance are Lp=10 nH, Ln=10 nH, Cp=50 pF, and Cn=50 pF.

In FIG. 6, a noise current flows through the heat dissipation conductor 2 via the capacitances Cp and Cn due to voltage oscillation of the parasitic inductance due to changes in the voltage Vds at turn-on and changes in the current Ids. Depending on the magnitude of the parasitic inductance or capacitance, the magnitude or vibration frequency of the noise current flowing through the capacitances Cp and Cn changes, and if they cannot be canceled out, the noise current flows out. In FIG. 6, the condition of (Lp×Cp)=(Ln×Cn) is satisfied, and the current Icp and the current Icn are canceled, so the current Icom flowing out to the outside becomes zero.

FIG. 7 is a waveform diagram showing the turn-on operation under the conditions that the parasitic inductance and capacitance are Lp=5 nH, Ln=10 nH, Cp=50 pF, and Cn=50 pF.

In FIG. 7, the voltage Vds and the current Ids at turn-on are substantially the same as those in FIG. 6, but the oscillation amplitude of the current Ids is reduced due to the reduction in the parasitic inductance Lp. In FIG. 7, the condition is (Lp×Cp)≠(Ln×Cn), and the current Icp and the current Icn are different in amplitude and resonance frequency. Since the current Icp and the current Icn are not offset, the current Icom flows out to the outside in FIG.

FIG. 8 is a waveform diagram showing the turn-on operation under the conditions that the parasitic inductance and capacitance are Lp=5 nH, Ln=10 nH, Cp=50 pF, and Cn=25 pF.

In FIG. 8, the capacitance Cn was adjusted from the conditions of FIG. 7 so as to satisfy the condition of (Lp×Cp)=(Ln×Cn). Since the current Icp and the current Icn are canceled, the current Icom flowing out to the outside becomes zero.

FIG. 9 is a waveform diagram showing a turn-on operation under the conditions that the parasitic inductance and capacitance are Lp=5 nH, Ln=10 nH, Cp=100 pF, and Cn=50 pF.

In FIG. 9, the capacitance Cp was adjusted from the conditions of FIG. 7 so as to satisfy the condition of (Lp×Cp)=(Ln×Cn). Since the current Icp and the current Icn are canceled, the current Icom flowing out to the outside becomes zero.

Thus, when the parasitic inductances Lp and Ln and the capacitances Cp and Cn satisfy the condition of (Lp×Cp)=(Ln×Cn), that is, (Lp×Cp) and (Ln×Cn). are equal to each other, it is possible to suppress the noise current that flows out through the heat radiation conductor 2 .

Although the mutual inductance existing between the parasitic inductances Lp and Ln is not shown in the embodiment, if the mutual inductance cannot be ignored, the mutual inductance can be taken into consideration and the effective inductances Lp and Ln can be used for calculation. Just do it.

Embodiment 2.
A semiconductor power module according to the second embodiment will be described below with reference to FIGS. 10 to 13. FIG.

In Embodiment 1, the effect is shown when the ratio of (Lp×Cp) to (Ln×Cn) is 1, that is, when (Lp×Cp)/(Ln×Cn)=1. In the second embodiment, the ratio of the larger one of (Lp×Cp) and (Ln×Cn) to the other is shown in the range of 0 to 1, and the noise reduction effect will be explained. Here, Ln=10 nH, Cp=50 pF, and Cn=50 pF are fixed, and Lp is changed to 0 nH, 9 nH, 9.9 nH, 9.99 nH, and 10 nH. Expressed as a ratio of (Lp*Cp) to (Ln*Cn), the ratios corresponding to the values of Lp are 0, 0.9, 0.99, 0.999 and 1, respectively. Expressing these as percentage errors, they are 100%, 10%, 1%, 0.1%, and 0%, respectively. A noise level is compared by carrying out the fast Fourier transform (FFT:Fast Fourier Transform) of the noise current Icom.

FIG. 10 is a diagram showing and comparing noise levels when Lp is changed. In FIG. 10, Lp was changed to 0 nH, 9 nH, 9.9 nH, 9.99 nH and 10 nH.

In FIG. 10, the noise decreases as the ratio of (Lp*Cp) to (Ln*Cn) approaches 1, and the error decreases by 1/10, ie, 20 dB for every 10-fold increase in accuracy. In the vicinity of 80 to 90 MHz where Lp=0 nH, the resonance point is different from other conditions because the parasitic inductance is greatly different.

Here, the amount of increase in noise due to the application of SiC or GaN to the switching waveform of a semiconductor element that is a noise source will be described. For simplicity, the switching waveform is regarded as a trapezoidal wave, and the frequency spectrum of the trapezoidal wave is explained as the noise level.

FIG. 11 is a trapezoidal wave for explaining the frequency spectrum.
In FIG. 11, the trapezoidal wave is defined by amplitude A, period T, pulse width t, rise time _tr , and fall time _tf . Here, it is assumed that t _r =t _f . The envelope function Envelope of the frequency spectrum of the trapezoidal wave can be expressed by the following equation (7) using the frequency f.

Here, considering that the amplitude of |sin(x)/x| can be expressed using

FIG. 12 is a log-log graph showing the envelope function Envelope(f) and the boundary function Bounds(f) with respect to the frequency f.

In FIG. 12, the envelope function Envelope(f) is indicated by a dotted line, and the boundary function Bounds(f) is indicated by a solid line. The boundary function Bounds(f) in FIG. 12 shows a constant noise level in the region of f<1/πt, and decreases in accordance with the frequency f in the region of 1/πt<f<1/ _πtr . When the frequency f is increased tenfold, the noise level becomes 1/10, which is a change of -20dB when expressed in decibels. Also, in the region of 1/πt _r <f, the noise level becomes 1/100 when the frequency f is increased tenfold, resulting in a change of −40 dB.

The boundary function Bounds(f) will be used to explain the increase in the noise level of a power converter using SiC or GaN with respect to a conventional power converter using Si.

FIG. 13 is a graph showing boundary functions Bounds(f) for two types of trapezoidal waves.

A dashed line in FIG. 13 is a boundary function of a trapezoidal wave assuming a conventional power converter using Si. Here, assuming a driving frequency of 10 kHz and an on-duty of 50%, each parameter of the trapezoidal wave was set to period T=100 μs, pulse width t=50 μs, rise and fall time t _r =100 ns. A solid line in FIG. 13 is a boundary function of a trapezoidal wave assuming a power conversion device to which SiC or GaN is applied. Here, assuming that the drive frequency is 100 kHz, which is ten times that of the trapezoidal wave of the power converter using Si, each parameter of the trapezoidal wave is the period T, the pulse width t, and the rise/fall time _tr was set to 1/10. Comparing the two types of boundary functions, when SiC or GaN is applied, there is an increase of 20-40 dB at the same frequency compared to when Si is used.

Thus, it is expected that the noise level will increase by 20 dB or more when applying SiC or GaN. For this reason, noise reduction of 20 dB is required in order to bring the noise current flowing out through the capacitances Cp and Cn to a noise level equivalent to that of the conventional art. Considering the worst condition where the ratio of (Lp×Cp) to (Ln×Cn) is zero, that is, Lp=0 nH, conditions for realizing a noise reduction of 20 dB are examined.

Referring again to FIG. 10, if the ratio of (Lp×Cp) to (Ln×Cn) is set to 0.9 or more, that is, Lp=9 to 10 nH, a noise reduction of 20 dB compared to the case of Lp=0 nH is achieved. can be realized.

Embodiment 3.
Embodiment 3 relates to a specific configuration of lower arm semiconductor element 8 .

FIG. 14 is a schematic cross-sectional view showing a first specific configuration example of the lower arm semiconductor element 8. As shown in FIG.
The lower arm semiconductor element 8 of FIG. 14 includes a normally-off lateral semiconductor element 81 . The horizontal semiconductor element 81 has a positive electrode 81p and a negative electrode 81n on its front surface, and is connected to the negative electrode plate 5 on its rear surface. 14, the connection conductor 11 is connected to the negative electrode 81n of the horizontal semiconductor element 81, and the connection conductor 12 is connected to the positive electrode 81p of the horizontal semiconductor element 81. In the configuration of FIG. 14, negative electrode 81n and positive electrode 81p of horizontal semiconductor element 81 correspond to negative electrode 8n and positive electrode 8p of lower arm semiconductor element 8, respectively. The rear surface of the horizontal semiconductor element 81 has the same potential as the negative electrode plate 5 .

FIG. 15 is a schematic cross-sectional view showing a second specific configuration example of the lower arm semiconductor element 8. As shown in FIG.
The lower arm semiconductor element 8 of FIG. 15 includes a normally-off horizontal semiconductor element 81 and an insulating layer 82 . The rear surface of the horizontal semiconductor element 81 is connected to the negative electrode plate 5 via the insulating layer 82 . 15, negative electrode 81n and positive electrode 81p of horizontal semiconductor element 81 correspond to negative electrode 8n and positive electrode 8p of lower arm semiconductor element 8, respectively. The rear surface of the lateral semiconductor element 81 becomes a floating potential.

FIG. 16 is a schematic cross-sectional view showing a specific third configuration example of the lower arm semiconductor element 8. As shown in FIG.
The lower arm semiconductor element 8 of FIG. 16 includes a normally-on horizontal semiconductor element 83 and a normally-off vertical semiconductor element 84 . The rear surface of the horizontal semiconductor element 83 is connected to the negative electrode plate 5 , and the positive electrode 84p of the normally-off vertical semiconductor element 84 is electrically connected to the negative electrode 83n on the surface of the normally-on horizontal semiconductor element 83 . The connection conductor 11 is connected to the negative electrode 84 n of the normally-off vertical semiconductor element 84 and the negative electrode plate 5 . Although not shown, the gate electrode of the normally-on horizontal semiconductor element 83 is electrically connected to the negative electrode plate 5 or to a place having the same potential as the negative electrode plate 5 . 16, the negative electrode 84n of the vertical semiconductor element 84 and the positive electrode 83p of the horizontal semiconductor element 83 respectively correspond to the negative electrode 8n and positive electrode 8p of the lower arm semiconductor element 8 in FIG. The rear surface of the horizontal semiconductor element 83 has the same potential as the negative electrode plate 5 .

FIG. 17 is a schematic cross-sectional view showing a fourth specific configuration example of the lower arm semiconductor element 8. As shown in FIG.
The lower arm semiconductor element 8 of FIG. 17 includes an insulating layer 82 in addition to the constituent elements of FIG. An insulating layer 82 is interposed between the back surface of the horizontal semiconductor element 83 and the negative electrode plate 5 . 17, the negative electrode 84n of the vertical semiconductor element 84 and the positive electrode 83p of the horizontal semiconductor element 83 respectively correspond to the negative electrode 8n and positive electrode 8p of the lower arm semiconductor element 8 in FIG. The rear surface of the horizontal semiconductor element 83 becomes a floating potential.

The lower arm semiconductor element 8 shown in FIGS. 16 and 17 has a configuration in which a vertical semiconductor element 84 and a horizontal semiconductor element 83 are cascode-connected. This configuration is generally known as a configuration for using a normally-on semiconductor element as a normally-off semiconductor element.

Embodiment 4.
A semiconductor power module 1 according to Embodiment 4 will be described with reference to FIGS. 18 to 30. FIG. Embodiment 4 is a specific configuration example of a method of adjusting the L value and the C value so that the ratio of the larger one of (Lp×Cp) and (Ln×Cn) to the other is 0.9 or more. Regarding.

FIG. 18 is a configuration example of a semiconductor power module before adjusting the ratio of (Lp×Cp) and (Ln×Cn). For ease of understanding, the sealing material 15 is not shown. In the configuration example of FIG. 18, the positive electrode plate 4 and the negative electrode plate 5 have the same area. In this case, the capacitance values of the electrostatic capacitances Cp and Cn formed between the heat dissipation conductor 2 are the same. Compared with the current path from the positive terminal 41 to the upper arm semiconductor element 7 , the connection conductor 11 exists in the current path from the negative terminal 51 to the lower arm semiconductor element 8 . Since the connecting conductor 11 has a smaller cross-sectional area than the negative electrode plate 5, the parasitic inductance Ln on the negative electrode side tends to be larger than the parasitic inductance Lp on the positive electrode side. That is, in the configuration example of FIG. 18, there is a relationship of (Lp×Cp)<(Ln×Cn). Therefore, in order to make the ratio of (Lp × Cp) and (Ln × Cn), whichever is larger, the other to 0.9 or more, it is necessary to increase Lp or Cp or decrease Ln or Cn .

A specific configuration example for adjusting the L value and the C value will be described with reference to FIGS. 19 to 26 and 27 to 30. FIG.

19 to 26 show configuration examples of the electrodes and connection conductors of the semiconductor power module 1 in which the L value is adjusted.

FIG. 19 is a diagram showing a first configuration example for increasing Lp. In FIG. 19, the distance between the upper arm semiconductor element 7 and the positive electrode terminal 41 is made larger than the distance between the lower arm semiconductor element 8 and the negative terminal 51 in order to increase Lp.

FIG. 20 is a diagram showing a second configuration example for increasing Lp. In FIG. 20, the positive electrode plate 4 and the positive electrode terminal 41 are connected by the connection conductor 14 in order to increase Lp.

FIG. 21 is a diagram showing a third configuration example for increasing Lp. In FIG. 21, slits 20a and 20b are added in the vicinity of the junction with the positive terminal 41 in the positive electrode plate 4 in order to increase Lp, thereby reducing the current cross-sectional area.

FIG. 22 is a diagram showing a fourth configuration example for increasing Lp. In FIG. 22, in order to increase Lp, in the positive electrode plate 4, a slit 20c is added near the junction with the positive electrode terminal 41 to reduce the cross-sectional area of current flow, and the current path to the upper arm semiconductor element 7 is reduced. is extended.

FIG. 23 is a diagram showing a fifth configuration example for increasing Lp. In FIG. 23, in order to increase Lp, a slit 20d is added in the vicinity of the junction with the positive electrode terminal 41 in the positive electrode plate 4 to reduce the cross-sectional area of the current flow and to increase the current path to the upper arm semiconductor element 7. is extended.

FIG. 24 is a diagram showing a sixth configuration example for increasing Lp. In FIG. 24, in order to increase Lp, in the positive electrode plate 4, a slit 20e is added in the vicinity of the junction with the positive electrode terminal 41 to reduce the cross-sectional area of current flow, and to increase the current path to the upper arm semiconductor element 7. is extended.

FIG. 25 is a diagram showing a seventh configuration example for increasing Lp. In FIG. 25 , in order to increase Lp, a slit 20 f is added in the vicinity of the junction with the positive electrode terminal 41 in the positive electrode plate 4 to reduce the cross-sectional area of the current flow and to increase the current path to the upper arm semiconductor element 7 . is extended.

FIG. 26 is a diagram showing an eighth configuration example for reducing Ln. In FIG. 26, in order to reduce Ln, connection conductors 11a and 11b are used to increase the number of connection conductors to two. Note that the number of connection conductors may be greater than two.

Also, although not shown, the cross-sectional area of the connection conductor 11 may be increased in order to reduce Ln. Slits may be added to the negative electrode plate 5 to increase Ln.

27 to 30 show configurations of electrodes and connecting conductors of the semiconductor power module 1 with adjusted C value.

FIG. 27 is a diagram showing a ninth configuration example for reducing Cn. In FIG. 27, the area of the negative electrode plate 5 is made smaller than the area of the positive electrode plate 4 in order to reduce Cn.

FIG. 28 is a diagram showing a tenth configuration example for increasing Cp. In FIG. 28, the area of the positive electrode plate 4 is made larger than the area of the negative electrode plate 5 in order to increase Cp. In the example of FIG. 28, Lp may decrease because the cross-sectional area from the positive electrode terminal 41 to the upper arm semiconductor element 7 increases.

FIG. 29 is a diagram showing an eleventh configuration example in which Cn is decreased and Cp is increased. In FIG. 29, in order to decrease Cn and increase Cp, the area of the negative electrode plate 5 is decreased and the area of the positive electrode plate 4 is increased so that the area of the negative electrode plate 5 is larger than the area of the positive electrode plate 4. is also smaller. In the example of FIG. 29, the current cross-sectional area from the negative terminal 51 to the connection conductor 11 decreases, and the current cross-sectional area from the positive terminal 41 to the upper arm semiconductor element 7 increases, so Ln increases and Lp increases. may decrease.

FIG. 30 shows a twelfth configuration example in which Cn is decreased and Cp is increased. In FIG. 30, in order to decrease Cn and increase Cp, in the configuration shown in FIG. 27, the positive electrode plate 4 is extended where the negative electrode plate 5 is removed.

Moreover, although not shown, the thickness of the insulating layer 3 may be partially increased or decreased, or materials having different dielectric constants may be used partially in order to adjust the capacitances Cp and Cn. The areas of the negative electrode plate 5 and the positive electrode plate 4 may be changed to increase Cn and decrease Cp.

The method of adjusting the L value and the C value described in this embodiment may combine a plurality of methods among the above. Also, the L value may be changed by a method such as changing the arrangement of terminals, and the method of adjusting the L value and the C value is not limited to the adjusting method described in this embodiment.

According to the semiconductor power module 1 of Embodiment 4, the ratio of the larger one of (Lp×Cp) and (Ln×Cn) to the other can be adjusted to 0.9 or more. That is, the semiconductor power module 1 can be adjusted so that 0.9<(Lp×Cp)/(Ln×Cn)<1/0.9, and the noise level can be reduced.

Embodiment 5.
A semiconductor power module 1 according to Embodiment 5 will be described with reference to FIGS. 1 and 31 to 33. FIG.

In FIG. 1, the input/output terminal 61 is arranged with a distance from the insulating layer 3 . This is because the upper arm semiconductor element 7 is arranged on the positive electrode plate 4 and the lower arm semiconductor element 8 is arranged on the negative electrode plate 5, so that no input/output electrode plate is required. Since the input/output electrode plate is not arranged on the insulating layer 3, the capacitance Cac between the input/output terminal 61 and the heat radiation conductor 2 is smaller than Cp and Cn.

Here, the capacitance generated between the parallel plates will be explained. Assuming that the dielectric constant in vacuum is ε ₀ , the relative dielectric constant ε _r , the facing area of the parallel plates is S, and the distance between the parallel plates is d, the capacitance C can be expressed by the following equation (9).

For example, if the dielectric constant of the insulating layer 3 or the sealing material 15 is _εr = 4, the facing area S = 10 mm ² , and the distance d = 1 mm, the capacitance C can be obtained by the following equation (10). .

FIG. 31 is a circuit diagram showing the configuration of the semiconductor power module according to the fifth embodiment.
FIG. 31 shows the capacitance Cac existing between the input/output terminal 61 and the heat radiation conductor 2 in addition to the configuration of FIG. 3 in the first embodiment.

FIG. 32 is a diagram comparing noise levels when the capacitance Cac is changed under the conditions of Lp=Ln=10 nH and Cp=Cn=50 pF. The capacitance Cac was changed to 0 pF, 0.1 pF, 1 pF, 10 pF and 100 pF. Note that Cac=0 pF is the same as the graph of Lp=10 nH in FIG.

FIG. 32 shows that the noise level increases by 20 dB for every 10-fold increase in capacitance Cac. Under the conditions of parasitic inductances Lp and Ln and capacitances Cp and Cn shown in FIG. 32, the noise level at Cac=1 pF and the ratio of (Lp×Cp) to (Ln×Cn) in FIG. The noise level of Lp=9 nH is almost the same in the frequency band of 30 MHz or higher.

FIG. 33 is a diagram comparing noise levels when Cac is varied under the conditions of Lp=9 nH, Ln=10 nH, and Cp=Cn=50 pF. The capacitance Cac was changed to 0 pF, 0.1 pF, 1 pF, 10 pF and 100 pF.

In FIG. 33, the noise levels of Cac=0 pF, 0.1 pF, and 1 pF are almost the same at frequencies of 30 MHz and higher. It is desirable to

Although the value of the capacitance Cac that maximizes the noise reduction effect varies depending on the values of the parasitic inductances Lp and Ln and the capacitances Cp and Cn, the capacitance Cac should generally be 1 pF or less. Further, setting the capacitance Cac to 1 pF or less means increasing the distance between the input/output terminal 61 and the heat radiation conductor 2, or reducing the facing area between the input/output terminal 61 and the heat radiation conductor 2. It can be realized by

According to the semiconductor power module 1 of Embodiment 5, the noise reduction effect can be maximized by reducing the capacitance Cac generated between the input/output terminal 61 and the heat radiation conductor 2 .

Embodiment 6.
The present embodiment applies the semiconductor power module 1 of the above-described first to sixth embodiments to a power converter. Although the present disclosure is not limited to a specific power converter, a case where the present disclosure is applied to a three-phase inverter will be described below as a sixth embodiment.

FIG. 34 is a block diagram showing the configuration of a power conversion system to which the power converter of this embodiment is applied.

A power conversion system 400 shown in FIG. 34 comprises a power supply 100, a capacitor 101, a snubber capacitor 102, external inductances 104 and 105, a power converter 200, and a load 300. FIG. The power supply 100 is a DC power supply and supplies DC power to the power converter 200 . The power supply 100 can be composed of various things, for example, it can be composed of a DC system, a solar battery, a storage battery, or it can be composed of a rectifier circuit or an AC/DC converter connected to an AC system. good too. Also, the power supply 100 may be configured by a DC/DC converter that converts DC power output from the DC system into predetermined power.

Power converter 200 is a three-phase inverter connected between power supply 100 and load 300 , converts DC power supplied from power supply 100 into AC power, and supplies AC power to load 300 . As shown in FIG. 34, the power conversion device 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, and a control circuit 203 that outputs a control signal for controlling the main conversion circuit 201 to the main conversion circuit 201. and

The load 300 is a three-phase electric motor driven by AC power supplied from the power converter 200 . Note that the load 300 is not limited to a specific application, but is an electric motor mounted on various electrical equipment, such as a hybrid vehicle or an electric vehicle, a railway vehicle, an elevator, or an electric motor for an air conditioner.

Details of the power converter 200 will be described below. The main conversion circuit 201 includes switching elements (7a to 7c, 8a to 8c) and freewheeling diodes (not shown). By switching the switching elements, the DC power supplied from the power supply 100 is converted to AC power. converted and supplied to load 300 . Although there are various specific circuit configurations of the main conversion circuit 201, the main conversion circuit 201 of the present embodiment is a two-level three-phase full bridge circuit.

The main conversion circuit 201 includes three semiconductor power modules 1a, 1b, 1c. At least one of semiconductor power modules 1a, 1b, and 1c of main conversion circuit 201 corresponds to semiconductor power module 1 of any one of the first to fifth embodiments described above. Each of the three semiconductor power modules 1a, 1b, 1c constitutes an upper and lower arm, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full bridge circuit. Output terminals of the upper and lower arms, that is, three output terminals of the main conversion circuit 201 are connected to the load 300 .

Further, the main conversion circuit 201 includes a drive circuit (not shown) for driving each switching element, but the drive circuit may be built in the semiconductor power modules 1a, 1b, 1c or A drive circuit may be provided separately from 1a, 1b, and 1c. The drive circuit generates a drive signal for driving the switching element of the main conversion circuit 201 and supplies it to the control electrode of the switching element of the main conversion circuit 201 . Specifically, in accordance with a control signal from the control circuit 203, which will be described later, a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrode of each switching element. When maintaining the switching element in the ON state, the driving signal is a voltage signal (ON signal) equal to or higher than the threshold voltage of the switching element, and when maintaining the switching element in the OFF state, the driving signal is equal to the threshold voltage of the switching element. It becomes a voltage signal (OFF signal) below the voltage.

The control circuit 203 controls the switching elements of the main converter circuit 201 so that desired power is supplied to the load 300 . Specifically, based on the power to be supplied to the load 300, the time (on time) during which each switching element of the main conversion circuit 201 should be in the ON state is calculated. For example, the main conversion circuit 201 can be controlled by PWM control that modulates the ON time of the switching element according to the voltage to be output. Then, a control command (control signal) to the drive circuit provided in the main conversion circuit 201 so that an ON signal is output to the switching element that should be in the ON state at each time point, and an OFF signal is output to the switching element that should be in the OFF state. to output The drive circuit outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element according to this control signal.

In the power conversion device 200 according to the present embodiment, the semiconductor power modules according to any one of the first to fifth embodiments are applied as the semiconductor power modules 1a, 1b, and 1c forming the main conversion circuit 201, so that noise reduction can be achieved. can be realized.

Positive terminals 41 a , 41 b , 41 c of semiconductor power modules 1 a , 1 b , 1 c are connected to a first end of snubber capacitor 102 , and negative terminals 51 a , 51 b, 51 c are connected to a second end of snubber capacitor 102 . Both ends of snubber capacitor 102 are connected to both ends of capacitor 101 via external inductances 104 and 105 . The negative side of capacitor 101 is connected to the ground node. The three semiconductor power modules 1a, 1b, 1c form parasitic inductances Lpa, Lpb, Lpc, Lna, Lnb, Lnc and capacitances Cpa, Cpb, Cpc, Cna, Cnb, Cnc.

In the configuration of the main conversion circuit 201, the ratio of the larger one of (Lpa×Cpa) and (Lna×Cna) to the other is 0.9 or more, and any one of (Lpb×Cpb) and (Lnb×Cnb) The ratio of the larger one to the other is 0.9 or more, and the ratio of the other to the larger one of (Lpc×Cpc) and (Lnc×Cnc) is 0.9 or more.

In other words, the semiconductor power modules 1a, 1b, 1c are configured so that the following equations (11), (12), (13) are established simultaneously.
0.9<(Lpa×Cpa)/(Lna×Cna)<1/0.9 (11)
0.9<(Lpb×Cpb)/(Lnb×Cnb)<1/0.9 (12)
0.9<(Lpc×Cpc)/(Lnc×Cnc)<1/0.9 (13)
By configuring the semiconductor power modules 1a, 1b, and 1c in this way, it is possible to provide the power converter 200 with reduced noise.

Although the power conversion device 200 to which the semiconductor power module shown in FIG. 4 is applied is shown here, the semiconductor power module shown in FIG. 3 or 31 may be applied to the power conversion device 200.

In the present embodiment, an example in which the present disclosure is applied to a two-level three-phase inverter has been described, but the present disclosure is not limited to this, and can be applied to various power converters. In this embodiment, a two-level power conversion device is used, but a three-level or multi-level power conversion device may be used. You can apply it. In addition, the present disclosure can be applied to a DC/DC converter or an AC/DC converter when power is supplied to a DC load or the like.

In addition, the power conversion device to which the present disclosure is applied is not limited to the case where the above-described load is an electric motor. It can also be used as a power conditioner such as a photovoltaic power generation system or an electric storage system.

(summary)
The above embodiments will be summarized with reference to the drawings again.

The present disclosure relates to semiconductor power modules. The semiconductor power module 1 described with reference to FIGS. 1 to 34 includes a grounded heat radiation conductor 2, an insulating layer 3 formed on the heat radiation conductor 2, a positive electrode plate 4 and a negative electrode plate 5, and a positive electrode terminal. 41 , a negative terminal 51 , an upper arm semiconductor element 7 , a lower arm semiconductor element 8 , a first connection conductor 11 , and a second connection conductor 12 .

A positive electrode plate 4 and a negative electrode plate 5 are provided on the insulating layer 3 . The positive electrode terminal 41 and the negative electrode terminal 51 are connected to the positive electrode plate 4 and the negative electrode plate 5, respectively. The upper arm semiconductor element 7 is arranged on the positive electrode plate 4, and the positive electrode plate 4 and the positive electrode are connected. A lower arm semiconductor element 8 is arranged on the negative electrode plate 5 . The first connection conductor 11 connects the negative electrode 8n of the lower arm semiconductor element 8 and the negative electrode plate 5 . The second connection conductor 12 connects the positive electrode 8p of the lower arm semiconductor element 8 and the negative electrode 7n of the upper arm semiconductor element 7 .

Lp represents the effective inductance in the current path from the positive electrode terminal 41 to the positive electrode of the upper arm semiconductor element 7, and Ln represents the current from the negative electrode terminal 51 through the negative electrode plate 5 and the first connection conductor 11 to the lower arm semiconductor element 8. Indicates the effective inductance in the current path to the negative electrode 8n, Cp indicates the capacitance between the positive electrode plate 4 and the heat dissipation conductor 2, and Cn indicates the capacitance between the negative electrode plate 5 and the heat dissipation conductor 2. When representing capacitance, 0.9<(Lp×Cp)/(Ln×Cn)<1/0.9.

By configuring the semiconductor power module 1 in this way, the imbalance between the effective inductance and the capacitance inside the semiconductor power module 1 on the positive terminal 41 side and the negative terminal 51 side is improved. As a result, the noise current flowing into the heat radiation conductor is canceled, and the noise current flowing out to the outside can be suppressed.

As shown in FIGS. 14-17, the lower arm semiconductor element 8 includes a horizontal semiconductor element 81 or 83. As shown in FIGS.

As shown in FIGS. 14 and 15, the horizontal semiconductor element 81 is a normally-off semiconductor element. A positive electrode 81p and a negative electrode 81n of the horizontal semiconductor element 81 correspond to the positive electrode 8p and the negative electrode 8n of the lower arm semiconductor element 8, respectively.

By applying the horizontal semiconductor element 81 to the lower arm semiconductor element 8 in this way, it is possible to realize a semiconductor power module in which the imbalance between the effective inductance and the capacitance is improved, thereby reducing noise.

As shown in FIGS. 16 and 17, the horizontal semiconductor element 83 is a normally-on semiconductor element. The lower arm semiconductor element 8 further includes a normally-off vertical semiconductor element 84 . The negative electrode 83n of the horizontal semiconductor element 83 and the positive electrode 84p of the vertical semiconductor element 84 are connected. The positive electrode 83p of the horizontal semiconductor element 83 corresponds to the positive electrode 8p of the lower arm semiconductor element 8, and the negative electrode 84n of the vertical semiconductor element 84 corresponds to the negative electrode 8n of the lower arm semiconductor element 8.

By applying the horizontal semiconductor element 83 and the vertical semiconductor element 84 to the lower arm semiconductor element 8 in this manner, a semiconductor power module with improved imbalance between the effective inductance and the capacitance can be realized and noise can be reduced. is.

As shown in FIGS. 1 and 2, the semiconductor power module 1 further includes an input/output terminal 61 and a third connection conductor 13 connecting the input/output terminal 61 to the negative electrode of the upper arm semiconductor element. The input/output terminal 61 is arranged with a distance from the insulating layer 3 . A capacitance formed between the input/output terminal 61 and the heat radiation conductor 2 is 1 pF or less. The third connection conductor 13 may be a conductor that connects the input/output terminal 61 to the positive electrode of the lower arm semiconductor element.

By configuring the semiconductor power module 1 in this manner, the capacitance of the input/output terminal 61 can be reduced. Thereby, the semiconductor power module 1 can further exhibit the noise reduction effect by improving the imbalance between the effective inductance and the capacitance.

The material of the upper arm semiconductor element 7 is silicon carbide, and the material of the horizontal semiconductor element included in the lower arm semiconductor element 8 is gallium nitride.

That is, even when using a power semiconductor device using SiC or GaN as a semiconductor substrate, it is possible to suppress an increase in noise accompanying an increase in switching speed or carrier frequency.

In another aspect, the present disclosure relates to a power conversion device 200 including the semiconductor power module 1 described above. By including the semiconductor power modules described in the first to fifth embodiments, it is possible to provide the power converter 200 with reduced noise.

In the first to sixth embodiments described above, the terminals, electrodes, and semiconductor elements may be directly connected or indirectly connected with solder or a conductive adhesive. The connection conductors 11 to 14 are made of a conductor such as aluminum or copper, and are not limited to wires, and may be in the form of ribbon wires, plates, or the like. Also, the heat radiation conductor 2 may be in the form of a thin plate.

It is also planned that each embodiment disclosed this time will be appropriately combined and carried out within a non-contradictory range. The embodiments disclosed this time should be considered as examples and not restrictive in all respects. The scope of the present invention is indicated by the scope of the claims rather than the description of the above-described embodiments, and is intended to include all modifications within the meaning and scope equivalent to the scope of the claims.

1, 1a, 1b, 1c semiconductor power module 2 heat dissipation conductor 3, 82 insulating layer 4 positive electrode plate 5 negative electrode plate 7 upper arm semiconductor element 8 lower arm semiconductor element 11, 11a, 12, 13, 14 connection conductor 15 sealing material 16 DC voltage source 17 load inductance 18 drive circuit 19 resistor 20a, 20c, 20d, 20e, 20f slit 41, 41a, 41b, 41c positive terminal 51, 51a negative electrode terminal, 61 input/output terminal, 81, 83 horizontal semiconductor element, 84 vertical semiconductor element, 100 power supply, 101 capacitor, 102 snubber capacitor, 104 external inductance, 200 power converter, 201 main conversion circuit, 203 control circuit, 300 load, 400 power conversion system, C, Cn, Cna, Cnb, Cnc, Cp, Cpa, Cpb, Cpc capacitance, Ln, Lna, Lnb, Lnc, Lp, Lpa, Lpb, Lpc parasitic inductance.

Claims (6)

a grounded heat dissipation conductor;
an insulating layer formed on the heat dissipation conductor;
a positive electrode plate and a negative electrode plate provided on the insulating layer;
a positive terminal and a negative terminal respectively connected to the positive electrode plate and the negative electrode plate;
an upper arm semiconductor element disposed on the positive electrode plate and having the positive electrode plate and the positive electrode connected to each other;
a lower arm semiconductor element disposed on the negative electrode plate;
a first connection conductor that connects the negative electrode of the lower arm semiconductor element and the negative electrode plate;
a second connection conductor that connects the positive electrode of the lower arm semiconductor element and the negative electrode of the upper arm semiconductor element;
Lp represents an effective inductance in a current path from the positive electrode terminal to the positive electrode of the upper arm semiconductor element,
Ln represents an effective inductance in a current path from the negative electrode terminal through the negative electrode plate and the first connection conductor to the negative electrode of the lower arm semiconductor element,
Cp indicates the capacitance between the positive electrode plate and the heat dissipation conductor,
When Cn denotes the capacitance between the negative electrode plate and the heat dissipation conductor,
0.9<(Lp×Cp)/(Ln×Cn)<1/0.9
and
The semiconductor power module , wherein the lower arm semiconductor element includes a horizontal semiconductor element . The horizontal semiconductor element is a normally-off semiconductor element,
2. The semiconductor power module according to claim 1 , wherein the positive and negative electrodes of said horizontal semiconductor element are the positive and negative electrodes of said lower arm semiconductor element, respectively. The horizontal semiconductor element is a normally-on semiconductor element,
the lower arm semiconductor element further includes a normally-off vertical semiconductor element,
the negative electrode of the horizontal semiconductor element and the positive electrode of the vertical semiconductor element are connected,
the positive electrode of the horizontal semiconductor element corresponds to the positive electrode of the lower arm semiconductor element,
2. The semiconductor power module according to claim 1 , wherein the negative electrode of said vertical semiconductor element corresponds to the negative electrode of said lower arm semiconductor element. an input/output terminal;
a third connection conductor that connects the input/output terminal to either the negative electrode of the upper arm semiconductor element or the positive electrode of the lower arm semiconductor element;
The input/output terminal is arranged at a distance from the insulating layer,
2. The semiconductor power module according to claim 1 , wherein a capacitance formed between said input/output terminal and said heat radiation conductor is 1 pF or less. The material of the upper arm semiconductor element is silicon carbide,
5. The semiconductor power module according to claim 1 , wherein said lateral semiconductor element is made of gallium nitride. a main conversion circuit having the semiconductor power module according to any one of claims 1 to 5 , for converting input power and outputting the power;
a control circuit that outputs a control signal for controlling the main conversion circuit to the main conversion circuit;
A power converter with

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