JP7276049B2 - Plating method - Google Patents

Description

The present invention provides a method for forming tin-based bumps (hereinafter sometimes simply referred to as bumps) that serve as protruding electrodes of tin or tin alloy on a substrate or silicon wafer when a semiconductor integrated circuit chip is mounted on a circuit substrate. It relates to a plating method. More specifically, the present invention relates to a filling plating method using a tin plating solution and a tin alloy plating solution (hereinafter sometimes referred to as a tin-based plating solution) for forming tin-based bumps .

For circuit boards on which semiconductor integrated circuit chips (hereafter referred to as semiconductor chips) are mounted, CSPs (Chip Size/Chip Size/ Currently, scale package type semiconductor devices are mainly manufactured. In order to connect the circuit board and the semiconductor chip, the via opening, which is the body of the via on the board side, is filled with tin or a tin alloy to form a bump, which is the protruding electrode of the protruding metal terminal. is loaded with a semiconductor chip.

Conventionally, as one method of forming tin-based bumps by filling with tin or tin alloy material, there is an electroplating method using a tin-based plating solution. In this method, after forming a tin or tin alloy plating film (hereinafter sometimes referred to as a tin-based plating film ), which is a tin-based plating deposition layer, which is a tin-based bump, in the via (recess) , a tin-based plating film is formed by heat treatment. Tin-based bumps are formed by melting the plated film.

A general method of forming bumps by electroplating will now be described with reference to FIG. As shown in FIG. 3A, a solder resist pattern having openings is formed on the surface of a substrate or silicon wafer 1 on which wiring is provided. Next, electroless plating is performed on the surface of the solder resist layer 2 to form a copper seed layer 3 for power supply. Next, a dry film resist layer 4 is formed on the surface of the copper seed layer 3, and a dry film resist pattern having openings is formed so as to connect with the openings of the solder resist layer 2. Next, as shown in FIG. Next, by supplying electric power through the copper seed layer 3, the inside of the via 6 of the dry film resist pattern is electrotin-plated, and the inside of the via 6 on the copper seed layer 3 is filled with tin, which is a tin-based plating deposition layer. A system plating film 7 is formed. Next, after the dry film resist layer and the copper seed layer are sequentially removed, the remaining tin-based plating film is melted by reflow treatment to form tin-based bumps 8 as shown in FIG. 3(b).

In the electroplating equipment, by changing the current density, the stirring strength of the plating solution, the concentration of the plating solution, etc., the properties of the plating are changed, and the physical properties and / or plating of the plating film in the via on the substrate or silicon wafer The surface shape of the film can be controlled. For example, by plating a pattern with vias using a filling plating solution containing a leveling agent that suppresses the growth of the plating film, it is possible to preferentially precipitate from the bottom of the vias due to the action of the leveling agent. . A plating method containing such a leveling agent is disclosed (see, for example, Patent Document 1 (claim 1, paragraph [0010])).

In the plating method of Patent Document 1, a substrate having recesses for through electrodes having an aspect ratio of 2 or more on the surface and an anode are placed in a plating solution containing a leveling agent that weakens the effect of suppressing the growth of the plating film when the stirring is weak. The plating solution between the substrate and the anode is stirred while a voltage is applied between the substrate and the anode so as to face each other, and the metal is filled in the recess for the through electrode, and the through electrode is filled with the metal. In this method, the stirring condition of the plating solution between the substrate and the anode is changed from high-speed stirring to low-speed stirring and the current density is increased as the aspect ratio of the unfilled portion of the recess becomes smaller. According to this plating method, the growth rate of the plating film from the bottom of the through electrode recess is not slowed down, and the metal such as copper is completely deposited in the through electrode recess without causing defects such as voids therein. It is said that it can be filled to

On the other hand, as another plating method, plating is disclosed in which copper plating is efficiently applied to fine grooves or holes while preventing the generation of voids to fill the wiring grooves on the base material (for example, Patent Document 2 (see paragraphs [0010] and [0017])). In the plating method of Patent Document 2, the first plating is performed at a low current with an average cathode current density of about 0.03 A/dm ² to 0.5 A/dm ² for about 10 seconds to 10 minutes, and the hole filling progresses. The subsequent plating is a method of plating by increasing the current density to about 0.5 A/dm ² to 10 A/dm ² , which is within the range of general conditions for metal plating baths. In this plating method, the subsequent plating is carried out under constant current conditions, or by increasing the current density in multiple steps or continuously.

Japanese Patent No. 5749302 Japanese Patent Application Laid-Open No. 2004-197228

The plating method of Patent Document 1 is used for a substrate having through-electrode recesses having an aspect ratio of 2 or more on the surface thereof, and the through-electrode recesses are formed without slowing down the growth rate of the plating film from the bottom of the through-electrode recesses. The object is to completely fill metal such as copper inside without causing defects such as voids inside. In order to achieve this object, in this plating method, as the aspect ratio of the unfilled portion of the through electrode recess decreases, the stirring condition is changed from high speed stirring to low speed stirring, thereby suppressing the growth of the plating film. By weakening the effect of the leveling agent and increasing the current density, it is possible to achieve plating in a short time.

However, Patent Document 1 does not specifically describe how much the plating current density is increased when the stirring condition is changed from high-speed stirring to low-speed stirring. In Patent Document 2, the first plating is performed at a low current with an average cathode current density of about 0.03 A/dm ² to 0.5 A/dm ² for about 10 seconds to 10 minutes. Then, subsequent plating is performed at a current density of about 0.5 A/dm ² to 10 A/dm ² . When the current density in the plating method of Patent Document 1 is increased in the same manner as in Patent Document 2, in this method, in a pattern in which different via pitches and/or multiple types of via diameters are mixed, a plurality of substrates or silicon wafers are formed. There is a problem that the depth of the recess on the upper surface of the plating film formed in the via becomes large, and the height of the bump after reflow becomes lower than intended.

Specifically, in the case of a pattern in which multiple types of vias with different via diameters are mixed, plating using a conventional tin or tin alloy plating solution improves the filling property of vias with either a small diameter or a large diameter. Although it is possible, the via-filling property on the other hand is degraded. That is, in a substrate having both small and large vias, when both vias are plated at the same time, for example, as shown in FIG. Even if the plating film 7a can be formed and the plating can be performed with a good filling property, the plating film 7b having a recess R formed on the upper surface of the large-diameter via 6b may be formed. When such a substrate 1 is reflowed, as shown in FIG. 4(c), there is a difference in bump height between a bump 8a made from a small-diameter via 6a and a bump 8b made from a large-diameter via 6b after reflow. There was a problem that bump height variation occurred. For this reason, as shown in FIG. 4(b), the via-filling properties for both the small-diameter via 6a and the large-diameter via 6b are improved, and flat plating films 7a and 7b without recesses on the upper surface are formed. are formed, and as shown in FIG. 4(d), both the heights of the bumps 8a and 8b are aligned to achieve uniform height of the bumps.

An object of the present invention is to provide a plating method that reduces the depth of recesses on the upper surface of a plating film formed in a plurality of vias on a substrate or a silicon wafer and makes the height of tin-based bumps uniform after reflow. to do .

The present inventors found that when the plating solution is changed from strong stirring to weak stirring as the filling of the plating via progresses, the action of the inhibitor (carbonyl group-containing compound) contained in the filling plating solution is suppressed and the plating film Tin is more likely to deposit in the center of the plating film, the depth of the recess on the top surface of the plating film is reduced, and the current density is made higher at the beginning of plating and lower at the end of plating than at the beginning of plating, so that the inhibitor becomes more effective. The present inventors have arrived at the present invention by paying attention to the fact that the filling property to the via is improved by acting effectively.

A first aspect of the present invention is a plating method for forming tin-based bumps in each of a plurality of vias on a substrate or a silicon wafer, wherein the plating solution used in the plating method contains at least a soluble tin salt containing stannous salt. Low-stirring plating containing a salt (A), a carbonyl group-containing compound (B), a surfactant (C), and an unsaturated carboxylic acid (D), in which the stirring speed of the plating solution is lower than at the start of plating and a low-current plating period in which the plating current density is lower than that at the start of plating.

A second aspect of the present invention is an invention based on the first aspect, and a plating method in which, after the low-current plating period, a high-current plating period in which the plating current density is higher than that of the low-current plating period is provided. is.

A third aspect of the present invention is an invention based on the first or second aspect, and is a plating method in which the plurality of vias are composed of a plurality of types of vias having different via diameters.

In the plating method of the first aspect of the present invention, by increasing the stirring speed of the tin-based plating solution at the initial stage of plating, the plating solution is sufficiently spread to the bottom of the via on the substrate or silicon wafer, and the plating film is formed in the via. Densely formed. In addition, in the low-stirring plating period, by setting the stirring speed lower than that in the initial stage of plating, the action of the inhibitor (carbonyl group-containing compound) contained in the tin-based plating solution is suppressed, and tin deposits in the center of the plating film. The depth of the recess on the upper surface of the plating film is reduced. In addition, by increasing the current density of the plating at the initial stage of plating, the suppressing agent acts more effectively and the via filling property is improved. As a result, the depth of the recess on the upper surface of the plating film formed in the via can be reduced, and the height of the tin-based bumps after reflow can be made uniform. Further, in the low-current plating period, by setting the current density of plating lower than that in the initial stage of plating, recesses are less likely to be formed on the upper surface of the plating film that has grown within the via.

In addition, in the plating method of the second aspect of the present invention, by providing a high-current plating period in which the current density is higher than that of the low-current plating period after the low-current plating period, the occurrence of recesses can be further suppressed. At the same time, variations in height of the tin-based bumps after reflow can be reduced.

In addition, in the plating method of the third aspect of the present invention, when forming a plating film in a plurality of types of vias having different via diameters, the stirring speed of the plating solution and the current density of the plating are changed during plating. Under the normal plating conditions, which do not require a large-diameter via, a deep recess is more likely to be formed on the upper surface of the plating film in the via than in a small-diameter via. As a result, recesses are less likely to be formed on the upper surface of the plating film formed in the large-diameter via, and the height of the tin-based bumps after reflow can be made uniform.

1A to 1C are cross-sectional configuration diagrams of a substrate with vias showing the plating method of the present embodiment in the order of steps; FIG. 1(a) is a cross-sectional configuration diagram of the substrate with vias before plating, FIG. 1(b) is a cross-sectional configuration diagram of the substrate with vias in which the stirring speed is increased at the initial stage of plating, and FIG. FIG. 4 is a cross-sectional configuration diagram of a substrate with vias in which the speed is lowered in the latter stage of plating; 2(a) is a cross-sectional configuration diagram of the silicon wafer with vias before plating in Example 1, and FIG. 2(b) is a cross-sectional configuration diagram of the silicon wafer with vias after plating in Example 1. FIG. FIG. 2 is a cross-sectional configuration diagram of forming a tin-based bump after forming a plating film in a general via. FIG. 3(a) is a cross-sectional view showing a plated film formed in the via, and FIG. 3(b) is a cross-sectional view after the dry film and copper seed layer are peeled off and the plated film is heated. FIG. 4(a) is a cross-sectional configuration diagram showing an example in which a plating film is unevenly formed in patterns with different via diameters, and FIG. 4(b) is a pattern in which via diameters are different and a plating film is uniformly formed. FIG. 4C is a cross-sectional configuration diagram showing an example, FIG. 4C shows an example in which the height of the bumps formed after peeling off the dry film and the copper seed layer in FIG. 4A and reflowing the plating film is uneven. FIG. 4D is a cross-sectional configuration diagram showing an example in which the height of the bumps formed after peeling off the dry film and the copper seed layer in FIG. 4B and reflowing the plating film is uniform. It is a sectional block diagram showing.

Next, a mode for carrying out the present invention will be described.

[Plating solution used in the plating method of the present embodiment]
The plating solution used in the plating method of the present embodiment is a tin or tin alloy plating solution comprising at least a soluble salt (A) containing a stannous salt, a carbonyl group-containing compound (B), and a surfactant It contains an agent (C) and an unsaturated carboxylic acid (D).

The tin alloy of the present embodiment is an alloy of tin and a predetermined metal selected from silver, copper, bismuth, nickel, antimony, indium, and zinc. Binary alloys such as bismuth alloys, tin-nickel alloys, tin-antimony alloys, tin-indium alloys, tin-zinc alloys, and ternary alloys such as tin-copper-bismuth and tin-copper-silver alloys.

Therefore, the soluble salt (A) of the present embodiment contains Sn ²⁺ , Ag ⁺ , Cu ⁺ , Cu ²⁺ , Bi ³⁺ , Ni ²⁺ , Sb ³⁺ , In ³⁺ , Zn ²⁺ and the like in the plating solution. means any soluble salt that generates various metal ions of, for example, oxides, halides, and metal salts of inorganic acids or organic acids.

Examples of metal oxides include stannous oxide, copper oxide, nickel oxide, bismuth oxide, antimony oxide, indium oxide, and zinc oxide. Examples of metal halides include stannous chloride, bismuth chloride, and bromide. Bismuth, cuprous chloride, cupric chloride, nickel chloride, antimony chloride, indium chloride, zinc chloride and the like.

Metal salts of inorganic or organic acids include copper sulfate, stannous sulfate, bismuth sulfate, nickel sulfate, antimony sulfate, bismuth nitrate, silver nitrate, copper nitrate, antimony nitrate, indium nitrate, nickel nitrate, zinc nitrate, and copper acetate. , nickel acetate, nickel carbonate, sodium stannate, stannous borofluoride, stannous methanesulfonate, silver methanesulfonate, copper methanesulfonate, bismuth methanesulfonate, nickel methanesulfonate, indium methanesulfonate, bismethane zinc sulfonate, stannous ethanesulfonate, bismuth 2-hydroxypropanesulfonate and the like.

The carbonyl group-containing compound (B) of the present embodiment acts as an inhibitor, and specifically includes, for example, 1-naphthaldehyde, 2-naphthaldehyde, 1-naphthoic acid, 2-naphthoic acid, benzaldehyde, benzalacetone, glutaraldehyde, crotonaldehyde, 2-hydroxy-1-naphthaldehyde, 2-methoxy-1-naphthaldehyde, 2-ethoxy-1-naphthaldehyde, 4-methoxy-1-naphthaldehyde, 1-hydroxy-2-naphthaldehyde , 6-hydroxy-2-naphthaldehyde, 6-methoxy-2-naphthaldehyde and the like can be used.

The surfactant (C) of the present embodiment includes ordinary anionic surfactants, cationic surfactants, nonionic surfactants and amphoteric surfactants.

Examples of anionic surfactants include polyoxyethylene (containing 12 mol of ethylene oxide) polyoxyalkylene alkyl ether sulfate such as sodium nonyl ether sulfate, sodium polyoxyethylene (containing 12 mol of ethylene oxide) sodium dodecylphenyl ether sulfate, and the like. polyoxyalkylene alkylphenyl ether sulfates, alkylbenzenesulfonates such as sodium dodecylbenzenesulfonate, naphtholsulfonates such as sodium 1-naphthol-4-sulfonate and disodium 2-naphthol-3,6-disulfonate , (poly)alkylnaphthalenesulfonates such as sodium diisopropylnaphthalenesulfonate and sodium dibutylnaphthalenesulfonate, and alkyl sulfates such as sodium dodecyl sulfate and sodium oleyl sulfate.

Cationic surfactants include mono-trialkylamine salts, dimethyldialkylammonium salts, trimethylalkylammonium salts, dodecyltrimethylammonium salts, hexadecyltrimethylammonium salts, octadecyltrimethylammonium salts, dodecyldimethylammonium salts, octadecenyl Dimethylethylammonium salt, dodecyldimethylbenzylammonium salt, hexadecyldimethylbenzylammonium salt, octadecyldimethylbenzylammonium salt, trimethylbenzylammonium salt, triethylbenzylammonium salt, hexadecylpyridinium salt, dodecylpyridinium salt, dodecylpicolinium salt, dodecylimidazo linium salts, oleyl imidazolinium salts, octadecylamine acetate, dodecylamine acetate and the like.

Examples of nonionic surfactants include sugar esters, fatty acid esters, C ₁ -C ₂₅ alkoxyl phosphates (salts), sorbitan esters, C ₁ -C ₂₂ aliphatic amides, ethylene oxide (EO) and/or propylene oxide (PO ), silicon-based polyoxyethylene ether, silicon-based polyoxyethylene ester, fluorine-based polyoxyethylene ether, fluorine-based polyoxyethylene ester, ethylene oxide and/or propylene oxide and alkyl Examples include sulfated or sulfonated adducts of condensation products with amines or diamines.

Amphoteric surfactants include betaines, carboxybetaines, imidazolinium betaines, sulfobetaines, aminocarboxylic acids and the like.

By using the unsaturated carboxylic acid (D) of the present embodiment together with the carbonyl group-containing compound (B), the growth of the plating film formed in the via is suppressed, the plating film is formed uniformly and densely, and the plating film It has the function of flattening the top surface. Examples of unsaturated carboxylic acids include methacrylic acid, crotonic acid, acrylic acid, and maleic acid.

The plating solution of the present embodiment may contain complexing agents, antioxidants, and the like in addition to the above components (A) to (D). When the plating solution contains a noble metal such as silver, the complexing agent stabilizes the noble metal ions and the like in the bath and homogenizes the composition of the precipitated alloy. Antioxidants are also used to prevent oxidation of soluble stannous salts to stannic salts.

Moreover, in this embodiment, organic acids and inorganic acids other than the unsaturated carboxylic acid (D), or salts thereof may be contained. Examples of the above organic acids include organic sulfonic acids such as alkanesulfonic acids, alkanolsulfonic acids and aromatic sulfonic acids, or aliphatic carboxylic acids. acid, hydrochloric acid, sulfuric acid, nitric acid, perchloric acid and the like. The salts include alkali metal salts, alkaline earth metal salts, ammonium salts, amine salts, sulfonates, and the like. The component is preferably an organic sulfonic acid from the viewpoint of the solubility of metal salts and ease of wastewater treatment.

As the alkanesulfonic acid, those represented by the chemical formula C _n H _2n+1 SO ₃ H (eg, n = 1 to 5, preferably 1 to 3) can be used. Specifically, methanesulfonic acid, ethane Sulfonic acid, 1-propanesulfonic acid, 2-propanesulfonic acid, 1-butanesulfonic acid, 2-butanesulfonic acid, pentanesulfonic acid, hexanesulfonic acid, decanesulfonic acid, dodecanesulfonic acid and the like.

As the alkanolsulfonic acid, those represented by the chemical formula C _p H _2P+1 --CH(OH)--C _q H _2q --SO ₃ H (for example, p=0 to 6, q=1 to 5) can be used. Specifically, in addition to 2-hydroxyethane-1-sulfonic acid, 2-hydroxypropane-1-sulfonic acid, 2-hydroxybutane-1-sulfonic acid, 2-hydroxypentane-1-sulfonic acid and the like, 1 - hydroxypropane-2-sulfonic acid, 3-hydroxypropane-1-sulfonic acid, 4-hydroxybutane-1-sulfonic acid, 2-hydroxyhexane-1-sulfonic acid, 2-hydroxydecane-1-sulfonic acid, 2 -Hydroxydodecane-1-sulfonic acid and the like.

The aromatic sulfonic acid is basically benzenesulfonic acid, alkylbenzenesulfonic acid, phenolsulfonic acid, naphthalenesulfonic acid, alkylnaphthalenesulfonic acid, etc. Specifically, 1-naphthalenesulfonic acid, 2-naphthalene Sulfonic acid, toluenesulfonic acid, xylenesulfonic acid, p-phenolsulfonic acid, cresolsulfonic acid, sulfosalicylic acid, nitrobenzenesulfonic acid, sulfobenzoic acid, diphenylamine-4-sulfonic acid and the like.

Examples of the aliphatic carboxylic acid include acetic acid, propionic acid, butyric acid, citric acid, tartaric acid, gluconic acid, sulfosuccinic acid, and trifluoroacetic acid.

Further, the predetermined soluble metal salt (A) can be used singly or in combination, and the content in the plating solution is preferably 30 g/L to 100 g/L, more preferably 40 g/L to 60 g/L. More preferred. If the content is too less than the lower limit, the productivity tends to drop, and if the content exceeds the upper limit, the cost of the plating solution tends to rise.

The carbonyl group-containing compound (B) can be used singly or in combination, and the content in the plating solution is preferably 0.005 g/L to 50 g/L, and is 0.01 g/L to 10 g/L. is more preferred. If the content is less than the lower limit, the electrical conductivity tends to be low and the voltage tends to rise.

The surfactant (C) can be used singly or in combination, and the content in the plating solution is preferably 0.1 g/L to 50 g/L, more preferably 5 g/L to 20 g/L. . If the content is too less than the lower limit, or if the content exceeds the upper limit, a uniform plating film may not be formed.

The unsaturated carboxylic acid (D) can be used singly or in combination, and the content in the plating solution is preferably 0.05 g/L to 50 g/L, and is 0.5 g/L to 20 g/L. is more preferred. If the content is too less than the lower limit, it may not be possible to reduce the height variation of the tin-based bumps after reflow, and if the content exceeds the upper limit, the appearance of the plating film may be poor.

The addition concentration of each of the above components (A) to (D) is arbitrarily adjusted and selected according to the plating method such as barrel plating, rack plating, high-speed continuous plating, rackless plating, and bump plating.

[Plating method of the present embodiment]
Next, the plating method of this embodiment will be described. A characteristic configuration of the plating method of the present embodiment is to change the stirring speed of the plating solution and the current density of the plating during plating. The temperature of the electroplating solution of the present embodiment is preferably 70°C or less, more preferably 10°C to 40°C. The electroplating apparatus of this embodiment can adjust the current density in the range of 0.1 A/dm ² to 100 A/dm ² when forming the plating film. Hereinafter, the unit of current density, A/dm ^{2 ,} may be referred to as "ASD". In addition, the plating solution stirring device in the electroplating apparatus is a paddle stirring device in which a paddle provided with a plurality of stirring rods extending in the vertical direction reciprocates in the horizontal direction parallel to the surface of the substrate or silicon wafer to stir the plating solution. is. This stirring device can adjust the stirring speed in the range of 0.1 cm/second to 30 cm/second.

In this embodiment, the term “initial plating” refers to the period from the start of plating until 25% to 85% of the required plating time has passed. The time required for plating is determined according to the target film thickness of the plating film.
The low-stirring plating period is set after the initial stage of plating, and is a plating period in which the stirring speed is lower than that at the start of plating (initial stage of plating), and occupies 15% to 75% of the required plating time.
The low-current plating period is set after the initial stage of plating, and is a plating period in which the current density is lower than that at the start of plating (initial stage of plating), and occupies 15% to 75% of the time required for plating.
The high-current plating period is provided after the low-current plating period, is a plating period in which the current density is higher than that of the low-current plating period, and is 15% or less of the required plating time.
In addition, the low-agitation plating period and the low-current plating period or the high-current plating period may overlap.

(First plating method)
In the first plating method, the stirring speed of the plating solution is increased from the early stage to the middle stage of plating and decreased during the late stage of plating, and the plating current density is increased at the early stage of plating and decreased from the middle stage to the late stage of plating. Specifically, from the early stage to the middle stage of plating, the stirring speed of the plating solution is preferably in the range of 10 cm/second to 25 cm/second for strong stirring. Also, in the initial stage of plating, it is preferable to adjust the current density of plating to a range of 2 A/dm ² to 6 A/dm ² . In the latter stage of plating, it is preferable to set the stirring speed of the plating solution to a weak stirring range of 2 cm / sec to 15 cm / sec. It is preferable to adjust within the range of 1 A/dm ² to 3 A/dm ² . The stirring speed for weak stirring is preferably 10% to 50% of the stirring speed for strong stirring. In this first plating method, the late plating period corresponds to the low agitation plating period, and the middle to late plating period corresponds to the low current plating period.

(Second plating method)
In the second plating method, the stirring speed of the plating solution is increased from the early stage to the middle stage of plating, and is decreased in the late stage of plating, and the current density of the plating is increased in the early stage of plating, decreased in the middle stage of plating, and lowered in the late stage of plating. Lower than the initial stage of plating and higher than the middle stage of plating. Specifically, from the early stage to the middle stage of plating, the stirring speed of the plating solution is preferably in the range of 10 cm/sec to 15 cm/sec for strong stirring. At the initial stage of plating, it is preferable to adjust the current density of plating to the range of 2 A/dm ² to 6 A/dm ² . Further, in the middle stage of plating, it is preferable to adjust the current density of plating to a range of 1 A/dm ² to 3 A/dm ² , which is lower than the current density in the initial stage of plating. Furthermore, in the latter stage of plating, the stirring speed ^of the plating solution is preferably set to a weak stirring range of 2 cm/sec to 15 cm/sec. It is preferred to adjust to the range of dm ² . In this second plating method, the latter period of plating corresponds to the low agitation plating period, the middle period of plating corresponds to the low current plating period, and the latter period of plating corresponds to the high current plating period.

An example of this first plating method will be described with reference to the drawings. As shown in FIG. 1(a), a substrate 10 with vias is prepared in which a solder resist layer 12 and a dry film resist layer 14 are formed on a substrate 11. As shown in FIG. The copper seed layer shown in FIG. 3 is omitted and not shown. This substrate with vias 10 has a small-diameter first via 16a and a large-diameter second via 16b. The via diameter is not particularly limited.

As shown in FIG. 1B, from the initial stage to the middle stage of plating, under the above plating conditions, the plating film 17a grows uniformly in the first via 16a with a small diameter, and the top surface of the plating film 17a becomes flat. On the other hand, a recess R is formed on the upper surface of the plated film 17b in the large-diameter second via 16b. As shown in FIG. 1(c), in the subsequent plating stage, the plated film 17a grows smoothly in the small-diameter first via 16a under the above-described plating conditions, and the upper surface of the plated film 17a becomes convex. On the other hand, in the large-diameter second via 16b, the depth of the recess R formed on the upper surface of the plating film 17b is reduced.
Here, the case where two types of vias with different via diameters, that is, the first via 16a with a small diameter and the second via 16b with a large diameter, are formed. Different vias may be formed on the substrate or silicon wafer.

[Substrate with Via and Silicon Wafer with Via According to the Present Embodiment]
In the substrate with vias of the present embodiment, the recess depth of the upper surface of the tin-based plating film formed in the plurality of vias on the substrate is 4.0 μm or less, and the tin-based plating film is formed by reflowing the tin-based plating film. Variation in bump height is 9.5% or less.
The silicon wafer with vias of the present embodiment has a recess depth of 4.0 μm or less on the upper surface of the tin-based plating film formed in the plurality of vias on the silicon wafer, and is formed by reflowing the tin-based plating film. Variation in height of tin-based bumps is 9.5% or less.
According to the substrate with vias or silicon wafer with vias of the present embodiment, the recess depth of the upper surface of the tin-based plating film formed in the plurality of vias of the substrate or silicon is small, and the height of the tin-based bumps after reflow is can be made uniform.
The recess depth is preferably 2.5 μm or less, more preferably 2.0 μm or less. The height variation of the tin-based bumps is more preferably 9.0% or less, and even more preferably 8.0% or less.

Next, examples of the present invention will be described in detail together with comparative examples.

<Bath preparation and composition of plating solution>
Three types of plating solutions, Sn plating solution, SnAg plating solution and SnCu plating solution, used in Examples and Comparative Examples were prepared as described below.

(Sn plating solution bath preparation)
An aqueous Sn methanesulfonic acid solution is mixed with methanesulfonic acid as a free acid and catechol as an antioxidant to form a uniform solution, and then polyoxyethylene laurylamine and a carbonyl group-containing compound as surfactants. 1-naphthaldehyde was added as a solvent and isopropanol was added as a solvent. Finally, deionized water was added to prepare a Sn plating solution having the following composition. The Sn methanesulfonic acid aqueous solution was prepared by electrolyzing a metal Sn plate in the methanesulfonic acid aqueous solution.

(Composition of Sn plating solution)
Sn methanesulfonate (as Sn ²⁺ ): 60 g/L
Methanesulfonic acid (as free acid): 120 g/L
Catechol: 0.9g/L
Polyoxyethylene laurylamine: 15 g/L
1-naphthaldehyde: 0.05g/L
Crotonic acid: 1.8g/L
Isopropanol: 5g/L
Deionized water: balance

(SnAg plating solution bath preparation)
Methanesulfonic acid as a free acid, catechol as an antioxidant, and thiourea as a complexing agent were mixed and dissolved in an aqueous solution of Sn methanesulfonate, and then an aqueous solution of Ag methanesulfonate was added and mixed. . After mixing to form a uniform solution, polyoxyethylene laurylamine as a surfactant, benzaldehyde as a carbonyl group-containing compound, and isopropanol as a solvent were added. Finally, deionized water was added to prepare a SnAg plating solution having the following composition. The Sn methanesulfonic acid aqueous solution was prepared by electrolyzing the metal Sn plate, and the methanesulfonic acid Ag aqueous solution was prepared by electrolyzing the metal Ag plate in the methanesulfonic acid aqueous solution.

(Composition of SnAg plating solution)
Sn methanesulfonate (as Sn ²⁺ ): 80 g/L
Ag methanesulfonate (as Ag ⁺ ): 1.0 g/L
Methanesulfonic acid (as free acid): 150 g/L
Catechol: 1g/L
Thiourea: 2g/L
Polyoxyethylene laurylamine: 15 g/L
Benzaldehyde: 0.01g/L
Methacrylic acid: 3.5g/L
Isopropanol: 5g/L
Deionized water: balance

(Bath making of SnCu plating solution)
Methanesulfonic acid as a free acid, catechol as an antioxidant, and thiourea as a complexing agent were mixed and dissolved in an aqueous solution of Sn methanesulfonate, and then an aqueous solution of Cu methanesulfonate was added and mixed. . After mixing to form a uniform solution, polyoxyethylene laurylamine as a surfactant, 2-hydroxy-1-naphthaldehyde as a carbonyl group-containing compound, and isopropanol as a solvent were added. Finally, deionized water was added to prepare a SnCu plating solution having the following composition. The Sn methanesulfonic acid aqueous solution was prepared by electrolyzing a metal Sn plate, and the methanesulfonic acid Cu aqueous solution was prepared by electrolyzing a metal Cu plate in an aqueous methanesulfonic acid solution.

(Composition of SnCu plating solution)
Sn methanesulfonate (as Sn ²⁺ ): 80 g/L
Cu methanesulfonate (as Cu ²⁺ ): 1.5 g/L
Methanesulfonic acid (as free acid): 150 g/L
Catechol: 1g/L
Thiourea: 4g/L
Polyoxyethylene laurylamine: 15 g/L
2-hydroxy-1-naphthaldehyde: 0.01 g / L
Methacrylic acid: 1.8g/L
Isopropanol: 5g/L
Deionized water: balance

<Example 1>
As shown in FIG. 2A, on the surface of a silicon wafer (8 inches) 21, a base layer 21a composed of a titanium layer with a thickness of 100 nm and a copper layer with a thickness of 500 nm was formed by sputtering. Next, after applying a solder resist to form a solder resist layer 22 having a thickness of 5 μm, the resist layer was opened with an exposure machine to form a solder resist pattern. Electroless copper plating was applied to the solder resist layer 22 having an opening diameter of 15 μm to form a copper seed layer 23, which was electrically connected to the underlying layer 21a. Next, a dry film resist was applied to the surface of the copper seed layer 23 to form a dry film resist layer 24 having a thickness of 56 μm. Further, the dry film resist layer 24 is partially exposed through an exposure mask, and then developed, so that the first via 26a has a via diameter of 35 μm and the second via 26b has a via diameter of 35 μm. A silicon wafer 20 with vias of 75 μm was obtained. Although one first via 26a and one second via 26b are shown in FIG. 2(a), there are 1000 first vias 26a and 1000 second vias 26b on this silicon wafer. A total of 2000 were formed.

Using the Sn plating solution described above, the silicon wafer 20 with vias is immersed in a plating device (dip-type paddle stirrer) according to the “first plating method”, and the temperature of the plating solution is 25° C. under the following conditions. Then, electrotin plating is performed to form plating films 27a and 27b having a target thickness of 35 μm inside the first via 26a and the second via 26b of this silicon wafer with vias, respectively, as shown in FIG. 2(b). bottom.

(1) Current density for 6.5 minutes at the beginning of plating: 3ASD
Stirring speed of plating solution (reciprocating speed of paddle): 11 cm/sec for strong stirring (2) 10 minutes in the latter part of plating Current density: 1 ASD
Stirring speed of plating solution (reciprocating speed of paddle): 5 cm/sec for weak stirring shown in In Table 1, under the conditions indicated as "-" in the middle period of plating, there is no middle period of plating. was processed and completed.

<Examples 2 to 6, Comparative Examples 1 to 5>
A plating film was formed in the same manner as in Example 1, except that the plating solution, first and second via diameters, stirring speed, current density, and plating time were changed to the conditions shown in Table 1. In Comparative Examples 1 to 3, plating films were formed under a single condition without distinguishing between the early, middle and late stages of plating.

<Comparative test and evaluation>
Variations in (i) the recess depth of the top surface of the plating film and (ii) the bump height after reflowing the silicon wafers with vias in 11 types of silicon wafers with vias of Examples 1 to 6 and Comparative Examples 1 to 5 are as follows. It was measured by the method of These results are shown in Table 2 below.

(i) Recess depth of the top surface of the plating film 15 vias were randomly selected from the first vias and the second vias on the silicon wafer with vias before reflow, and the recess depths of these vias were measured. . The depth of the recess on the upper surface of the plating film formed in these vias was measured with a laser microscope, and the average value was calculated. Specifically, the recess depth was defined as the difference between the height of the central portion of the surface of the plating film and the height of the end portions of the plating film. When this average value was 4.0 μm or less, it was judged as “good”, and when it exceeded 4.0 μm, it was judged as “poor”.

(ii) Variation in bump height after reflow After reflowing the silicon wafer with vias, the height of the tin-based bump formed from the plating film was measured with a laser microscope. 1000 points were measured for each of the two types of diameters of the first via and the second via, and the variation in tin-based bump height was calculated by the following formula. In addition, the variation in the height of the tin-based bumps was calculated in the same manner for the entire via including the first via and the second via. The height of the tin-based bump was the distance from the base layer to the top of the bump (the highest point). In the following formula, the maximum tin-based bump height is defined as "maximum height," the minimum tin-based bump height is defined as "minimum height," and the average tin-based bump height is defined as "average height."" When this variation was 9.5% or less, it was judged as "good", and when it exceeded 9.5%, it was judged as "poor".
Bump height variation (%) = (maximum height - minimum height) / (2 x average height) x 100

As is clear from Table 2, in Comparative Example 1, in which the via diameter of the first via and the via diameter of the second via were both the same, 75 μm, strong stirring was continued during plating. The height variation of the tin-based bumps formed from the first via and the second via was small, 8.9% and 8.7%, which was good. The average value of the recess depth was 4.1 μm and 4.4 μm, which were deep and unsatisfactory.

In Comparative Example 2, in which the diameter of the first via was 50 μm and the diameter of the second via was 75 μm, weak stirring was continued during plating. The average value of the recess depth on the upper surface of the plating film formed inside each via was shallow at 0.7 μm and 1.2 μm, which was satisfactory. The variation was as large as 16.2% and 12.2%, which was unsatisfactory.

In Comparative Example 3, in which the diameter of the first via was 35 μm and the diameter of the second via was 75 μm, strong stirring was continued during plating. The height variations of the tin-based bumps formed from the vias are small, 9.4% and 8.3%, which are favorable. The average value of the recesses was as shallow as 1.7 μm, which was good, but the average depth of the recesses on the top surface of the plating film formed inside both the large-diameter second vias was as deep as 5.8 μm, which was unsatisfactory. .

In Comparative Example 4, in which both the via diameter of the first via and the via diameter of the second via were the same, 75 μm, the current density was kept constant during plating. The average value of the recess depth on the upper surface of the plating film formed inside each of the vias was 1.8 μm and 1.6 μm, which were good and shallow. , 9.6% and 9.8%.

In Comparative Example 5, in which both the via diameter of the first via and the via diameter of the second via were the same, 75 μm, the current density was kept constant during plating. The average value of the recess depth on the upper surface of the plating film formed inside each of the vias was 2.1 μm and 2.4 μm, which were good and shallow. , 9.9% and 10.3%.

On the other hand, in Examples 1 to 6, the plating solution of the first aspect of the present invention was used and the plating conditions of the first aspect were satisfied. Even if the via diameters of the vias are the same or different, the average value of the recess depth on the upper surface of the plating film formed inside each of the first via and the second via is within the range of 0.7 μm to 2.2 μm. It was shallow and good. Also, the variation in the height of the bumps formed from inside the two vias was within the range of 6.1% to 8.8%, which was good and small. In the entire via, the bump height variation was in the range of 6.9% to 9.2%, which was small and favorable.

The plating method of the present invention can be used to form bumps on substrates such as printed circuit boards, flexible printed circuit boards, film carriers and semiconductor integrated circuits, and to form bumps on silicon wafers.

10 substrate with vias 11 substrate 12 solder resist layer 14 dry film resist layers 16a, 16b vias 17a, 17b plating film

Claims (3)

In a plating method for forming a tin-based plating film on each of a plurality of vias on a substrate or silicon wafer,
The plating solution used in the plating method contains at least a soluble salt (A) containing a stannous salt, a carbonyl group-containing compound (B), a surfactant (C), and an unsaturated carboxylic acid (D). including
A low stirring plating period in which the stirring speed of the plating solution is lower than that at the start of plating,
A plating method characterized by providing a low-current plating period in which the current density of plating is lower than that at the start of plating. 2. The plating method according to claim 1, wherein a high-current plating period is provided after said low-current plating period, wherein the plating current density is higher than that of said low-current plating period. 3. The plating method according to claim 1, wherein said plurality of vias are composed of a plurality of types of vias having different via diameters.

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