JP7273383B2 - Scheduling method and scheduling device - Google Patents

Description

The present invention relates to a scheduling method and a scheduling apparatus that use FPGAs in time division.

2. Description of the Related Art In network communication equipment, there have been an increasing number of cases where communication equipment is realized using virtualization technology such as NFV (Network Function Virtualization). In virtualization technology, there are increasing cases of implementing communication devices using container technology, which is lighter than virtual machines.

On the other hand, virtualization technology runs on general-purpose servers, not dedicated hardware. By processing on the Central Processing Unit), problems such as a decrease in processing speed become apparent, and some processing is offloaded to GPUs (Graphics Processing Units) and FPGAs (Field Programmable Gate Arrays) instead of CPUs. However, the number of cases where it is used as one of the solutions to the problem is increasing.

When considering using an FPGA for various functions, it is sufficient to simply create circuit information for use in each function and prepare FPGAs with the circuit information set for the various functions. Especially when communication equipment is configured with containers and the number of types of functions (containers) becomes enormous, the cost is too high.

In general, when an FPGA is shared by multiple processes (containers), it is possible to physically divide the area or divide the usage time (time division). When the scale of the circuit to be used is large, the cost is still required, and the latter, for example, the task scheduling method of the CPU, for example, is problematic if it is simply used.

Patent Literature 1 discloses a mechanism for providing access to FPGAs as a service. Provisioning management for shared FPGA usage is described. When receiving a design package, which is the contents of the FPGA circuit from the user, a management payload is given, and a user key that conforms to the management payload is given and compiled, thereby managing user authentication and the start and end of use, Multiple users can share an FPGA as a service.

Japanese Patent Publication No. 2015-507234

However, when shared by a plurality of processes, the usage time of each process is short, so the method described in Patent Document 1 cannot be used as a management method in such a case. In addition, problems that may arise when simply using task scheduling of the CPU can be discussed in, for example, the round-robin method. FIG. 2(a) shows the processes in the task queue at a given time. The process time is the time from the start of execution of the function executed on the FPGA to the end. For example, when these processes are executed in a round robin method with a time quantum of 5, they are executed as shown in FIG. This is because the FPGA requires time to set the compiled circuit information binary file placed on the server host to the FPGA (for example, in OpenCL, the execution time of clCreateProgramWithBinary, clCreateKernel), so only the process time but also because the time of its pretreatment must be measured and taken into account.

The present invention has been made in view of such circumstances, and when a plurality of processes uses an FPGA in a time-sharing manner, scheduling is performed in consideration of the time for setting the circuit information of the process to be executed in the FPGA. It is an object to provide a method and a scheduling device.

(1) In order to achieve the above objects, the present invention takes the following measures. That is, the method of the present invention is a scheduling method in which a plurality of processes of one or a plurality of virtual communication devices uses an FPGA in a time-sharing manner, comprising the steps of: checking the processes set in a task queue; a step of acquiring a preprocessing time set in the FPGA for a binary file of the process to be executed; determining an order of the processes to be executed when a plurality of the processes are set in the task queue; and setting the binary file of the process, which is due to be executed, in the FPGA according to the determined order and executing the process, wherein the order of the process or the predetermined time for setting and executing the process is the It is determined based on the pretreatment time for each process.

As a result, when the FPGA is used by a plurality of processes in a time-sharing manner, scheduling can be performed in consideration of the time (preprocessing time) for setting the circuit information of the process to be executed in the FPGA.

(2) Also, the method of the present invention has a step of receiving and setting a policy setting request indicating a method for determining the order of the processes or the predetermined time, wherein the order of the processes or the predetermined time is , is determined based on the set policy and the preprocessing time for each process.

This makes it possible to determine the order of the processes or the predetermined time to set and execute the processes from different perspectives for each set policy.

(3) Also, in the method of the present invention, the predetermined time is determined for each process as the sum of the preprocessing time for each process and a time quantum that is the same for all the processes.

In this way, by setting the preprocessing time + time quantum as the allocated time, even if there is a process with a long preprocessing time, the time quantum is given as the actual processing time, so that unfinished processing does not occur. no. In addition, since the process time (actual processing time) is the same for all processes, the allocated time is substantially fair.

(4) Further, in the method of the present invention, in the step of obtaining the preprocessing time, the process time for each process is further obtained, and the order of the processes is determined according to the preprocessing time and the process time for each process. It is determined based on the initial process time which is the sum.

In this way, by determining the order of processes based on the initial process time that is the sum of the pretreatment time and the process time, the turnaround time can be reduced compared to the method that does not consider the pretreatment time.

(5) In addition, in the method of the present invention, when the same process is included in the plurality of processes set in the task queue, each Calculate the initial process time of the process.

In this way, in the method of determining the order of processes based on the initial process time, which is the sum of the preprocessing time and the process time for each process, if there are multiple identical processes in the task queue, the same process By calculating the preprocessing time limited to the case of continuously executing , a more appropriate process order can be set.

(6) Further, the method of the present invention has a step of obtaining order information indicating constraints on the order of a plurality of the processes, and the order of the processes includes the obtained policy, preprocessing time for each process, and the order information.

As a result, even if processes have order restrictions, an appropriate process order can be set based on the acquired policy, preprocessing time for each process, and order information.

(7) In addition, the method of the present invention has a step of obtaining priority information indicating the priority of a plurality of the processes, and the order of the processes is the obtained policy, the previous process for each process. It is determined based on the processing time and the priority information.

As a result, even when processes have priorities, the appropriate process order can be set based on the obtained policy, the preprocessing time for each process, and the priority information.

(8) Further, in the method of the present invention, when a plurality of processes set in the task queue include a process having the same priority information, each process having the same priority information Order is determined.

As a result, even when processes have priorities and there are processes with the same priority, an appropriate process order can be set based on the obtained policy, preprocessing time for each process, and priority information.

(9) Also, in the method of the present invention, during execution of the process set in the task queue, another When a process is set in the task queue, the execution of the process being executed is suspended, and execution of the suspended process is resumed after execution of the other process.

As a result, a high-priority process can be interrupted during process execution, and an appropriate process order can be set based on the obtained policy, preprocessing time for each process, and priority information.

(10) In addition, the method of the present invention has a step of acquiring wait ranking information indicating the current execution probability of the process executed within a certain past time, When the process to be used does not exist, the binary file of the process selected based on the waiting order information is preset in the FPGA.

As a result, the binary file of the process that is likely to be set next time can be set in the FPGA in advance and waited, and the preprocessing time can be shortened when the prediction is correct.

(11) Further, the scheduling device of the present invention is a scheduling device that allows a plurality of processes of one or a plurality of virtual communication devices to use an FPGA in a time-sharing manner, comprising: a task queue storing execution instructions of the processes; The processes set in the task queue are confirmed, and if a plurality of the processes are set in the task queue, the order of the processes to be executed is determined, and the order of execution arrives according to the determined order. a scheduling unit that requests setting of the binary file of the process to the FPGA and executes the set binary file; and a binary setting unit that sets the binary file of the process requested by the scheduling unit to the FPGA. , a preprocessing measurement unit that acquires the preprocessing time set in the FPGA for the set binary file of the process, and the order of the process or the predetermined time for setting and executing the process is determined by the It is determined based on the pretreatment time for each process.

As a result, when the FPGA is used by a plurality of processes in a time-sharing manner, scheduling can be performed in consideration of the time (preprocessing time) for setting the circuit information of the process to be executed in the FPGA.

According to the present invention, when the FPGA is used by a plurality of processes in a time-sharing manner, the time-sharing is usually supported by scheduling the circuit information of the process to be executed in consideration of the time to set it in the FPGA. Even an FPGA that does not have a memory can be used in a time-sharing manner, and the resources of the FPGA can be used efficiently without increasing the cost.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing an example of the concept of virtualization of communication devices using container technology and the relationship between container technology and FPGA, which is the basis of the scheduling method and scheduling device according to the present embodiment; FIG. 2 is a conceptual diagram showing a table showing an example of the process of the conventional method and allotted time therefor; 1 is a block diagram showing an example of a schematic configuration of a scheduling device according to a first embodiment; FIG. (a) and (b) are tables respectively showing examples of information stored in a DB. FIG. 11 is a block diagram showing an example of a schematic configuration of a scheduling device according to a second embodiment; FIG. 9 is a flow chart showing an example of the operation of the scheduling device according to the second embodiment; 9 is a flow chart showing an example of the operation of the scheduling device according to the second embodiment; 4A and 4B are conceptual diagrams showing a table showing a specific example of the process of Example 1 and allocation time therefor, respectively; FIG. 4 is a table showing a specific example of the process of Example 1. FIG. FIG. 10 is a conceptual diagram showing the allocated time of Example 1 for the specific example of the process shown in FIG. 9; (a) to (c) are respectively a table showing a specific example of the process of the second embodiment, a conceptual diagram showing the order of the normal shortest job priority method, and a conceptual diagram showing the order of the shortest job priority method of the present invention. is. 8A and 8B are a table showing a specific example of the process of the third embodiment and a conceptual diagram showing the order of the shortest job priority method of the present invention, respectively; FIG. 8A and 8B are a table showing a specific example of the process of the third embodiment and a conceptual diagram showing the order of the shortest job priority method of the present invention, respectively; FIG. 11 is a flow chart showing an example of the operation of the scheduling device of Example 3; It is a table showing a specific example of the process of the fourth embodiment. FIG. 16 is a conceptual diagram showing a fourth example order and allotted times for the process embodiment shown in FIG. 15; FIG. 16 is a conceptual diagram showing a fourth example order and allotted times for the process embodiment shown in FIG. 15; FIG. 14 is a table showing a specific example of a process of a modification of the fourth embodiment; FIG. 10A and 10B are a table showing a specific example of the process of the fifth embodiment and a conceptual diagram showing the order and allocation time, respectively; FIG. FIG. 13 is a table showing a specific example of the process of the sixth embodiment; FIG.

When the FPGA is used in multiple processes in a time-sharing manner, the inventors of the present invention usually cope with the use of time-sharing by scheduling in consideration of the time for setting the circuit information of the process to be executed in the FPGA. The present inventors have found that even an FPGA that does not have a circuit can be used in a time-sharing manner, leading to the present invention.

That is, the method of the present invention is a scheduling method in which a plurality of processes of one or a plurality of virtual communication devices uses an FPGA in a time-sharing manner, comprising the steps of: checking the processes set in a task queue; a step of acquiring a preprocessing time set in the FPGA for a binary file of the process to be executed; determining an order of the processes to be executed when a plurality of the processes are set in the task queue; and setting the binary file of the process, which is due to be executed, in the FPGA according to the determined order and executing the process, wherein the order of the process or the predetermined time for setting and executing the process is the It is determined based on the pretreatment time for each process.

As a result, the inventors of the present invention have found that even an FPGA that does not normally support time-division use can be used in time-division, and FPGA resources can be efficiently used without increasing costs. bottom. Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings. In order to facilitate understanding of the description, the same reference numerals are given to the same components in each drawing, and overlapping descriptions are omitted.

[Concept of relationship between container technology and FPGA]
FIG. 1 is a diagram showing an example of the concept of virtualization of communication equipment using container technology and the relationship between container technology and FPGA, which is the basis of the scheduling method and scheduling apparatus according to the present embodiment. A virtual communication device operates by being composed of one or more containers. Each container is configured as a set of one or more processes. A virtual communication device can be, for example, a router, a firewall, a base station, a mobile core, etc., but is not limited to these. A process is a division of processing performed by a virtual communication device for each one or a plurality of functions. For example, if the virtual communication device is a router, the process may include a packet filtering function, a communication protocol managing function, etc., but is not limited to this.

Individual processes are executed by consuming hardware resources, but the resources consumed by each process are different. For example, "process-e" in FIG. 1 indicates that it is executed using the CPU. On the other hand, "process-a", "process-i", and "process-u" in FIG. It means that FIG. 1 shows a circuit in which "process-a", "process-i", and "process-u" are set to FPGAs named "binary-A", "binary-B", and "binary-C", respectively. Indicates that it corresponds to the setting.

In this way, when one binary file is set, one FPGA is used for executing processes corresponding to that binary file, and is simultaneously used for executing processes corresponding to other binary files. never Also, when the FPGA is used to execute a process corresponding to another binary file, the binary file is newly set up and then used. That is, in the present invention, when one FPGA is used for different processes, it is used in time division. A plurality of FPGAs may exist because they are managed individually.

[First Embodiment]
(Configuration of scheduling device)
FIG. 3 is a block diagram showing an example of a schematic configuration of a scheduling device according to this embodiment. Although FIG. 3 describes implementation within one server 10, each element may be implemented in a separate server. "Process-a" indicates a process of a certain virtualized network device. The FPGA 20 is an FPGA mounted in the server, and an example in which one FPGA is mounted in the server 10 will be described. The scheduling device 100 comprises a task queue 110 , a scheduling section 120 , a binary setting section 130 and a preprocessing measurement section 140 .

The task queue 110 is a place for storing execution instructions of processes processed by the FPGA 20, and the instructions stored in the task queue 110 are executed according to the policy. A policy is a standard for determining the process execution order and execution time. For example, there are criteria such as emphasizing fairness and emphasizing reduction in turnaround time. In this embodiment, it is assumed that the policy is set in advance.

The scheduler 120 checks the processes set in the task queue 110 . In this embodiment, the scheduler 120 periodically checks the task queue 110 .

When a plurality of processes are set in the task queue 110, the scheduling unit 120 determines the order of the processes to be executed, and in accordance with the determined order, sends the binary data of the processes whose execution order has arrived to the binary setting unit 130. Request the setting of the file to the FPGA 20 . Also, when one process is set in the task queue 110 , the scheduling unit 120 requests the binary setting unit 130 to set the binary file of that process to the FPGA 20 . Also, the scheduler 120 executes a binary file set in the FPGA 20 .

The order of the processes or the predetermined time (allocation time) for setting and executing the processes is determined based on the preprocessing time for each process, which will be described later. As a result, even an FPGA that does not normally support time-division use can be used in time-division, and FPGA resources can be efficiently used without increasing costs.

The binary setting unit 130 sets the binary file of the process requested by the scheduling unit 120 to the FPGA 20 . In the present invention, FPGA circuit information corresponding to one process is compiled in advance and managed as a binary file. A binary file corresponding to each process is stored in the DB50. The binary setting unit 130 acquires necessary information from the DB50.

The preprocessing measurement unit 140 acquires the preprocessing time when the binary file of the process set in the task queue 110 is set in the FPGA 20 . The preprocessing time may acquire a value set in advance for each process or for each binary file. It is preferable to use the average value of the obtained values as the pretreatment time. This is because setting the binary file for the FPGA differs in setting time depending on the circuit scale, so it is better to measure how much time it takes each time the setting is actually made, based on a more realistic preprocessing time. can determine the order of the processes or the predetermined time at which to set and execute the processes.

The measured set times are sent to a DB (database) 50, which holds at least one of the measured values up to now, their average values, average values for a predetermined number of measurements, and the like. Although the measurement method is not limited, for example, when the scheduling device 100 is configured based on OpenCL, the execution time of clCreateProgramWithBinary and clCreateKernel during binary setting can be measured as the preprocessing time.

FIGS. 4A and 4B are tables showing examples of information stored in the DB 50, respectively. The DB 50 stores the binary file for each process, the preprocessing time for each process measured by the preprocessing measurement unit 140, the process time for each process, and the initial processing time (initial processing time) that is the sum of the preprocessing time and the process time for each process. and other information is stored. In addition, order information indicating restrictions on the order of a plurality of processes used in an embodiment described later, priority information indicating the priority of a plurality of processes, current status of processes executed within a certain time in the past. Information necessary for coping with various policies, such as waiting order information indicating a high possibility of execution of a task, may be stored. Information stored in the DB is updated as necessary.

[Second embodiment]
(Configuration of scheduling device)
FIG. 5 is a block diagram showing an example of a schematic configuration of a scheduling device according to this embodiment. The scheduling device 200 is composed of a task queue 110 , a scheduling section 120 , a binary setting section 130 , a preprocessing measurement section 140 and a policy design section 210 . The functions of the task queue 110, the scheduling unit 120, the binary setting unit 130, and the preprocessing measurement unit 140 are the same as those of the first embodiment, and thus description thereof is omitted.

The policy design unit 210 sets a policy indicating how to determine the predetermined time for setting and executing the process order or the binary file of the process in the FPGA 20 . The policy design unit 210 is a functional unit that the user requests to set what is to be emphasized in process scheduling.

The scheduling apparatus 200 includes the policy design unit 210 so that the user can set a policy that the user places importance on, and the user can select a policy according to the process to be processed by the FPGA 20 and the amount of processing.

(Description of an example of operation)
Next, an example of the operation of the scheduling apparatus according to this embodiment will be described using the flowcharts of FIGS. 6 and 7. FIG. 6 and 7 are flowcharts showing an example of the operation of the scheduling device according to this embodiment.

6 and 7 include functional units, DBs, and user setting requests that make up the scheduling apparatus. Each functional unit takes charge of obtaining information from the DB. First, a user requests the scheduling device to set a policy (step S1). Next, the policy design unit determines the time to consider according to the set policy (step S2). The time to consider (consideration time) includes at least the preprocessing time. For example, it is possible to decide whether to consider the preprocessing time or the initial processing time, which is the sum of the preprocessing time and the processing time, according to the set policy. The consideration time may be any time for each policy as long as it is calculated based on the preprocessing time. Next, the policy design unit notifies the schedule unit of policy setting (set) (step S3).

Next, the scheduler receives the policy setting (set) (step S4) and determines the consideration time (step S5). During that time, processes are set in the task queue (step S6). Then, the task queue is checked (step S7), and if the process is set (step S8-YES), the value of the consideration time is checked in the DB (step S9). The DB receives the confirmation message of the value of the consideration time (step S10), and returns the value (step S11). Then, the scheduler determines the schedule based on the value of the consideration time (step S12). Note that the value of the consideration time includes at least the preprocessing time of the binary file corresponding to the set process. Determining the schedule also includes determining at least the order in which the processes are to be executed or the predetermined time at which the processes are to be set and executed.

Also, the task queue is checked (step S7), and if the process is not set (step S8-NO), the process returns to step S7 and the task queue is checked again.

After determining the schedule, the scheduling section determines whether or not to change the circuit information, and if so (step S13-YES), instructs the binary setting section to set the circuit of the corresponding process (step S14). Judgment whether to change the circuit information is to check and judge whether the binary file of the process to be executed is set in the FPGA. It is preferable to confirm or query the binary setting unit. Also, the setting of the circuit of the relevant process is the setting of the binary file corresponding to the relevant process.

The binary setting unit receives the instruction to set the circuit of the process (step S15), and confirms the binary (binary file) of the process in the DB (step S16). The DB receives the binary confirmation message (step S17) and returns the binary information (binary file) to the binary setting section (step S18). The binary setting unit sets the binary in the FPGA (step S19), and requests the preprocessing measurement unit to measure the binary setting time (step S20).

The preprocessing measurement unit receives the binary set time measurement request message (step S21) and starts measurement. Then, when the measurement is completed (step S22), the DB is notified of the measured value (step S23). The DB receives the measured value (step S24), calculates and stores the average value of the pretreatment time (step S25).

On the other hand, after completing the binary setting (step S26), the binary setting unit notifies the scheduling unit of the completion of the circuit setting of the corresponding process (step S27). The scheduler receives the circuit setting completion notification of the relevant process (step S28), and executes the relevant process (step S29). After execution, it is determined whether all the processes have been completed, and if completed (step S30--YES), the process ends. After the end, if the policy is not to be changed, the process may return to step S7 and check the task queue.

Also, the scheduler determines whether all the processes have been completed, and if not (step S30-NO), returns to step S13 and determines whether to change the circuit information.

Also, the scheduler determines whether or not to change the circuit information in step S13, and if not (step S13-NO), executes the corresponding process (step S29).

The scheduling device according to this embodiment can operate in this manner. It should be noted that the scheduling apparatus according to the first embodiment can also perform the same operation except that the policy design unit is not provided. It should be noted that the above description of operation is an example of operation, and the present invention is not limited to this.

In the above descriptions of the first embodiment and the second embodiment, an example in which the scheduling device is implemented in hardware was described to facilitate understanding of the description. As such, the present invention can be partially or wholly implemented in software. Also, the present invention can be implemented not only as one piece of software, but also as a processing method executed between multiple functional elements implemented on one or more servers. The same applies to the following examples.

[Example]
Next, an example will be described. In the following embodiments, the so-called round-robin method, which determines the time to allocate FPGAs to each process with an emphasis on fairness between processes, and the so-called shortest job priority method, which reduces the turnaround time, are adopted. Although an example in the case of the case will be described, the present invention is not limited to this. The present invention includes a method of scheduling in consideration of the setting time (preprocessing time) for the FPGA when the binary file of the circuit data used in each process is set in the FPGA in a time division manner.

(Example 1)
First, the method of emphasizing fairness will be explained. When the policy design unit is set to emphasize fairness, the scheduling device emphasizes substantially fair allocation of the allocated time between processes. In this case, the scheduling unit allocates the time to each process by adding the preprocessing time for each process to the time quantum common to all processes. As specific examples, the case of scheduling the process in FIG. 8A and the case of scheduling the process in FIG. 9 will be described. FIGS. 8A and 8B are conceptual diagrams showing a table showing a specific example of the process of this embodiment and allocation times, respectively. FIG. 9 is a table showing a specific example of the process of this embodiment. FIG. 10 is a conceptual diagram illustrating the allotted time for the specific example of the process shown in FIG.

For example, when scheduling the process in FIG. 8(a) with a time quantum of 5, the preprocessing time 2 + time quantum 5 is allocated to 'process-a', and the pre-processing time 5 + time is allocated to 'process-i'. Quantum 5 is assigned time 10, and "process-u" is scheduled to be assigned time 9 with preprocessing time 4+time quantum 5, and is executed as shown in FIG. 8(b).

Also, as an example where the process time is longer than the above, the case of scheduling the process in FIG. 9 will be described. For example, if the time quantum is set to 5 in the same way as above, and the process in FIG. 5+time quantum 5 is assigned time 10, and "process-u" is scheduled to be assigned time 9 with preprocessing time 4+time quantum 5, and is executed as shown in FIG.

In this way, by setting the preprocessing time + time quantum as the allocated time, even if there is a process with a long preprocessing time, the time quantum is given as the actual processing time. No unfinished processing occurs, as in the example shown in b). In addition, all processes have the same time quantum (actual processing time), so the allocated time is substantially fair.

(Example 2)
Next, a method for reducing the turnaround time will be explained. As a typical scheduling method for reducing the turnaround time, there is the shortest job priority method. Normally, in the shortest job priority method, the job with the shortest process time is preferentially executed, but in the present invention, the job with the shortest initial process time, which is the sum of the preprocessing time and the process time, is preferentially executed. be.

As a specific example, the case of scheduling the process of FIG. 11(a) will be described. 11A to 11C respectively show a table showing a specific example of the process of this embodiment, a conceptual diagram showing the order of the normal shortest job priority system, and the order of the shortest job priority system of the present invention. It is a conceptual diagram. In the normal shortest job priority method, the job with the shortest process time is preferentially executed. It is executed in the order of "process-u" and "process-a". The turnaround time in this case is (7+13+18)/3≈12.67. On the other hand, in the shortest job priority method of the present invention, the job having the shortest initial process time, which is the sum of the preprocessing time and the process time, is preferentially executed. Therefore, the process in FIG. 11A is executed in the order of "process-a", "process-u", and "process-i". The turnaround time in this case is (5+11+18)/3≈11.33.

In this way, by preferentially executing the process with the shortest initial process time, which is the sum of the pretreatment time and the process time, the turnaround time can be reduced compared to the method that does not consider the pretreatment time.

(Example 3)
Next, in the method of reducing the turnaround time, a method will be described in which a plurality of identical processes are contained in the task queue. When the same process is included in the plurality of processes set in the task queue, it is preferable to calculate the initial process time of each process only when the same process is executed continuously. In other words, if there are multiple identical processes in the task queue, add up the time at which each process ends in the other combinations, excluding those in which the same processes are not consecutive, from the combination of the order of each process. , the pattern with the smallest total value is scheduled.

As specific examples, the case of scheduling the process in FIG. 12(a) and the case of scheduling the process in FIG. 13(a) will be described. 12(a) and 12(b) are respectively a table showing a specific example of the process of this embodiment and a conceptual diagram showing the order of the shortest job priority method of the present invention. Assume that the task queue has "process - ah, ah, ah, ah". At this time, the initial process time of each process when two "processes" are executed in succession is calculated. Then, the initial process time for "process-a" is 5, the first process time for the first "process-i" is 7, the first process time for the second "process-i" is 9, and the first process time for "process-i" is 9. , the initial process time is 6. However, the two "processes" are executed consecutively. At this time, there are six possible orders: "I agree," "I agree," "I agree," "I agree," "I agree," and "I agree." The order in which the around time is the shortest is "matching" shown in FIG. 11, and its value is 12.5.

Consecutive processes, on the other hand, do not necessarily have shorter turnaround times if they are executed first. The process shown in FIG. 13(a) is a process in which the pretreatment time of "process-i" in FIG. 12(a) is changed to 10. FIG. When scheduling the process shown in Figure 13(a), the possible order is the same as above: , "good", and the order with the shortest turnaround time is "good" shown in FIG. 13(b).

(Example of operation of embodiment 3)
An example of the operation of Example 3 will be described with reference to the flowchart of FIG. 14 is a flowchart illustrating an example of the operation of the scheduling device according to the third embodiment; FIG. First, the task queue is checked (step T1). Next, it is checked whether or not the same process exists in the task queue. If the same process does not exist (step T2-NO), the processes are sorted in ascending order of initial process time (step T3), and the processes are executed in that order ( Step T8), the process ends when all the processes are executed.

On the other hand, it is checked whether or not the same process exists in the task queue, and if the same process exists (step T2--YES), the process order pattern is calculated (step T4). Next, discontinuous identical processes are excluded from the calculated order patterns (step T5), and the total value of the process end times of the calculated order patterns is calculated (step T6). Then, the calculated total values are rearranged in ascending order (step T7), the processes are executed in that order (step T8), and the process ends when all the processes have been executed.

In this way, in the method of reducing the turnaround time, the turnaround time can be reduced by considering the preprocessing time even when the task queue contains a plurality of identical processes.

(Example 4)
Consideration of preprocessing time and the like can also be utilized when taking into consideration order restrictions and priorities between processes when applying FPGA time division. For example, by providing priority values (priority information) as shown in FIG. 15, it is possible to express order restrictions and priorities between processes. In the example of FIG. 15, the larger the priority value, the higher the priority, and "process-a" and "process-u" are executed after "process-i". For example, when this is executed with round robin and time quantum 5, as shown in Fig. 16, the time quantum plus the preprocessing time is assigned to each, and "process-i" is executed first. Become.

Also, when the processes in the task queue are as shown in FIG. 15 and the shortest job is prioritized, the processes are executed as shown in FIG.

In this way, the order of processes when processes have priorities is determined based on the set policy, preprocessing time for each process, and priority information. As a result, even when processes have priorities, the appropriate process order can be set based on the obtained policy, the preprocessing time for each process, and the priority information.

Further, when a plurality of processes set in the task queue include processes having the same priority information, it is preferable that the order of the processes is determined for each process having the same priority information. As a result, even when processes have priorities and there are processes with the same priority, an appropriate process order can be set based on the obtained policy, preprocessing time for each process, and priority information.

(Modification of Example 4)
In the case of the priority values shown in FIG. 15, there are differences in priority, including the same value, among all processes, and this can be used to express order constraints, but only among some processes. Order information indicating order constraints may be provided. For example, the process shown in FIG. 18 indicates that the process must be executed in numerical order of the order information, "process-a" indicates execution after "process-i", and "process "-u" indicates that it can be executed at any stage before "process-i", between "process-i" and "process-a", or after "process-a".

Thus, the order of processes when there is order information is determined based on the set policy, the preprocessing time for each process, and the order information. As a result, even if processes have order restrictions, an appropriate process order can be set based on the acquired policy, preprocessing time for each process, and order information.

(Example 5)
Even when the preemption (stopping the running process and executing the high priority process when a high priority task newly arrives in the task queue) method is selected, the time division of the FPGA For application, it is necessary to consider the pretreatment time and the like. For example, when the shortest job priority method is selected and the "process" arrives late as shown in FIG. 19(a) and preemption is performed, the process is executed as shown in FIG. 19(b). However, it should be noted that this embodiment is slightly different from the flow charts of FIGS. According to the flow charts of FIGS. 6 and 7, after executing "process-a, u" with an arrival time of 0, the task queue is checked, so the arrival of "process-i" is not noticed.

Therefore, in order to execute as shown in FIG. 19(b), periodic confirmation of the task queue should be performed independently of process execution, or it should be confirmed that a high-priority process has entered the task queue (task queue etc.) must inform the scheduler.

(Example 6)
Next, a method of shortening the processing time of a process by setting some circuit information (binary file) in the FPGA and waiting while there is no process using the FPGA will be described. Preprocessing time can be reduced by setting the circuit information of the process using the FPGA to be executed next in the FPGA and waiting.

Therefore, the waiting order information as shown in FIG. 20 is newly provided in the DB. This holds information about which process was called how many times per fixed time in the past, and further holds the value obtained by multiplying it by the preprocessing time as a weight. A large weight means that the preprocessing time that is frequently used or becomes a bottleneck is large, and the one with the highest priority is set as the waiting time of the FPGA. This method is also useful when there are a plurality of FPGAs. For example, when there are two FPGAs, the 1st binary is set to the first FPGA, and the 2nd binary is set to the second FPGA. By waiting for a long time, the turnaround time can be reduced more efficiently. Note that this method is effectively used in a method for reducing turnaround time, but even when it is executed in round robin, it is effective at least in the sense that the initial preprocessing time is shortened.

INDUSTRIAL APPLICABILITY As described above, the scheduling method and scheduling apparatus of the present invention allow scheduling in consideration of the time for setting the circuit information of the process to be executed in the FPGA when the FPGA is used in a time-sharing manner for a plurality of processes. Therefore, even an FPGA that does not normally support time-division use can be used in time-division, and FPGA resources can be used efficiently without increasing costs.

10 server 20 FPGA
50 DB
100, 200 scheduling device 110 task queue 120 scheduling unit 130 binary setting unit 140 preprocessing measurement unit 210 policy design unit

Claims (10)

A scheduling method for using an FPGA in a time division manner in a plurality of processes of one or more virtual communication devices,
verifying the processes set in a task queue;
obtaining a preprocessing time at which the set binary file of the process is set in the FPGA;
determining the order of the processes to be executed when a plurality of the processes are set in the task queue;
setting the binary file of the process, which has reached the order to be executed, in the FPGA according to the determined order and executing it;
The allotted time for setting the binary file of the process to the FPGA and executing it is determined for each process as the sum of the preprocessing time for each process and a time quantum that is the same for all the processes. Method. A scheduling method for using an FPGA in a time division manner in a plurality of processes of one or more virtual communication devices,
verifying the processes set in a task queue;
obtaining a preprocessing time at which the set binary file of the process is set in the FPGA;
determining the order of the processes to be executed when a plurality of the processes are set in the task queue;
setting the binary file of the process, which has reached the order to be executed, in the FPGA according to the determined order and executing it;
In the step of acquiring the preprocessing time, further acquiring the process time for each process;
The method, wherein the order of the processes is determined based on an initial process time which is the sum of the pretreatment time and the process time for each process. A scheduling method for using an FPGA in a time division manner in a plurality of processes of one or more virtual communication devices,
receiving and setting a policy setting request indicating how to determine the order of the processes or the allotted time for setting and executing the binary files of the processes on the FPGA;
verifying the processes set in a task queue;
obtaining a preprocessing time at which the set binary file of the process is set in the FPGA;
obtaining order information indicating a constraint on the order of some of the processes among the plurality of processes;
determining the order of the processes to be executed when a plurality of the processes are set in the task queue;
setting the binary file of the process, which has reached the order to be executed, in the FPGA according to the determined order and executing it;
The method, wherein the order of the processes is determined based on the set policy, the consideration time including the preprocessing time for each process, and the order information . A scheduling method for using an FPGA in a time division manner in a plurality of processes of one or more virtual communication devices,
verifying the processes set in a task queue;
obtaining a preprocessing time at which the set binary file of the process is set in the FPGA;
determining the order of the processes to be executed when a plurality of the processes are set in the task queue;
a step of setting a binary file of the process whose execution order has arrived in the FPGA according to the determined order and executing it;
obtaining wait ranking information indicating the current execution probability of the process that was executed within a certain period of time in the past;
The order of the processes or the allocated time for setting and executing the binary files of the processes in the FPGA is determined based on the consideration time including the preprocessing time for each process ,
A method, wherein a binary file of the process selected based on the waiting order information is preset in the FPGA when the process using the FPGA does not exist. When the same process is included in the plurality of processes set in the task queue, the initial process time of each process is calculated only when the same process is executed continuously. 3. A method as claimed in claim 2 . Acquiring waiting order information indicating the current execution probability of the process that was executed within a certain time in the past;
4. The method according to any one of claims 1 to 3 , wherein when the process using the FPGA does not exist, the binary file of the process selected based on the waiting order information is preset in the FPGA. The method described in . A scheduling device that allows multiple processes of one or more virtual communication devices to use an FPGA in a time-sharing manner,
a task queue storing execution instructions of the process;
confirming the processes set in the task queue, determining the order of the processes to be executed when a plurality of the processes are set in the task queue, and determining the order of execution according to the determined order; a scheduling unit that requests setting of the binary file of the process that has arrived to the FPGA and executes the set binary file;
a binary setting unit that sets the binary file of the process requested by the schedule unit in the FPGA;
a preprocessing measurement unit that acquires the preprocessing time set in the FPGA by the binary file of the set process,
The allotted time for setting the binary file of the process to the FPGA and executing it is determined for each process as the sum of the preprocessing time for each process and a time quantum that is the same for all the processes. scheduling device. A scheduling device that allows multiple processes of one or more virtual communication devices to use an FPGA in a time-sharing manner,
a task queue storing execution instructions of the process;
confirming the processes set in the task queue, determining the order of the processes to be executed when a plurality of the processes are set in the task queue, and determining the order of execution according to the determined order; a scheduling unit that requests setting of the binary file of the process that has arrived to the FPGA and executes the set binary file;
a binary setting unit that sets the binary file of the process requested by the schedule unit in the FPGA;
a preprocessing measurement unit that acquires the preprocessing time set in the FPGA by the binary file of the set process,
The scheduler obtains a process time for each process,
The scheduling apparatus, wherein the order of the processes is determined based on an initial process time that is the sum of preprocessing time and process time for each process. A scheduling device that allows multiple processes of one or more virtual communication devices to use an FPGA in a time-sharing manner,
a policy design unit for setting a policy indicating a method for determining the allocation time for setting and executing the order of the processes or the binary files of the processes in the FPGA;
a task queue storing execution instructions of the process;
confirming the processes set in the task queue, determining the order of the processes to be executed when a plurality of the processes are set in the task queue, and determining the order of execution according to the determined order; a scheduling unit that requests setting of the binary file of the process that has arrived to the FPGA and executes the set binary file;
a binary setting unit that sets the binary file of the process requested by the schedule unit in the FPGA;
a preprocessing measurement unit that acquires the preprocessing time set in the FPGA by the binary file of the set process,
The scheduling unit acquires order information indicating constraints on the order of some of the processes among the plurality of processes,
The scheduling device, wherein the order of the processes is determined based on the set policy, the consideration time including the preprocessing time for each process, and the order information . A scheduling device that allows multiple processes of one or more virtual communication devices to use an FPGA in a time-sharing manner,
a task queue storing execution instructions of the process;
confirming the processes set in the task queue, determining the order of the processes to be executed when a plurality of the processes are set in the task queue, and determining the order of execution according to the determined order; a scheduling unit that requests setting of the binary file of the process that has arrived to the FPGA and executes the set binary file;
a binary setting unit that sets the binary file of the process requested by the schedule unit in the FPGA;
a preprocessing measurement unit that acquires the preprocessing time set in the FPGA by the binary file of the set process,
The scheduling unit obtains waiting order information indicating a current probability of execution of the processes that were executed within a certain period of time in the past,
The order of the processes or the allocated time for setting and executing the binary files of the processes in the FPGA is determined based on the consideration time including the preprocessing time for each process ,
The scheduling device, wherein the binary setting unit presets the binary file of the process selected based on the waiting order information in the FPGA when the process using the FPGA does not exist.

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