JP2021157482A - Scheduling method and scheduling device - Google Patents

Abstract

To provide a scheduling method and a scheduling device that make schedules in consideration of time when circuit information of a process to be performed is set in an FPGA when the FPGA is used in a plurality of processes in a time division manner.SOLUTION: A scheduling method by which an FPGA is used in a time division manner in a plurality of processes of one or more virtual communication apparatuses includes the steps of: confirming processes set in a task queue; acquiring preprocessing time when binary files of the set processes are set in the FPGA; when a plurality of processes are set in the task queue, determining the order of the processes to be executed; setting in the FPGA the binary file of a process whose execution order has arrived according to the determined order, and executing the binary file. The order of processes or the predetermined time when a process is set and executed is determined based on the preprocessing time for each process.SELECTED DRAWING: Figure 3

Description

The present invention relates to a scheduling method and a scheduling device that utilize FPGA in a time division manner.

In network communication equipment, there are an increasing number of cases where communication equipment is realized by using virtualization technology as represented by NFV (Network Function Virtualization). As for virtualization technology, there are an increasing number of cases where communication devices are realized by using container technology, which is lighter than virtual machines.

On the other hand, since virtualization technology operates on a general-purpose server, etc., rather than dedicated hardware, the functions of communication devices that have been processed by ASICs (Application Specific Integrated Circuits), etc., are the functions of general-purpose CPUs (general-purpose CPUs). By processing on the Central Processing Unit), problems such as a decrease in processing speed become apparent, and some processing is offloaded to GPU (Graphics Processing Unit) or FPGA (Field Programmable Gate Array) instead of CPU. However, the number of cases where it is used as one of the solutions to the problem is increasing.

When considering the use of FPGA for various functions, it is sufficient to simply create circuit information for use in each function and prepare FPGAs for which the circuit information is set for various functions. In particular, when a communication device is configured with a container or the like and the types of functions (containers) become enormous, the method is too expensive.

Generally, when FPGA is shared by multiple processes (containers), a method of physically dividing the area or dividing the usage time (time division) can be considered, but the former is used by one process. When the scale of the circuit to be used becomes large, the cost is still high, and the latter has a problem if, for example, the task scheduling method of the CPU is simply used.

Patent Document 1 discloses a mechanism for providing access to FPGA as a service. It describes provisioning management for using shared FPGA. When a design package, which is the circuit content of the FPGA, is received from the user, a management payload is attached, and a user key that matches the management payload is assigned and compiled to manage user authentication and start / end of use. The FPGA can be shared by a plurality of users as a service.

Special Table 2015-507234

However, when sharing by a plurality of processes, the usage time of each one is short, so that the method described in Patent Document 1 cannot be used as a management method in such a case. Further, the problem that may occur when the task scheduling of the CPU is simply used can be discussed in, for example, the round robin method. FIG. 2A shows a process in the task queue at some point in time. The process time is the time from the start to the end of execution of the function executed on the FPGA. For example, when these processes are executed by the time-quantum 5 round-robin method, they are executed as shown in FIG. 2 (b), and the execution of "process-i" is indefinite. This is because FPGA requires time to set the binary file of compiled circuit information placed on the host of the server to FPGA (for example, execution time of clCreateProgramWithBinary, clCreateKernel in OpenCL), so only the process time. Not only because it is necessary to measure the time of its pretreatment and take it into account.

The present invention has been made in view of such circumstances, and when the FPGA is used in a plurality of processes in a time-divided manner, scheduling is performed in consideration of the time for setting the circuit information of the process to be executed in the FPGA. It is an object of the present invention to provide a method and a scheduling device.

(1) In order to achieve the above object, the present invention has taken the following measures. That is, the method of the present invention is a scheduling method in which the FPGA is used in a plurality of processes of one or a plurality of virtual communication devices in a time-divided manner, and is set with a step of confirming the process set in the task queue. A step of acquiring the preprocessing time set in the FPGA for the binary file of the process, and a step of determining the order of the processes to be executed when a plurality of the processes are set in the task queue. The order of the processes or the predetermined time for setting and executing the processes includes the steps of setting and executing the binary files of the processes that have arrived in the order of execution according to the determined order in the FPGA. Determined based on pre-processing time for each process.

As a result, when the FPGA is used in a plurality of processes in a time-division manner, it is possible to schedule the circuit information of the process to be executed in consideration of the time (preprocessing time) for setting the FPGA in the FPGA.

(2) Further, the method of the present invention has a step of accepting and setting a policy setting request indicating a method for determining the order of the processes or the predetermined time, and the order of the processes or the predetermined time is defined as the process. , Determined based on the set policy and pretreatment time for each process.

This makes it possible to determine the order of processes or the predetermined time for setting and executing processes from different viewpoints for each set policy.

(3) Further, in the method of the present invention, the predetermined time is determined for each process as the sum of the pretreatment time for each process and the same time quantum for all the processes.

In this way, by setting the pre-processing time + time quantum as the allocated time, even if there is a process with a long pre-processing time, the actual processing time is given by the time quantum, so processing that does not end occurs. There is no. Moreover, since the process time (actual processing time) is equal in all processes, the allocation time in a practical sense is fair.

(4) Further, in the method of the present invention, in the step of acquiring the pretreatment time, the process time for each process is further acquired, and the order of the processes is the pretreatment time and the process time for each process. Determined based on the sum of the initial process times.

In this way, by determining the process order based on the initial process time, which is the sum of the preprocessing time and the process time, the turnaround time can be reduced as compared with the method in which the preprocessing time is not considered.

(5) Further, in the method of the present invention, when the same process is included in the plurality of processes set in the task queue, each of them is limited to the case where the same process is continuously executed. Calculate the initial process time of the process.

In this way, in the method of determining the order of processes based on the initial process time, which is the sum of the preprocessing time and the process time for each process, if the same process is contained in the task queue more than once, the same process By calculating the preprocessing time only when the above is executed continuously, a more appropriate process order can be set.

(6) Further, the method of the present invention includes a step of acquiring order information indicating a plurality of restrictions on the order of the processes, and the order of the processes includes the acquired policy, the pretreatment time for each process, and the like. And it is determined based on the above-mentioned order information.

As a result, even if the process has an order constraint, an appropriate process order can be set based on the acquired policy, the preprocessing time for each process, and the order information.

(7) Further, the method of the present invention includes a step of acquiring priority information indicating the high priority of the plurality of processes, and the order of the processes is the acquired policy and the pre-process for each process. It is determined based on the processing time and the priority information.

As a result, even if the processes have priorities, the appropriate process order can be set based on the acquired policy, the preprocessing time for each process, and the priority information.

(8) Further, in the method of the present invention, when a plurality of the processes set in the task queue include a process having the same priority information, the process of the process having the same priority information is included in the process. The order is determined.

As a result, even if the processes have priorities and there are processes having the same priority, it is possible to set an appropriate process order based on the acquired policy, the preprocessing time for each process, and the priority information.

(9) Further, in the method of the present invention, another other having the priority information having a higher priority than the priority information of the running process during the execution of the process set in the task queue. When a process is set in the task queue, the execution of the running process is interrupted, and after the execution of the other process, the execution of the interrupted process is resumed.

As a result, a high-priority process can be interrupted during the execution of the process, and an appropriate process order can be set based on the acquired policy, the preprocessing time for each process, and the priority information.

(10) Further, the method of the present invention includes a step of acquiring standby order information indicating the current high possibility of execution of the process executed within a certain time in the past, and the FPGA is used. When the process to be used does not exist, the binary file of the process selected based on the standby order information is preset in the FPGA.

As a result, the binary file of the process that is likely to be set next time can be set in the FPGA in advance and waited, and the preprocessing time can be shortened when the prediction is correct.

(11) Further, the scheduling device of the present invention is a scheduling device that uses FPGA in a plurality of processes of one or a plurality of virtual communication devices in a time-divided manner, and includes a task queue for storing execution instructions of the processes and the above. Check the processes set in the task queue, and if a plurality of the processes are set in the task queue, determine the order of the processes to be executed, and the order of execution arrives according to the determined order. A schedule unit that requests the setting of the binary file of the process to the FPGA and executes the set binary file, and a binary setting unit that sets the binary file of the process requested by the schedule unit to the FPGA. The set binary file of the process includes a preprocessing measuring unit for acquiring the preprocessing time set in the FPGA, and the order of the processes or a predetermined time for setting and executing the process is described as described above. Determined based on pre-processing time for each process.

As a result, when the FPGA is used in a plurality of processes in a time-division manner, it is possible to schedule the circuit information of the process to be executed in consideration of the time (preprocessing time) for setting the FPGA in the FPGA.

According to the present invention, when FPGA is used in time division in a plurality of processes, the use of time division is usually supported by scheduling the circuit information of the process to be executed in consideration of the time to be set in FPGA. Even if the FPGA is not used, it can be used in a time division manner, and the FPGA resources can be used efficiently without increasing the cost.

It is a figure which shows an example of the concept of the virtualization of the communication equipment using the container technology, which is the basis of the scheduling method and the scheduling apparatus which concerns on this embodiment, and the relationship between a container technology and an FPGA. It is a table which shows the specific example of the process of the conventional method, and is the conceptual diagram which shows the allocation time with respect to it. It is a block diagram which shows an example of the schematic structure of the scheduling apparatus which concerns on 1st Embodiment. (A) and (b) are tables showing examples of information stored in the DB, respectively. It is a block diagram which shows an example of the schematic structure of the scheduling apparatus which concerns on 2nd Embodiment. It is a flowchart which shows an example of the operation of the scheduling apparatus which concerns on 2nd Embodiment. It is a flowchart which shows an example of the operation of the scheduling apparatus which concerns on 2nd Embodiment. Each of (a) and (b) is a table showing a specific example of the process of the first embodiment, and a conceptual diagram showing the allocated time for the table. It is a table which shows the specific example of the process of Example 1. It is a conceptual diagram which shows the allocation time of Example 1 with respect to the specific example of the process shown in FIG. (A) to (c) are a table showing a specific example of the process of the second embodiment, a conceptual diagram showing the order of the usual shortest job priority method, and a conceptual diagram showing the order of the shortest job priority method of the present invention, respectively. Is. (A) and (b) are a table showing a specific example of the process of the third embodiment, and a conceptual diagram showing the order of the shortest job priority method of the present invention, respectively. (A) and (b) are a table showing a specific example of the process of the third embodiment, and a conceptual diagram showing the order of the shortest job priority method of the present invention, respectively. It is a flowchart which shows an example of the operation of the scheduling apparatus of Example 3. FIG. It is a table which shows the specific example of the process of 4th Example. FIG. 5 is a conceptual diagram showing the order and allotted time of the fourth embodiment with respect to the specific example of the process shown in FIG. FIG. 5 is a conceptual diagram showing the order and allotted time of the fourth embodiment with respect to the specific example of the process shown in FIG. It is a table which shows the specific example of the process of the modification of the 4th Example. (A) and (b) are a table showing a specific example of the process of the fifth embodiment, and a conceptual diagram showing an order and an allotted time, respectively. It is a table which shows the specific example of the process of 6th Example.

When the FPGA is used in time division in a plurality of processes, the present inventors usually cope with the use of time division by scheduling the circuit information of the process to be executed in consideration of the time to be set in the FPGA. We have found that even an FPGA that has not been used can be used in a time-division manner, and have come to the present invention.

That is, the method of the present invention is a scheduling method in which the FPGA is used in a plurality of processes of one or a plurality of virtual communication devices in a time-divided manner, and is set with a step of confirming the process set in the task queue. A step of acquiring the preprocessing time set in the FPGA for the binary file of the process, and a step of determining the order of the processes to be executed when a plurality of the processes are set in the task queue. The order of the processes or the predetermined time for setting and executing the processes includes the steps of setting and executing the binary files of the processes that have arrived in the order of execution according to the determined order in the FPGA. Determined based on pre-processing time for each process.

As a result, the present inventors can normally use FPGAs that do not support the use of time division in time division, and can efficiently use the resources of FPGA without increasing the cost. bottom. Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings. In order to facilitate understanding of the description, the same reference number is assigned to the same component in each drawing, and duplicate description is omitted.

[Concept of the relationship between container technology and FPGA]
FIG. 1 is a diagram showing an example of the concept of virtualization of communication equipment using the container technology and the relationship between the container technology and the FPGA, which is the basis of the scheduling method and the scheduling device according to the present embodiment. A virtual communication device is composed of one or more containers and operates. Each container is organized as a set of one or more processes. The virtual communication device may be, for example, a router, a firewall, a base station, a mobile core, or the like, but is not limited thereto. A process is a process obtained by dividing a process performed by a virtual communication device into one or a plurality of functions. For example, when the virtual communication device is a router, a function of filtering packets, a function of managing a communication protocol, and the like can be considered as processes, but the process is not limited to this.

Individual processes are executed by consuming hardware resources, but there are differences in the resources consumed by each process. For example, "process-e" in FIG. 1 indicates that it is executed using a CPU. On the other hand, "process-a", "process-i", and "process-u" in FIG. 1 are executed using the FPGA via a binary file which is a circuit setting for each process set in the FPGA. It represents that. In FIG. 1, circuits in which "process-a", "process-i", and "process-u" are set in FPGAs "binary-A", "binary-B", and "binary-C", respectively. Indicates that it corresponds to the setting.

In this way, one FPGA is used for the execution of the process corresponding to the binary file when one binary file is set, and is used simultaneously for the execution of the process corresponding to the other binary file. There is nothing. Also, when the FPGA is used to execute a process corresponding to another binary file, the binary file is newly set and then used. That is, in the present invention, when one FPGA is used for different processes, it is used in time division. Since each FPGA is managed, a plurality of FPGAs may exist.

[First Embodiment]
(Scheduling device configuration)
FIG. 3 is a block diagram showing an example of a schematic configuration of the scheduling device according to the present embodiment. Although the implementation in one server 10 is described in FIG. 3, each element may be implemented in another server. "Process-A" indicates the process of a virtualized network device. The FPGA 20 is an FPGA mounted in the server, and an example in which one FPGA is mounted in the server 10 will be described. The scheduling device 100 is composed of a task queue 110, a schedule unit 120, a binary setting unit 130, and a preprocessing measurement unit 140.

The task queue 110 is a place for storing execution instructions of a process to be processed by the FPGA 20, and executes the instructions stored in the task queue 110 according to the policy. Policy is a standard for determining the execution order and execution time of processes. For example, there are criteria such as emphasizing fairness and emphasizing reduction of turnaround time. In this embodiment, it is assumed that the policy is set in advance.

The schedule unit 120 confirms the process set in the task queue 110. In the present embodiment, the schedule unit 120 periodically confirms the task queue 110, but the schedule may be started at the timing when the process is set in the task queue 110.

When a plurality of processes are set in the task queue 110, the schedule unit 120 determines the order of the processes to be executed, and according to the determined order, the binary setting unit 130 is notified of the binary of the process to be executed. Request the setting of the file to FPGA20. When one process is set in the task queue 110, the schedule unit 120 requests the binary setting unit 130 to set the binary file of the process in the FPGA 20. Further, the schedule unit 120 executes the binary file set in the FPGA 20.

The order of processes or a predetermined time (allocated time) for setting and executing a process is determined based on the preprocessing time for each process described later. As a result, even an FPGA that does not normally support the use of time division can be used in time division, and the resources of the FPGA can be efficiently used without increasing the cost.

The binary setting unit 130 sets the binary file of the process requested by the schedule unit 120 in the FPGA 20. In the present invention, the FPGA circuit information corresponding to one process is pre-compiled and managed as a binary file. The binary file corresponding to each process is stored in the DB 50. The binary setting unit 130 acquires necessary information from the DB 50.

The preprocessing measurement unit 140 acquires the preprocessing time when the binary file of the process set in the task queue 110 is set in the FPGA 20. The preprocessing time may be a value set in advance for each process or for each binary file, but each time the binary file is set in the FPGA 20, the preprocessing measurement unit 140 measures the set time to measure it. It is preferable to set the average value of the plurality of values as the pretreatment time. This is because the setting time of the binary file for FPGA differs depending on the circuit scale, so it is more realistic to measure how long it takes each time you actually set it, based on the preprocessing time. This is because the order of processes or the predetermined time for setting and executing processes can be determined.

The measured set time is transmitted to the DB (database) 50, and the DB 50 holds at least one of the measured values so far, their average value, the average value for a predetermined number of measurements, and the like. The measuring method is not limited, but for example, when the scheduling device 100 is configured based on OpenCL, the execution time of clCreateProgramWithBinary and clCreateKernel at the time of setting the binary can be measured as the preprocessing time.

4 (a) and 4 (b) are tables showing examples of information stored in the DB 50, respectively. The DB 50 is a binary file for each process, the preprocessing time for each process measured by the preprocessing measurement unit 140, the process time for each process, and the initial processing time (initial process time) which is the sum of the preprocessing time and the process time for each process. Information such as is stored. In addition, order information indicating the order constraint of a plurality of processes used in the examples described later, priority information indicating the high priority of a plurality of processes, and the current state of processes executed within a certain time in the past. Information necessary for responding to various policies such as waiting order information indicating the high possibility of execution may be stored. In addition, the information stored in the DB is updated as needed.

[Second Embodiment]
(Scheduling device configuration)
FIG. 5 is a block diagram showing an example of a schematic configuration of the scheduling device according to the present embodiment. The scheduling device 200 is composed of a task queue 110, a schedule unit 120, a binary setting unit 130, a preprocessing measurement unit 140, and a policy design unit 210. Since the functions of the task queue 110, the schedule unit 120, the binary setting unit 130, and the preprocessing measurement unit 140 are the same as those in the first embodiment, the description thereof will be omitted.

The policy design unit 210 sets a policy that indicates how to set the process sequence or the binary file of the process in the FPGA 20 to determine a predetermined time to execute. The policy design unit 210 is a functional unit that requires the user to set what to prioritize in process scheduling. For example, emphasis on fairness and emphasis on reduction of turnaround time are set.

By including the policy design unit 210, the scheduling device 200 can set the policy to be emphasized by the user, and the user can select the policy according to the process to be processed by the FPGA 20 and the processing amount.

(Explanation of an example of operation)
Next, an example of the operation of the scheduling device according to the present embodiment will be described with reference to the flowcharts of FIGS. 6 and 7. 6 and 7 are flowcharts showing an example of the operation of the scheduling device according to the present embodiment.

6 and 7 include setting requests of each functional unit, DB, and user constituting the scheduling device. Each functional unit is in charge of acquiring information from the DB. First, the user requests the scheduling device to set the policy (step S1). Next, the policy design unit determines the time to be considered according to the policy to be set (step S2). The time to be considered (considered time) includes at least the pretreatment time. For example, it is possible to determine whether to consider the preprocessing time or the initial process time including the preprocessing time and the process time according to the policy to be set. The consideration time may be any time for each policy as long as it is calculated based on the pretreatment time. Next, the policy design unit notifies the schedule unit of the policy setting (set) (step S3).

Next, the schedule unit receives the policy setting (set) (step S4) and determines the consideration time (step S5). Meanwhile, the process is set in the task queue (step S6). Then, the task queue is confirmed (step S7), and when the process is set (step S8-YES), the value of the consideration time is confirmed in the DB (step S9). The DB receives the confirmation message of the value of the consideration time (step S10), and returns the value (step S11). Then, the schedule unit determines the schedule based on the value of the consideration time (step S12). The value of the consideration time includes at least the preprocessing time of the binary file corresponding to the set process. In addition, determining the schedule includes at least setting the order in which the processes are executed or determining the predetermined time for executing the processes.

Further, the task queue is confirmed (step S7), and if the process is not set (step S8-NO), the process returns to step S7 and the task queue is confirmed again.

After determining the schedule, the schedule unit determines whether or not to change the circuit information, and when changing (step S13-YES), instructs the binary setting unit to set the circuit of the corresponding process (step S14). The decision whether to change the circuit information is to check and judge whether the binary file of the process to be executed is set in the FPGA. You may check the FPGA directly, but the previous process is performed. It is preferable to check or contact the binary settings section. The circuit setting of the corresponding process is the setting of the binary file corresponding to the corresponding process.

The binary setting unit receives the instruction for setting the circuit of the corresponding process (step S15), and confirms the corresponding binary (binary file) of the process in the DB (step S16). The DB receives the binary confirmation message (step S17) and returns the binary information (binary file) to the binary setting unit (step S18). The binary setting unit sets the binary in the FPGA (step S19), and requests the preprocessing measurement unit to measure the binary setting time (step S20).

The preprocessing measurement unit receives the measurement request message for the binary set time (step S21), and starts the measurement. Then, when the measurement is completed (step S22), the measured value is notified to the DB (step S23). The DB receives the measured value (step S24), calculates and stores the average value of the preprocessing time (step S25).

On the other hand, after the binary setting is completed (step S26), the binary setting unit notifies the schedule unit of the completion of the circuit setting of the corresponding process (step S27). The schedule unit receives the circuit setting completion notification of the corresponding process (step S28), and executes the corresponding process (step S29). After execution, it is determined whether all the processes have been completed, and if so, the process ends (step S30-YES). If the policy is not changed after the end, the process may be performed to return to step S7 and check the task queue.

Further, the schedule unit determines whether all the processes have been completed, and if not completed (step S30-NO), returns to step S13 and determines whether to change the circuit information.

Further, the schedule unit determines whether or not to change the circuit information in step S13, and if it does not change (step S13-NO), executes the corresponding process (step S29).

The scheduling device according to the present embodiment can operate in this way. The scheduling device according to the first embodiment can also perform the same operation except that it does not have a policy design unit. The above description of the operation is an example of the operation, and the present invention is not limited thereto.

In the above description of the first embodiment and the second embodiment, the scheduling device is implemented in hardware for easy understanding, but it is understood by the description of the above flowchart. As such, the present invention allows some or all of the scheduling devices to be implemented in software. Further, the present invention can be implemented not only as one software but also as a processing method executed between elements of a plurality of functions implemented on one or a plurality of servers. The same applies to the following examples.

[Example]
Next, an embodiment will be described. In the following examples, a method based on the so-called round robin method, in which the time for allocating FPGA to each process is determined with an emphasis on fairness between processes, and the so-called shortest job priority method, in which the turnaround time is reduced, are adopted. However, the present invention is not limited to this. The present invention includes a method of scheduling a binary file of circuit data used in each process in consideration of the setting time (preprocessing time) in the FPGA when setting the binary file in the FPGA by time division.

(Example 1)
First, a method of emphasizing fairness will be described. When the policy design department is set to emphasize fairness, the scheduling device shall place importance on allocating the allocated time between processes substantially fairly. In this case, the schedule section sets the time to be allocated to each process by adding the preprocessing time for each process to the time quantum common to all processes. As a specific example, the case of scheduling the process of FIG. 8A and the case of scheduling the process of FIG. 9 will be described. 8 (a) and 8 (b) are a table showing a specific example of the process of this embodiment and a conceptual diagram showing an allotted time, respectively. FIG. 9 is a table showing a specific example of the process of this embodiment. FIG. 10 is a conceptual diagram showing the allocation time for the specific example of the process shown in FIG.

For example, when the process of FIG. 8 (a) is scheduled with the time quantum as 5, the preprocessing time 2 + time quantum 5 is allocated time 7 for "process-a", and the preprocessing time 5 + time is set for "process-i". It is scheduled to allocate the allocation time 10 in the quantum 5 and the allocation time 9 in the preprocessing time 4 + the time quantum 5 in the “process”, and execute as shown in FIG. 8 (b).

Further, as an example in which the process time is longer than the above, the case of scheduling the process of FIG. 9 will be described. For example, when the process of FIG. 9 is scheduled with the time quantum set to 5 in the same manner as above, the preprocessing time is 2 for "process-a" + the allocated time is 7 for time quantum 5, and the preprocessing time is set for "process-i". It is scheduled to allocate the allocation time 10 with 5 + time quantum 5 and the allocation time 9 with the preprocessing time 4 + time quantum 5 for "process-u", and execute as shown in FIG.

By setting the preprocessing time + time quantum as the allocated time in this way, even if there is a process with a long preprocessing time, the actual processing time is given by the time quantum. As in the example shown in b), a process that does not end does not occur. In addition, since the time quantum (actual processing time) is equal in all processes, the allocated time in a practical sense is fair.

(Example 2)
Next, a method of reducing the turnaround time will be described. There is a shortest job priority method as a typical scheduling method that reduces the turnaround time. Normally, in the shortest job priority method, the one with the shortest process time is preferentially executed, but in the present invention, the one with the shortest initial process time, which is the sum of the preprocessing time and the process time, is preferentially executed. NS.

As a specific example, the case of scheduling the process of FIG. 11A will be described. 11A to 11C show a table showing a specific example of the process of the present embodiment, a conceptual diagram showing the order of the usual shortest job priority method, and the order of the shortest job priority method of the present invention, respectively. It is a conceptual diagram. In the normal shortest job priority method, the one with the shortest process time is executed with priority. Therefore, in the process of FIG. 11 (a), as shown in FIG. 11 (b), "process-i", It is executed in the order of "process-u" and "process-a". The turnaround time in this case is (7 + 13 + 18) / 3≈12.67. On the other hand, in the shortest job priority method of the present invention, the one with the shortest initial process time, which is the sum of the preprocessing time and the process time, is preferentially executed. Therefore, in the process of FIG. 11A, the process is executed in the order of "process-a", "process-u", and "process-i". The turnaround time in this case is (5 + 11 + 18) / 3≈11.33.

In this way, by preferentially executing the process that has the shortest initial process time, which is the sum of the preprocessing time and the process time, the turnaround time can be reduced as compared with the method that does not consider the preprocessing time.

(Example 3)
Next, in the method of reducing the turnaround time, a method when a plurality of the same processes are contained in the task queue will be described. When the same process is included in the plurality of processes set in the task queue, it is preferable to calculate the initial process time of each process only when the same process is executed consecutively. In other words, if there are multiple identical processes in the task queue, the time for each process to finish in other combinations is added, except for those in which the same process is not continuous, from the combination of the order of each process. , Schedule with the pattern with the smallest total value.

As a specific example, the case of scheduling the process of FIG. 12 (a) and the case of scheduling the process of FIG. 13 (a) will be described. 12 (a) and 12 (b) are a table showing a specific example of the process of the present embodiment and a conceptual diagram showing the order of the shortest job priority method of the present invention, respectively. Suppose that "Process-A, I, I, U" is set in the task queue. At this time, the initial process time of each process when two "processes" are executed in succession is calculated. Then, the initial process time of "process-a" is 5, the initial process time of the first "process-i" is 7, the initial process time of the second "process-i" is 9, and "process-u". The initial process time is 6. However, the two "processes" are executed in succession. At this time, there are six possible orders: "good", "good", "good", "good", "good", and "good". The order in which the around time is minimized is "good match" shown in FIG. 11, and the value is 12.5.

On the other hand, continuous processes do not always have a smaller turnaround time when executed first. The process shown in FIG. 13 (a) is a process in which the preprocessing time of “process-i” in FIG. 12 (a) is changed to 10. When scheduling the process shown in FIG. 13 (a), the possible order is "good", "good", "good", "good", "good" in the same manner as above. , "Aui", of which the order in which the turnaround time is minimized is "Aui" shown in FIG. 13 (b).

(Example of operation of Example 3)
An example of the operation of the third embodiment will be described with reference to the flowchart of FIG. FIG. 14 is a flowchart showing an example of the operation of the scheduling device of the third embodiment. First, the task queue is confirmed (step T1). Next, check whether the same process exists in the task queue, and if the same process does not exist (step T2-NO), sort in ascending order of initial process time (step T3), and execute the processes in that order (step T3). Step T8), when all the processes are executed, the process ends.

On the other hand, it is confirmed whether or not the same process exists in the task queue, and if the same process exists (step T2-YES), the process order pattern is calculated (step T4). Next, the total value of each process end time is calculated in the calculated order patterns except that the same process is not continuous from the calculated order patterns (step T6). Then, the calculated total values are sorted in ascending order (step T7), the processes are executed in that order (step T8), and the process ends when all the processes are executed.

In this way, in the method of reducing the turnaround time, even if a plurality of the same processes are included in the task queue, the turnaround time can be reduced by considering the preprocessing time.

(Example 4)
When applying FPGA time division, consideration such as preprocessing time can be utilized even when considering order constraints and priorities between processes. For example, by providing priority values (priority information) as shown in FIG. 15, it is possible to express order constraints and priorities between processes. In the example of FIG. 15, it is shown that the higher the priority value is, the higher the priority is, and that "process-a" and "process-u" are executed after "process-i". For example, when this is executed in round robin and time quantum 5, as shown in FIG. 16, the time quantum plus the preprocessing time is assigned to each, and "process-i" is executed first. Become.

Further, when the process in the task queue is shown in FIG. 15 and the shortest job priority is given, the process is executed as shown in FIG.

In this way, when a process has a priority, the order of the processes is determined based on the set policy, the preprocessing time for each process, and the priority information. As a result, even if the processes have priorities, the appropriate process order can be set based on the acquired policy, the preprocessing time for each process, and the priority information.

Further, when a plurality of processes set in the task queue include processes having the same priority information, it is preferable that the process order is determined for each process having the same priority information. As a result, even if the processes have priorities and there are processes having the same priority, it is possible to set an appropriate process order based on the acquired policy, the preprocessing time for each process, and the priority information.

(Example 4 modified example)
In the case of the priority value shown in FIG. 15, there is a difference in priority including the same value among all processes, and this can be used to express an order constraint, but only between some processes. Order information indicating order restrictions may be provided. For example, the process shown in FIG. 18 indicates that the process needs to be executed in the numerical order of the order information, "process-a" indicates that it is executed after "process-i", and "process". "U" indicates that it may be executed at any stage before "process-i", between "process-i" and "process-a", and after "process-a".

In this way, the order of the processes when there is order information is determined based on the set policy, the preprocessing time for each process, and the order information. As a result, even if the process has an order constraint, an appropriate process order can be set based on the acquired policy, the preprocessing time for each process, and the order information.

(Example 5)
FPGA time division even when the preemption method (stopping the running process and executing the high priority process when a new high priority arrives in the task queue) is selected. For application, it is necessary to consider the pretreatment time and the like. For example, when the shortest job priority method is selected, the "process-i" arrives with a delay as shown in FIG. 19A, and preemption is performed, the process is executed as shown in FIG. 19B. However, it should be noted that this embodiment is slightly different from the flowcharts of FIGS. 6 and 7. According to the flowcharts of FIGS. 6 and 7, after executing "process-a, u" with an arrival time of 0, the task queue is confirmed, so that the arrival of "process-i" is not noticed.

Therefore, in order to execute as shown in FIG. 19B, periodical confirmation of the task queue is performed independently of the process execution, or a process having a high priority has entered the task queue (task queue). Etc.) Another mechanism needs to inform the schedule department.

(Example 6)
Next, a method of shortening the process processing time by setting one of the circuit information (binary files) in the FPGA and waiting for the time when the process using the FPGA does not exist will be described. The preprocessing time can be reduced by setting the circuit information of the process that uses the FPGA to be executed next in the FPGA and waiting.

Therefore, the standby order information as shown in FIG. 20 is newly provided in the DB. This holds information about which process was called how many times in a certain time in the past, and holds a value obtained by multiplying it by the preprocessing time as a weight. When this weight is large, it means that the preprocessing time which is frequently used or becomes a bottleneck is large, and the one having the highest rank is set as the standby time of FPGA. This method is also useful when there are a plurality of FPGAs. For example, when there are two FPGAs, the first binary is set on the first and the second binary is set on the second. By waiting, the turnaround time can be reduced more efficiently. Although this method is effectively used in a method of reducing the turnaround time, it is also effective in the sense that at least the initial pretreatment time is shortened when it is executed in round robin.

As described above, in the scheduling method and the scheduling device of the present invention, when the FPGA is used in a plurality of processes in a time-division manner, the scheduling is performed in consideration of the time for setting the circuit information of the process to be executed in the FPGA. Therefore, even an FPGA that does not normally support the use of time division can be used in time division, and the resources of the FPGA can be efficiently used without increasing the cost.

10 server 20 FPGA
50 DB
100, 200 Scheduling device 110 Task queue 120 Schedule unit 130 Binary setting unit 140 Preprocessing measurement unit 210 Policy design unit

Claims (11)

It is a scheduling method that uses FPGA in time division in multiple processes of one or more virtual communication devices.
A step to check the process set in the task queue and
The step of acquiring the preprocessing time when the set binary file of the process is set in the FPGA, and
When a plurality of the processes are set in the task queue, a step of determining the order of the processes to be executed and a step of determining the order of the processes to be executed.
Including the step of setting and executing the binary file of the process which has arrived in the order of execution according to the determined order in the FPGA.
A method characterized in that the order of the processes or a predetermined time for setting and executing the processes is determined based on the preprocessing time for each process. It has a step of accepting and setting a policy setting request indicating how to determine the order of the processes or the predetermined time.
The method according to claim 1, wherein the order of the processes or the predetermined time is determined based on the set policy and the pretreatment time for each process. The method according to claim 1, wherein the predetermined time is determined for each process as the sum of the pretreatment time for each process and the same time quantum for all the processes. In the step of acquiring the preprocessing time, the process time for each process is further acquired.
The method according to claim 1, wherein the order of the processes is determined based on the initial process time, which is the sum of the preprocessing time and the process time for each process. When the same process is included in a plurality of the processes set in the task queue, the initial process time of each process is calculated only when the same process is executed consecutively. The method according to claim 4, which is characterized. It has a step of acquiring order information indicating the order constraint of a plurality of the processes.
The method according to claim 2, wherein the order of the processes is determined based on the set policy, the pretreatment time for each process, and the order information. It has a step of acquiring priority information indicating the high priority of a plurality of the processes.
The method according to claim 2, wherein the order of the processes is determined based on the set policy, the pretreatment time for each process, and the priority information. When a plurality of the processes set in the task queue include processes having the same priority information, the claim is characterized in that the order of the processes is determined for each process having the same priority information. Item 7. The method according to item 7. When another process having the priority information having a higher priority than the priority information of the running process is set in the task queue during the execution of the process set in the task queue. The method according to claim 7 or 8, wherein the execution of the process being executed is interrupted, and after the execution of the other process, the execution of the interrupted process is resumed. It has a step of acquiring waiting order information indicating the current likelihood of execution of the process executed within a certain time in the past.
Any of claims 1 to 9, wherein a binary file of the process selected based on the standby order information is preset in the FPGA when the process using the FPGA does not exist. The method described in. A scheduling device that allows FPGAs to be used in time division in multiple processes of one or more virtual communication devices.
A task queue that stores the execution instructions of the process,
The process set in the task queue is confirmed, and when a plurality of the processes are set in the task queue, the order of the processes to be executed is determined, and the order of execution is determined according to the determined order. A schedule unit that requests the setting of the incoming binary file of the process to the FPGA and executes the set binary file, and
A binary setting unit that sets the binary file of the process requested by the schedule unit in the FPGA, and
The binary file of the set process is provided with a preprocessing measurement unit for acquiring the preprocessing time set in the FPGA.
A scheduling apparatus characterized in that the order of the processes or a predetermined time for setting and executing the processes is determined based on the preprocessing time for each process.

Images