JP7259625B2 - Transimpedance amplifier circuit - Google Patents

Description

The present disclosure relates to transimpedance amplifier circuits.

Conventionally, there is a transimpedance amplifier circuit that converts an optical signal for optical communication into an electrical signal (see Patent Documents 1 and 2, for example). In Patent Document 1, a transistor for extracting a direct current, a transistor for extracting an alternating current, and a TIA section composed of an inverting amplifier circuit and a feedback resistance element are provided at the cathode and anode of a photodiode, respectively. , is described. In this transimpedance amplifier circuit, the source potential of the transistor for extracting alternating current is provided by the buffer so as to match the input potential of the TIA section, the gate of the transistor is connected to the control circuit, and the drain of the transistor is It is connected to the input terminal of the TIA section. The gate voltage is adjusted so that the amplitude of the differential output signal is constant, and the amplitude is controlled so that the input current from the photodiode is not distorted in the output of the TIA section.

U.S. Pat. No. 9,774,305 JP 2012-10107 A

In the transimpedance amplifier circuit disclosed in Patent Literature 1, the source of the transistor for extracting alternating current is grounded by a buffer, and the source potential is constant over the range from direct current to high frequency. Further, since a signal obtained by integrating the error between the signal amplitude and the target potential is supplied from the control circuit to the gate of the transistor, a constant voltage is supplied at high frequencies. On the other hand, the input impedance of the TIA section is usually about 10 to 100Ω, and potential fluctuations may occur with the input current from the photodiode, so the drain potential of the transistor may fluctuate slightly. A transistor for extracting alternating current operates as a resistive element because the source voltage and the drain voltage are substantially the same. However, since the drain potential fluctuates slightly, the on-resistance value between the drain and source of the transistor (the resistance value of the resistance element) can change. As a result, the resistance value changes depending on whether the drain potential is high or low, and this may cause a difference in the amount of alternating current drawn. This difference results in distortion and can affect signal quality.

This disclosure describes a transimpedance amplifier circuit that can improve signal quality.

A transimpedance amplifier circuit according to one aspect of the present disclosure is a circuit that generates a differential voltage signal according to an input current signal generated by a light receiving element. This transimpedance amplifier circuit includes an input terminal that receives an input current signal, a single-ended amplifier circuit that converts the current signal into a voltage signal, and a differential voltage signal that is generated according to the difference between the voltage signal and the reference voltage signal. A differential amplifier circuit, a control current generation circuit that generates a control current based on the integrated value of the difference, and a bypass circuit that generates a DC bypass current and an AC bypass current according to the control current. A current signal is generated by subtracting a DC bypass current and an AC bypass current from the input current signal. The bypass circuit includes a control circuit to which a control current is input, and a variable resistance circuit that generates an AC bypass current according to the control current. The control circuit generates an offset current having a predetermined offset current value, and amplifies a difference between the current generated by amplifying the control current and the offset current with a first amplification factor to generate a first control current. . The variable resistance circuit has a first drain for receiving a first control current, a first gate electrically connected to the first drain, a first source for receiving a reference voltage signal, and a reference voltage signal. a first substrate terminal; a first resistive element; a second drain electrically connected to the input terminal; A second field effect transistor having a second gate electrically connected, a second source supplied with the reference voltage signal, and a second substrate terminal supplied with the reference voltage signal. The second field effect transistor is configured such that a first capacitance between the second gate and the second drain and a second capacitance between the second gate and the second source are equal to each other. The resistance value of the first resistance element is greater than the impedance of the first capacitor. The variable resistance circuit causes an AC bypass current to flow from the second drain to the second source in response to the first control current.

According to the present disclosure, signal quality can be improved.

FIG. 1 is a diagram schematically showing the configuration of an optical receiver that includes a transimpedance amplifier circuit according to one embodiment. FIG. 2 is a diagram showing a circuit configuration example of the integrating circuit shown in FIG. FIG. 3 is a diagram showing the relationship between the control current supplied to the control circuit shown in FIG. 1 and the current generated by the control circuit. FIG. 4 is a diagram showing a circuit configuration example of the control circuit shown in FIG. FIG. 5 is a diagram for explaining the inter-terminal capacitance of the field effect transistor shown in FIG. FIG. 6 is a diagram showing an example of capacitance values of inter-terminal capacitances shown in FIG. FIG. 7(a) is a diagram showing changes in total harmonic distortion with respect to input light average power in the transimpedance amplifier circuit shown in FIG. FIG. 7(b) is a diagram showing changes in the output amplitude of the TIA section with respect to the input light average power in the transimpedance amplifier circuit shown in FIG. FIG. 7(c) is a diagram showing changes in amplitude at each terminal of the field effect transistor with respect to the input light average power in the transimpedance amplifier circuit shown in FIG. FIG. 8(a) is a diagram showing changes in total harmonic distortion with respect to input light average power in the transimpedance amplifier circuit of the comparative example. FIG. 8(b) is a diagram showing changes in the output amplitude of the TIA section with respect to the input light average power in the transimpedance amplifier circuit of the comparative example. FIG. 8(c) is a diagram showing changes in amplitude at each terminal of the field effect transistor with respect to the input light average power in the transimpedance amplifier circuit of the comparative example.

[Description of Embodiments of the Present Disclosure]
First, the contents of the embodiments of the present disclosure will be listed and described.

A transimpedance amplifier circuit according to one aspect of the present disclosure is a circuit that generates a differential voltage signal according to an input current signal generated by a light receiving element. This transimpedance amplifier circuit includes an input terminal that receives an input current signal, a single-ended amplifier circuit that converts the current signal into a voltage signal, and a differential voltage signal that is generated according to the difference between the voltage signal and the reference voltage signal. A differential amplifier circuit, a control current generation circuit that generates a control current based on the integrated value of the difference, and a bypass circuit that generates a DC bypass current and an AC bypass current according to the control current. A current signal is generated by subtracting a DC bypass current and an AC bypass current from the input current signal. The bypass circuit includes a control circuit to which a control current is input, and a variable resistance circuit that generates an AC bypass current according to the control current. The control circuit generates an offset current having a predetermined offset current value, and amplifies a difference between the current generated by amplifying the control current and the offset current with a first amplification factor to generate a first control current. . The variable resistance circuit has a first drain for receiving a first control current, a first gate electrically connected to the first drain, a first source for receiving a reference voltage signal, and a reference voltage signal. a first substrate terminal; a first resistive element; a second drain electrically connected to the input terminal; A second field effect transistor having a second gate electrically connected, a second source supplied with the reference voltage signal, and a second substrate terminal supplied with the reference voltage signal. The second field effect transistor is configured such that a first capacitance between the second gate and the second drain and a second capacitance between the second gate and the second source are equal to each other. The resistance value of the first resistance element is greater than the impedance of the first capacitor. The variable resistance circuit causes an AC bypass current to flow from the second drain to the second source in response to the first control current.

In this transimpedance amplifier circuit, the second gate of the second field effect transistor is electrically connected to the first gate of the first field effect transistor through the first resistance element, and the first field effect transistor is a diode. It is connected. Thus, the second gate is connected to the reference voltage signal via the differential resistance of the first resistive element and the first field effect transistor. However, since the resistance value of the first resistance element is larger than the impedance of the first capacitance between the second gate and the second drain, the first resistance element separates the second gate from the first gate in terms of high frequency ( isolated). Therefore, the voltage between the second drain and the second source is divided by the first capacitance between the second gate and the second drain and the second capacitance between the second gate and the second source. voltage is applied to the second gate. Since the second field effect transistor is configured such that the first capacitance and the second capacitance are equal to each other, a voltage about half the voltage between the second drain and the second source is applied to the second gate. be done. This suppresses the differential resistance value of the second field effect transistor from fluctuating due to the voltage between the second drain and the second source. As a result, the occurrence of distortion is suppressed, so that signal quality can be improved.

The variable resistance circuit may further include a second resistance element. A reference voltage signal may be supplied to the second substrate terminal via a second resistive element. The second field effect transistor is configured such that a third capacitance between the second substrate terminal and the second drain and a fourth capacitance between the second substrate terminal and the second source are equal to each other. good too. The resistance value of the second resistance element may be greater than the impedance of the third capacitor. Since the second substrate terminal is electrically connected to the second gate through the inter-terminal capacitance, the potential of the second substrate terminal can affect the second gate potential through the inter-terminal capacitance. On the other hand, the second substrate terminal is supplied with the reference voltage signal via the second resistance element, and the resistance value of the second resistance element is greater than the impedance of the third capacitor. Therefore, the second substrate terminal can be isolated from the outside of the second field effect transistor in high frequency by the second resistance element. The second field effect transistor is configured such that a third capacitance between the second substrate terminal and the second drain and a fourth capacitance between the second substrate terminal and the second source are equal to each other. Therefore, a voltage about half the voltage between the second drain and the second source is applied to the second substrate terminal. As a result, the potential of the second substrate terminal becomes approximately the same as the second gate potential, so that the influence of the potential of the second substrate terminal on the second gate potential can be reduced. As a result, the occurrence of distortion is further suppressed, so that signal quality can be further improved.

The bypass circuit may further comprise a feedback current source that produces a DC bypass current in response to the control current. The control circuit may control the feedback current source such that the DC bypass current increases as the control current increases. In this case, it is possible to realize control for removing the DC component and gain control of the transimpedance amplifier circuit with a single control loop, so that it is possible to suppress an increase in circuit size.

The control circuit may generate the second control current by amplifying the control current with a second amplification factor. The feedback current source has a third electric field having a third drain for receiving a second control current, a third gate electrically connected to the third drain, and a third source electrically connected to ground potential. an effect transistor, a fourth drain electrically connected to the input terminal, a fourth gate electrically connected to the third drain and the third gate, and a fourth source electrically connected to the third source. and a fourth field effect transistor having. The feedback current source may pass a DC bypass current from the fourth drain to the fourth source in response to the second control current. In this case, since the third field effect transistor is diode-connected, when the third drain of the third field effect transistor receives the second control current, a gate-source voltage is applied between the third gate and the third source. is generated. The third gate and fourth gate are electrically connected to each other, and the third source and fourth source are electrically connected to each other, so that the gate-source voltage of the fourth field effect transistor is 3 equal to the gate-source voltage of a field effect transistor. In the fourth field effect transistor, the fourth source is electrically connected to the third source, that is, the ground potential, and the fourth drain is electrically connected to the input terminal. The potential difference increases. Thereby, the fourth field effect transistor operates in the saturation region. Therefore, the fourth field effect transistor functions as a current source, and the output impedance of the fourth drain becomes large. Therefore, although the AC component of the input current signal hardly flows into the fourth field effect transistor, the DC component of the input current signal can flow into the fourth field effect transistor as a DC bypass current. As the control current increases, the voltage between the gate and the source of the third field effect transistor increases, so that the DC component of the input current signal is extracted as a DC bypass current from the input current signal. Removal is done properly.

The transimpedance amplifier circuit may further include a reference voltage generation circuit that generates a reference voltage signal. The reference voltage generation circuit may include an amplifier and a feedback resistance element electrically connected between the input and output of the amplifier. In this case, the output impedance of the reference voltage generating circuit becomes low over a wide frequency range. That is, the impedance of the variable resistance circuit viewed from the input terminal of the single-ended amplifier circuit becomes low over a wide frequency range. Therefore, it is possible to easily extract the AC bypass current from the input current signal.

[Details of the embodiment of the present disclosure]
A specific example of a transimpedance amplifier circuit according to an embodiment of the present disclosure will be described below with reference to the drawings. The present disclosure is not limited to these examples, but is indicated by the scope of the claims, and is intended to include all modifications within the scope and meaning equivalent to the scope of the claims.

FIG. 1 is a diagram schematically showing the configuration of an optical receiver that includes a transimpedance amplifier circuit according to one embodiment. FIG. 2 is a diagram showing a circuit configuration example of the integrating circuit shown in FIG. FIG. 3 is a diagram showing the relationship between the control current supplied to the control circuit shown in FIG. 1 and the current generated by the control circuit. FIG. 4 is a diagram showing a circuit configuration example of the control circuit shown in FIG. FIG. 5 is a diagram for explaining the inter-terminal capacitance of the field effect transistor shown in FIG. FIG. 6 is a diagram showing an example of capacitance values of inter-terminal capacitances shown in FIG.

The optical receiver 1B shown in FIG. 1 receives an optical signal Pin transmitted from an optical transmitter (not shown). The optical receiver 1B includes a light receiving element PD and a transimpedance amplifier circuit 10B. The light receiving element PD receives the optical signal Pin and generates a photocurrent Ipd (input current signal) corresponding to the optical signal Pin. The photocurrent Ipd may contain a DC component. Examples of the light receiving element PD include photodiodes and avalanche photodiodes. One terminal of the light receiving element PD is electrically connected to a predetermined bias voltage VPD, and the other terminal of the light receiving element PD outputs a photocurrent Ipd.

The transimpedance amplifier circuit 10B receives the photocurrent Ipd generated by the photodetector PD and generates differential voltage signals Vout and Voutb, which are voltage signals, according to the photocurrent Ipd. The differential voltage signals Vout, Voutb are a pair of complementary signals. The transimpedance amplifier circuit 10B has an input terminal 10a. A photocurrent Ipd is input to the input terminal 10a.

The transimpedance amplifier circuit 10B includes a TIA (TransImpedance Amplifier) section 11 (single-ended amplifier circuit), a reference voltage generator circuit 12, a differential amplifier circuit 13, a control current generator circuit 14, and a bypass circuit 15B. Prepare.

The TIA unit 11 is a circuit that converts the current signal Iin into a voltage signal Vtia. Specifically, the TIA section 11 includes a voltage amplifier 11a and a feedback resistance element 11b. The input terminal and the output terminal of the voltage amplifier 11a are electrically connected via the feedback resistance element 11b. That is, the feedback resistance element 11b is electrically connected between the input and output of the voltage amplifier 11a. The current signal Iin is generated by extracting the DC bypass current Iaoc and the AC bypass current Iagc from the photocurrent Ipd. The DC bypass current Iaoc and the AC bypass current Iagc are controlled by the bypass circuit 15B, the details of which will be described later. The increase/decrease of the voltage signal Vtia is inverted with respect to the increase/decrease of the current signal Iin. The voltage amplifier 11a is, for example, an inverting amplifier circuit. The TIA section 11 outputs the voltage signal Vtia to the differential amplifier circuit 13 and the control current generation circuit 14 . The gain of the TIA section 11 (the ratio of the magnitude of the voltage signal Vtia to the magnitude of the current signal Iin) is determined by the resistance value (transimpedance) of the feedback resistance element 11b.

The reference voltage generation circuit 12 is a circuit that generates a reference voltage signal Vref, which is a DC voltage signal. The reference voltage generation circuit 12 outputs the reference voltage signal Vref to the differential amplifier circuit 13, the control current generation circuit 14, and the bypass circuit 15B. The reference voltage signal Vref has a predetermined voltage value (fixed value). The reference voltage generation circuit 12 may be configured such that the output impedance is low over a wide band. In this embodiment, the reference voltage generation circuit 12 includes a voltage amplifier 12a (amplifier) and a feedback resistance element 12b, similarly to the TIA section 11. FIG. An input terminal and an output terminal of the voltage amplifier 12a are electrically connected via a feedback resistance element 12b. That is, the feedback resistance element 12b is electrically connected between the input and output of the voltage amplifier 12a. Since the reference voltage generation circuit 12 has a circuit configuration similar to that of the TIA section 11, the reference voltage signal Vref is generated so as to compensate (offset) changes in the voltage signal Vtia due to changes in the power supply voltage and temperature of the voltage amplifier 11a. obtain.

The differential amplifier circuit 13 is a circuit that generates differential voltage signals Vout and Voutb according to the difference ΔVtia (error) between the voltage signal Vtia and the reference voltage signal Vref. In other words, the differential amplifier circuit 13 uses the reference voltage signal Vref to convert the single (single-phase) voltage signal Vtia into the differential voltage signals Vout and Voutb. The differential amplifier circuit 13 generates differential voltage signals Vout and Voutb by amplifying the difference ΔVtia. The differential amplifier circuit 13 outputs the differential voltage signals Vout and Voutb to a subsequent circuit (not shown).

The control current generation circuit 14 is a circuit that generates the control current Icnt based on the integrated value of the difference ΔVtia between the voltage signal Vtia and the reference voltage signal Vref. The control current generation circuit 14 includes an integration circuit 41 and an OTA (Operational Transconductance Amplifier) 42 .

The integration circuit 41 is a circuit that integrates the difference ΔVtia. As shown in FIG. 2, the integration circuit 41 has input terminals 41a and 41b and output terminals 41c and 41d. The input terminal 41a is electrically connected to the output terminal of the reference voltage generation circuit 12 (voltage amplifier 12a), and the reference voltage signal Vref is input to the input terminal 41a. The input terminal 41b is electrically connected to the output terminal of the TIA section 11 (voltage amplifier 11a), and the voltage signal Vtia is input to the input terminal 41b. The output terminal 41 c is electrically connected to the inverting input terminal of the OTA 42 and outputs the voltage signal Vinn to the OTA 42 . The output terminal 41 d is electrically connected to the non-inverting input terminal of the OTA 42 and outputs the voltage signal Vinp to the OTA 42 .

The integration circuit 41 includes an operational amplifier 43 , resistance elements 44 and 45 , and capacitors 46 and 47 . The operational amplifier 43 has a non-inverting input terminal 43a, an inverting input terminal 43b, an inverting output terminal 43c, and a non-inverting output terminal 43d. The non-inverting input terminal 43a is electrically connected to the input terminal 41a through the resistance element 44. As shown in FIG. The inverting input terminal 43b is electrically connected through the resistance element 45 to the input terminal 41b. The inverting output terminal 43c is electrically connected to the output terminal 41c and electrically connected to the non-inverting input terminal 43a via the capacitor . That is, the capacitor 46 connects the inverting output terminal 43c and the non-inverting input terminal 43a by negative feedback. The non-inverting output terminal 43d is electrically connected to the output terminal 41d and is electrically connected via the capacitor 47 to the inverting input terminal 43b. That is, the capacitor 47 connects between the non-inverting output terminal 43d and the inverting input terminal 43b by negative feedback.

Here, the gain of the operational amplifier 43 is infinite, the resistance value R1 of the resistance element 44 and the resistance value R2 of the resistance element 45 are equal to each other, and the capacitance value C1 of the capacitor 46 and the capacitance value C2 of the capacitor 47 are equal to each other. , the integration circuit 41 operates as an integrator with a time constant R1×C1.

The OTA 42 is a circuit that converts a differential voltage signal (voltage signal Vinp and voltage signal Vinn) into a control current Icnt that is a single current signal (error current). The OTA 42 has a known circuit configuration, for example, a configuration in which a current mirror circuit is added to a differential amplifier circuit. The OTA 42 has transconductance, and the input/output impedance of the OTA 42 is, for example, infinite. The control current Icnt is obtained by multiplying the input differential voltage, which is the difference between the voltage signal Vinp and the voltage signal Vinn input to the OTA 42, by the transconductance. The difference between the voltage signal Vinp and the voltage signal Vinn changes according to the integrated value of the difference ΔVtia. The OTA 42 outputs the control current Icnt to the bypass circuit 15B.

The bypass circuit 15B is a circuit that generates a DC bypass current Iaoc and an AC bypass current Iagc according to the control current Icnt. The bypass circuit 15B includes a control circuit 51, a feedback current source 52, and a variable resistance circuit 53B.

A control current Icnt is input to the control circuit 51 . Control circuit 51 controls feedback current source 52 so that DC bypass current Iaoc increases as control current Icnt increases. When the control current Icnt exceeds the current value of the offset current Iofs, the control circuit 51 controls the variable resistance circuit 53B so that the AC bypass current Iagc increases as the control current Icnt increases. The current value of the offset current Iofs is a predetermined current value (fixed value). Specifically, the control circuit 51 receives the control current Icnt from the control current generating circuit 14 (OTA 42), and generates a control current Iaocnt (second control current) and a control current Iagccnt (first control current) according to the control current Icnt. to generate The control circuit 51 outputs a control current Iaocnt to the feedback current source 52 and controls the feedback current source 52 with the control current Iaocnt. The control circuit 51 outputs a control current Iagccnt to the variable resistance circuit 53B, and controls the variable resistance circuit 53B with the control current Iagccnt.

As shown in FIG. 3, the current value of the control current Iaocnt is proportional to the current value of the control current Icnt. The current value of the control current Iaocnt is α times the current value of the control current Icnt (Iaocnt=α×Icnt). The control circuit 51 generates the control current Iaocnt by, for example, amplifying the control current Icnt with an amplification factor α. The current value of control current Iagccnt is proportional to the current value of control current Icnt when the current value of control current Icnt is greater than the current value of offset current Iofs. In other words, the current value of the control current Iagccnt is γ times the current value obtained by subtracting the current value of the offset current Iofs from the control current Icnt (Iagccnt=γ×(Icnt−Iofs)). The control circuit 51 generates, for example, an offset current Iofs having a predetermined current value (offset current value), and a current generated by amplifying the control current Icnt (here, the control current Icnt) and the offset current Iofs. A control current Iagccnt is generated by amplifying the difference with an amplification factor γ. Thus, the control current Iaocnt adjusts the amplification factor α, and the control current Iagccnt adjusts the offset current value for determining the current at which automatic gain control (AGC) starts and the control sensitivity of the AGC. The amplification factor γ to be determined is adjusted.

Control circuit 51 shown in FIG. 4 has a circuit configuration for realizing control current Iaocnt and control current Iagccnt shown in FIG. As shown in FIG. 4, the control circuit 51 has an input terminal 51a, output terminals 51b and 51c, and a power supply terminal 51d. The input terminal 51a is electrically connected to the output terminal of the control current generation circuit 14 (OTA 42), and the control current Icnt is input to the input terminal 51a. The output terminal 51 b is electrically connected to the input terminal 52 a of the feedback current source 52 and outputs the control current Iaocnt to the feedback current source 52 . The output terminal 51c is electrically connected to the control terminal 53a of the variable resistance circuit 53B, and outputs the control current Iagccnt to the variable resistance circuit 53B. The power supply terminal 51d is electrically connected to a power supply wiring that supplies a power supply voltage VCC, and the power supply voltage VCC is supplied to the power supply terminal 51d.

The control circuit 51 includes transistors 61 to 69 and a current source 70 . The transistors 61 to 69 are, for example, field effect transistors (MOSFET) having a MOS (Metal-Oxide-Semiconductor) structure. In the example shown in FIG. 4, transistors 61-63 are N-channel MOS transistors and transistors 64-69 are P-channel MOS transistors.

Transistors 61-63 form a current mirror circuit. Transistor 61 functions as an input transistor and transistors 62 and 63 function as output transistors. The sources of transistors 61-63 are electrically connected to ground potential GND. The gate and drain of the transistor 61 are electrically connected to each other and further to the input terminal 51a. The respective gates of transistors 62 and 63 are electrically connected to the gate and drain of transistor 61 . The drain of transistor 62 is electrically connected to the drain and gate of transistor 64 . The drain of transistor 63 is electrically connected through node N to the drain and gate of transistor 68 .

Since the transistors 61 and 62 and the transistors 61 and 63 respectively form a current mirror circuit, for example, the output current (drain current) proportional to the magnitude of the drain current (control current Icnt) of the transistor 61 is generated by the transistors. They are output from the drains of 62 and 63, respectively. Here, for convenience of explanation, the current mirror ratio is assumed to be 1:1:1. Therefore, the control current Icnt input to the input terminal 51a is copied by the transistors 61 to 63, and the control currents Icnt are output from the drains of the transistors 62 and 63, respectively. Note that the control current Icnt flows toward the drains of the transistors 62 and 63 .

Transistors 64 and 65 form a current mirror circuit. Transistor 64 functions as an input transistor and transistor 65 functions as an output transistor. The sources of transistors 64 and 65 are electrically connected to power supply terminal 51d. The gate and drain of transistor 64 are electrically connected together and to the drain of transistor 62 . The gate of transistor 65 is electrically connected to the gate and drain of transistor 64 . A drain of the transistor 65 is electrically connected to the output terminal 51b.

The control current Icnt output from the drain of the transistor 62 is input to the drain of the transistor 64 , and the output current (drain current) proportional to the magnitude of the drain current (control current Icnt) of the transistor 64 is applied to the transistor 65 . is output from the drain of as a control current Iaocnt. Here, the current mirror ratio of the current mirror circuit formed by the transistors 64 and 65 is set to 1:α. That is, the control current Iaocnt is a current (α×Icnt) of a magnitude obtained by amplifying the control current Icnt by α times. Note that the control current Iaocnt flows from the drain of the transistor 65 toward the output terminal 51b.

Transistors 66 and 67 form a current mirror circuit. Transistor 66 functions as an input transistor and transistor 67 functions as an output transistor. The sources of the transistors 66 and 67 are electrically connected to the power supply terminal 51d. The gate and drain of transistor 66 are electrically connected together and to a current source 70 . The gate of transistor 67 is electrically connected to the gate and drain of transistor 66 . The drain of transistor 67 is electrically connected through node N to the drain and gate of transistor 68 .

The reference current Iref supplied from the current source 70 is input to the drain of the transistor 66 , and the output current (drain current) of the transistor 67 is proportional to the magnitude of the drain current (reference current Iref) of the transistor 66 . It is output from the drain as an offset current Iofs. Here, the current mirror ratio of the current mirror circuit composed of transistors 66 and 67 is set to 1:m. That is, the offset current Iofs is a current (m×Iref) having a magnitude obtained by amplifying the reference current Iref by m times. Note that offset current Iofs flows from the drain of transistor 67 toward node N. FIG. The value of m is arbitrarily selected according to the optical power desired to operate the AGC. Since the current value of the reference current Iref is a fixed value, the current value (offset current value) of the offset current Iofs is also a fixed value.

Transistors 68 and 69 form a current mirror circuit. Transistor 68 functions as an input transistor and transistor 69 functions as an output transistor. The sources of transistors 68 and 69 are electrically connected to power supply terminal 51d. The gate and drain of the transistor 68 are electrically connected to each other, and further electrically connected to the drain of the transistor 63 and the drain of the transistor 67 through the node N. The gate of transistor 69 is electrically connected to the gate and drain of transistor 68 . A drain of the transistor 69 is electrically connected to the output terminal 51c.

Control current Icnt output from the drain of transistor 63 is combined with offset current Iofs output from the drain of transistor 67 at node N. FIG. Specifically, the offset current Iofs is subtracted (subtracted) from the control current Icnt. At this time, only when the current value of the control current Icnt is greater than the current value of the offset current Iofs, the difference current (Icnt-Iofs) flows to the drain of the transistor 68, and the magnitude of the drain current (difference current) of the transistor 68 is is output from the drain of the transistor 69 as the control current Iagccnt. Here, the current mirror ratio of the current mirror circuit composed of transistors 68 and 69 is set to 1:γ. That is, the control current Iagccnt is a current (γ×(Icnt−Iofs)) obtained by amplifying the difference current (Icnt−Iofs) by γ times. Note that the control current Iagccnt flows from the drain of the transistor 69 toward the output terminal 51c.

On the other hand, when the current value of the control current Icnt is smaller than the current value of the offset current Iofs, no current flows through the transistor 68. Therefore, the diode-connected transistor 68 causes the potential of the node N to rise to the power supply voltage VCC side. pulled up with a high resistance to Also, since the voltage between the drain and the source of the transistor 67 becomes small, the transistors 66 and 67 do not operate as a current mirror circuit. At this time, since the transistor 67 operates in the triode region (linear region), the potential of the node N is pulled up to the power supply voltage VCC side with a low resistance. The triode region is the condition in which the result of subtracting the threshold voltage from the gate-source voltage of the transistor is greater than the drain-source voltage. Since no gate-source voltage is applied to the transistor 68 , the resistance value of the transistor 67 to which the gate-source voltage is applied is smaller than the resistance value of the transistor 68 . As a result of the transistor 67 operating in the triode region, the transistor 67 cannot supply the offset current Iofs, and all of the control current Icnt from the transistor 63 flows through the transistor 67 . Thus, control current Iagccnt is output from output terminal 51c only when the current value of control current Icnt is greater than the current value of offset current Iofs (in the region of Icnt-Iofs>0).

Although the input/output characteristics of FIG. 3 are obtained by the control circuit 51 shown in FIG. 4, the current mirror ratio can be changed as appropriate. Further, as the circuit configuration of the control circuit 51, another circuit configuration that can obtain the input/output characteristics of FIG. 3 may be adopted.

Feedback current source 52 constitutes an Auto-Offset Control (AOC) circuit. The feedback current source 52 is a circuit that generates a DC bypass current Iaoc according to the control current Icnt. More specifically, feedback current source 52 generates DC bypass current Iaoc in response to control current Iaocnt. The feedback current source 52 has an input terminal 52a, an output terminal 52b, and a ground terminal 52c. The input terminal 52 a is electrically connected to the output terminal 51 b of the control circuit 51 and receives the control current Iaocnt from the control circuit 51 . The output terminal 52b is electrically connected to the input terminal 10a and outputs a DC bypass current Iaoc. Ground terminal 52c is electrically connected to ground potential GND. The feedback current source 52 includes a field effect transistor 54 (third field effect transistor) and a field effect transistor 55 (fourth field effect transistor).

Each of field effect transistors 54 and 55 is, for example, an N-channel MOS transistor. The size of field effect transistor 54 and the size of field effect transistor 55 may be the same or different. Sources of field effect transistors 54 and 55 are electrically connected to each other and to ground potential GND via ground terminal 52c. The drain of field effect transistor 54 is electrically connected to output terminal 51b of control circuit 51 via input terminal 52a and receives control current Iaocnt from control circuit 51 . The gate of field effect transistor 54 is electrically connected to the drain of field effect transistor 54 . The drain of the field effect transistor 55 is electrically connected to the input terminal 10a through the output terminal 52b. The gate of field effect transistor 55 is electrically connected to the drain and gate of field effect transistor 54 .

In the feedback current source 52 configured in this manner, the control current Iaocnt flowing from the input terminal 52a flows through the diode-connected field effect transistor 54, thereby causing a gate current between the gate and the source of the field effect transistor 54. • Generate a source-to-source voltage Vgs1. The gates of the field effect transistors 54 and 55 are electrically connected to each other, and the sources of the field effect transistors 54 and 55 are electrically connected to each other. The gate-source voltage of the effect transistor 55 is equal to the gate-source voltage Vgs1. Since the source of the field effect transistor 55 is electrically connected to the ground potential GND, the source potential is approximately 0V. On the other hand, the drain of the field effect transistor 55 is applied with the input potential of the TIA section 11 (for example, about 0.5 to 2 V). Therefore, field effect transistor 55 is operating in the saturation region. The saturation region is the condition where the result of subtracting the threshold voltage from the gate-to-source voltage of the transistor is less than the drain-to-source voltage. In the saturation region, even if the drain voltage of the field effect transistor 55 increases, the degree to which the drain current increases is smaller than that in the linear region. Therefore, the impedance (output impedance) of the output terminal 51b becomes a relatively large value.

That is, the field effect transistors 54 and 55 form a current mirror circuit and output a DC bypass current Iaoc proportional to the control current Iaocnt. In other words, the feedback current source 52 causes the DC bypass current Iaoc to flow from the drain of the field effect transistor 55 to the source of the field effect transistor 55 according to the control current Iaocnt. As a result, the DC bypass current Iaoc is drawn from the photocurrent Ipd. As a result, the DC component and the low frequency component are removed from the difference ΔVtia, and the potential of the voltage signal Vtia is adjusted to the potential of the reference voltage signal Vref (DC offset control).

The variable resistance circuit 53B is a circuit that generates an AC bypass current Iagc according to the control current Icnt. More specifically, variable resistance circuit 53B generates AC bypass current Iagc according to control current Iagccnt. The variable resistance circuit 53B has a control terminal 53a, a resistance terminal 53b, and a resistance terminal 53c. Control terminal 53 a is electrically connected to output terminal 51 c of control circuit 51 and receives control current Iagccnt from control circuit 51 . The resistance terminal 53b is electrically connected to the input terminal 10a. Resistance terminal 53 c is electrically connected to an output terminal of reference voltage generation circuit 12 (voltage amplifier 12 a ) and receives reference voltage signal Vref from reference voltage generation circuit 12 . The variable resistance circuit 53B includes a field effect transistor 56 (first field effect transistor), a field effect transistor 57 (second field effect transistor), a resistance element 58 (first resistance element), and a resistance element 59 (second resistance element) and

Each of field effect transistors 56 and 57 is, for example, an N-channel MOS transistor. The size of field effect transistor 56 and the size of field effect transistor 57 may be the same or different. The sources of the field effect transistors 56 and 57 are electrically connected to each other and to the output terminal of the reference voltage generating circuit 12 (voltage amplifier 12a) through the resistance terminal 53c. A reference voltage signal Vref is input (supplied) to the sources of the field effect transistors 56 and 57 . The drain of field effect transistor 56 is electrically connected to output terminal 51c of control circuit 51 via control terminal 53a and receives control current Iagccnt from control circuit 51 . The gate of field effect transistor 56 is electrically connected to the drain of field effect transistor 56 . The drain of field effect transistor 57 is electrically connected to input terminal 10a through resistor terminal 53b. The gate of the field effect transistor 57 is electrically connected to the drain and gate of the field effect transistor 56 via the resistive element 58 .

Here, the field effect transistor has a substrate terminal, which is not usually shown in the circuit diagram. A substrate terminal (represented by a dotted line in FIG. 1) of the field effect transistor 56 is electrically connected to an output terminal of the reference voltage generating circuit 12 (voltage amplifier 12a) via a resistor terminal 53c. A reference voltage signal Vref is input (supplied) to the substrate terminal of the field effect transistor 56 . A substrate terminal of the field effect transistor 57 is electrically connected to an output terminal of the reference voltage generating circuit 12 (voltage amplifier 12a) via the resistance element 59 and the resistance terminal 53c. A reference voltage signal Vref is input (supplied) to the substrate terminal of the field effect transistor 57 via the resistance element 59 . Since no direct current flows through the substrate terminal of the field effect transistor 57, the (direct current) potential of the substrate terminal of the field effect transistor 57, like the (direct current) potential of the substrate terminal of the field effect transistor 56, is equal to the reference voltage signal Vref. set to a potential.

As shown in FIG. 5, the field effect transistor 57 has a capacitive component between each terminal of gate (G), source (S), drain (D), and substrate terminal (B). FIG. 6 shows an example of the capacitance value of each capacitance component. 6, the field effect transistor 57 is a 130 nm CMOS process, the gate width (channel width) W of the field effect transistor 57 is 30 μm, and the gate length (channel length) L of the field effect transistor 57 is 0. .13 .mu.m, a typical capacitance value when field effect transistor 57 operates in the deep triode region. A deep triode region is a condition in which the result of subtracting the threshold voltage from the gate-to-source voltage of the transistor is much greater than the drain-to-source voltage.

The capacitance value of the gate-source capacitance Cgs (second capacitance) and the capacitance value of the gate-drain capacitance Cgd (first capacitance) are equal to each other, ie, 7.1 fF. The capacitance value of the drain-source capacitance Cds is 2.6 fF. The capacitance value of the capacitance Cgb between the gate and the substrate terminal, the capacitance value of the capacitance Csb (fourth capacitance) between the source and the substrate terminal, and the capacitance value Cdb (third capacitance) between the drain and the substrate terminal The capacitance values are equal to each other and are 0.6 fF. Thus, the field effect transistor 57 has symmetrical capacitances (capacitance Cgs and capacitance Cgd) on the source side and the drain side with respect to the gate. In other words, field effect transistor 57 is configured such that capacitance Cgd and capacitance Cgs are equal to each other. Similarly, the field effect transistor 57 also has symmetrical capacitances (capacitance Csb and capacitance Cdb) on the source side and the drain side with respect to the substrate terminal. In other words, field effect transistor 57 is configured such that capacitance Cdb and capacitance Csb are equal to each other.

The number of fingers indicating the number of gates of a field effect transistor is an odd number. By setting the number of drains equal to the number of sources, the capacitance values of the capacitances Cgs and Cgd are equal to each other, and the capacitance values of the capacitances Csb and Cdb are equal to each other. A transistor 57 is obtained.

The capacitance value of the capacitance Csb is about 1/10 that of the capacitance Cgs, and the capacitance value of the capacitance Cdb is about 1/10 that of the capacitance Cgd. Capacitance Csb and capacitance Cdb have junction capacitance associated with a PN junction as their main component, whereas capacitance Cgs and capacitance Cgd have their main components overlap capacitance due to the gate oxide film. As described above, the capacitance Csb and the capacitance Cdb are sufficiently smaller than the capacitances Cgs and Cgd unless the areas of the source and drain are intentionally increased.

The resistance value Rg of the resistance element 58 is sufficiently larger than the impedance Zcgd due to the capacitance Cgd and the impedance Zcgs due to Cgs at high frequencies. The resistance value Rb of the resistance element 59 is sufficiently larger than the impedance Zcdb caused by the capacitance Cdb and the impedance Zcsb caused by the capacitance Csb.

In the variable resistance circuit 53B configured as described above, the control current Iagccnt flowing from the control terminal 53a flows through the diode-connected field effect transistor 56, thereby causing a gate current between the gate and the source of the field effect transistor 56. • Generate a source-to-source voltage Vgs2. The gate of field effect transistor 56 and the gate of field effect transistor 57 are electrically connected to each other through resistor element 58, and the source of field effect transistor 56 and the source of field effect transistor 57 are electrically connected to each other. It is Since the gate resistances of field effect transistors 56 and 57 are much larger than the resistance value of resistance element 58, the gate-source voltage of field effect transistor 57 is equal to gate-source voltage Vgs2. A reference voltage signal Vref is supplied to the source of the field effect transistor 57 , and the input potential of the TIA section 11 is applied to the drain of the field effect transistor 57 . Since the reference voltage signal Vref has substantially the same potential as the input potential of the TIA section 11, the field effect transistor 57 operates in the deep triode region. In the linear region, as the drain voltage of field effect transistor 57 increases, so does the drain current. Especially when the drain voltage is relatively small, it can be considered that the drain current varies (linearly) in proportion to the drain voltage. Let us denote the ratio of drain voltage to drain current as a resistance value _RAGC . That is, the field effect transistors 56 and 57 of the variable resistance circuit 53B are alternately grounded by the reference voltage generating circuit 12, and the field effect transistor 57 is biased in the deep triode region.

Using the intrinsic gain (gain coefficient) β of the field effect transistor 57 and the threshold voltage Vth, the drain current Id of the field effect transistor 57 biased in the triode region (that is, the AC bypass current Iagc) is given by Equation (1): can be represented by The intrinsic gain β is a value that depends on the semiconductor process of field effect transistor 57 .

In the triode region, if the potential difference between the drain and the source is small, the magnitude relationship between the drain potential and the source potential may be reversed. In this case, the terminal with the lowest voltage with respect to the gate functions as the source. Since circuit symbols of transistors are used for convenience in expressing circuits, the representation of terminals of transistors in circuit diagrams and the actual operation of transistors may not match. Here, the terminals are switched as appropriate so that the drain-source voltage Vds is 0 or more, and the terminal with the low potential is regarded as the source.

Here, since the field effect transistor 56 is diode-connected, the gate of the field effect transistor 57 is controlled by the differential resistance of the resistance element 58 and the diode-connected field effect transistor 56 to the reference voltage generating circuit 12 (voltage amplifier 12a). is electrically connected to the output terminal of The differential resistance value of the diode-connected field effect transistor 56 is approximately several kΩ, which is considerably smaller than the impedance Zcgd due to the capacitance Cgd of the field effect transistor 57 . Impedance Zcgd is, for example, 22 kΩ at 1 GHz. Assuming that the resistance value Rg of the resistance element 58 is 0Ω, the gate potential of the field effect transistor 56 follows the low impedance source potential (the potential of the reference voltage signal Vref). In this case, as shown in equation (2), the gate-source voltage Vgs2 is expressed by adding the drain-source voltage Vds to the gate-source voltage Vgs0. The gate-source voltage Vgs0 is the gate-source voltage when the drain-source voltage Vds is 0V.

By substituting equation (2) into equation (1), equation (3) is obtained. As shown in Equation (3), the drain current Id (AC bypass current Iagc) is proportional to the square of the drain-source voltage Vds, and thus contains nonlinear components.

As shown in Equation (4), the differential resistance value Rd (resistance value R _AGC ) is obtained by differentiating Equation (3) with respect to the drain-source voltage Vds and calculating the reciprocal of the operation result. As shown in equation (4), the resistance value _RAGC changes according to the drain-source voltage Vds. Since the drain potential is modulated according to the photocurrent Ipd, the resistance value _RAGC varies nonlinearly.

As shown in equation (5), the transconductance gm in the triode region is obtained by differentiating equation (3) with the gate-source voltage Vgs0. In the triode region, the drain-source voltage Vds is less than the voltage obtained by subtracting the threshold voltage Vth from the gate-source voltage Vgs2. Especially in the deep triode region, the drain-source voltage Vds is much smaller than the voltage obtained by subtracting the threshold voltage Vth from the gate-source voltage Vgs2, so the transconductance in the triode region gm is negligibly small compared to the transconductance in saturated operation.

On the other hand, since the resistance value Rg of the resistance element 58 is larger than the impedance Zcgd due to the capacitance Cgd (Rg>>Zcgd), the gate of the field effect transistor 57 and the gate of the field effect transistor 56 are controlled by the resistance element 58 at high frequencies ( a.c.) separated (isolated). Since the capacitance value of the capacitance Cgs and the capacitance value of the capacitance Cgd are equal to each other, the drain-source voltage Vds is divided in half, and the gate of the field effect transistor 57 is supplied with a voltage half the drain-source voltage Vds. (Vds/2) is applied.

Since the gate of the field effect transistor 57 can be electrically connected to the substrate terminal of the field effect transistor 57 via the capacitance Cgb at high frequencies, the potential of the substrate terminal of the field effect transistor 57 changes to the potential of the field effect transistor 57 via the capacitance Cgb. It can slightly affect the gate potential. However, since the resistance value Rb of the resistance element 59 is larger than the impedance Zcdb due to the capacitance Cdb (Rb>>Zcdb), the substrate terminal of the field effect transistor 57 is connected to the source of the field effect transistor 57 by the resistance element 59 at a high frequency. separated (isolated). Since the capacitance value of the capacitance Csb and the capacitance value of the capacitance Cdb are equal to each other, the drain-source voltage Vds is divided in half, and the substrate terminal of the field effect transistor 57 has half the drain-source voltage Vds. A voltage (Vds/2) is applied. Therefore, the influence of the potential of the substrate terminal of field effect transistor 57 on the gate potential of field effect transistor 57 is reduced.

In this case, as shown in equation (6), the gate-source voltage Vgs2 is expressed by adding half the drain-source voltage Vds to the gate-source voltage Vgs0.

By substituting equation (6) into equation (1), equation (7) is obtained. As shown in Equation (7), the drain current Id (AC bypass current Iagc) is proportional to the drain-source voltage Vds and therefore does not contain nonlinear components.

Furthermore, as shown in Equation (8), the differential resistance value Rd (resistance value R _AGC ) is obtained by differentiating Equation (7) with respect to the drain-source voltage Vds and calculating the reciprocal of the operation result. be done. As shown in equation (8), the resistance value _RAGC does not change with the drain-source voltage Vds.

That is, by superimposing half the drain-source voltage Vds (Vds/2) on the gate voltage of the field effect transistor 57 operating in the triode region, the differential resistance value Rd (resistance value R _AGC ) does not depend on the drain-source voltage Vds, and does not fluctuate from the resistance value when the drain-source voltage Vds is 0V.

That is, although the variable resistance circuit 53B has a circuit configuration similar to that of the feedback current source 52, it does not operate as a current mirror circuit, and the field effect transistor 57 is controlled by the gate-source voltage Vgs2. operates as a linear variable resistor. Since the potential of the resistor terminal 53b and the potential of the resistor terminal 53c are substantially the same, almost no DC component of the photocurrent Ipd flows through the variable resistor circuit 53B, and a part of the AC component of the photocurrent Ipd flows through the variable resistor circuit 53B ( It flows into the field effect transistor 57) as an AC bypass current Iagc. In other words, the variable resistance circuit 53B causes the AC bypass current Iagc to flow between the drain and source of the field effect transistor 57 according to the control current Iagccnt.

That is, when the photocurrent Ipd increases, the difference ΔVtia increases, and the control current Icnt exceeds the current value of the offset current Iofs, the control current Iagccnt is supplied to the variable resistance circuit 53B. As a result, a gate-source voltage Vgs2 is generated in the field effect transistors 56 and 57 . As the gate-source voltage Vgs2 increases, the resistance value _RAGC of the field effect transistor 57 decreases, so that part of the signal component (AC component) of the photocurrent Ipd excluding the DC component is extracted as the AC bypass current Iagc. . As a result, the possibility of saturation of the TIA section 11 by a large signal input is reduced.

As described above, a current proportional to the drain-source voltage flows between the drain and source of the field effect transistor 57 biased in the deep triode region (linear region). Since the reference voltage signal Vref has substantially the same potential as the input potential of the TIA section 11, no DC current flows and the AC bypass current Iagc does not disturb the DC offset control. A change in the resistance value _RAGC of field effect transistor 57 affects only the characteristics of the AOC control gain.

Also, since the resistance value _RAGC of the field effect transistor 57 does not depend on the drain-source voltage Vds, the AC bypass current Iagc is extracted from the photocurrent Ipd with low distortion. As a result, distortion is suppressed.

Next, the effects of the transimpedance amplifier circuit 10B will be described. FIG. 7(a) is a diagram showing changes in total harmonic distortion with respect to input light average power in the transimpedance amplifier circuit shown in FIG. FIG. 7(b) is a diagram showing changes in the output amplitude of the TIA section with respect to the input light average power in the transimpedance amplifier circuit shown in FIG. FIG. 7(c) is a diagram showing changes in amplitude at each terminal of the field effect transistor with respect to the input light average power in the transimpedance amplifier circuit shown in FIG. FIG. 8(a) is a diagram showing changes in total harmonic distortion with respect to input light average power in the transimpedance amplifier circuit of the comparative example. FIG. 8(b) is a diagram showing changes in the output amplitude of the TIA section with respect to the input light average power in the transimpedance amplifier circuit of the comparative example. FIG. 8(c) is a diagram showing changes in amplitude at each terminal of the field effect transistor with respect to the input light average power in the transimpedance amplifier circuit of the comparative example.

The horizontal axes of FIGS. 7(a) to 7(c) and FIGS. 8(a) to 8(c) represent the input light average power Pin_ave, which is the average value of the optical input power of the optical signal Pin. (unit: dBm). The vertical axis of (a) of FIG. 7 and (a) of FIG. 8 represents the total harmonic distortion (THD) (unit: %) of the output waveform (the waveform of the differential voltage signals Vout and Voutb). show. The vertical axes in (b) of FIG. 7 and (b) of FIG. 8 indicate the amplitude (unit: mVpp) of the voltage signal Vtia. The vertical axes in (c) of FIG. 7 and (c) of FIG.

In the calculation results shown in FIGS. 7A to 7C, the resistance value Rg of the resistance element 58 is set to 200 kΩ, and the resistance value Rb of the resistance element 59 is set to 5 kΩ (hereinafter referred to as "Example"). In the calculation results shown in FIGS. 8A to 8C, the resistance value Rg of the resistance element 58 and the resistance value Rb of the resistance element 59 are both set to 0Ω (hereinafter referred to as “comparative example”). called.). The current value of the offset current Iofs is set so that the AGC operates when the input optical average power Pin_ave exceeds around -1 dBm. As the total harmonic distortion factor, the total harmonic distortion factor is calculated taking into consideration up to the 10th harmonic. In order to prevent distortion from occurring in the differential amplifier circuit 13 at the subsequent stage, the size of the field effect transistor 57 is determined so that the amplitude of the voltage signal Vtia does not exceed 500 mVpp at maximum. The gain (voltage gain) of the TIA section 11 is set to 10 times, and the resistance value of the feedback resistance element 11b is set to 550Ω. An optical signal obtained by intensity modulation with a sine wave of 1 GHz is used as the optical signal Pin, and the amplitude of the optical signal Pin is set to be the same as the input optical average power Pin_ave (approximately 5 dB in extinction ratio). It is A photoelectric conversion gain of the light receiving element PD is set to 1.0 A/W for simplifying the calculation.

Comparing (a) of FIG. 7 with (a) of FIG. 8, when the input light average power Pin_ave is 3 dBm, the THD is 5.2% in the comparative example, whereas the THD is 5.2% in the example. It can be seen that it is reduced to 4.1%. Comparing (b) of FIG. 7 and (b) of FIG. 8, it can be seen that the amplitude of the voltage signal Vtia is controlled in the same way in the comparative example and the working example. In other words, although the extraction amount of the AC bypass current Iagc in the example is the same as that in the comparative example, it can be seen that the THD of the example is better than the THD of the comparative example. According to (c) of FIG. 8, since the gate-source voltage Vgs2 of the comparative example is represented by Equation (2), it can be seen that the amplitude of the gate potential Vg is approximately equal to the amplitude of the source potential Vs. On the other hand, according to FIG. 7(c), in the embodiment, the amplitude of the gate potential Vg is approximately half the amplitude of the drain potential Vd. This indicates that the drain-source voltage Vds of the field effect transistor 57 is divided by the capacitance Cgs and the capacitance Cgd, and the gate-source voltage Vgs2 is expressed by Equation (6). According to (c) of FIG. 7 and (c) of FIG. 8, in both the comparative example and the working example, the amplitude of the source potential Vs increases when the average input light power Pin_ave exceeds -1 dB. This is because the reference voltage signal Vref is modulated by the photocurrent Ipd as the AC bypass current Iagc increases because the output impedance of the reference voltage generation circuit 12 is not zero. As described above, at the time of gain control (at the time of AGC operation), the embodiment can improve THD by about 1% as compared with the comparative example.

As described above, in the transimpedance amplifier circuit 10B, the bypass circuit 15B generates the DC bypass current Iaoc and the AC bypass current Iagc. A current signal Iin is generated by withdrawing Iagc. Then, the TIA unit 11 converts the current signal Iin into a voltage signal Vtia, and the differential amplifier circuit 13 generates differential voltage signals Vout and Voutb according to the difference ΔVtia between the voltage signal Vtia and the reference voltage signal Vref. In the variable resistance circuit 53B, the field effect transistor 56 is diode-connected. Therefore, when the drain of the field effect transistor 56 receives the control current Iagccnt, the gate-source voltage Vgs2 is applied across the gate and source of the field effect transistor 56. is generated. The gate of the field effect transistor 56 and the gate of the field effect transistor 57 are electrically connected to each other through a resistance element 58, and the source of the field effect transistor 56 and the source of the field effect transistor 57 are supplied with a reference voltage signal Vref. supplied. Since the gate resistances of field effect transistors 56 and 57 are much larger than resistance value Rg of resistance element 58, the gate-source voltage of field effect transistor 57 is equal to gate-source voltage Vgs2.

A reference voltage signal Vref is supplied to the source of the field effect transistor 57, and the drain of the field effect transistor 57 is electrically connected to the input terminal 10a. This causes the field effect transistor 57 to operate in the (deep) triode region. Therefore, the field effect transistor 57 functions as a variable resistor, and the output impedance of the drain of the field effect transistor 57 becomes low. Since there is almost no potential difference between the drain and source of the field effect transistor 57, the DC component of the photocurrent Ipd hardly flows into the field effect transistor 57, but the AC component of the photocurrent Ipd flows through the field effect transistor 57 as the AC bypass current Iagc. can flow into Since the control current Iagccnt is obtained by amplifying the difference between the current generated by amplifying the control current Icnt and the offset current Iofs with the amplification factor γ, when the control current Icnt exceeds the current value of the offset current Iofs Furthermore, as the control current Icnt increases, the control current Iagccnt increases, and the gate-source voltage Vgs2 of the field effect transistor 56 also increases. Therefore, when the photocurrent Ipd has a small or medium signal strength, the extraction of the AC bypass current Iagc is suppressed, and the attenuation of the AC component of the photocurrent Ipd can be avoided. When the photocurrent Ipd has a large signal strength, the AC component of the photocurrent Ipd can be attenuated because the AC component of the photocurrent Ipd is extracted from the photocurrent Ipd as the AC bypass current Iagc. Thus, the variable resistance circuit 53B controls the gain of the transimpedance amplifier circuit 10B.

The gate of the field effect transistor 57 is electrically connected to the gate of the field effect transistor 56 through the resistance element 58, and since the field effect transistor 56 is diode-connected, the gate of the field effect transistor 57 is connected to the resistance It is connected to the output terminal (reference voltage signal Vref) of the reference voltage generation circuit 12 via the element 58 and the differential resistance of the field effect transistor 56 . However, since the resistance value Rg of the resistance element 58 is larger than the impedance Zcgd by the capacitance Cgd, the gates of the field effect transistors 57 and 56 can be separated (isolated) in high frequency by the resistance element 58 . Therefore, a voltage obtained by dividing the drain-source voltage Vds by the capacitance Cgd and the capacitance Cgs is applied to the gate of the field effect transistor 57 . Since the field effect transistor 57 is configured such that the capacitance Cgd and the capacitance Cgs are equal to each other, a voltage approximately half the drain-source voltage Vds is applied to the gate of the field effect transistor 57 . This suppresses the differential resistance value (resistance value R _AGC ) of the field effect transistor 57 from fluctuating due to the drain-source voltage Vds. As a result, the occurrence of distortion is suppressed, so that signal quality can be improved.

Note that the output impedance of the resistance terminal 53b may be determined in consideration of the input impedance Zin of the TIA section 11. FIG. For example, when the variable gain ratio of the TIA section 11 is A (A is a real number greater than 1), the output impedance of the resistance terminal 53b is set to Zin/(A-1). As a result, if the value of the current signal Iin of the TIA unit 11 when AGC is not performed is Iinoff, the value Iinon of the current signal Iin when AGC is performed is Iinon=Iinoff/A. For example, when A=2, the output impedance of the resistor terminal 53b is substantially equal to Zin, and when A is larger than 2, the output impedance of the resistor terminal 53b is made smaller than Zin. Therefore, when performing AOC and AGC simultaneously, the output impedance of the output terminal 52b is set to be larger than the output impedance of the resistance terminal 53b. By the way, when AGC is not performed, the output impedance of the resistance terminal 53b may be 100×Zin or more. The output impedance of resistor terminal 53b can be considered equal to the resistance value _RAGC described above. For example, by making the gate voltage of the field effect transistor 57 substantially equal to the threshold voltage of the field effect transistor 57, the output impedance of the resistor terminal 53b is increased. Since the input impedance Zin and the output impedance of the resistor terminal 53b can have different frequency characteristics, it is sufficient that the above relationship is satisfied at least within a predetermined frequency range (band).

Since the substrate terminal of the field effect transistor 57 is electrically connected to the gate of the field effect transistor 57 via the capacitance Cgb, the potential of the substrate terminal of the field effect transistor 57 is applied to the gate of the field effect transistor 57 via the capacitance Cgb. Can affect potentials. On the other hand, the substrate terminal of the field effect transistor 57 is supplied with the reference voltage signal Vref through the resistance element 59, and the resistance value Rb of the resistance element 59 is larger than the impedance Zcdb due to the capacitance Cdb (Rb >> Zcdb ), and is larger than the impedance Zcsb due to the capacitance Csb (Rb>>Zcsb), the substrate terminal of the field effect transistor 57 can be isolated from the outside of the field effect transistor 57 in high frequency by the resistor element 59 . Since the field effect transistor 57 is configured such that the capacitance Cdb and the capacitance Csb are equal to each other, a voltage approximately half the drain-source voltage Vds is applied to the substrate terminal of the field effect transistor 57 . As a result, the potential of the substrate terminal of the field effect transistor 57 becomes approximately the same as the gate potential of the field effect transistor 57, so that the influence of the potential of the substrate terminal of the field effect transistor 57 on the gate potential of the field effect transistor 57 is reduced. becomes possible. As a result, the occurrence of distortion is further suppressed, so that signal quality can be further improved.

The bypass circuit 15B includes a feedback current source 52 that generates a DC bypass current Iaoc according to the control current Icnt, and a variable resistance circuit 53B that generates an AC bypass current Iagc according to the control current Icnt. The control circuit 51 controls the feedback current source 52 so that the DC bypass current Iaoc increases as the control current Icnt increases, and the control current Icnt increases when the control current Icnt exceeds the current value of the offset current Iofs. The variable resistance circuit 53B is controlled so that the AC bypass current Iagc increases as the voltage increases. According to this configuration, it is possible to realize the control of removing the DC component and the gain control of the transimpedance amplifier circuit 10B with a single control loop, so that it is possible to suppress an increase in the circuit scale. Become.

In the feedback current source 52, the field effect transistor 54 is diode-connected. Therefore, when the drain of the field effect transistor 54 receives the control current Iaocnt, the gate-source voltage Vgs1 is applied between the gate and source of the field effect transistor 54. is generated. Since the gates of the field effect transistors 54 and 55 are electrically connected to each other, and the sources of the field effect transistors 54 and 55 are electrically connected to each other, the electric field The gate-source voltage of the effect transistor 55 becomes equal to the gate-source voltage Vgs1. The source of the field effect transistor 55 is electrically connected to the source of the field effect transistor 54, that is, the ground potential GND, and the drain of the field effect transistor 55 is electrically connected to the input terminal 10a. The potential difference between the source and the drain increases. As a result, the field effect transistor 55 operates in the saturation region. Therefore, the field effect transistor 55 functions as a current source, and the output impedance of the drain of the field effect transistor 55 is increased. The component can flow into field effect transistor 55 as a DC bypass current Iaoc. Then, as the control current Icnt increases, the gate-source voltage Vgs1 of the field effect transistor 54 increases, so the drain current of the field effect transistor 55 increases accordingly, and the DC component of the photocurrent Ipd becomes the DC bypass current. Iaoc is extracted from the photocurrent Ipd, and the DC component is properly removed from the photocurrent Ipd. The level of the output impedance of the output terminal 52b may be determined in consideration of the input impedance of the TIA section 11. FIG. For example, when the input impedance of the TIA section 11 is Zin, the output impedance of the output terminal 52b may be 100×Zin or more. Since the input impedance Zin and the output impedance of the output terminal 52b can have different frequency characteristics, it is sufficient that such a relationship is satisfied at least within a predetermined frequency range (band).

The reference voltage generation circuit 12 includes a voltage amplifier 12a and a feedback resistance element 12b electrically connected between the input and output of the voltage amplifier 12a. With this configuration, the output impedance of the reference voltage generating circuit 12 is low over a wide frequency range. That is, the impedance of the variable resistance circuit 53B viewed from the input terminal of the TIA section 11 becomes low over a wide frequency range. Therefore, the AC bypass current Iagc can be easily extracted from the photocurrent Ipd.

Since the DC component is removed using the high impedance feedback current source 52, the AC component of the photocurrent Ipd is less affected (the AC component does not flow). On the other hand, gain control is performed by bypassing the AC component of the photocurrent Ipd using the variable resistance circuit 53B. (DC component does not flow). As a result, interference between DC component removal control and gain control can be avoided.

As described above, according to the transimpedance amplifier circuit 10B, the gain control of the transimpedance amplifier circuit 10B and the DC offset control for setting the difference ΔVtia to 0 can be controlled by a single control loop without mutual interference. and gain control can be performed with low distortion.

Note that the transimpedance amplifier circuit according to the present disclosure is not limited to the above embodiments.

The circuit configurations of the TIA section 11, the reference voltage generation circuit 12, the differential amplifier circuit 13, the control current generation circuit 14, and the bypass circuit 15B are not limited to those shown in the above embodiments. For example, the TIA unit 11 may be configured to convert the current signal Iin into the voltage signal Vtia. The reference voltage generation circuit 12 may be configured to be able to supply the reference voltage signal Vref. The control current generation circuit 14 may be configured to generate the control current Icnt based on the integrated value of the difference ΔVtia.

The control circuit 51 is not limited to the circuit configuration shown in FIG. 4, and may be configured to generate the control current Iaocnt and the control current Iagccnt shown in FIG. Feedback current source 52 may be configured to generate DC bypass current Iaoc such that DC bypass current Iaoc increases as control current Iaocnt increases. The feedback current source 52 includes, for example, instead of the diode-connected field effect transistor 54, a resistive element provided to change the gate-source voltage of the field effect transistor 55 according to the control current Iaocnt. good too. The source of field effect transistor 55 may not be electrically connected to ground potential GND, and the source potential of field effect transistor 55 may be set so that field effect transistor 55 operates in the saturation region. . That is, the source potential of field effect transistor 55 is set such that the drain potential of field effect transistor 55 is higher than the source potential of field effect transistor 55 . Also, the bypass circuit 15B does not have to control the feedback current source 52 and the variable resistance circuit 53B with a single control loop.

Since the potential of the substrate terminal of the field effect transistor 57 does not significantly affect the gate potential, the variable resistance circuit 53B does not need to include the resistance element 59 (that is, the resistance value Rb=0). 57 may not be configured such that capacitance Cdb and capacitance Csb are equal to each other. Even in this case, the differential resistance value (resistance value R _AGC ) of the field effect transistor 57 is suppressed from fluctuating due to the drain-source voltage Vds. As a result, the occurrence of distortion is suppressed, so that signal quality can be improved.

Further, the transimpedance amplifier circuit 10B may not include the reference voltage generation circuit 12, and the transimpedance amplifier circuit 10B may be supplied with the reference voltage signal Vref from an external reference voltage generation circuit.

In the above embodiment, the magnitude of the control current Iaocnt (DC bypass current Iaoc) is adjusted by the amplification factor α. and the current mirror ratio of transistors 61,62. Similarly, the magnitude of the DC bypass current Iaoc may be adjusted by the current mirror ratio of the field effect transistors 54,55.

In the above embodiment, the magnitude of the control current Iagccnt (AC bypass current Iagc) is adjusted by the current values of the amplification factor γ and the offset current Iofs. It may be adjusted by the amplification factor γ, the current mirror ratio of the transistors 61 and 63, and the current value of the offset current Iofs. Similarly, the magnitude of the AC bypass current Iagc may be adjusted by the size of the field effect transistor 56, the size of the field effect transistor 57, and the like.

In the above embodiment, the field effect transistors 54 and 55 and the transistors 61 to 69 are field effect transistors, but the field effect transistors 54 and 55 and the transistors 61 to 69 are bipolar transistors. good too. When field effect transistors 54, 55 and transistors 61-69 are bipolar transistors, the gate, source and drain of the field effect transistors are read as base, emitter and collector, respectively.

DESCRIPTION OF SYMBOLS 1B... Optical receiver, 10B... Transimpedance amplifier circuit, 10a... Input terminal, 11... TIA section (single-ended amplifier circuit), 11a... Voltage amplifier, 11b... Feedback resistance element, 12... Reference voltage generation circuit, 12a... Voltage amplifier (amplifier) 12b Feedback resistance element 13 Differential amplifier circuit 14 Control current generation circuit 15B Bypass circuit 41 Integration circuit 41a Input terminal 41b Input terminal 41c Output terminal 41d output terminal 42 OTA 43 operational amplifier 43a non-inverting input terminal 43b inverting input terminal 43c inverting output terminal 43d non-inverting output terminal 44 resistive element 45 resistive element 46...capacitor 47...capacitor 51...control circuit 51a...input terminal 51b...output terminal 51c...output terminal 51d...power supply terminal 52...feedback current source 52a...input terminal 52b...output terminal 52c Ground terminal 53B Variable resistance circuit 53a Control terminal 53b Resistance terminal 53c Resistance terminal 54 Field effect transistor (third field effect transistor) 55 Field effect transistor (fourth field effect transistor) , 56... Field effect transistor (first field effect transistor), 57... Field effect transistor (second field effect transistor), 58... Resistance element (first resistance element), 59... Resistance element (second resistance element), 61 ~ 69... Transistor 70... Current source Cdb... Capacity (third capacity) Cds... Capacity Cgb... Capacity Cgd... Capacity (first capacity) Cgs... Capacity (second capacity) Csb... Capacity (second capacity) 4 capacity), GND... Ground potential, Iaoc... DC bypass current, Iaocnt... Control current (second control current), Iagc... AC bypass current, Iagccnt... Control current (first control current), Icnt... Control current, Iin... current signal, Iofs...offset current, Ipd...photocurrent (input current signal), Iref...reference current, N...node, Pin...optical signal, PD...light receiving element, VCC...power supply voltage, Vgs1...gate-source voltage, Vgs2... gate-source voltage, Vinn... voltage signal, Vinp... voltage signal, Vout, Voutb... differential voltage signal, VPD... bias voltage, Vref... reference voltage signal, Vtia... voltage signal.

Claims (5)

A transimpedance amplifier circuit that generates a differential voltage signal in response to an input current signal generated by a light receiving element,
an input terminal for receiving the input current signal;
a single-ended amplifier circuit that converts a current signal into a voltage signal;
a differential amplifier circuit that generates the differential voltage signal according to the difference between the voltage signal and a reference voltage signal;
a control current generation circuit that generates a control current based on the integrated value of the difference;
a bypass circuit that generates a DC bypass current and an AC bypass current according to the control current;
with
the current signal is generated by subtracting the DC bypass current and the AC bypass current from the input current signal;
The bypass circuit includes a control circuit to which the control current is input, and a variable resistance circuit that generates the AC bypass current according to the control current,
The control circuit generates an offset current having a predetermined offset current value, and amplifies a difference between the current generated by amplifying the control current and the offset current with a first amplification factor to obtain a first control current. to generate
The variable resistance circuit is
a first drain receiving the first control current; a first gate electrically connected to the first drain; a first source supplied with the reference voltage signal; a first field effect transistor having a substrate terminal;
a first resistance element;
A second drain electrically connected to the input terminal, a second gate electrically connected to the first drain and the first gate via the first resistance element, and the reference voltage signal are supplied. a second field effect transistor having a second source to which the reference voltage signal is applied and a second substrate terminal to which the reference voltage signal is applied;
with
The second field effect transistor is configured such that a first capacitance between the second gate and the second drain and a second capacitance between the second gate and the second source are equal to each other. is composed of
the resistance value of the first resistance element is greater than the impedance of the first capacitor;
The variable resistance circuit is a transimpedance amplifier circuit that causes the AC bypass current to flow from the second drain to the second source according to the first control current. The variable resistance circuit further comprises a second resistance element,
The reference voltage signal is supplied to the second substrate terminal via the second resistance element,
In the second field effect transistor, a third capacitance between the second substrate terminal and the second drain and a fourth capacitance between the second substrate terminal and the second source are equal to each other. is configured as
2. The transimpedance amplifier circuit according to claim 1, wherein the resistance value of said second resistance element is greater than the impedance of said third capacitor. The bypass circuit further comprises a feedback current source that generates the DC bypass current according to the control current,
3. The transimpedance amplifier circuit according to claim 1, wherein said control circuit controls said feedback current source such that said DC bypass current increases as said control current increases. The control circuit generates a second control current by amplifying the control current with a second amplification factor,
The feedback current source is
a third field effect transistor having a third drain for receiving the second control current, a third gate electrically connected to the third drain, and a third source electrically connected to ground potential; ,
a fourth drain electrically connected to the input terminal; a fourth gate electrically connected to the third drain and the third gate; and a fourth source electrically connected to the third source. and a fourth field effect transistor having
with
4. The transimpedance amplifier circuit according to claim 3, wherein said feedback current source causes said DC bypass current to flow from said fourth drain to said fourth source according to said second control current. further comprising a reference voltage generation circuit that generates the reference voltage signal;
5. The transimpedance amplifier circuit according to claim 1, wherein said reference voltage generation circuit comprises an amplifier and a feedback resistance element electrically connected between input and output of said amplifier. .

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