JP7251387B2 - Transimpedance amplifier circuit - Google Patents

Description

The present disclosure relates to transimpedance amplifier circuits.

Conventionally, there is a transimpedance amplifier circuit that converts an optical signal for optical communication into an electrical signal (see Patent Documents 1 and 2, for example). Optical signals having various signal intensities can be input to such a transimpedance amplifier circuit, for example, when used in a PON (Passive Optical Network) type optical access system. Optical signals also have a DC component as well as an AC component that carries information. For this reason, the transimpedance amplifier circuit has a function to remove the DC component contained in the electrical signal converted from the optical signal, and a function to control the gain to ensure a dynamic range that can handle various signal strengths. , is required.

For example, Patent Document 1 discloses an amplifier that converts an input current into an output voltage, a differential amplifier that converts the output voltage into a differential output signal, and a bypass circuit that extracts a bypass current from a photocurrent generated by a photodiode. , is described. In this amplifier circuit, the bypass circuit extracts the bypass current so that the average value of the output voltage and the reference voltage match. Patent Literature 2 describes a transimpedance amplifier circuit that includes a control circuit that controls the removal of direct current and a control circuit that controls the amplitude of the differential output voltage.

JP 2012-10107 A U.S. Pat. No. 9,774,305

In the amplifier circuit disclosed in Patent Document 1, a diode and a current source are connected between an input terminal and a ground potential, and the diode is driven by an emitter follower circuit included in a bypass circuit. Since the output impedance of the emitter follower circuit is low over a wide frequency range, the bypass current can contain not only a DC component but also an AC component. Therefore, although the DC component is removed from the photocurrent, the AC component is also removed, reducing the amplitude of the output voltage and lowering the gain of the transimpedance amplifier circuit. In such a transimpedance amplifier circuit, when a small signal with a small signal strength and a signal with a medium signal strength are input as a photocurrent, the diode is turned off in order to prevent the AC component from being attenuated. can be considered to be In this case, since the DC component is not removed from the input current of the amplifier, the output voltage becomes higher than the reference voltage, and the input signal of the differential amplifier is modulated biased toward the high level side of the signal logic. As a result, the differential output signal may be distorted, degrading the signal quality.

On the other hand, in the transimpedance amplifier circuit disclosed in Patent Document 2, different control circuits control the removal of the DC component of the input current and the control of the amplitude. Therefore, the circuit scale becomes large.

In the present disclosure, a transimpedance amplifier circuit that can appropriately perform DC component removal control and gain control while suppressing the circuit scale will be described.

A transimpedance amplifier circuit according to one aspect of the present disclosure is a circuit that generates a differential voltage signal according to an input current signal generated by a light receiving element. This transimpedance amplifier circuit includes an input terminal that receives an input current signal, a single-ended amplifier circuit that converts the current signal into a voltage signal, and a differential voltage signal that is generated according to the difference between the voltage signal and the reference voltage signal. A differential amplifier circuit, a control current generation circuit that generates a control current based on an integral value of a difference between a voltage signal and a reference voltage signal, and a bypass circuit that generates a DC bypass current and an AC bypass current according to the control current. And prepare. A current signal is generated by subtracting a DC bypass current and an AC bypass current from the input current signal. The bypass circuit includes a control circuit to which a control current is input, a feedback current source that generates a DC bypass current according to the control current, and a variable resistance circuit that generates an AC bypass current according to the control current. The control circuit controls the feedback current source so that the DC bypass current increases as the control current increases, and when the control current exceeds a predetermined offset current value, the AC bypass current increases as the control current increases. The variable resistance circuit is controlled so that

According to the present disclosure, it is possible to appropriately perform DC component removal control and gain control while reducing the circuit scale.

FIG. 1 is a diagram schematically showing the configuration of an optical receiver that includes a transimpedance amplifier circuit according to one embodiment. FIG. 2 is a diagram showing a circuit configuration example of the integrating circuit shown in FIG. FIG. 3 is a diagram showing the relationship between the control current supplied to the control circuit shown in FIG. 1 and the current generated by the control circuit. FIG. 4 is a diagram showing a circuit configuration example of the control circuit shown in FIG. FIG. 5 is a diagram showing DC (Direct Current) offset characteristics and gain characteristics in the transimpedance amplifier circuit shown in FIG.

[Description of Embodiments of the Present Disclosure]
First, the contents of the embodiments of the present disclosure will be listed and described.

A transimpedance amplifier circuit according to one aspect of the present disclosure is a circuit that generates a differential voltage signal according to an input current signal generated by a light receiving element. This transimpedance amplifier circuit includes an input terminal that receives an input current signal, a single-ended amplifier circuit that converts the current signal into a voltage signal, and a differential voltage signal that is generated according to the difference between the voltage signal and the reference voltage signal. A differential amplifier circuit, a control current generation circuit that generates a control current based on an integral value of a difference between a voltage signal and a reference voltage signal, and a bypass circuit that generates a DC bypass current and an AC bypass current according to the control current. And prepare. A current signal is generated by subtracting a DC bypass current and an AC bypass current from the input current signal. The bypass circuit includes a control circuit to which a control current is input, a feedback current source that generates a DC bypass current according to the control current, and a variable resistance circuit that generates an AC bypass current according to the control current. The control circuit controls the feedback current source so that the DC bypass current increases as the control current increases, and when the control current exceeds a predetermined offset current value, the AC bypass current increases as the control current increases. The variable resistance circuit is controlled so that

In this transimpedance amplifier circuit, a feedback current source generates a DC bypass current, a variable resistance circuit generates an AC bypass current, and the DC bypass current and the AC bypass current are extracted from the input current signal generated by the light receiving element. A current signal is thus generated. Then, the single-ended amplifier circuit converts the current signal into a voltage signal, and the differential amplifier circuit generates a differential voltage signal according to the difference between the voltage signal and the reference voltage signal. A control current is generated based on the integrated value of the difference between the voltage signal and the reference voltage signal, and the feedback current source is controlled so that the DC bypass current increases as the control current increases. is withdrawn from the input current signal as a DC bypass current to remove the DC component from the input current signal. On the other hand, when the control current exceeds a predetermined offset current value, the variable resistance circuit is controlled such that the AC bypass current increases as the control current increases. Therefore, when the input current signal is relatively small, the drawing of the AC bypass current is suppressed, and the attenuation of the AC component can be avoided. When the input current signal is relatively large, the AC component of the input current signal can be attenuated because the AC component of the input current signal is withdrawn from the input current signal as the AC bypass current. Since the feedback current source and the variable resistance circuit are both controlled by one control circuit, it is possible to appropriately control the removal of the DC component and control the gain while suppressing the circuit scale.

The control circuit may generate the first control current by amplifying the control current with a first amplification factor. A feedback current source has a first electric field having a first drain for receiving a first control current, a first gate electrically connected to the first drain, and a first source electrically connected to ground potential. an effect transistor, a second drain electrically connected to the input terminal, a second gate electrically connected to the first drain and the first gate, and a second source electrically connected to the first source. and a second field effect transistor having. The feedback current source may pass a DC bypass current from the second drain to the second source in response to the first control current. In this case, since the first field effect transistor is diode-connected, when the first drain of the first field effect transistor receives the first control current, a gate-source voltage is generated between the first gate and the first source. is generated. Since the first gate and the second gate are electrically connected to each other, and the first source and the second source are electrically connected to each other, the voltage between the gate and the source of the second field effect transistor is 1 equal to the gate-source voltage of a field effect transistor. In the second field effect transistor, the second source is electrically connected to the first source, that is, the ground potential, and the second drain is electrically connected to the input terminal. The potential difference increases. Thereby, the second field effect transistor operates in the saturation region. Therefore, the second field effect transistor functions as a current source, and the output impedance of the second drain becomes large. Therefore, although the AC component of the input current signal hardly flows into the second field effect transistor, the DC component of the input current signal can flow into the second field effect transistor as a DC bypass current. As the control current increases, the voltage between the gate and the source of the first field effect transistor increases, so that the DC component of the input current signal is extracted as a DC bypass current from the input current signal. Removal is done properly.

The control circuit may generate an offset current having an offset current value, and generate a second control current by amplifying a difference between the current generated by amplifying the control current and the offset current with a second amplification factor. You may The variable resistance circuit is a third field effect transistor having a third drain receiving a second control current, a third gate electrically connected to the third drain, and a third source supplied with a reference voltage signal. a fourth drain electrically connected to the input terminal; a fourth gate electrically connected to the third drain and the third gate; and a fourth source supplied with a reference voltage signal. 4 field effect transistors. The variable resistance circuit may pass an AC bypass current from the fourth drain to the fourth source in response to the second control current. In this case, since the third field effect transistor is diode-connected, when the third drain of the third field effect transistor receives the second control current, a gate-source voltage is applied between the third gate and the third source. is generated. The third gate and the fourth gate are electrically connected to each other, and the reference voltage signal is supplied to the third source and the fourth source, so that the gate-source voltage of the fourth field effect transistor is the third It is equal to the gate-source voltage of a field effect transistor. In the fourth field effect transistor, since the reference voltage signal is supplied to the fourth source and the fourth drain is electrically connected to the input terminal, there is almost no potential difference between the fourth drain and the fourth source. This causes the fourth field effect transistor to operate in the (deep) triode region (linear region). Therefore, the fourth field effect transistor functions as a variable resistor and the output impedance of the fourth drain becomes low. Since there is almost no potential difference between the fourth drain and the fourth source, the DC component of the input current signal hardly flows into the fourth field effect transistor, but the AC component of the input current signal acts as an AC bypass current through the fourth field effect transistor. can flow into When the control current exceeds a predetermined offset current value, the voltage between the gate and the source of the third field effect transistor increases as the control current increases. is suppressed, and attenuation of the AC component can be avoided. When the input current signal is relatively large, the AC component of the input current signal can be attenuated because the AC component of the input current signal is withdrawn from the input current signal as the AC bypass current. Therefore, the variable resistance circuit appropriately controls the gain of the transimpedance amplifier.

The transimpedance amplifier circuit may further include a reference voltage generation circuit that generates a reference voltage signal. The reference voltage generation circuit may include an amplifier and a feedback resistance element electrically connected between the input and output of the amplifier. In this case, the output impedance of the reference voltage generating circuit becomes low over a wide frequency range. That is, the impedance of the variable resistance circuit viewed from the input terminal of the single-ended amplifier circuit becomes low over a wide frequency range. Therefore, it is possible to easily extract the AC bypass current from the input current signal.

[Details of the embodiment of the present disclosure]
A specific example of a transimpedance amplifier circuit according to an embodiment of the present disclosure will be described below with reference to the drawings. The present disclosure is not limited to these examples, but is indicated by the scope of the claims, and is intended to include all modifications within the scope and meaning equivalent to the scope of the claims.

FIG. 1 is a diagram schematically showing the configuration of an optical receiver that includes a transimpedance amplifier circuit according to one embodiment. FIG. 2 is a diagram showing a circuit configuration example of the integrating circuit shown in FIG. FIG. 3 is a diagram showing the relationship between the control current supplied to the control circuit shown in FIG. 1 and the current generated by the control circuit. FIG. 4 is a diagram showing a circuit configuration example of the control circuit shown in FIG.

The optical receiver 1 shown in FIG. 1 receives an optical signal Pin transmitted from an optical transmitter (not shown). The optical receiver 1 includes a light receiving element PD and a transimpedance amplifier circuit 10 . The light receiving element PD receives the optical signal Pin and generates a photocurrent Ipd (input current signal) corresponding to the optical signal Pin. The photocurrent Ipd may contain a DC component. Examples of the light receiving element PD include photodiodes and avalanche photodiodes. One terminal of the light receiving element PD is electrically connected to a predetermined bias voltage VPD, and the other terminal of the light receiving element PD outputs a photocurrent Ipd.

The transimpedance amplifier circuit 10 receives the photocurrent Ipd generated by the photodetector PD and generates differential voltage signals Vout and Voutb, which are voltage signals, according to the photocurrent Ipd. The differential voltage signals Vout, Voutb are a pair of complementary signals. The transimpedance amplifier circuit 10 has an input terminal 10a. A photocurrent Ipd is input to the input terminal 10a.

The transimpedance amplifier circuit 10 includes a TIA (TransImpedance Amplifier) section 11 (single-ended amplifier circuit), a reference voltage generator circuit 12, a differential amplifier circuit 13, a control current generator circuit 14, and a bypass circuit 15. Prepare.

The TIA unit 11 is a circuit that converts the current signal Iin into a voltage signal Vtia. Specifically, the TIA section 11 includes a voltage amplifier 11a and a feedback resistance element 11b. The input terminal and the output terminal of the voltage amplifier 11a are electrically connected via the feedback resistance element 11b. That is, the feedback resistance element 11b is electrically connected between the input and output of the voltage amplifier 11a. The current signal Iin is generated by extracting the DC bypass current Iaoc and the AC bypass current Iagc from the photocurrent Ipd. The DC bypass current Iaoc and the AC bypass current Iagc are controlled by the bypass circuit 15, the details of which will be described later. The increase/decrease of the voltage signal Vtia is inverted with respect to the increase/decrease of the current signal Iin. The voltage amplifier 11a is, for example, an inverting amplifier circuit. The TIA section 11 outputs the voltage signal Vtia to the differential amplifier circuit 13 and the control current generation circuit 14 . The gain of the TIA section 11 (the ratio of the magnitude of the voltage signal Vtia to the magnitude of the current signal Iin) is determined by the resistance value (transimpedance) of the feedback resistance element 11b.

The reference voltage generation circuit 12 is a circuit that generates a reference voltage signal Vref, which is a DC voltage signal. The reference voltage generator circuit 12 outputs the reference voltage signal Vref to the differential amplifier circuit 13 and the control current generator circuit 14 . The reference voltage signal Vref has a predetermined voltage value (fixed value). The reference voltage generation circuit 12 may be configured such that the output impedance is low over a wide band. In this embodiment, the reference voltage generation circuit 12 includes a voltage amplifier 12a (amplifier) and a feedback resistance element 12b, similarly to the TIA section 11. FIG. An input terminal and an output terminal of the voltage amplifier 12a are electrically connected via a feedback resistance element 12b. That is, the feedback resistance element 12b is electrically connected between the input and output of the voltage amplifier 12a. Since the reference voltage generation circuit 12 has a circuit configuration similar to that of the TIA section 11, the reference voltage signal Vref is generated so as to compensate (offset) changes in the voltage signal Vtia due to changes in the power supply voltage and temperature of the voltage amplifier 11a. obtain.

The differential amplifier circuit 13 is a circuit that generates differential voltage signals Vout and Voutb according to the difference ΔVtia (error) between the voltage signal Vtia and the reference voltage signal Vref. In other words, the differential amplifier circuit 13 uses the reference voltage signal Vref to convert the single (single-phase) voltage signal Vtia into the differential voltage signals Vout and Voutb. The differential amplifier circuit 13 generates differential voltage signals Vout and Voutb by amplifying the difference ΔVtia. The differential amplifier circuit 13 outputs the differential voltage signals Vout and Voutb to a subsequent circuit (not shown).

The control current generation circuit 14 is a circuit that generates the control current Icnt based on the integrated value of the difference ΔVtia between the voltage signal Vtia and the reference voltage signal Vref. The control current generation circuit 14 includes an integration circuit 41 and an OTA (Operational Transconductance Amplifier) 42 .

The integration circuit 41 is a circuit that integrates the difference ΔVtia. As shown in FIG. 2, the integration circuit 41 has input terminals 41a and 41b and output terminals 41c and 41d. The input terminal 41a is electrically connected to the output terminal of the reference voltage generation circuit 12 (voltage amplifier 12a), and the reference voltage signal Vref is input to the input terminal 41a. The input terminal 41b is electrically connected to the output terminal of the TIA section 11 (voltage amplifier 11a), and the voltage signal Vtia is input to the input terminal 41b. The output terminal 41 c is electrically connected to the inverting input terminal of the OTA 42 and outputs the voltage signal Vinn to the OTA 42 . The output terminal 41 d is electrically connected to the non-inverting input terminal of the OTA 42 and outputs the voltage signal Vinp to the OTA 42 .

The integration circuit 41 includes an operational amplifier 43 , resistance elements 44 and 45 , and capacitors 46 and 47 . The operational amplifier 43 has a non-inverting input terminal 43a, an inverting input terminal 43b, an inverting output terminal 43c, and a non-inverting output terminal 43d. The non-inverting input terminal 43a is electrically connected to the input terminal 41a through the resistance element 44. As shown in FIG. The inverting input terminal 43b is electrically connected through the resistance element 45 to the input terminal 41b. The inverting output terminal 43c is electrically connected to the output terminal 41c and electrically connected to the non-inverting input terminal 43a via the capacitor . That is, the capacitor 46 connects the inverting output terminal 43c and the non-inverting input terminal 43a by negative feedback. The non-inverting output terminal 43d is electrically connected to the output terminal 41d and is electrically connected via the capacitor 47 to the inverting input terminal 43b. That is, the capacitor 47 connects between the non-inverting output terminal 43d and the inverting input terminal 43b by negative feedback.

Here, the gain of the operational amplifier 43 is infinite, the resistance value R1 of the resistance element 44 and the resistance value R2 of the resistance element 45 are equal to each other, and the capacitance value C1 of the capacitor 46 and the capacitance value C2 of the capacitor 47 are equal to each other. , the integration circuit 41 operates as an integrator with a time constant R1×C1.

The OTA 42 is a circuit that converts a differential voltage signal (voltage signal Vinp and voltage signal Vinn) into a control current Icnt that is a single current signal (error current). The OTA 42 has a known circuit configuration, for example, a configuration in which a current mirror circuit is added to a differential amplifier circuit. The OTA 42 has transconductance, and the input/output impedance of the OTA 42 is, for example, infinite. The control current Icnt is obtained by multiplying the input differential voltage, which is the difference between the voltage signal Vinp and the voltage signal Vinn input to the OTA 42, by the transconductance. The difference between the voltage signal Vinp and the voltage signal Vinn changes according to the integrated value of the difference ΔVtia. The OTA 42 outputs the control current Icnt to the bypass circuit 15 .

The bypass circuit 15 is a circuit that generates a DC bypass current Iaoc and an AC bypass current Iagc according to the control current Icnt. The bypass circuit 15 includes a control circuit 51 , a feedback current source 52 and a variable resistance circuit 53 .

A control current Icnt is input to the control circuit 51 . Control circuit 51 controls feedback current source 52 so that DC bypass current Iaoc increases as control current Icnt increases. When the control current Icnt exceeds the current value of the offset current Iofs, the control circuit 51 controls the variable resistance circuit 53 so that the AC bypass current Iagc increases as the control current Icnt increases. The current value of the offset current Iofs is a predetermined current value (fixed value). Specifically, the control circuit 51 receives the control current Icnt from the control current generation circuit 14 (OTA 42), and generates a control current Iaocnt (first control current) and a control current Iagccnt (second control current) according to the control current Icnt. to generate The control circuit 51 outputs a control current Iaocnt to the feedback current source 52 and controls the feedback current source 52 with the control current Iaocnt. The control circuit 51 outputs a control current Iagccnt to the variable resistance circuit 53 and controls the variable resistance circuit 53 with the control current Iagccnt.

As shown in FIG. 3, the current value of the control current Iaocnt is proportional to the current value of the control current Icnt. The current value of the control current Iaocnt is α times the current value of the control current Icnt (Iaocnt=α×Icnt). The control circuit 51 generates the control current Iaocnt by, for example, amplifying the control current Icnt with an amplification factor α. The current value of control current Iagccnt is proportional to the current value of control current Icnt when the current value of control current Icnt is greater than the current value of offset current Iofs. In other words, the current value of the control current Iagccnt is γ times the current value obtained by subtracting the current value of the offset current Iofs from the control current Icnt (Iagccnt=γ×(Icnt−Iofs)). The control circuit 51 generates, for example, an offset current Iofs having a predetermined current value (offset current value), and a current generated by amplifying the control current Icnt (here, the control current Icnt) and the offset current Iofs. A control current Iagccnt is generated by amplifying the difference with an amplification factor γ. Thus, the control current Iaocnt adjusts the amplification factor α, and the control current Iagccnt adjusts the offset current value for determining the current at which automatic gain control (AGC) starts and the control sensitivity of the AGC. The amplification factor γ to be determined is adjusted.

Control circuit 51 shown in FIG. 4 has a circuit configuration for realizing control current Iaocnt and control current Iagccnt shown in FIG. As shown in FIG. 4, the control circuit 51 has an input terminal 51a, output terminals 51b and 51c, and a power supply terminal 51d. The input terminal 51a is electrically connected to the output terminal of the control current generation circuit 14 (OTA 42), and the control current Icnt is input to the input terminal 51a. The output terminal 51 b is electrically connected to the input terminal 52 a of the feedback current source 52 and outputs the control current Iaocnt to the feedback current source 52 . The output terminal 51 c is electrically connected to the control terminal 53 a of the variable resistance circuit 53 and outputs the control current Iagccnt to the variable resistance circuit 53 . The power supply terminal 51d is electrically connected to a power supply wiring that supplies a power supply voltage VCC, and the power supply voltage VCC is supplied to the power supply terminal 51d.

The control circuit 51 includes transistors 61 to 69 and a current source 70 . The transistors 61 to 69 are, for example, field effect transistors (MOSFET) having a MOS (Metal-Oxide-Semiconductor) structure. In the example shown in FIG. 4, transistors 61-63 are N-channel MOS transistors and transistors 64-69 are P-channel MOS transistors.

Transistors 61-63 form a current mirror circuit. Transistor 61 functions as an input transistor and transistors 62 and 63 function as output transistors. The sources of transistors 61-63 are electrically connected to ground potential GND. The gate and drain of the transistor 61 are electrically connected to each other and further to the input terminal 51a. The respective gates of transistors 62 and 63 are electrically connected to the gate and drain of transistor 61 . The drain of transistor 62 is electrically connected to the drain and gate of transistor 64 . The drain of transistor 63 is electrically connected through node N to the drain and gate of transistor 68 .

Since the transistors 61 and 62 and the transistors 61 and 63 respectively form a current mirror circuit, for example, the output current (drain current) proportional to the magnitude of the drain current (control current Icnt) of the transistor 61 is generated by the transistors. They are output from the drains of 62 and 63, respectively. Here, for convenience of explanation, the current mirror ratio is assumed to be 1:1:1. Therefore, the control current Icnt input to the input terminal 51a is copied by the transistors 61 to 63, and the control currents Icnt are output from the drains of the transistors 62 and 63, respectively. Note that the control current Icnt flows toward the drains of the transistors 62 and 63 .

Transistors 64 and 65 form a current mirror circuit. Transistor 64 functions as an input transistor and transistor 65 functions as an output transistor. The sources of transistors 64 and 65 are electrically connected to power supply terminal 51d. The gate and drain of transistor 64 are electrically connected together and to the drain of transistor 62 . The gate of transistor 65 is electrically connected to the gate and drain of transistor 64 . A drain of the transistor 65 is electrically connected to the output terminal 51b.

The control current Icnt output from the drain of the transistor 62 is input to the drain of the transistor 64 , and the output current (drain current) proportional to the magnitude of the drain current (control current Icnt) of the transistor 64 is applied to the transistor 65 . is output from the drain of as a control current Iaocnt. Here, the current mirror ratio of the current mirror circuit formed by the transistors 64 and 65 is set to 1:α. That is, the control current Iaocnt is a current (α×Icnt) of a magnitude obtained by amplifying the control current Icnt by α times. Note that the control current Iaocnt flows from the drain of the transistor 65 toward the output terminal 51b.

Transistors 66 and 67 form a current mirror circuit. Transistor 66 functions as an input transistor and transistor 67 functions as an output transistor. The sources of the transistors 66 and 67 are electrically connected to the power supply terminal 51d. The gate and drain of transistor 66 are electrically connected together and to a current source 70 . The gate of transistor 67 is electrically connected to the gate and drain of transistor 66 . The drain of transistor 67 is electrically connected through node N to the drain and gate of transistor 68 .

The reference current Iref supplied from the current source 70 is input to the drain of the transistor 66 , and the output current (drain current) of the transistor 67 is proportional to the magnitude of the drain current (reference current Iref) of the transistor 66 . It is output from the drain as an offset current Iofs. Here, the current mirror ratio of the current mirror circuit composed of transistors 66 and 67 is set to 1:m. That is, the offset current Iofs is a current (m×Iref) having a magnitude obtained by amplifying the reference current Iref by m times. Note that offset current Iofs flows from the drain of transistor 67 toward node N. FIG. The value of m is arbitrarily selected according to the optical power desired to operate the AGC. Since the current value of the reference current Iref is a fixed value, the current value (offset current value) of the offset current Iofs is also a fixed value.

Transistors 68 and 69 form a current mirror circuit. Transistor 68 functions as an input transistor and transistor 69 functions as an output transistor. The sources of transistors 68 and 69 are electrically connected to power supply terminal 51d. The gate and drain of the transistor 68 are electrically connected to each other, and further electrically connected to the drain of the transistor 63 and the drain of the transistor 67 through the node N. The gate of transistor 69 is electrically connected to the gate and drain of transistor 68 . A drain of the transistor 69 is electrically connected to the output terminal 51c.

Control current Icnt output from the drain of transistor 63 is combined with offset current Iofs output from the drain of transistor 67 at node N. FIG. Specifically, the offset current Iofs is subtracted (subtracted) from the control current Icnt. At this time, only when the current value of the control current Icnt is greater than the current value of the offset current Iofs, the difference current (Icnt-Iofs) flows to the drain of the transistor 68, and the magnitude of the drain current (difference current) of the transistor 68 is is output from the drain of the transistor 69 as the control current Iagccnt. Here, the current mirror ratio of the current mirror circuit composed of transistors 68 and 69 is set to 1:γ. That is, the control current Iagccnt is a current (γ×(Icnt−Iofs)) obtained by amplifying the difference current (Icnt−Iofs) by γ times. Note that the control current Iagccnt flows from the drain of the transistor 69 toward the output terminal 51c.

On the other hand, when the current value of the control current Icnt is smaller than the current value of the offset current Iofs, no current flows through the transistor 68. Therefore, the diode-connected transistor 68 causes the potential of the node N to rise to the power supply voltage VCC side. pulled up with a high resistance to Also, since the voltage between the drain and the source of the transistor 67 becomes small, the transistors 66 and 67 do not operate as a current mirror circuit. At this time, since the transistor 67 operates in the triode region, the potential of the node N is pulled up to the power supply voltage VCC side with a low resistance. The triode region is the condition in which the result of subtracting the threshold voltage from the gate-source voltage of the transistor is greater than the drain-source voltage. Since no gate-source voltage is applied to the transistor 68 , the resistance value of the transistor 67 to which the gate-source voltage is applied is smaller than the resistance value of the transistor 68 . As a result of the transistor 67 operating in the triode region, the transistor 67 cannot supply the offset current Iofs, and all of the control current Icnt from the transistor 63 flows through the transistor 67 . Thus, control current Iagccnt is output from output terminal 51c only when the current value of control current Icnt is greater than the current value of offset current Iofs (in the region of Icnt-Iofs>0).

Although the input/output characteristics of FIG. 3 are obtained by the control circuit 51 shown in FIG. 4, the current mirror ratio can be changed as appropriate. Further, as the circuit configuration of the control circuit 51, another circuit configuration that can obtain the input/output characteristics of FIG. 3 may be adopted.

Feedback current source 52 constitutes an Auto-Offset Control (AOC) circuit. The feedback current source 52 is a circuit that generates a DC bypass current Iaoc according to the control current Icnt. More specifically, feedback current source 52 generates DC bypass current Iaoc in response to control current Iaocnt. The feedback current source 52 has an input terminal 52a, an output terminal 52b, and a ground terminal 52c. The input terminal 52 a is electrically connected to the output terminal 51 b of the control circuit 51 and receives the control current Iaocnt from the control circuit 51 . The output terminal 52b is electrically connected to the input terminal 10a and outputs a DC bypass current Iaoc. Ground terminal 52c is electrically connected to ground potential GND. Feedback current source 52 includes a field effect transistor 54 and a field effect transistor 55 .

Each of field effect transistors 54 and 55 is, for example, an N-channel MOS transistor. The size of field effect transistor 54 and the size of field effect transistor 55 may be the same or different. Sources of field effect transistors 54 and 55 are electrically connected to each other and to ground potential GND via ground terminal 52c. The drain of field effect transistor 54 is electrically connected to output terminal 51b of control circuit 51 via input terminal 52a and receives control current Iaocnt from control circuit 51 . The gate of field effect transistor 54 is electrically connected to the drain of field effect transistor 54 . The drain of the field effect transistor 55 is electrically connected to the input terminal 10a through the output terminal 52b. The gate of field effect transistor 55 is electrically connected to the drain and gate of field effect transistor 54 .

In the feedback current source 52 configured in this manner, the control current Iaocnt flowing from the input terminal 52a flows through the diode-connected field effect transistor 54, thereby causing a gate current between the gate and the source of the field effect transistor 54. • Generate a source-to-source voltage Vgs1. The gates of the field effect transistors 54 and 55 are electrically connected to each other, and the sources of the field effect transistors 54 and 55 are electrically connected to each other. The gate-source voltage of the effect transistor 55 is equal to the gate-source voltage Vgs1. Since the source of the field effect transistor 55 is electrically connected to the ground potential GND, the source potential is approximately 0V. On the other hand, the drain of the field effect transistor 55 is applied with the input potential of the TIA section 11 (for example, about 0.5 to 2 V). Therefore, field effect transistor 55 is operating in the saturation region. The saturation region is the condition where the result of subtracting the threshold voltage from the gate-to-source voltage of the transistor is less than the drain-to-source voltage. In the saturation region, even if the drain voltage of the field effect transistor 55 increases, the degree to which the drain current increases is smaller than that in the linear region. Therefore, the impedance (output impedance) of the output terminal 51b becomes a relatively large value.

That is, the field effect transistors 54 and 55 form a current mirror circuit and output a DC bypass current Iaoc proportional to the control current Iaocnt. In other words, the feedback current source 52 causes the DC bypass current Iaoc to flow from the drain of the field effect transistor 55 to the source of the field effect transistor 55 according to the control current Iaocnt. As a result, the DC bypass current Iaoc is drawn from the photocurrent Ipd. As a result, the DC component and the low frequency component are removed from the difference ΔVtia, and the potential of the voltage signal Vtia is adjusted to the potential of the reference voltage signal Vref (DC offset control).

The variable resistance circuit 53 is a circuit that generates an AC bypass current Iagc according to the control current Icnt. More specifically, variable resistance circuit 53 generates AC bypass current Iagc according to control current Iagccnt. The variable resistance circuit 53 has a control terminal 53a, a resistance terminal 53b, and a resistance terminal 53c. Control terminal 53 a is electrically connected to output terminal 51 c of control circuit 51 and receives control current Iagccnt from control circuit 51 . The resistance terminal 53b is electrically connected to the input terminal 10a. Resistance terminal 53 c is electrically connected to an output terminal of reference voltage generation circuit 12 (voltage amplifier 12 a ) and receives reference voltage signal Vref from reference voltage generation circuit 12 . The variable resistance circuit 53 includes field effect transistors 56 and 57 .

Each of field effect transistors 56 and 57 is, for example, an N-channel MOS transistor. The size of field effect transistor 56 and the size of field effect transistor 57 may be the same or different. The sources of the field effect transistors 56 and 57 are electrically connected to each other and to the output terminal of the reference voltage generating circuit 12 (voltage amplifier 12a) through the resistance terminal 53c. A reference voltage signal Vref is input (supplied) to the sources of the field effect transistors 56 and 57 . The drain of field effect transistor 56 is electrically connected to output terminal 51c of control circuit 51 via control terminal 53a and receives control current Iagccnt from control circuit 51 . The gate of field effect transistor 56 is electrically connected to the drain of field effect transistor 56 . The drain of field effect transistor 57 is electrically connected to input terminal 10a through resistor terminal 53b. The gate of field effect transistor 57 is electrically connected to the drain and gate of field effect transistor 56 .

In the variable resistance circuit 53 configured as described above, the control current Iagccnt flowing from the control terminal 53a flows through the diode-connected field effect transistor 56, thereby causing a gate current between the gate and the source of the field effect transistor 56. • Generate a source-to-source voltage Vgs2. The gates of the field effect transistors 56 and 57 are electrically connected to each other, and the sources of the field effect transistors 56 and 57 are electrically connected to each other. The gate-source voltage of the effect transistor 57 is equal to the gate-source voltage Vgs2. A reference voltage signal Vref is supplied to the source of the field effect transistor 57 , and the input potential of the TIA section 11 is applied to the drain of the field effect transistor 57 . Since the reference voltage signal Vref has substantially the same potential as the input potential of the TIA section 11, the field effect transistor 57 operates in a deep triode region (linear region). A deep triode region is a condition in which the result of subtracting the threshold voltage from the gate-to-source voltage of the transistor is much greater than the drain-to-source voltage. In the linear region, as the drain voltage of field effect transistor 57 increases, so does the drain current. Especially when the drain voltage is relatively small, it can be considered that the drain current varies (linearly) in proportion to the drain voltage. Let us denote the ratio of drain voltage to drain current as a resistance value _RAGC .

The resistance value _RAGC of the field effect transistor 57 is expressed by Equation (1) using the intrinsic gain β of the field effect transistor 57 and the threshold voltage Vth. In addition, the intrinsic gain β is determined by the process and size of the field effect transistor 57 . As shown in equation (1), as the gate-source voltage Vgs2 increases, the resistance value _RAGC decreases.

That is, although the variable resistance circuit 53 has the same circuit configuration as the feedback current source 52, it does not operate as a current mirror circuit, and the field effect transistor 57 is controlled by the gate-source voltage Vgs2. operates as a variable resistor Since the potential of the resistor terminal 53b and the potential of the resistor terminal 53c are substantially the same, almost no DC component of the photocurrent Ipd flows through the variable resistor circuit 53, and a part of the AC component of the photocurrent Ipd flows through the variable resistor circuit 53 ( It flows into the field effect transistor 57) as an AC bypass current Iagc. In other words, the variable resistance circuit 53 causes the AC bypass current Iagc to flow between the drain and source of the field effect transistor 57 according to the control current Iagccnt.

That is, when the photocurrent Ipd increases, the difference ΔVtia increases, and the control current Icnt exceeds the current value of the offset current Iofs, the control current Iagccnt is supplied to the variable resistance circuit 53 . As a result, a gate-source voltage Vgs2 is generated in the field effect transistors 56 and 57 . As the gate-source voltage Vgs2 increases, the resistance value _RAGC of the field effect transistor 57 decreases, so that part of the signal component (AC component) of the photocurrent Ipd excluding the DC component is extracted as the AC bypass current Iagc. . As a result, the possibility of saturation of the TIA section 11 by a large signal input is reduced.

A current proportional to the drain-source voltage flows between the drain and source of the field effect transistor 57 biased in the deep triode region (linear region). Since the reference voltage signal Vref has substantially the same potential as the input potential of the TIA section 11, no DC current flows and the AC bypass current Iagc does not disturb the DC offset control. A change in the resistance value of the field effect transistor 57 affects only the characteristics of the AOC control gain.

Next, the effects of the transimpedance amplifier circuit 10 will be described. 5 is a diagram showing DC offset characteristics and gain characteristics in the transimpedance amplifier circuit shown in FIG. 1. FIG. The dashed line shown in FIG. 5 indicates the DC offset characteristic. The DC offset characteristic indicates the dependence of the DC offset amount on the optical input level of the optical signal Pin. A solid line in FIG. 5 indicates the gain characteristic. The gain characteristic indicates the dependence of the transimpedance gain Zt of the transimpedance amplifier circuit 10 on the optical input level of the optical signal Pin.

As described above, when extracting current from the photocurrent Ipd, it is possible to control the DC component (the DC bypass current Iaoc) and the AC component (the AC bypass current Iagc) separately. Therefore, for a small signal of -30 dBm to -15 dBm, no AC component is extracted from the photocurrent Ipd. Therefore, at small signals, only the DC offset is controlled by drawing only the DC bypass current Iaoc from the photocurrent Ipd.

When the optical input level of the signal exceeds -15 dBm, the control current Iagccnt begins to flow through the variable resistance circuit 53, and the resistance value _RAGC of the field effect transistor 57 decreases. As a result, the AC bypass current Iagc is drawn from the photocurrent Ipd, and the transimpedance gain Zt of the transimpedance amplifier circuit 10 begins to decrease. As the transimpedance gain Zt decreases, the open-loop transfer gain of the control loop decreases, so that the amount of DC offset suppression decreases slightly. However, since this amount of suppression is of a magnitude expressed in units of μV, the amount of variation in the DC offset is so small that it can be ignored with respect to the signal amplitude. Therefore, distortion due to saturation of the transimpedance amplifier circuit 10 is suppressed in a wide range of optical input levels, and stable reception characteristics can be obtained.

Further, in the transimpedance amplifier circuit 10, a single control loop (single integration circuit 41 and single control circuit 51) can realize DC offset control and gain control, so that the circuit scale is reduced. It is possible to suppress the increase in size. Further, by adjusting the response of the control circuit 51 (amplification factor α, amplification factor γ, current values of the offset current Iofs, etc.), the optical input level can be arbitrarily controlled.

As described above, in the transimpedance amplifier circuit 10, the feedback current source 52 generates the DC bypass current Iaoc, the variable resistance circuit 53 generates the AC bypass current Iagc, and the photocurrent Ipd generated by the light receiving element PD , the DC bypass current Iaoc and the AC bypass current Iagc are extracted to generate the current signal Iin. Then, the TIA unit 11 converts the current signal Iin into a voltage signal Vtia, and the differential amplifier circuit 13 generates differential voltage signals Vout and Voutb according to the difference ΔVtia between the voltage signal Vtia and the reference voltage signal Vref. A control current Icnt is generated based on the integrated value of the difference ΔVtia, and the feedback current source 52 is controlled so that the DC bypass current Iaoc increases as the control current Icnt increases. The current Iaoc is extracted from the photocurrent Ipd, and the DC component is removed from the photocurrent Ipd. On the other hand, when control current Icnt exceeds the current value of offset current Iofs, variable resistance circuit 53 is controlled such that AC bypass current Iagc increases as control current Icnt increases. Therefore, when the photocurrent Ipd is relatively small, the DC component of the photocurrent Ipd is extracted as the DC bypass current Iaoc, but the extraction of the AC bypass current Iagc is suppressed. Attenuation of the AC component of the photocurrent Ipd can be avoided. When the photocurrent Ipd is relatively large, the DC component of the photocurrent Ipd is extracted as the DC bypass current Iaoc, and the AC component of the photocurrent Ipd is extracted as the AC bypass current Iagc from the photocurrent Ipd. The AC component of the photocurrent Ipd can be attenuated while removing the DC component of the photocurrent Ipd. Since the feedback current source 52 and the variable resistance circuit 53 are both controlled by the single control circuit 51, it is possible to perform DC component removal control and gain control in a single control loop. As a result, it becomes possible to perform DC component removal control and gain control while reducing the circuit scale.

In the feedback current source 52, the field effect transistor 54 is diode-connected. Therefore, when the drain of the field effect transistor 54 receives the control current Iaocnt, the gate-source voltage Vgs1 is applied between the gate and source of the field effect transistor 54. is generated. Since the gates of the field effect transistors 54 and 55 are electrically connected to each other, and the sources of the field effect transistors 54 and 55 are electrically connected to each other, the electric field The gate-source voltage of the effect transistor 55 is equal to the gate-source voltage Vgs1. The source of the field effect transistor 55 is electrically connected to the source of the field effect transistor 54, that is, the ground potential GND, and the drain of the field effect transistor 55 is electrically connected to the input terminal 10a. The potential difference between the source and the drain increases. As a result, the field effect transistor 55 operates in the saturation region. Therefore, the field effect transistor 55 functions as a current source, and the output impedance of the drain of the field effect transistor 55 is increased. The component can flow into field effect transistor 55 as a DC bypass current Iaoc. Then, as the control current Icnt increases, the gate-source voltage Vgs1 of the field effect transistor 54 increases, so the drain current of the field effect transistor 55 increases accordingly, and the DC component of the photocurrent Ipd becomes the DC bypass current. Iaoc is extracted from the photocurrent Ipd, and the DC component is properly removed from the photocurrent Ipd. The level of the output impedance of the output terminal 52b may be determined in consideration of the input impedance of the TIA section 11. FIG. For example, when the input impedance of the TIA section 11 is Zin, the output impedance of the output terminal 52b may be 100×Zin or more. Since the input impedance Zin and the output impedance of the output terminal 52b can have different frequency characteristics, it is sufficient that such a relationship is satisfied at least within a predetermined frequency range (band).

In the variable resistance circuit 53, the field effect transistor 56 is diode-connected. Therefore, when the drain of the field effect transistor 56 receives the control current Iagccnt, the gate-source voltage Vgs2 is applied across the gate and source of the field effect transistor 56. is generated. Since the gates of the field effect transistors 56 and 57 are electrically connected to each other, and the sources of the field effect transistors 56 and 57 are electrically connected to each other, the electric field The gate-source voltage of the effect transistor 57 is equal to the gate-source voltage Vgs2. A reference voltage signal Vref is supplied to the source of the field effect transistor 57, and the drain of the field effect transistor 57 is electrically connected to the input terminal 10a. This causes the field effect transistor 57 to operate in the (deep) triode region. Therefore, the field effect transistor 57 functions as a variable resistor, and the output impedance of the drain of the field effect transistor 57 becomes low. Since there is almost no potential difference between the drain and source of the field effect transistor 57, the DC component of the photocurrent Ipd hardly flows into the field effect transistor 57, but the AC component of the photocurrent Ipd flows through the field effect transistor 57 as the AC bypass current Iagc. can flow into When the control current Icnt exceeds the current value of the offset current Iofs, the gate-source voltage Vgs2 of the field effect transistor 56 increases as the control current Icnt increases. It is possible to suppress the withdrawal of the AC bypass current Iagc and avoid the attenuation of the AC component. When the photocurrent Ipd is relatively large, the AC component of the photocurrent Ipd is extracted as the AC bypass current Iagc from the photocurrent Ipd, so that the AC component of the photocurrent Ipd can be attenuated. Therefore, the variable resistance circuit 53 controls the gain of the transimpedance amplifier circuit 10 .

Note that the output impedance of the resistance terminal 53b may be determined in consideration of the input impedance Zin of the TIA section 11. FIG. For example, when the variable gain ratio of the TIA section 11 is A (A is a real number greater than 1), the output impedance of the resistance terminal 53b is set to Zin/(A-1). As a result, if the value of the current signal Iin of the TIA unit 11 when AGC is not performed is Iinoff, the value Iinon of the current signal Iin when AGC is performed is Iinon=Iinoff/A. For example, when A=2, the output impedance of the resistor terminal 53b is substantially equal to Zin, and when A is larger than 2, the output impedance of the resistor terminal 53b is made smaller than Zin. Therefore, when performing AOC and AGC simultaneously, the output impedance of the output terminal 52b is set to be larger than the output impedance of the resistance terminal 53b. By the way, when AGC is not performed, the output impedance of the resistance terminal 53b may be 100×Zin or more. The output impedance of resistor terminal 53b can be considered equal to the resistance value _RAGC described above. For example, by making the gate voltage of the field effect transistor 57 substantially equal to the threshold voltage of the field effect transistor 57, the output impedance of the resistor terminal 53b is increased. Since the input impedance Zin and the output impedance of the resistor terminal 53b can have different frequency characteristics, it is sufficient that the above relationship is satisfied at least within a predetermined frequency range (band).

The reference voltage generation circuit 12 includes a voltage amplifier 12a and a feedback resistance element 12b electrically connected between the input and output of the voltage amplifier 12a. With this configuration, the output impedance of the reference voltage generating circuit 12 is low over a wide frequency range. That is, the impedance of the variable resistance circuit 53 viewed from the input terminal of the TIA section 11 becomes low over a wide frequency range. Therefore, the AC bypass current Iagc can be easily extracted from the photocurrent Ipd.

Since the DC component is removed using the high impedance feedback current source 52, the AC component of the photocurrent Ipd is less affected (the AC component does not flow). On the other hand, the gain control is performed by bypassing the AC component of the photocurrent Ipd using the variable resistance circuit 53. Since the potential of the drain and the source of the field effect transistor 57 are substantially equal, the DC of the photocurrent Ipd is controlled. It has little effect on components (DC components do not flow). As a result, interference between DC component removal control and gain control can be avoided.

Note that the transimpedance amplifier circuit according to the present disclosure is not limited to the above embodiments.

The circuit configurations of the TIA section 11, the reference voltage generation circuit 12, the differential amplifier circuit 13, the control current generation circuit 14, and the bypass circuit 15 are not limited to those shown in the above embodiments. For example, the TIA unit 11 may be configured to convert the current signal Iin into the voltage signal Vtia. The reference voltage generation circuit 12 may be configured to be able to supply the reference voltage signal Vref. The control current generation circuit 14 may be configured to generate the control current Icnt based on the integrated value of the difference ΔVtia.

The control circuit 51 is not limited to the circuit configuration shown in FIG. 4, and may be configured to generate the control current Iaocnt and the control current Iagccnt shown in FIG. Feedback current source 52 may be configured to generate DC bypass current Iaoc such that DC bypass current Iaoc increases as control current Iaocnt increases. The feedback current source 52 includes, for example, instead of the diode-connected field effect transistor 54, a resistive element provided to change the gate-source voltage of the field effect transistor 55 according to the control current Iaocnt. good too. The source of the field effect transistor 55 does not have to be electrically connected to the ground potential GND, as long as the potential of the source of the field effect transistor 55 is set so that the field effect transistor 55 operates in the saturation region. good. That is, the potential of the source of the field effect transistor 55 is set such that the potential of the drain of the field effect transistor 55 is higher than the potential of the source of the field effect transistor 55 .

Variable resistance circuit 53 may be configured to generate AC bypass current Iagc such that AC bypass current Iagc increases as AC bypass current Iagc increases. Instead of the diode-connected field effect transistor 56, the variable resistance circuit 53 may include a resistance element provided to change the voltage between the gate and source of the field effect transistor 57 according to the control current Iagccnt. . The source of the field effect transistor 57 may not be electrically connected to the output terminal of the reference voltage generating circuit 12, and the source of the field effect transistor 57 may be connected so that the field effect transistor 57 operates in the triode region. It is sufficient if the potential is set. That is, the source potential of the field effect transistor 57 is set so that the drain potential of the field effect transistor 57 and the source potential of the field effect transistor 57 are substantially equal.

Further, the transimpedance amplifier circuit 10 may not include the reference voltage generation circuit 12, and the transimpedance amplifier circuit 10 may be supplied with the reference voltage signal Vref from an external reference voltage generation circuit.

In the above embodiment, the magnitude of the control current Iaocnt (DC bypass current Iaoc) is adjusted by the amplification factor α. and the current mirror ratio of transistors 61,62. Similarly, the magnitude of the DC bypass current Iaoc may be adjusted by the current mirror ratio of the field effect transistors 54,55.

In the above embodiment, the magnitude of the control current Iagccnt (AC bypass current Iagc) is adjusted by the current values of the amplification factor γ and the offset current Iofs. It may be adjusted by the amplification factor γ, the current mirror ratio of the transistors 61 and 63, and the current value of the offset current Iofs. Similarly, the magnitude of the AC bypass current Iagc may be adjusted by the size of the field effect transistor 56, the size of the field effect transistor 57, and the like.

In the above embodiment, the field effect transistors 54 and 55 and the transistors 61 to 69 are field effect transistors, but the field effect transistors 54 and 55 and the transistors 61 to 69 are bipolar transistors. good too. When field effect transistors 54, 55 and transistors 61-69 are bipolar transistors, the gate, source and drain of the field effect transistors are read as base, emitter and collector, respectively.

DESCRIPTION OF SYMBOLS 1... Optical receiver 10... Transimpedance amplifier circuit 10a... Input terminal 11... TIA part (single-ended amplifier circuit) 11a... Voltage amplifier 11b... Feedback resistance element 12... Reference voltage generation circuit 12a... Voltage amplifier 12b Feedback resistance element 13 Differential amplifier circuit 14 Control current generation circuit 15 Bypass circuit 41 Integration circuit 41a Input terminal 41b Input terminal 41c Output terminal 41d Output terminals 42... OTA 43... Operational amplifier 43a... Non-inverting input terminal 43b... Inverting input terminal 43c... Inverting output terminal 43d... Non-inverting output terminal 44... Resistance element 45... Resistance element 46... Capacitor , 47 Capacitor 51 Control circuit 51a Input terminal 51b Output terminal 51c Output terminal 51d Power supply terminal 52 Feedback current source 52a Input terminal 52b Output terminal 52c Ground terminal , 53... variable resistance circuit, 53a... control terminal, 53b... resistance terminal, 53c... resistance terminal, 54... field effect transistor, 55... field effect transistor, 56... field effect transistor, 57... field effect transistor, 61 to 69... Transistor 70 Current source GND Ground potential Iagc AC bypass current Iagccnt control current (second control current) Iaoc DC bypass current Iaocnt control current (first control current) Icnt control current , Iin...current signal, Iofs...offset current, Ipd...photocurrent (input current signal), Iref...reference current, N...node, Pin...optical signal, PD...light receiving element, VCC...power supply voltage, Vgs1...gate/source voltage between gate and source, Vinn: voltage signal, Vinp: voltage signal, Vout, Voutb: differential voltage signal, VPD: bias voltage, Vref: reference voltage signal, Vtia: voltage signal.

Claims (4)

A transimpedance amplifier circuit that generates a differential voltage signal in response to an input current signal generated by a light receiving element,
an input terminal for receiving the input current signal;
a single-ended amplifier circuit that converts a current signal into a voltage signal;
a differential amplifier circuit that generates the differential voltage signal according to the difference between the voltage signal and a reference voltage signal;
a control current generation circuit that generates a control current based on the integrated value of the difference;
a bypass circuit that generates a DC bypass current and an AC bypass current in accordance with the control current;
with
the current signal is generated by subtracting the DC bypass current and the AC bypass current from the input current signal;
The bypass circuit includes a control circuit to which the control current is input, a feedback current source that generates the DC bypass current according to the control current, and a variable resistance circuit that generates the AC bypass current according to the control current. and
The control circuit controls the feedback current source so that the DC bypass current increases as the control current increases, and the control current increases when the control current exceeds a predetermined offset current value. a transimpedance amplifier circuit that controls the variable resistance circuit so that the AC bypass current increases as the current increases. The control circuit generates a first control current by amplifying the control current with a first amplification factor,
The feedback current source is
a first field effect transistor having a first drain for receiving said first control current, a first gate electrically connected to said first drain, and a first source electrically connected to ground potential; ,
a second drain electrically connected to the input terminal; a second gate electrically connected to the first drain and the first gate; and a second source electrically connected to the first source. and a second field effect transistor having
with
2. The transimpedance amplifier circuit according to claim 1, wherein said feedback current source causes said DC bypass current to flow from said second drain to said second source according to said first control current. The control circuit generates an offset current having the offset current value, and amplifies a difference between the current generated by amplifying the control current and the offset current with a second amplification factor to generate a second control current. generate and
The variable resistance circuit is
a third field effect transistor having a third drain receiving the second control current, a third gate electrically connected to the third drain, and a third source supplied with the reference voltage signal;
a fourth drain electrically connected to the input terminal; a fourth gate electrically connected to the third drain and the third gate; and a fourth source supplied with the reference voltage signal. a fourth field effect transistor having
with
3. The transimpedance amplifier circuit according to claim 1, wherein said variable resistance circuit causes said alternating current bypass current to flow from said fourth drain to said fourth source according to said second control current. further comprising a reference voltage generation circuit that generates the reference voltage signal;
4. The transimpedance amplifier circuit according to claim 1, wherein said reference voltage generating circuit comprises an amplifier and a feedback resistance element electrically connected between input and output of said amplifier. .

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